JP2013122799A - Nonvolatile semiconductor storage device - Google Patents

Nonvolatile semiconductor storage device Download PDF

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Publication number
JP2013122799A
JP2013122799A JP2011270386A JP2011270386A JP2013122799A JP 2013122799 A JP2013122799 A JP 2013122799A JP 2011270386 A JP2011270386 A JP 2011270386A JP 2011270386 A JP2011270386 A JP 2011270386A JP 2013122799 A JP2013122799 A JP 2013122799A
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Prior art keywords
memory cell
data
voltage
level
writing
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JP2011270386A
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Japanese (ja)
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Mitsuyoshi Honma
充祥 本間
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Toshiba Corp
株式会社東芝
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3427Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628Programming or writing circuits; Data input circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/10Programming or data input circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436Arrangements for verifying correct programming or erasure
    • G11C16/3454Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459Circuits or methods to verify correct programming of nonvolatile memory cells
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series

Abstract

The probability of erroneous reading is reduced.
A nonvolatile semiconductor memory device includes a memory cell array connected to a plurality of word lines and a plurality of bit lines and having a plurality of memory cells capable of storing n values (n is a natural number of 3 or more); It includes a control circuit 9 that controls the voltage of the word line and the bit line in accordance with the write data and performs a write operation for writing data to the memory cell and a verify operation for determining the threshold voltage of the memory cell. The control circuit 9 performs a verify operation using the first determination voltage and the second determination voltage when writing the first memory cell to the first threshold voltage. Then, when the threshold voltage of the first memory cell is equal to or higher than the first determination voltage and lower than the second determination voltage, the control circuit 9 writes the write data of the second memory cell adjacent to the first memory cell. Whether to complete the writing of the first memory cell or to continue the writing is determined based on the above.
[Selection] Figure 10

Description

  Embodiments described herein relate generally to a nonvolatile semiconductor memory device.

  A NAND flash memory is known as a kind of electrically rewritable nonvolatile semiconductor memory device. As a technique for increasing the data storage capacity of the NAND flash memory, a multi-level (MLC) storage system is used in which the threshold distribution of memory cells is subdivided and the memory cells can store a plurality of bits. .

  In the memory cell of the NAND flash memory, writing is performed by applying a writing voltage to the control gate of the memory cell and injecting electrons into the charge storage layer using a potential difference between the control gate and the substrate. In addition, in the NAND flash memory, writing is performed in units of all memory cells connected to one word line because of its circuit configuration.

  When electrons are injected into a charge storage layer for a certain memory cell due to the influence of capacitive coupling, the threshold voltage of an adjacent memory cell that has already been written may shift. Further, as the memory cell is miniaturized, the amount by which the threshold voltage of the memory cell shifts changes according to the data pattern of the adjacent memory cell, which affects the threshold distribution. For this reason, data in the memory cell cannot be read correctly, that is, erroneous reading increases, and the reliability of the NAND flash memory may be lowered.

JP 2003-196988 A

  Embodiments provide a nonvolatile semiconductor memory device capable of reducing the probability of erroneous reading.

  A nonvolatile semiconductor memory device according to an embodiment includes a memory cell array connected to a plurality of word lines and a plurality of bit lines and having a plurality of memory cells capable of storing n values (n is a natural number of 3 or more), and write data And a control circuit for controlling the voltage of the word line and the bit line and writing data to the memory cell and performing a verify operation for determining the threshold voltage of the memory cell. The control circuit performs a verify operation using the first determination voltage and the second determination voltage (first determination voltage <second determination voltage) when the first memory cell is written to the first threshold voltage. When the threshold voltage of the first memory cell is equal to or higher than the first determination voltage and lower than the second determination voltage, the write data of the second memory cell adjacent to the first memory cell Whether to complete the writing of the first memory cell or to continue the writing.

1 is a block diagram showing a configuration of a nonvolatile semiconductor memory device according to a first embodiment. FIG. 2 is a circuit diagram showing a configuration of a memory cell array and a sense amplifier circuit shown in FIG. 1. The circuit diagram which shows an example of a sense amplifier unit (SAU). The circuit diagram which shows an example of a data control unit (DCU). 6A and 6B illustrate a relationship between a threshold voltage of a memory cell and data. FIG. 6 is a schematic diagram illustrating an example of a writing operation. FIG. 5 is a schematic diagram for explaining a write operation according to the first embodiment. The figure explaining the data allocation of a data latch circuit. The figure which shows the mode of the data of the data latch circuit regarding a focused cell and an adjacent cell. 6 is a flowchart showing a write operation according to the first embodiment. The figure which shows the relationship between the threshold voltage of a memory cell and the data of a data latch circuit after A level write verification. The figure which shows the mode of the data of the data latch circuit regarding a focused cell and an adjacent cell. 9 is a flowchart showing a write operation according to the second embodiment.

  Hereinafter, embodiments will be described with reference to the drawings. However, the drawings are schematic or conceptual, and the dimensions and ratios of the drawings are not necessarily the same as actual ones. The following embodiments exemplify apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the present invention is specified by the shape, structure, arrangement, etc. of components. Is not to be done. In the following description, elements having the same function and configuration are denoted by the same reference numerals, and redundant description will be given only when necessary.

[First Embodiment]
[1. Configuration of Nonvolatile Semiconductor Memory Device]
FIG. 1 is a block diagram showing a configuration of the nonvolatile semiconductor memory device 1 according to the first embodiment. In the present embodiment, a NAND flash memory will be described as an example of the nonvolatile semiconductor memory device 1.

  In FIG. 1, the memory cell array 2 is configured by arranging a plurality of memory cells in a matrix. The memory cell is composed of an electrically rewritable EEPROM cell. The memory cell array 2 is provided with a plurality of bit lines, a plurality of word lines, and a source line in order to control the voltage of the memory cells.

  The word line control circuit 3 serving as a row decoder is connected to a plurality of word lines, and selects and drives the word lines when reading, writing, and erasing data. The sense amplifier circuit 4 is connected to a plurality of bit lines, and controls the voltage of the bit lines when reading, writing, and erasing data. The sense amplifier circuit 4 detects data on the bit line when reading data, and applies a voltage corresponding to the write data to the bit line when writing data. The column decoder 5 generates a column selection signal for selecting a bit line according to the output signal of the address decoder 8 and sends this column selection signal to the sense amplifier circuit 4.

  The input / output control circuit 6 receives various commands CMD, an address signal ADD, and data DT (including write data) supplied from the outside. When writing data, the write data is sent from the input / output control circuit 6 to the sense amplifier circuit 4 via the data input / output buffer 7. At the time of data reading, the read data read to the sense amplifier circuit 4 is sent to the input / output control circuit 6 via the data input / output buffer 7, and the input / output control circuit 6 outputs an external HM (for example, a memory controller or , Host).

  The address signal ADD sent from the input / output control circuit 6 to the data input / output buffer 7 is sent to the address decoder 8. The address decoder 8 decodes the address signal ADD, sends the row address to the word line control circuit 3, and sends the column address to the column decoder 5.

  The command CMD sent from the input / output control circuit 6 to the data input / output buffer 7 is sent to the control circuit (controller) 9. The control circuit 9 is supplied with external control signals such as a chip enable signal / CE, a write enable signal / WE, a read enable signal / RE, an address latch enable signal ALE, and a command latch enable signal CLE from the external HM. The control circuit 9 generates a control signal for controlling a data write / erase sequence and a control signal for controlling data read based on an external control signal and a command CMD supplied in accordance with an operation mode. This control signal is sent to the word line control circuit 3, the sense amplifier circuit 4, the control voltage generation circuit 10, and the like. The control circuit 9 comprehensively controls various operations of the nonvolatile semiconductor memory device 1 using this control signal. Further, the control circuit 9 may not be arranged in the nonvolatile semiconductor memory device 1. That is, it may be disposed in a semiconductor device different from the nonvolatile semiconductor memory device 1 or may be disposed in the external HM.

  The control voltage generation circuit 10 includes a memory cell array 2, a word line control circuit 3, and a sense amplifier circuit 4 according to various control signals sent from the control circuit 9, such as a read voltage, a write voltage, a verify voltage, and an erase voltage. Generates voltages necessary for various operations.

  The parameter storage unit 11 is connected to the input / output control circuit 6 and the control circuit 9 and stores parameters suitable for the quality of the chip determined in the test process.

  FIG. 2 is a circuit diagram showing configurations of the memory cell array 2 and the sense amplifier circuit 4 shown in FIG. The memory cell array 2 includes a plurality of blocks BLK. Each block BLK is a data erasing unit. Each block BLK includes a plurality of NAND strings NS. Each NAND string NS is composed of a plurality of memory cells MC (also referred to as memory cell transistors) and two select gate transistors ST1 and ST2. In FIG. 2, a configuration in which the NAND string NS includes 32 memory cells MC is shown as an example. For example, an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is used as the selection gate transistors ST1 and ST2.

  The memory cell MC includes a charge storage layer (for example, a floating gate electrode, an insulating film having a trap, or a film in which these layers are stacked) formed on a semiconductor substrate (well) with a gate insulating film interposed therebetween, and charge storage. A stacked gate structure having a control gate electrode formed on a layer with an intergate insulating film interposed therebetween is provided. The memory cell MC can store, for example, data of a plurality of bits (or three or more values) in one memory cell MC in accordance with a change in threshold voltage due to the amount of electrons injected into the charge storage layer. .

  Current paths between adjacent memory cells MC in the NAND string NS are connected in series. One end of the memory cells MC connected in series is connected to the source of the select gate transistor ST1, and the other end is connected to the drain of the select gate transistor ST2.

  The control gate electrodes of the memory cells MC in the same row are commonly connected to one word line WL. The gate electrodes of the select gate transistors ST1 (or ST2) in the same row are commonly connected to a select gate line SGD (or SGS). The drain of the select gate transistor ST1 is connected to the bit line BL. The source of the select gate transistor ST2 is connected to the source line SRC.

  A plurality of memory cells MC connected to the same word line WL constitute a page. Data writing and reading are collectively performed on the memory cells MC in one page. The memory cell array 2 is configured such that data of a plurality of pages is erased at once, and the unit of erasure is a block BLK.

  The bit line BL commonly connects the drains of the select gate transistors ST1 between the blocks BLK. That is, NAND strings NS in the same column in the plurality of blocks BLK are connected to the same bit line BL.

  The sense amplifier circuit 4 includes a plurality of sense amplifier units (SAU) 4a and a plurality of data control units (DCU) 4b. The plurality of sense amplifier units 4a are connected to the plurality of bit lines BL0 to BLn, respectively. The plurality of data control units 4b are connected to the corresponding plurality of sense amplifier units 4a, respectively. A plurality of sense amplifier units 4a constitute one sense amplifier unit group 4-1a, and a plurality of data control units 4b constitute one data control unit group 4-1b. Each sense amplifier unit 4a detects and holds data read from the memory cell to the bit line when reading data. Each of the plurality of data control units 4b is connected to the data input / output buffer 7 via column selection transistors CT0 to CTn that operate according to column selection signals SEL0 to SELn.

  Further, the arbitrary data control unit 4b is connected to the data control unit adjacent in the row direction, and is configured to be able to exchange data with the data control unit adjacent to the data control unit 4b. Yes. Adjacent data control units in the row direction are connected by two signal lines, one of which is used to send data to the other, and the other signal line is , One is used to receive data from the other.

  In a write operation (also called a program operation), a read operation, and a program verify operation (also called a verify operation), a bit line connected to the sense amplifier unit 4a is selected and one word line is selected. . A write or read operation is performed simultaneously by applying a write or read voltage to all the memory cells connected to the selected word line.

[1-1. Configuration of Sense Amplifier Unit 4a]
FIG. 3 is a circuit diagram showing an example of the sense amplifier unit (SAU) 4a. The sense amplifier unit 4a includes a plurality of P-channel MOS transistors (hereinafter referred to as PMOS) 20, 21, 22, 23 and a plurality of N-channel MOS transistors (hereinafter referred to as NMOS) 31, 32, 33, 34, 35. , 36, and 37, and a latch circuit LAT1 formed of, for example, two clocked inverter circuits.

  The source of the PMOS 20 is connected to a node to which the power supply voltage Vdd is supplied, and the drain is connected to the data control unit (DCU) 4b via the PMOS 21 and NMOS 31 and 32. The gate of the PMOS 20 is connected to the node INV of the latch circuit LAT1. A signal BLC1 is supplied to the gate of the PMOS 21, and signals BLC2 and BLC3 are supplied to the gates of the NMOS 31 and 32, respectively. A connection node between the NMOS 31 and the NMOS 32 is connected to the bit line BL and grounded via the NMOSs 33 and 34. The gate of the NMOS 33 is connected to the node INV of the latch circuit LAT1, and the NMOS 33 is controlled by data held in the latch circuit LAT1. Further, the signal DIS is supplied to the gate of the NMOS 34.

  The source of the PMOS 22 is connected to a node to which the power supply voltage Vdd is supplied, and the drain is connected to the data control unit 4b via the PMOS 23, NMOS 36, and NMOS 37. A signal BLC 4 is supplied to the gate of the PMOS 22, and the gate of the PMOS 23 is connected to a connection node between the PMOS 21 and the NMOS 31 via the NMOS 35. A signal XXL is supplied to the gate of the NMOS 35, and a reset signal RST is supplied to the gate of the NMOS 36. A signal BLC5 is supplied to the gate of the NMOS 37. The latch circuit LAT1 is connected to the NMOS 36 in parallel.

  The operation of the sense amplifier unit 4a configured as described above will be schematically described.

(Write operation)
When writing data to the memory cell, first, the reset signal RST is once set to the high level (hereinafter referred to as H level), and the latch circuit LAT1 is reset. That is, the node INV of the latch circuit LAT1 is set to L level. Thereafter, the signals BLC1, BLC4, and DIS are set to low level (hereinafter referred to as L level).

  Thereafter, the signals BLC2, BLC3, and XXL are set to the H level, the signal BLC4 is set to the L level, and data is taken in from the data control unit 4b. When this data is at L level “0” indicating writing, the gate of the PMOS 23 becomes L level, and the PMOS 23 is turned on. Therefore, the H level “1” is set in the latch circuit LAT1. When the data is at the H level “1” indicating non-write, the PMOS 23 is turned off. Therefore, L level “0” is set in the latch circuit LAT1. That is, when writing data, the node INV of the latch circuit LAT1 is set to H level, and when not writing, the node INV is set to L level.

  Next, the signals BLC1, BLC3, DIS, and XXL are set to the L level, the signal BLC2 is set to the H level, and the bit line BL is charged to the H level. Thereafter, signal DIS is set to H level. Then, when the node INV of the latch circuit LAT1 is at the H level indicating writing, the NMOS 33 is turned on, and the bit line charge is discharged via the NMOSs 33 and 34. When the node INV of the latch circuit LAT1 is at L level indicating non-writing, the NMOS 33 is turned off, so that the bit line potential is held at H level.

  Thereafter, when the selection gate line SGD of the selection gate transistor ST1 connecting the bit line and the NAND string shown in FIG. 2 is set to H level, the potential of the bit line is transferred to the channel of the memory cell. At the same time, the write voltage Vpgm is applied to the word line of the selected memory cell. Therefore, in the case of a write cell, the channel is at the L level (Vss), the word line is at the write voltage Vpgm, and writing is performed. In the case of a non-write cell, the channel is at the H level (= Vdd−Vt: Vt is the threshold voltage of the selection gate transistor), the word line is Vpgm, the potential difference between the word line and the channel is not sufficiently large, and writing is performed. (Do not write).

(Read operation)
When reading data from the memory cell, first, the reset signal RST is once set to H level, and the latch circuit LAT1 is reset. Thereafter, the signals BLC1, BLC3, DIS, and XXL are set to the L level, the signal BLC2 is set to the H level, and the bit line is charged to the H level. Thereafter, the signal BLC2 is set to L level, and a read voltage is applied to the selected word line. When the threshold voltage of the memory cell is higher than the read voltage, the memory cell is turned off and the bit line is held at the H level. When the threshold voltage of the memory cell is lower than the read voltage, the memory cell is turned on and the bit line charge is discharged. For this reason, the bit line becomes L level. Next, the signal BLC3 is set to H level, and the potential of the bit line is read to the data control unit 4b.

(Program verify operation)
After the write operation, a program verify operation for verifying the threshold voltage of the memory cell is performed. The program verify operation is almost the same as the read operation. In the program verify operation, after a bit line is charged to H level, a predetermined verify voltage is applied to the selected word line. When the threshold voltage of the memory cell has reached the verify voltage, the memory cell is turned off. For this reason, the potential of the bit line is held at the H level. Further, when the threshold voltage of the memory cell does not reach the verify voltage, the memory cell is turned on. For this reason, the potential of the bit line becomes L level.

  In this state, the signals BLC1, BLC2, and XXL are at the H level, the signals BLC4, BLC3, DIS, and RST are at the L level, and the potential of the bit line BL is held in the latch circuit LAT1. That is, when the threshold voltage of the memory cell has reached the verify voltage and the potential of the bit line BL is at the H level, the PMOS 23 is turned off. Therefore, the L level is held in the latch circuit LAT1. Further, when the threshold voltage of the memory cell does not reach the verify voltage and the potential of the bit line BL is L level, the PMOS 23 is turned on. Therefore, the latch circuit LAT1 is held at the H level. That is, when the verification is passed, the potential of the node INV of the latch circuit LAT1 is L level, and when the verification is not passed, the potential of the node INV is H level.

  Further, the data of the inversion node INVn of the latch circuit LAT1 is transferred to the data control unit 4b with the signal BLC5 at the H level and the NMOS 37 turned on.

[1-2. Configuration of Data Control Unit 4b]
FIG. 4 is a circuit diagram showing an example of the data control unit (DCU) 4b. The data control unit 4b includes, for example, four data latch circuits DL0 to DL3, a bus 41, and a data forming circuit 42.

  One end of the bus 41 is connected to the corresponding sense amplifier unit 4 a and the other end is connected to the data input / output buffer 7.

  The data latch circuit DL0 includes a latch circuit LAT2 and a transfer gate 43. The latch circuit LAT2 is connected to the bus 41 via the transfer gate 43. The transfer gate 43 is controlled by a signal φ and its inverted signal φn. The data latch circuits DL1 to DL3 have the same configuration as the data latch circuit DL0, and the signals supplied to the transfer gates are different. Therefore, the data latch circuits DL0 to DL3 can be selectively connected to the bus 41.

  The data forming circuit 42 includes a latch circuit LAT3, PMOSs 52 to 56, NMOSs 61 to 70, an inverter circuit 71, and NMOSs 72 to 75. The source of the PMOS 51 is connected to a node to which the power supply voltage Vdd is supplied. A set signal SET1 is supplied to the gate of the PMOS 51, and the drain is connected to the latch circuit LAT3. Further, the drain of the PMOS 51 is grounded via the NMOS 61 and grounded via the NMOSs 62 and 63. A reset signal RST2 is supplied to the gate of the NMOS 61, and a signal LATH is supplied to the gate of the NMOS 62. The gate of the NMOS 63 is connected to the output terminal of the inverter circuit 71 whose input terminal is connected to the bus 41. Further, the drain of the PMOS 51 is grounded via the NMOSs 64 and 65. A signal LATL is supplied to the gate of the NMOS 64, and the gate of the NMOS 65 is connected to the bus 41.

  Between the node to which the power supply voltage Vdd is supplied and the bus 41, a series circuit of PMOSs 52 and 53, a series circuit of PMOSs 54 and 55, and a PMOS 56 are connected.

  The signal BUSH2 is supplied to the gate of the PMOS 52, and the gate of the PMOS 53 is connected to the node LATn of the LAT3. The PMOSs 52 and 53 are circuits that charge the bus 41 to the H level according to the signal BUSH2 and the potential of the node LATn of the LAT3.

  The signal BUSL2 is supplied to the gate of the PMOS 54, and the gate of the PMOS 55 is connected to the node LAT of the LAT3. The PMOSs 54 and 55 are circuits that charge the bus 41 to the H level according to the signal BUSL2 and the potential of the node LAT of the LAT3.

  A set signal SET2 is supplied to the gate of the PMOS 56. The PMOS 56 is a circuit that charges the bus 41 to the H level in response to the set signal SET2.

  Between the bus 41 and the ground, a series circuit of NMOSs 66 and 67, a series circuit of NMOSs 68 and 69, and an NMOS 70 are connected.

  The signal BUSH1 is supplied to the gate of the NMOS 66, and the gate of the NMOS 67 is connected to the node LATn of LAT3. The NMOSs 66 and 67 are circuits that discharge the bus 41 to the L level according to the signal BUSH1 and the potential of the node LATn of the LAT3.

  A signal BUSL1 is supplied to the gate of the NMOS 68, and the gate of the NMOS 69 is connected to the node LAT of the LAT3. The NMOSs 68 and 69 are circuits that discharge the bus 41 to the L level according to the signal BUSL1 and the potential of the node LAT of the LAT3.

  A reset signal RST2 is supplied to the gate of the NMOS 70. The NMOS 70 is a circuit that discharges the bus 41 to the L level in response to the reset signal RST2.

  A series circuit of NMOSs 72 and 73 and a series circuit of NMOSs 74 and 75 are connected between the bus 41 and the ground.

  A signal BUSLP is supplied to the gate of the NMOS 72, and the gate of the NMOS 73 is connected to LATP (the node LAT of the latch circuit LAT3 included in the data control unit adjacent to the left side in the row direction of the data control unit). The NMOSs 72 and 73 are circuits that discharge the bus 41 to the L level according to the signal BUSLP and the potential of the node LATP.

  A signal BUSLN is supplied to the gate of the NMOS 74, and the gate of the NMOS 75 is connected to the node LATN (the node LAT of the latch circuit LAT3 included in the data control unit adjacent to the right side in the row direction of the data control unit). . The NMOSs 74 and 75 are circuits that discharge the bus 41 to the L level according to the signal BUSLN and the potential of the node LATN.

  The data control unit 4b can hold data in the data latch circuits DL0 to DL3 and process the held data. That is, as will be described later, the data control unit 4b is configured to be able to perform operations corresponding to, for example, logical product “AND”, “NAND”, logical sum “OR”, and inversion of the held data.

(Basic operation of the data control unit)
The basic operation of the data control unit 4b will be described. The 2-bit write data supplied from the data input / output buffer 7 is latched bit by bit in the data latch circuits DL0 and DL1. Here, the data latch circuits DL0 and DL1 hold, for example, lower page data and upper page data, respectively. The data latch circuit DL2 is used to hold flag data indicating that the verification has passed. The data latch circuit DL3 is used for holding data transferred from an adjacent data control unit. Data in the data latch circuits DL0 to DL3 can be transferred to the bus 41 via the transfer gate 43.

  When the data of the bus 41 is taken into the latch circuit LAT3, the reset signal RST2 is set to the H level, the NMOSs 61 and 70 are turned on, and the bus 41 and the latch circuit LAT3 are reset to the L level.

  Next, the set signal SET1 is set to L level to turn on the PMOS 51, and the latch circuit LAT3 is set to H level. Thus, when data is taken into the latch circuit LAT3, the latch circuit LAT3 is first set to the H level. Thereafter, data is transferred to the bus 41 from any of the data latch circuits DL0 to DL3, for example. In this state, the signal LATH is set to H level. When the data on the bus 41 is at the H level, the output signal of the inverter circuit 71 is at the L level, and the NMOS 63 remains off. For this reason, the latch circuit LAT3 remains at the H level.

  When the bus 41 is at L level, the output signal of the inverter circuit 71 is at H level, and the NMOS 63 is turned on. For this reason, the latch circuit LAT3 is discharged through the NMOSs 62 and 63 and becomes L level.

  Next, an operation when the data on the bus 41 is inverted and fetched into the latch circuit LAT3 will be described. As described above, data is transferred to the bus 41 in a state where the latch circuit LAT3 is set to the H level. Thereafter, the signal LATL is set to H level and the signal LATH is set to L level. When the data on the bus 41 is at the H level, the NMOS 65 is turned on. For this reason, the latch circuit LAT3 is discharged through the NMOSs 64 and 65 and becomes L level.

  When the bus 41 is at the L level, the NMOS 65 remains off. For this reason, the latch circuit LAT3 remains at the H level.

  In this way, by transferring the data held in the latch circuit LAT3 to the data latch circuits DL0 to DL3, the data in the data latch circuits DL0 to DL3 can be manipulated.

(Inverting operation of data stored in data latch circuit)
An inversion operation for inverting data in the data latch circuits DL0 to DL3 will be described. First, the bus 41 is charged by the above-described operation, and any one of the transfer gates 43 of the data latch circuits DL0 to DL3 is opened. For example, when the transfer gate 43 of the data latch circuit DL0 is opened and the node DT of the data latch circuit DL0 is at H level, the bus 41 is discharged via the clocked inverter circuit of the data latch circuit DL0, and the node DT Is inverted to the bus 41.

  Next, after resetting LAT3 as described above, signal SET1 is set to L level and node LAT of LAT3 is set to H level.

  Next, when the signal LATL is set to H level, when the bus 41 is discharged by the data of the data latch circuit DL0, the node LAT is set to H level, and when the bus 41 remains charged, the NMOS 65 is turned on. Therefore, node LAT is discharged to L level.

  Next, as described above, when the bus 41 is charged and the signal BUSH1 is set to the H level, when the node LAT is at the H level (the LAT3 node LATn is at the L level), the bus 41 maintains the H level, When L level (LAT3 node LATn is at H level), the bus 41 is at L level.

  Finally, after resetting the latch circuit LAT2 of the data latch circuit DL0, the data on the bus 41 is taken into the latch circuit LAT2 via the transfer gate 43 by opening the transfer gate 43. As a result, when the data on the bus 41 is at the H level, the node DT is at the L level, and when the data on the bus 41 is at the L level, the node DT is at the H level.

  To summarize the above series of operations, the inverted data of the node DT of the latch circuit LAT2 is transferred to the bus 41, and further inverted data of this inverted data is transferred to the latch circuit LAT3. The data of the latch circuit LAT3 is transferred to the bus 41, and the inverted data of the bus 41 is held at the node DT of the latch circuit LTA2. In this way, the node DT of the data latch circuits DL0 to DL3 is inverted.

  The basic operation of the data control unit 4b is not limited to this, and can be performed by other operations. Based on this operation, data “AND”, “NAND”, and “OR” operations can be performed.

(Data transfer operation between adjacent data control units)
As shown in FIG. 2, the data control unit 4b is connected to a data control unit adjacent in the row direction, and data can be exchanged with the data control unit adjacent in the row direction of the data control unit 4b. It is configured as follows. In order to perform this data transfer operation, the data control unit 4b (specifically, the data forming circuit 42) includes NMOSs 72 to 75.

  As described above, when the bus 41 is charged and the signal BUSLP is set to the H level, when the node LATP is at the L level, the bus 41 maintains the H level, and when the node LATP is at the H level, the bus 41 becomes the L level. . With this operation, the inverted data of the latch circuit LAT3 included in the data control unit adjacent to the left side of the data control unit can be transferred to the bus 41. Thereafter, the data latch circuit DL3 holds the data of the bus 41.

  Similarly, when the bus 41 is charged and the signal BUSLN is set to the H level as described above, when the node LATN is at the L level, the bus 41 maintains the H level, and when the node LATN is at the H level, the bus 41 is set to the L level. Become a level. With this operation, the inverted data of the latch circuit LAT3 included in the data control unit adjacent to the right side of the data control unit can be transferred to the bus 41. Thereafter, the data latch circuit DL3 holds the data of the bus 41.

[2. Operation of Nonvolatile Semiconductor Memory Device]
Next, the operation of the nonvolatile semiconductor memory device 1 configured as described above will be described. The memory cell MC of this embodiment can store data of 2 bits or more (or three values, for example, the number of threshold distributions is 3 or more) in one memory cell MC. Hereinafter, a case where the memory cell MC stores 2-bit data will be described as an example.

  FIG. 5 is a diagram for explaining the relationship between the threshold voltage of the memory cell MC and data. The 2-bit data is represented by “xy” by the upper page data “x” and the lower page data “y”. Here, for example, Er level = “11”, A level = “01” according to the threshold distribution. , B level = “00”, and C level = “10”. In the case of a 2-bit data storage system, data writing (programming) requires two writing operations of a lower page program and an upper page program.

  The Er level is an erased state (for example, negative threshold voltage) having the lowest threshold voltage of the memory cell. FIG. 5A shows the threshold distribution of the memory cell when the lower page is programmed, and the threshold voltage Vth of the memory cell is set to either the Er level or the LM (Lower Middle) level. The lower page program is an operation for selectively setting an Er level memory cell to the LM level. The memory cell at the LM level is a memory cell whose lower page data is “0” data.

  FIG. 5B shows a threshold distribution when the upper page is programmed. The upper page program includes a first upper page program that selectively sets memory cells at the Er level to the A level, and a second upper page program that selectively sets memory cells at the LM level to the B level and the C level. Including. In these two types of upper page programs, “0” and “1” data are selectively given to the selected page in one write sequence, and a program voltage is simultaneously applied.

  FIG. 6 is a schematic diagram for explaining an example of the write operation. In the write operation, a step of applying a write voltage to the word line to raise the threshold voltage of the memory cell and a step of checking (verifying) the threshold voltage of the memory cell are repeatedly executed and connected to the word line. When the verification of all the memory cells (or a predetermined number or more memory cells) of the selected page passes, the writing of the word line is completed and the writing of the next word line is performed. Further, the write operation in the block BLK is performed in order from the word line WL close to the source line SRC, for example.

  As shown in FIG. 6A, when the memory cell is written to the A level, the determination voltage AV that the A level verification passes and the determination voltage AVL slightly lower than the determination voltage AV (higher than the Er level) are two. A determination voltage is prepared and the verify operation is performed in two steps. In the verify operation, a memory cell having a threshold voltage that is equal to or higher than the determination voltage AVL and lower than the determination voltage AV applies an intermediate voltage between 0 V and Vdd to the bit line in the next write voltage application operation. As a result, the variation amount (rise amount) of the threshold voltage can be reduced as compared with the case where 0 V is applied to the bit line. As a result, as shown in FIG. 6B, the threshold voltage distribution can be narrowed.

  However, the narrow distribution obtained by this method is also affected by capacitive coupling in the process of writing when the adjacent cell is written to a threshold voltage higher than the A level, and as a result, as shown in FIG. Distribution spreads like a broken line.

  Therefore, in this embodiment, the determination voltage of the target cell is determined when the write data of the adjacent cell adjacent to the target cell written in the A level in the row direction has a threshold voltage (B and C levels) higher than the A level. The voltage AV is set to be equal to or higher than the determination voltage AV. Thereby, even when the threshold voltage of the target cell shifts due to capacitive coupling with the adjacent cell, it is possible to suppress the spread of the threshold distribution of the A level memory cell.

  FIG. 7 is a schematic diagram for explaining the write operation according to the present embodiment. As shown in FIG. 7A, verification is performed using two verification voltages AVL and AV, and a group of memory cells (first group) having a threshold voltage equal to or higher than the determination voltage AVL and lower than the determination voltage AV. ). Then, the first group is further divided into two groups based on data (adjacent data) of adjacent cells adjacent to the target cell. That is, it is checked whether the cell of interest having a threshold voltage that is equal to or higher than the AVL level and lower than the AV level includes the B or C level (B / C level) in the adjacent data or does not include the B or C level in the adjacent data.

  In the verify operation after the write voltage is applied, when a target cell having a threshold voltage that is equal to or higher than the determination voltage AVL and lower than the determination voltage AV includes B or C level in the adjacent data, the write is completed for the target cell (write Prohibited). On the other hand, when a target cell having a threshold voltage that is equal to or higher than the determination voltage AVL and lower than the determination voltage AV does not include the B or C level in the adjacent data, an intermediate potential is applied to the bit line from the next write voltage application operation. Is applied. The A level threshold distribution for which writing has been completed by such a method is as shown by the solid line in FIG. Thereafter, since the memory cells at the B and C levels are written, the memory cells having a threshold voltage that is equal to or higher than the determination voltage AVL and lower than the determination voltage AV are distributed as shown by a broken line due to the influence of capacitive coupling. As a result, the threshold distribution of the A level memory cell is narrower than that at the completion of the A level write.

  Next, a control method for determining whether or not the target cell is a memory cell having a threshold voltage that is equal to or higher than the determination voltage AVL and lower than the determination voltage AV and that includes B or C level in adjacent data will be described. FIG. 8 is a diagram for explaining data allocation of the data latch circuits DL0 to DL2.

  The data latch circuit DL0 stores lower page data among 2-bit write data. The data latch circuit DL1 stores upper page data out of 2-bit write data. The data latch circuit DL2 stores pass / fail data as a result of the verification of the lower verify voltage (corresponding to the determination voltage AVL in the case of the A level). Assume that the verify pass is “1” data and the verify fail is “0” data. In memory cells in which writing has been completed (including memory cells that have passed the verification of the determination voltage AV), the data in the data latch circuits DL1 to DL2 is set to “111”.

  FIG. 9 shows the state of data in the data latch circuits DL0 to DL2 regarding the target cell and adjacent cells. The target cell is an arbitrary memory cell included in the selected page connected to the selected word line WLn and is a memory cell written to the A level. The adjacent cell 1 is a memory cell that is connected to the selected word line WLn and is adjacent to the left side of the target cell. The adjacent cell 2 is a memory cell connected to the selected word line WLn and adjacent to the right side of the target cell. The adjacent cell 1, the target cell, and the adjacent cell 2 are connected to the bit lines BLm-1, BLm, and BLm + 1, respectively. In the example of FIG. 9, there is one target cell. However, in the case where the adjacent cell itself is handled as the target cell, the calculation is divided into two times, an even cell and an odd cell. Run.

First, calculation of odd (odd) cells will be described. The calculation of the odd (odd) cell is performed as the following equation. Note that “odd” is the data latch circuit of the target cell, “even1” is the data latch circuit of the adjacent cell 1, and “even2” is the data latch circuit of the adjacent cell 2. “˜” means inversion, “|” means logical sum “OR”, “&” means logical product “AND”, and “→” means data storing operation.
(~ DL0 (even1) | ~ DL0 (even2)) & DL0 (odd) & ~ DL1 (odd) & DL2 (odd) | DL1 (odd) → DL1 (odd)
Specifically, in order to determine that the write data of the adjacent cell (adjacent cell 1 or adjacent cell 2) is at the B or C level, the inverted data of the data latch circuit DL0 of the adjacent cell is used. When the logical sum of the inverted data of the data latch circuit DL0 of the adjacent cell 1 and the adjacent cell 2 is “1”, it can be seen that at least one of the adjacent cell 1 and the adjacent cell 2 is at the B or C level.

  Subsequently, in order to determine that the target cell is a memory cell written to the A level and has a threshold voltage that is equal to or higher than the determination voltage AVL and lower than the determination voltage AV as a result of the verification, an operation “DL0 & ˜DL1 & DL2” is performed. To the cell of interest. When the logical product with the above-mentioned operation is “1”, the target cell is a memory cell written to the A level, and has a threshold voltage that is equal to or higher than the determination voltage AVL and lower than the determination voltage AV. And it can be determined that the adjacent cell 1 or the adjacent cell 2 is at the B or C level. At this time, in order to use verification of the target cell as a pass, the result of logical OR with the data latch circuit DL1 of the target cell is also substituted into the data latch circuit DL1 of the target cell. As a result, the data latch circuits DL0 to DL2 of the target cell are set to “111”, the writing of the target cell is completed, and the target cell is set to write prohibition in the subsequent write operation.

Subsequently, the same operation as for odd cells is performed on even cells. The calculation of the even cell is performed as shown in the following formula.
(~ DL0 (odd1) | ~ DL0 (odd2)) & DL0 (even) & ~ DL1 (even) & DL2 (even) | DL1 (even) → DL1 (even)
This calculation completes the preparation for the next writing. Thereafter, a write operation (application of a write voltage) is performed based on data in the data latch circuit.

A state where the result of the above calculation is “1”, that is, a state where “the target cell is at the A level and at least one of the adjacent cell 1 and the adjacent cell 2 is at the B or C level” is satisfied. And the adjacent cell 2 has the following data pattern. The write data (Er, A, B, C) is represented by the notation “(adjacent cell 1) − (target cell) − (adjacent cell 2)”.
(Data pattern including C level in adjacent cells)
“C-A-C”, “C-A-B”, “C-A-A”, “C-A-Er”, “B-A-C”, “A-A-C”, “Er” -7 data patterns of A-C "(data pattern including B level or less in adjacent cells)
Five data patterns of “B-A-B”, “B-A-A”, “B-A-Er”, “A-A-B”, “Er-A-B” Data pattern as described above In this case, and when the determination voltage of the target cell is equal to or higher than the determination voltage AVL and lower than the determination voltage AV, the target cell is written.

  FIG. 10 is a flowchart showing the write operation according to the present embodiment. FIG. 10 shows a write operation in the target cell, and therefore the write operation in FIG. 10 is executed for all the memory cells in the selected page.

  First, after the sense amplifier circuit 4 sets the bit line voltage according to the write data and the previous verify result, the word line control circuit 3 applies the write voltage for writing the A level to the selected word line (step). S100). Subsequently, the sense amplifier circuit 4 and the word line control circuit 3 execute a verify operation using the determination voltages AVL and AV (step S101).

  Subsequently, when the verification of the determination voltage AVL is “fail” in step S102, the cell of interest continues to be written (step S103). That is, the sense amplifier circuit 4 sets the data of the data latch circuit so as to continue the writing with the bit line voltage set to 0 V for the cell of interest.

  If the verification of the determination voltage AVL is “pass” in step S102, the control circuit 9 determines whether at least one adjacent data of the adjacent cell 1 and the adjacent cell 2 adjacent to both sides of the target cell is at the B or C level. Is determined (step S104). If the adjacent data is at the B or C level in step S104, the target cell is completely written (step S105). That is, the sense amplifier circuit 4 sets data in the data latch circuit so that writing to the target cell is prohibited.

  If the adjacent data is not at the B or C level in step S104, the control circuit 9 determines whether or not the AV level verification has passed (step S106). If the AV level verification is a pass in step S106, the target cell is written (step S105). That is, the sense amplifier circuit 4 sets data in the data latch circuit so that writing to the target cell is prohibited.

  If the verify at the AV level is “fail” in step S106, the adjacent cell is not at the B or C level, so that the target cell continues to be written (step S107). That is, the sense amplifier circuit 4 sets the data in the data latch circuit so as to continue writing with the bit line voltage being the intermediate voltage for the cell of interest.

  After the above control is performed on all the memory cells included in the selected page, the current write stage (application of the write voltage and verification) is completed. Thereafter, the next write stage is executed using the write voltage to which the step-up voltage is added.

  FIG. 11 is a diagram showing the relationship between the threshold voltage of the memory cell and the data in the data latch circuit after the A level write verify. In this embodiment, the write state of the memory cell is classified into four patterns after the A level write verify, that is, after the verify operation of the determination voltages AVL and AV.

  As the first pattern, when the verification of both the AVL level and the AV level is not passed, that is, the threshold voltage Vth of the memory cell is lower than the AVL level, the normal write operation for setting the bit line to 0 V continues. Is called. At this time, the data in the data latch circuits DL0 to DL2 is “100”.

  When the verification at the AVL level passes and the verification at the AV level fails, that is, when the threshold voltage Vth of the memory cell is equal to or higher than the AVL level and lower than the AV level, the write state is determined after examining the data of the adjacent cells. The Specifically, when the threshold voltage Vth of the memory cell is equal to or higher than the determination voltage AVL and lower than the determination voltage AV, and the write data of the adjacent cell is at the Er or A level, the write operation using the bit line as an intermediate voltage is performed. Continued (second pattern). The data in the data latch circuits DL0 to DL2 at this time is “101”. On the other hand, when the threshold voltage Vth of the memory cell is equal to or higher than the determination voltage AVL and lower than the determination voltage AV, and the write data of the adjacent cell is at the B or C level, the memory cell is prohibited from being written (third pattern ). The data in the data latch circuits DL0 to DL2 at this time is “111”.

  As a fourth pattern, when both the verification of the determination voltage AVL and the determination voltage AV pass, that is, when the threshold voltage Vth of the memory cell is equal to or higher than the AV level, the memory cell is prohibited from writing. The data in the data latch circuits DL0 to DL2 at this time is “111”.

[3. effect]
As described above in detail, in the first embodiment, the nonvolatile semiconductor memory device 1 is connected to a plurality of word lines and a plurality of bit lines, and can store a plurality of n values (n is a natural number of 3 or more). Control for performing a memory cell array 2 having memory cells, a write operation for controlling the voltages of word lines and bit lines in accordance with write data, writing data to the memory cells, and a verify operation for determining the threshold voltage of the memory cells. And a circuit 9. The control circuit 9 performs a verify operation using the determination voltages AVL and AV (AVL <AV) when writing the target cell to the A level. Then, when the threshold voltage of the target cell is equal to or higher than the AVL level and lower than the AV level, and the adjacent cell adjacent to the target cell is written to a threshold voltage (B or C level) higher than the A level, The writing of the target cell is completed.

  Therefore, according to the first embodiment, even when the threshold voltage of the cell of interest shifts from the threshold voltage immediately after the completion of writing due to capacitive coupling with adjacent cells, the threshold distribution of the A-level memory cell is prevented from spreading. Can do. As a result, the threshold distribution of the memory cells can be narrowed. As a result, the data in the memory cell can be read accurately, so that the nonvolatile semiconductor memory device 1 that can reduce erroneous reading can be realized.

  Further, in the present embodiment, the threshold fluctuation can be compensated according to the data pattern between adjacent cells, so that the threshold distribution of the memory cell can be narrowed even when the memory cell is further miniaturized. .

  Further, the target cell is a memory cell written to the A level, the threshold voltage of the target cell is equal to or higher than the determination voltage AVL and lower than the determination voltage AV, and the adjacent cell adjacent to the target cell is equal to or lower than the A level threshold voltage ( (Er or A level), the control circuit 9 performs writing by applying an intermediate voltage between the ground voltage Vss and the power supply voltage Vdd to the bit line. Thereby, since the amount of increase in the threshold voltage of the target cell can be reduced, the threshold distribution of the memory cell can be narrowed.

[Second Embodiment]
The shift amount of the threshold voltage of the memory cell (target cell) increases as the difference in threshold voltage between the target cell and the adjacent cell increases. That is, when the target cell is written at the A level and the adjacent cell is at the C level, the shift amount of the threshold voltage of the target cell is larger than when the adjacent cell is at the B level. Therefore, in the second embodiment, when the threshold voltage Vth of the target cell is equal to or higher than the determination voltage AVL and lower than the determination voltage AV, and the adjacent cell is at the C level (the state in which the threshold voltage is the highest), The writing is completed.

  FIG. 12 shows the state of data in the data latch circuits DL0 to DL2 regarding the target cell and adjacent cells. In the example of FIG. 12, there is one target cell. However, in the case where the adjacent cell itself is actually handled as the target cell, the calculation is executed in two steps of an even cell and an odd cell. .

First, calculation of odd (odd) cells will be described. The calculation of the odd (odd) cell is performed as the following equation. Note that “odd” is the data latch circuit of the target cell, “even1” is the data latch circuit of the adjacent cell 1, and “even2” is the data latch circuit of the adjacent cell 2.
(~ DL0 (even1) & DL1 (even1) | ~ DL0 (even2) & DL1 (even2)) & DL0 (odd) & ~ DL1 (odd) & DL2 (odd) | DL1 (odd) → DL1 (odd)
Specifically, in order to determine that the write data of the adjacent cell (adjacent cell 1 or adjacent cell 2) is at the C level, the data of the data latch circuits DL0 and DL1 of the adjacent cell are used. When the logical product of the inverted data of the data latch circuit DL0 of the adjacent cell 1 and the data of the data latch circuit DL1 of the adjacent cell 1 is “1”, it can be seen that the adjacent cell 1 is at the C level. Since the same applies to the adjacent cell 2, when the logical sum of the operation result of the adjacent cell 1 and the operation result of the adjacent cell 2 is “1”, at least one of the adjacent cell 1 and the adjacent cell 2 is at the C level. I understand that.

  Subsequently, in order to determine that the target cell is a memory cell written to the A level and has a threshold voltage that is equal to or higher than the determination voltage AVL and lower than the determination voltage AV as a result of the verification, an operation “DL0 & ˜DL1 & DL2” is performed. To the cell of interest. When the logical product with the above-mentioned operation is “1”, the target cell is a memory cell written to the A level, and has a threshold voltage that is equal to or higher than the determination voltage AVL and lower than the determination voltage AV. And it can be determined that the adjacent cell 1 or the adjacent cell 2 is at the C level. At this time, in order to use verification of the target cell as a pass, the result of logical OR with the data latch circuit DL1 of the target cell is also substituted into the data latch circuit DL1 of the target cell. As a result, the data latch circuits DL0 to DL2 of the target cell are set to “111”, the writing of the target cell is completed, and the target cell is set to write prohibition in the subsequent write operation.

Subsequently, the same operation as for odd cells is performed on even cells. The calculation of the even cell is performed as shown in the following formula.
(~ DL0 (odd1) & DL1 (odd1) | ~ DL0 (odd2) & DL1 (odd2)) & DL0 (even) & ~ DL1 (even) & DL2 (even) | DL1 (even) → DL1 (even)
This calculation completes the preparation for the next writing. Thereafter, a write operation (application of a write voltage) is performed based on data in the data latch circuit.

A state in which the result of the above calculation is “1”, that is, a state in which “the target cell is at the A level and at least one of the adjacent cell 1 and the adjacent cell 2 is at the C level” is satisfied. Cell 2 has the following data pattern. The write data (Er, A, B, C) is represented by the notation “(adjacent cell 1) − (target cell) − (adjacent cell 2)”.
“C-A-C”, “C-A-B”, “C-A-A”, “C-A-Er”, “B-A-C”, “A-A-C”, “Er” Seven Data Patterns of -A-C "In the case of the data pattern as described above, and when the threshold voltage of the target cell is equal to or higher than the determination voltage AVL and lower than the determination voltage AV, the target cell is set to be written.

  FIG. 13 is a flowchart showing a write operation according to the present embodiment. FIG. 13 shows a write operation in the target cell, and therefore the write operation in FIG. 13 is executed for all the memory cells in the selected page.

  In the write operation according to the present embodiment, when the verification of the determination voltage AVL is a pass in step S202, the control circuit 9 causes the adjacent data C level of at least one of the adjacent cells 1 and 2 adjacent to both sides of the target cell. It is determined whether or not (step S204). If the adjacent data is at the C level in step S204, the target cell is completely written (step S205). That is, the sense amplifier circuit 4 sets data in the data latch circuit so that writing to the target cell is prohibited. The other steps are the same as those in the flowchart of FIG. 10 described in the first embodiment.

(effect)
As described above in detail, according to the second embodiment, the threshold voltage Vth of the memory cell (target cell) is equal to or higher than the determination voltage AVL and lower than the determination voltage AV, and the adjacent cell has the C level (the highest threshold voltage). In the case of (state), it can be controlled to complete the writing of the cell of interest.

  This makes it possible to reduce the shift amount of the threshold voltage of the target cell when an adjacent cell adjacent to the target cell written to the A level is written to the C level (the highest threshold voltage). Other effects are the same as those of the first embodiment.

  In each of the above embodiments, a configuration in which one memory cell stores 2 bits is shown, but the present invention can be similarly applied to a case where one memory cell stores 3 bits or more. Further, in each of the above embodiments, the case where the target cell is written to the A level is described, but the present invention can be similarly applied to the case where the target cell is written to a threshold voltage other than the A level.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 1 ... Nonvolatile semiconductor memory device, 2 ... Memory cell array, 3 ... Word line control circuit, 4 ... Sense amplifier circuit, 4a ... Sense amplifier unit, 4b ... Data control unit, 5 ... Column decoder, 6 ... Input / output control circuit, DESCRIPTION OF SYMBOLS 7 ... Data input / output buffer, 8 ... Address decoder, 9 ... Control circuit, 10 ... Control voltage generation circuit, 11 ... Parameter storage part.

Claims (5)

  1. A memory cell array connected to a plurality of word lines and a plurality of bit lines and having a plurality of memory cells capable of storing n values (n is a natural number of 3 or more);
    A control circuit for controlling a voltage of a word line and a bit line according to write data and performing a write operation for writing data to the memory cell and a verify operation for determining a threshold voltage of the memory cell;
    Comprising
    The control circuit includes:
    When writing the first memory cell to the first threshold voltage, a verify operation is performed using the first determination voltage and the second determination voltage (first determination voltage <second determination voltage),
    When a threshold voltage of the first memory cell is equal to or higher than the first determination voltage and lower than the second determination voltage, based on write data of a second memory cell adjacent to the first memory cell Determining whether to write to the first memory cell or to continue writing;
    A non-volatile semiconductor memory device.
  2.   The control circuit includes a first threshold voltage of the first memory cell that is equal to or higher than the first determination voltage and lower than the second determination voltage, and the second memory cell is higher than the first threshold voltage. The nonvolatile semiconductor memory device according to claim 1, wherein writing to the first memory cell is completed when the threshold voltage is written to 2.
  3. The control circuit includes a first threshold voltage of the first memory cell that is equal to or higher than the first determination voltage and lower than the second determination voltage, and the second memory cell is equal to or lower than the first threshold voltage. When the threshold voltage of 3 is written, an intermediate voltage is applied to the bit line connected to the first memory cell to continue writing to the first memory cell;
    The intermediate voltage includes a first bit line voltage used when writing a memory cell having a threshold voltage lower than the first determination voltage, and a second bit line voltage used when writing the memory cell to the write inhibition (first bit voltage). 3. The nonvolatile semiconductor memory device according to claim 1, wherein the non-volatile semiconductor memory device is set between 1 bit line voltage <second bit line voltage). 4.
  4. The control circuit prohibits writing to a third memory cell having a threshold voltage equal to or higher than the second determination voltage;
    4. The nonvolatile semiconductor memory device according to claim 1, wherein the first memory cell in which the writing has been completed is set to the same bias as that of the third memory cell. 5.
  5. A latch circuit for storing memory cell write data and verify results;
    5. The first latch circuit connected to the first memory cell has a data path between the first latch circuit connected to the second memory cell and the latch circuit connected to the second memory cell. The non-volatile semiconductor memory device described in 1.
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