JP2013120945A - Light-emitting element and light-emitting device - Google Patents

Light-emitting element and light-emitting device Download PDF

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JP2013120945A
JP2013120945A JP2013058453A JP2013058453A JP2013120945A JP 2013120945 A JP2013120945 A JP 2013120945A JP 2013058453 A JP2013058453 A JP 2013058453A JP 2013058453 A JP2013058453 A JP 2013058453A JP 2013120945 A JP2013120945 A JP 2013120945A
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semiconductor layer
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JP5701921B2 (en
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Shigenobu Sekine
重信 関根
Yurina Sekine
由莉奈 関根
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Napra Co Ltd
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Abstract

PROBLEM TO BE SOLVED: To provide a light-emitting element and a light-emitting device, which greatly improve a current density in a PN junction; maximize a heat sink effect (heat radiation effect); and achieve an increased light emission amount and improved light emission efficiency.SOLUTION: A light-emitting device comprises: an overlapping part where a PN semiconductor lamination structure 1, a P-type semiconductor layer 11 and an N-type semiconductor layer 13 overlap each other; and a non-overlapping part 14 where the PN semiconductor lamination structure 1, the P-type semiconductor layer 11 and the N-type semiconductor layer 13 do not overlap each other. The non-overlapping part 14 is arranged lateral to the overlapping part and has a width W1 viewed in arrangement direction narrower than a width W2 of the overlapping part, and the N-type semiconductor layer 13 appears. A P-side electrode 5 and an N-side electrode 7 are provided on a surface on the side opposite to a light emission surface 30. The N-side electrode 7 is provided on the N-type semiconductor layer 13 in the non-overlapping part 14 and electrically insulated from the P-type semiconductor layer 11 and the P-side electrode 5 by an insulation gap G1. The P-side electrode 5 covers almost an entire surface of the P-type semiconductor layer 11 except the insulation gap G1.

Description

本発明は、発光ダイオードを用いた発光素子及び発光デバイスに関する。   The present invention relates to a light emitting element and a light emitting device using a light emitting diode.

発光ダイオードを用いた発光素子は、省エネルギー、長寿命という利点があり、照明装置、カラー画像表示装置、液晶パネルのバックライト、又は、交通信号灯などの光源として、注目されている。   A light-emitting element using a light-emitting diode has advantages of energy saving and long life, and has attracted attention as a light source such as a lighting device, a color image display device, a liquid crystal panel backlight, or a traffic light.

発光ダイオードを用いた発光素子は、例えば、青色発光素子を例に採ると、特許文献1に開示されているように、サファイアでなる基板の表面に、バッファ層、N型GaN層、活性層、P型GaN層、及び、透明電極層を順次に積層した構造となっている。   For example, when a light-emitting element using a light-emitting diode is a blue light-emitting element, as disclosed in Patent Document 1, a buffer layer, an N-type GaN layer, an active layer, A P-type GaN layer and a transparent electrode layer are sequentially stacked.

透明電極層の一部表面にはP側電極が形成されており、また、透明電極層、P型GaN層及び活性層の一部をドライエッチングし、N型GaN層の一部を露出させ、この露出したN型GaN層にN側電極を形成した構造となっている。N型GaN層の一部を露出させた部分は、P型GaN層及び活性層と、N型GaN層とが重ならない部分であり、その他が重なる部分となる。重なる部分が発光領域となり、重ならない部分は、非発光領域となる。特許文献2、3にも、同様の積層構造及び電極構造が開示されている。   A P-side electrode is formed on a part of the surface of the transparent electrode layer, and the transparent electrode layer, the P-type GaN layer and a part of the active layer are dry-etched to expose a part of the N-type GaN layer, An N-side electrode is formed on the exposed N-type GaN layer. The part where the part of the N-type GaN layer is exposed is a part where the P-type GaN layer and the active layer do not overlap with the N-type GaN layer, and the other part overlaps. The overlapping portion becomes a light emitting region, and the non-overlapping portion becomes a non-light emitting region. Patent Documents 2 and 3 also disclose similar laminated structures and electrode structures.

パッケージング基板への実装に当たって、従来は、フリップ・チップ(FC)として構成されたLEDチップ型の発光素子をサブマウント基板に実装し、更に、この組み立て体をパッケージング基板に実装し、サブマウント基板に形成された電極と、パッケージング基板に形成された電極とを、ワイヤ・ボンディングによって接続していた。   In mounting on a packaging substrate, conventionally, an LED chip type light emitting element configured as a flip chip (FC) is mounted on a submount substrate, and this assembly is further mounted on the packaging substrate, and the submount is mounted. The electrodes formed on the substrate and the electrodes formed on the packaging substrate are connected by wire bonding.

しかし、この組み立て構造では、AlN等の高価な材料で構成されたサブマウント基板を使用しなければならいことから、コスト高になる。しかも、サブマウント基板に形成された電極と、パッケージング基板に形成された電極とを、ワイヤ・ボンディングによって接続する必要があるため、ワイヤ・ボンディング装置が必要であり、生産設備費が増大し、それが製品コストに転嫁され、発光デバイスのコスト高を招いていた。   However, this assembly structure increases the cost because a submount substrate made of an expensive material such as AlN must be used. Moreover, since it is necessary to connect the electrode formed on the submount substrate and the electrode formed on the packaging substrate by wire bonding, a wire bonding apparatus is necessary, and the production equipment cost increases. This was passed on to the product cost, leading to high costs for light emitting devices.

上述した問題点を解決する手段として、特許文献4には、シリコン・サブマウントの一面に溝を形成し、その溝底部に2つのビア(貫通電極)を形成し、LEDダイスを、溝内にフリップ・チップ・マウントし、保護接着剤で溝を充填するLEDパッケージの製造方法が開示されている。   As means for solving the above-mentioned problems, Patent Document 4 discloses that a groove is formed on one surface of a silicon submount, two vias (penetrating electrodes) are formed at the bottom of the groove, and an LED die is placed in the groove. A method of manufacturing an LED package that is flip chip mounted and filled with grooves with a protective adhesive is disclosed.

このようなLEDパッケージ構造を採用する場合、従来は、P型半導体層、活性層及びN型半導体層が重なる部分に設けられる電極(通常は、P側電極)を、パッケージ側に備えられる貫通電極の端面の面積に合わせるのが一般的であった。このため、P側電極からP型半導体層に対する電流供給面積が、重なり面積よりもかなり小さな平面積に限定されてしまい、P型半導体層、活性層及びN型半導体層の接合部で見た電流密度が低下し、発光量、発光効率が低下するという問題点があった。   When such an LED package structure is employed, conventionally, an electrode (usually a P-side electrode) provided in a portion where the P-type semiconductor layer, the active layer, and the N-type semiconductor layer overlap is provided as a through electrode provided on the package side. In general, it was adjusted to the area of the end face. For this reason, the current supply area from the P-side electrode to the P-type semiconductor layer is limited to a flat area that is considerably smaller than the overlapping area, and the current viewed at the junction of the P-type semiconductor layer, the active layer, and the N-type semiconductor layer. There is a problem that the density is lowered, and the light emission amount and the light emission efficiency are lowered.

また、パッケージング基板側に備えられる貫通電極の横断面積が小さいため、パッケージとしたときの放熱性が悪く、発光素子の温度上昇を招き、特性が悪化する。この特性悪化を回避するためは、供給電流値を小さい値に抑制しなければならず、必然的に、発光量、発光効率の改善に限界を生じる結果になっていた。   Further, since the cross-sectional area of the through electrode provided on the packaging substrate side is small, the heat dissipation when packaged is poor, the temperature of the light emitting element is increased, and the characteristics are deteriorated. In order to avoid this deterioration of characteristics, the supply current value must be suppressed to a small value, which inevitably results in limitations on the improvement of the light emission amount and the light emission efficiency.

重ならない部分に設けられる電極(通常は、N側電極)についても、貫通電極の端面形状に合わせ、N側電極を貫通電極の端面に接合する構造を採用していたため、N型半導体層における電極接触面積が小さくなっている。このため、P側電極の場合ほどではないにしても、やはり、発光量、発光効率に悪影響を与える。また、N側電極と貫通電極との位置合わせが難しくなり、僅かな位置ずれを生じただけで、両者間の接続不良を生じやすくなる。上述した問題点を解決するため、N側電極や貫通電極の面積を大きくすると、重ならない部分の幅を増大させなければならず、反射的に、発光領域となる重なる部分の面積が縮小され、発光量及び発光効率が低下する。   The electrode (usually the N-side electrode) provided in the non-overlapping portion also employs a structure in which the N-side electrode is joined to the end surface of the through electrode in accordance with the shape of the end surface of the through electrode. The contact area is small. For this reason, even if not as much as in the case of the P-side electrode, the light emission amount and the light emission efficiency are adversely affected. In addition, it becomes difficult to align the N-side electrode and the through electrode, and a slight misalignment is likely to cause poor connection between the two. In order to solve the above-described problems, when the area of the N-side electrode or the through electrode is increased, the width of the non-overlapping portion must be increased, and the area of the overlapping portion that becomes the light emitting region is reduced reflectively, The light emission amount and the light emission efficiency are reduced.

特開2001−210867号公報JP 2001-210867 A 特開2009−71337号公報JP 2009-71337 A 特開2008−153634号公報JP 2008-153634 A 特開2009−111006号公報JP 2009-111006 A

本発明の課題は、PN接合部で見た電流密度を大幅に向上させるとともに、ヒートシンク効果(放熱効果)を最大化し、発光量の増大、発光効率向上を図った発光素子及び発光デバイスを提供することである。   An object of the present invention is to provide a light emitting element and a light emitting device that greatly improve the current density seen at the PN junction, maximize the heat sink effect (heat dissipation effect), increase the amount of light emission, and improve the light emission efficiency. That is.

上述した課題を解決するため、本発明に係る発光素子は、P型半導体層及びN型半導体層を積層したPN半導体積層構造と、前記P型半導体層のP側電極と、前記N型半導体層のN側電極とを含む。前記PN半導体積層構造は、前記P型半導体層及び前記N型半導体層が重なる部分と、重ならない部分とを有する。前記重ならない部分は、前記重なる部分の側方に配置され、配置方向で見た幅が、前記重なる部分よりも狭幅である。   In order to solve the above-described problems, a light-emitting element according to the present invention includes a PN semiconductor stacked structure in which a P-type semiconductor layer and an N-type semiconductor layer are stacked, a P-side electrode of the P-type semiconductor layer, and the N-type semiconductor layer. N-side electrode. The PN semiconductor multilayer structure has a portion where the P-type semiconductor layer and the N-type semiconductor layer overlap and a portion where they do not overlap. The non-overlapping portion is disposed on the side of the overlapping portion, and the width viewed in the arrangement direction is narrower than the overlapping portion.

前記P側電極及びN側電極は、光出射面とは反対側の面にあり、前記P側電極及び前記N側電極のうちの一方の電極(例えば、P側電極)は、前記P型半導体層及び前記N型半導体層のうちの一方(例えば、P型半導体層)の表面であって、重なる部分に設けられている。他方の電極(例えば、N側電極)は、前記重ならない部分において、他方の半導体層(例えば、N型半導体層)の上に設けられ、前記一方の半導体層(例えば、P型半導体層)及び前記一方の電極(例えば、P側電極)から、絶縁ギャップにより電気絶縁されている。上記構造において、前記一方の電極(例えば、P側電極)は、前記絶縁ギャップを除き、前記一方の半導体層(例えば、P型半導体層)の前記表面のほぼ全面を覆っている。   The P-side electrode and the N-side electrode are on a surface opposite to the light emitting surface, and one of the P-side electrode and the N-side electrode (for example, the P-side electrode) is the P-type semiconductor. One of the layers and the N-type semiconductor layer (for example, a P-type semiconductor layer) is provided on the overlapping portion. The other electrode (for example, N-side electrode) is provided on the other semiconductor layer (for example, N-type semiconductor layer) in the non-overlapping portion, and the one semiconductor layer (for example, P-type semiconductor layer) and The one electrode (for example, P-side electrode) is electrically insulated by an insulation gap. In the above structure, the one electrode (for example, the P-side electrode) covers substantially the entire surface of the one semiconductor layer (for example, the P-type semiconductor layer) except for the insulating gap.

上述したように、P側電極及びN側電極は、光出射面とは反対側の面にあるから、P側電極及びN側電極によって光出射面積が縮小されることがない。このため、発光量が大きく、発光効率の高い発光素子を実現することができるとともに、貫通電極等に対して、フリップ・チップ方式によって接続することができ、ワイヤ・ボンディング構造を採る必要がない。   As described above, since the P-side electrode and the N-side electrode are on the surface opposite to the light emission surface, the light emission area is not reduced by the P-side electrode and the N-side electrode. Therefore, it is possible to realize a light-emitting element having a large light emission amount and high light emission efficiency, and can be connected to a through electrode or the like by a flip-chip method, and there is no need to adopt a wire bonding structure.

半導体積層構造は、P型半導体層及び前N型半導体層が重なる部分と、重ならない部分とを有し、重ならない部分は、重なる部分の側方に配置され、配置方向で見た幅が、重なる部分よりも狭幅であるから、重なる部分で見た発光面積が最大化され、発光量が大きく、発光効率の高い発光素子を実現することができる。   The semiconductor stacked structure has a portion where the P-type semiconductor layer and the previous N-type semiconductor layer overlap and a portion that does not overlap, and the portion that does not overlap is arranged on the side of the overlapping portion, and the width seen in the arrangement direction is Since the width is narrower than the overlapping portion, the light emitting area viewed at the overlapping portion is maximized, the light emission amount is large, and a light emitting element with high light emission efficiency can be realized.

P側電極及びN側電極のうちの一方の電極(例えば、P側電極)は、P型半導体層及びN型半導体層のうちの他方(例えば、P型半導体層)の表面に設けられており、他方の電極(例えば、N側電極)は、他方の半導体層(例えば、P型半導体層)から絶縁ギャップによって電気絶縁して一方の半導体層(例えば、N型半導体層)に設けられている。したがって、N側電極及びP側電極により、半導体積層構造に電流を供給し、発光動作をさせることができる。   One of the P-side electrode and the N-side electrode (for example, the P-side electrode) is provided on the surface of the other of the P-type semiconductor layer and the N-type semiconductor layer (for example, the P-type semiconductor layer). The other electrode (for example, the N-side electrode) is electrically insulated from the other semiconductor layer (for example, the P-type semiconductor layer) by an insulating gap and is provided in one semiconductor layer (for example, the N-type semiconductor layer). . Therefore, the N-side electrode and the P-side electrode can supply a current to the semiconductor multilayer structure to perform a light emitting operation.

更に重要な構成及びその作用効果として、一方の電極(例えば、P側電極)は、絶縁ギャップを除き、一方の半導体層(例えば、P型半導体層)の表面のほぼ全面を覆っているから、P側電極からP型半導体層に対する電流供給面積が、重なり面積と同程度の面積に拡大される。このため、P型半導体層、活性層及びN型半導体層の接合部で見た電流密度が大幅に向上し、発光量、発光効率も向上する。一方の電極(例えば、P側電極)の面積は、絶縁ギャップの幅を、電気絶縁に必要な寸法まで最小化することにより、最大化することができる。   More importantly, as one of the most important structures and operational effects, one electrode (for example, the P-side electrode) covers almost the entire surface of one semiconductor layer (for example, the P-type semiconductor layer) except for the insulating gap. The current supply area from the P-side electrode to the P-type semiconductor layer is expanded to the same area as the overlapping area. For this reason, the current density seen at the junction of the P-type semiconductor layer, the active layer, and the N-type semiconductor layer is greatly improved, and the light emission amount and the light emission efficiency are also improved. The area of one electrode (eg, the P-side electrode) can be maximized by minimizing the width of the insulating gap to the dimensions required for electrical insulation.

しかも、パッケージ側に備えられる貫通電極の横断面積を、最大化された一方の電極(例えば、P側電極)の面積まで拡大し、一方の電極(例えば、P側電極)及び貫通電極によるヒートシンク効果(放熱特性)を、最大化することができる。   Moreover, the cross-sectional area of the through electrode provided on the package side is expanded to the area of one maximized electrode (for example, the P-side electrode), and the heat sink effect by the one electrode (for example, the P-side electrode) and the through electrode (Heat dissipation characteristics) can be maximized.

他方の電極(例えば、N側電極)は、重ならない部分に設けられているから、重ならない部分を狭幅化して、重なる部分における発光面積の減少を回避しながら、電極面積を増大させることができる。即ち、他方の電極(例えば、N側電極)について、幅と直交する長さ方向に拡張することにより、電極面積を拡大することができる。このため、発光量の増大、発光効率向上を図るとともに、位置ずれによる接続不良を回避し得る。   Since the other electrode (for example, the N-side electrode) is provided in a non-overlapping portion, the non-overlapping portion can be narrowed to increase the electrode area while avoiding a decrease in the light emitting area in the overlapping portion. it can. That is, the electrode area can be expanded by extending the other electrode (for example, the N-side electrode) in the length direction orthogonal to the width. For this reason, it is possible to increase the light emission amount and improve the light emission efficiency, and to avoid poor connection due to misalignment.

本発明に係る発光デバイスは、上述した発光素子を、基板と組み合わせることによって構成される。基板は、一面に発光素子搭載領域を有し、前記発光素子搭載領域の面内に厚み方向に設けられた第1電極及び第2電極の端面が露出しており、前記第1電極は、端面の面積が前記一方の電極(例えば、P側電極)の電極面積に合わせられている。   The light emitting device according to the present invention is configured by combining the above light emitting element with a substrate. The substrate has a light emitting element mounting region on one surface, and end faces of the first electrode and the second electrode provided in a thickness direction are exposed in the surface of the light emitting element mounting region, and the first electrode Is matched to the electrode area of the one electrode (for example, the P-side electrode).

前記発光素子は、前記発光素子搭載領域に搭載され、前記一方の電極(例えば、P側電極)が前記第1電極に接合され、前記他方の電極(例えば、N側電極)が前記第2電極に接合されている。これにより、発光素子に対して、第1電極及び一方の電極(例えば、P側電極)による略同一断面積の電流供給路が形成されるから、発光素子の電流密度を向上させ、発光量、発光効率を向上させることができる。   The light emitting element is mounted in the light emitting element mounting region, the one electrode (for example, a P-side electrode) is joined to the first electrode, and the other electrode (for example, the N-side electrode) is connected to the second electrode. It is joined to. Thereby, since the current supply path having substantially the same cross-sectional area is formed by the first electrode and one electrode (for example, the P-side electrode) for the light emitting element, the current density of the light emitting element is improved, the light emission amount, Luminous efficiency can be improved.

以上述べたように、本発明によれば、PN接合部で見た電流密度を大幅に向上させるとともに、ヒートシンク効果(放熱効果)を最大化し、発光量の増大、発光効率向上を図った発光素子及び発光デバイスを提供することができる。   As described above, according to the present invention, the current density seen at the PN junction is greatly improved, the heat sink effect (heat dissipation effect) is maximized, the light emission amount is increased, and the light emission efficiency is improved. And a light-emitting device can be provided.

本発明の他の目的、構成及び利点については、添付図面を参照し、更に詳しく説明する。添付図面は、単に、例示に過ぎない。   Other objects, configurations and advantages of the present invention will be described in more detail with reference to the accompanying drawings. The accompanying drawings are merely examples.

本発明に係る発光素子の一形態を示す断面図である。It is sectional drawing which shows one form of the light emitting element which concerns on this invention. 図1に示した発光素子の底面図である。It is a bottom view of the light emitting element shown in FIG. 本発明に係る発光素子を組み込んだ発光デバイスを示す断面図である。It is sectional drawing which shows the light-emitting device incorporating the light emitting element which concerns on this invention. 図3の4−4線断面図である。FIG. 4 is a cross-sectional view taken along line 4-4 of FIG. 図3の5−5線断面図である。FIG. 5 is a sectional view taken along line 5-5 of FIG.

図1及び図2を参照すると、本発明に係る発光素子は、透明結晶層3の光出射面30とは反対側の他面に、P型半導体層11及びN型半導体層13を積層したPN半導体積層構造1を含んでいる。P型半導体層11及びN型半導体層13の間には、活性層12が設けられる。透明結晶層3は、代表的にはサファイアであり、その一面が光出射面30となる。サファイアで構成される透明結晶層3は、層厚が3μm〜200μmの範囲であることが好ましい。サファイアによって構成されている透明結晶層3の一面上には、バッファ層(図示しない)があり、PN半導体積層構造1は、バッファ層を介して、透明結晶層3の上に成長させてある。   Referring to FIGS. 1 and 2, the light emitting device according to the present invention is a PN in which a P-type semiconductor layer 11 and an N-type semiconductor layer 13 are stacked on the other surface of the transparent crystal layer 3 opposite to the light emitting surface 30. A semiconductor multilayer structure 1 is included. An active layer 12 is provided between the P-type semiconductor layer 11 and the N-type semiconductor layer 13. The transparent crystal layer 3 is typically sapphire, and one surface thereof becomes the light emitting surface 30. The transparent crystal layer 3 made of sapphire preferably has a layer thickness in the range of 3 μm to 200 μm. A buffer layer (not shown) is provided on one surface of the transparent crystal layer 3 made of sapphire, and the PN semiconductor multilayer structure 1 is grown on the transparent crystal layer 3 through the buffer layer.

PN半導体積層構造1は、発光素子において周知である。PN接合を持ち、代表的にはIII−V族化合物半導体が用いられる。もっとも、公知技術に限らず、これから提案されることのある化合物半導体を含むことができる。本発明において、発光素子は、赤色発光素子、緑色発光素子、青色発光素子、橙色発光素子の何れであってもよいし、白色発光素子であってもよい。それらの発光素子において、PN半導体積層構造1を構成する半導体材料及びその製造方法は既に知られている。   The PN semiconductor multilayer structure 1 is well known in a light emitting device. A PN junction is typically used and a III-V compound semiconductor is typically used. However, it is possible to include not only known techniques but also compound semiconductors that may be proposed in the future. In the present invention, the light emitting element may be any of a red light emitting element, a green light emitting element, a blue light emitting element, and an orange light emitting element, or a white light emitting element. In these light emitting devices, the semiconductor material constituting the PN semiconductor multilayer structure 1 and the manufacturing method thereof are already known.

本発明に係る発光素子は、P型半導体層11及びN型半導体層13を積層したPN半導体積層構造1と共に、P型半導体層11のP側電極5と、N型半導体層13のN側電極7とを含んでいる。P側電極5及びN側電極7は、例えば、パケージに設けられた貫通電極等の外部電極に対して、フリップ・チップ接続されるものであって、光出射面30とは反対側の面に設けられている。   The light emitting device according to the present invention includes a PN semiconductor multilayer structure 1 in which a P-type semiconductor layer 11 and an N-type semiconductor layer 13 are laminated, a P-side electrode 5 of the P-type semiconductor layer 11, and an N-side electrode of the N-type semiconductor layer 13. 7 and so on. For example, the P-side electrode 5 and the N-side electrode 7 are flip-chip connected to an external electrode such as a through electrode provided in the package, and are on the surface opposite to the light emitting surface 30. Is provided.

P側電極5及びN側電極7のうち、P側電極5は、光出射面30とは反対側に位置するP型半導体層11の表面に設けられた電極である。P側電極5は、絶縁ギャップG1を除き、P型半導体層11の表面のほぼ全面を覆っている。一方、N側電極7は、P型半導体層11及び活性層12を切欠いて形成した重ならない部分14を埋め、N型半導体層13に設けられている。重ならない部分14には、N側電極7を、P型半導体層11及び活性層12から電気絶縁する電気絶縁層9が充填されている。電気絶縁層9は、N側電極7及びP側電極5の間に露出するP型半導体層11の表面をも覆っており、N側電極7は、重ならない部分14において、P型半導体層11及びP側電極7から絶縁ギャップG1により電気絶縁されている。   Of the P-side electrode 5 and the N-side electrode 7, the P-side electrode 5 is an electrode provided on the surface of the P-type semiconductor layer 11 located on the side opposite to the light emitting surface 30. The P-side electrode 5 covers almost the entire surface of the P-type semiconductor layer 11 except for the insulating gap G1. On the other hand, the N-side electrode 7 fills a non-overlapping portion 14 formed by cutting out the P-type semiconductor layer 11 and the active layer 12 and is provided in the N-type semiconductor layer 13. The non-overlapping portion 14 is filled with an electrical insulating layer 9 that electrically insulates the N-side electrode 7 from the P-type semiconductor layer 11 and the active layer 12. The electrical insulating layer 9 also covers the surface of the P-type semiconductor layer 11 exposed between the N-side electrode 7 and the P-side electrode 5, and the N-side electrode 7 is located in the portion 14 where it does not overlap with the P-type semiconductor layer 11. The P-side electrode 7 is electrically insulated by an insulation gap G1.

P型半導体層11及びN型半導体層13は、重ならない部分14を除き、活性層12を介して互いに重なっており、重なる部分が発光領域となる。N側電極7及びP側電極5の配置方向で見たN側電極7の幅W1は、P側電極5の幅W2よりも著しく小さい。例えば、幅W2に対する幅W1の割合は、1〜40%の範囲に選定することができる。幅方向に直交する長さL1は、実施の形態では、N側電極7及びP側電極5ともに、ほぼ等しくなっている。   The P-type semiconductor layer 11 and the N-type semiconductor layer 13 are overlapped with each other through the active layer 12 except for a portion 14 that does not overlap, and the overlapping portion becomes a light emitting region. The width W1 of the N-side electrode 7 viewed in the arrangement direction of the N-side electrode 7 and the P-side electrode 5 is significantly smaller than the width W2 of the P-side electrode 5. For example, the ratio of the width W1 to the width W2 can be selected in the range of 1 to 40%. In the embodiment, the length L1 orthogonal to the width direction is substantially equal for both the N-side electrode 7 and the P-side electrode 5.

電気絶縁層9は、有機絶縁層又は無機絶縁層の何れであってもよい。また、N側電極7は、めっき法、溶融金属充填法、流動性導電材埋め込み法等によって形成することができる。重ならない部分14は、この実施の形態では、PN半導体積層構造1の全長にわたって形成されているが、長さ方向の中間部に設けてもよい。また、帯状に限らず、他の形状であってもよい。   The electrical insulating layer 9 may be either an organic insulating layer or an inorganic insulating layer. The N-side electrode 7 can be formed by a plating method, a molten metal filling method, a fluid conductive material embedding method, or the like. In this embodiment, the non-overlapping portion 14 is formed over the entire length of the PN semiconductor multilayer structure 1, but it may be provided in an intermediate portion in the length direction. Further, the shape is not limited to the belt shape, but may be other shapes.

上述したように、P側電極5及びN側電極7は、光出射面30とは反対側にあるから、P側電極5及びN側電極7によって光出射面積が縮小されることがない。このため、発光量が大きく、発光効率の高い発光素子を実現することができるとともに、貫通電極等に対して、フリップ・チップ方式によって接続することができる。信頼性、作業性の悪いワイヤ・ボンディング構造を採る必要がない。   As described above, since the P-side electrode 5 and the N-side electrode 7 are on the side opposite to the light emitting surface 30, the light emitting area is not reduced by the P-side electrode 5 and the N-side electrode 7. Therefore, it is possible to realize a light-emitting element having a large light emission amount and high light emission efficiency, and can be connected to a through electrode or the like by a flip-chip method. There is no need to adopt a wire bonding structure with poor reliability and workability.

PN半導体積層構造1は、P型半導体層11及びN型半導体層13が重なる部分と、重ならない部分14とを有し、重ならない部分14は、重なる部分の側方に配置されている。N側電極7の周囲は、電気絶縁層9によって埋められているが、電気絶縁層9の厚みは薄いので、重ならない部分14の幅をN側電極7の幅W1とみなせる。また、重なる部分の幅は、P側電極5の幅W2とみなせる。この状態では、重ならない部分14は、幅W2に対する幅W1の割合が1〜40%の範囲になる。したがって、発光面積が最大化され、発光量が大きく、発光効率の高い発光素子を実現することができる。   The PN semiconductor multilayer structure 1 has a portion where the P-type semiconductor layer 11 and the N-type semiconductor layer 13 overlap and a portion 14 that does not overlap, and the portion 14 that does not overlap is disposed on the side of the overlapping portion. Although the periphery of the N-side electrode 7 is filled with the electrical insulating layer 9, the thickness of the non-overlapping portion 14 can be regarded as the width W1 of the N-side electrode 7 because the thickness of the electrical insulating layer 9 is thin. Further, the width of the overlapping portion can be regarded as the width W2 of the P-side electrode 5. In this state, the non-overlapping portion 14 has a ratio of the width W1 to the width W2 in the range of 1 to 40%. Accordingly, it is possible to realize a light-emitting element having a maximum light emission area, a large light emission amount, and high light emission efficiency.

P側電極5及びN側電極7のうち、P側電極5は、P型半導体層11の表面に設けられており、N側電極7は、P型半導体層11から、電気絶縁層9によって電気絶縁してN型半導体層13に設けられている。したがって、N側電極7及びP側電極5により、PN半導体積層構造1に電流を供給し、発光動作をさせることができる。   Of the P-side electrode 5 and the N-side electrode 7, the P-side electrode 5 is provided on the surface of the P-type semiconductor layer 11, and the N-side electrode 7 is electrically connected to the P-type semiconductor layer 11 by the electrical insulating layer 9. Insulating is provided in the N-type semiconductor layer 13. Therefore, the N-side electrode 7 and the P-side electrode 5 can supply a current to the PN semiconductor multilayer structure 1 to perform a light emitting operation.

しかも、P側電極5は、絶縁ギャップG1及び不可避的に生じる絶縁部分を除き、P型半導体層11の表面のほぼ全面を覆っているから、P側電極5からP型半導体層11に対する電流供給面積が、重なり面積と同程度の面積に拡大される。このため、P型半導体層11、活性層12及びN型半導体層13の接合部で見た電流密度が大幅に向上し、発光量、発光効率も向上する。上記構造のもとでは、P側電極5の面積は、絶縁ギャップG1を、電気絶縁に必要な寸法まで最小化すること、及び、N側電極7の幅W1を最小化することにより、最大化することができる。   Moreover, since the P-side electrode 5 covers almost the entire surface of the P-type semiconductor layer 11 except for the insulating gap G1 and the inevitable insulating portion, current supply from the P-side electrode 5 to the P-type semiconductor layer 11 is achieved. The area is enlarged to the same area as the overlapping area. For this reason, the current density seen at the junction of the P-type semiconductor layer 11, the active layer 12, and the N-type semiconductor layer 13 is greatly improved, and the light emission amount and the light emission efficiency are also improved. Under the above structure, the area of the P-side electrode 5 is maximized by minimizing the insulating gap G1 to the size required for electrical insulation and minimizing the width W1 of the N-side electrode 7. can do.

N側電極7は、重ならない部分14に設けられているから、重ならない部分14を狭幅化して、重なる部分における発光面積の減少を回避しながら、電極面積を増大させることができる。即ち、N側電極7について、幅W1と直交する長さ方向L1に拡張することにより、電極面積を拡大することができる。このため、発光量の増大、発光効率向上を図りつつ、位置ずれによる接続不良を回避し得る。   Since the N-side electrode 7 is provided in the non-overlapping portion 14, the non-overlapping portion 14 can be narrowed to increase the electrode area while avoiding a decrease in the light emitting area in the overlapping portion. That is, the electrode area can be expanded by extending the N-side electrode 7 in the length direction L1 perpendicular to the width W1. For this reason, it is possible to avoid poor connection due to misalignment while increasing the light emission amount and improving the light emission efficiency.

図3〜図5を参照すると、本発明に係る発光素子を、基板に搭載した発光デバイスが図示されている。基板2は、一面に発光素子搭載領域S1を有し、発光素子搭載領域S1の面内に厚み方向に設けられた第1電極21及び第2電極22の端面が露出している。第1電極21は、端面の面積がP側電極5の電極面積と、ほぼ同じになっている。第2電極22も同様であって、端面の面積がN側電極7の電極面積と、ほぼ同じになっている。第1電極21及び第2電極22は、一般には、パッケージ基板等でなる基板1を、厚み方向に貫通するように設けられた貫通電極となる。第1及び第2電極21,22とN側電極7及びP側電極5は、Au−Sn系接合材、はんだペースト、Agペースト、Cu拡散ペースト等によって接合することができる。   3 to 5, a light emitting device in which a light emitting element according to the present invention is mounted on a substrate is illustrated. The substrate 2 has a light emitting element mounting region S1 on one surface, and end faces of the first electrode 21 and the second electrode 22 provided in the thickness direction in the surface of the light emitting element mounting region S1 are exposed. The area of the end surface of the first electrode 21 is substantially the same as the electrode area of the P-side electrode 5. The second electrode 22 is the same, and the area of the end face is substantially the same as the electrode area of the N-side electrode 7. The first electrode 21 and the second electrode 22 are generally through electrodes provided so as to penetrate the substrate 1 made of a package substrate or the like in the thickness direction. The first and second electrodes 21 and 22 and the N-side electrode 7 and the P-side electrode 5 can be joined by an Au—Sn bonding material, a solder paste, an Ag paste, a Cu diffusion paste, or the like.

発光素子100は、発光素子搭載領域S1に搭載され、P側電極5が第1電極21に接合され、N側電極7が第2電極22に接合されている。これにより、発光素子100に対して、第1電極21及びP側電極5による略同一断面積の電流供給路が形成されるから、発光素子100の電流密度を向上させ、発光量、発光効率を向上させることができる。   The light emitting element 100 is mounted in the light emitting element mounting region S <b> 1, the P-side electrode 5 is bonded to the first electrode 21, and the N-side electrode 7 is bonded to the second electrode 22. As a result, a current supply path having substantially the same cross-sectional area is formed by the first electrode 21 and the P-side electrode 5 with respect to the light emitting element 100, so that the current density of the light emitting element 100 is improved, and the light emission amount and the light emission efficiency are increased. Can be improved.

しかも、パッケージング基板等でなる基板2に貫通電極として備えられる第1電極21の横断面積を、最大化されたP側電極5の面積まで拡大し、P側電極5及び貫通電極たる第1電極21によるヒートシンク効果(放熱効果)を、最大化することができる。   In addition, the cross-sectional area of the first electrode 21 provided as a through electrode in the substrate 2 made of a packaging substrate or the like is expanded to the area of the maximized P side electrode 5, and the P side electrode 5 and the first electrode as the through electrode The heat sink effect (heat radiation effect) by 21 can be maximized.

実施の形態では、第2電極22も、端面の面積がN側電極7の電極面積と、ほぼ同じになっているから、N側電極7及び貫通電極たる第2電極22によるヒートシンク効果(放熱効果)も向上させることができる。また、N側電極7の第2電極22に対する位置ずれによる接続不良を生じることがない。   In the embodiment, since the end surface area of the second electrode 22 is substantially the same as the electrode area of the N-side electrode 7, the heat sink effect (heat dissipation effect) by the N-side electrode 7 and the second electrode 22 that is a through electrode is also provided. ) Can also be improved. Further, there is no connection failure due to the displacement of the N-side electrode 7 with respect to the second electrode 22.

本発明に係る発光素子及び発光デバイスは、単一の発光素子、複数の発光素子を例えばマトリクス状に配置した面発光装置、照明装置、液晶ディスプレイ用バックライト、信号灯等、広範な用途を持っている。   The light-emitting element and the light-emitting device according to the present invention have a wide range of uses such as a single light-emitting element, a surface light-emitting device in which a plurality of light-emitting elements are arranged in a matrix, a lighting device, a backlight for a liquid crystal display, a signal lamp, and the like. Yes.

以上、好ましい実施例を参照して本発明の内容を具体的に説明したが、本発明の基本的技術思想及び教示に基づいて、当業者であれば、種種の変形態様を採り得ることは自明である。   Although the contents of the present invention have been specifically described above with reference to the preferred embodiments, it is obvious that those skilled in the art can take various modifications based on the basic technical idea and teachings of the present invention. It is.

1 PN半導体積層構造
3 透明結晶層
5 N側電極
7 P側電極
DESCRIPTION OF SYMBOLS 1 PN semiconductor laminated structure 3 Transparent crystal layer 5 N side electrode 7 P side electrode

Claims (4)

P型半導体層及びN型半導体層を積層したPN半導体積層構造と、前記P型半導体層のP側電極と、前記N型半導体層のN側電極とを含む発光素子であって、
前記PN半導体積層構造は、前記P型半導体層及び前記N型半導体層が重なる部分と、重ならない部分とを有し、
前記重ならない部分は、前記重なる部分の側方に配置され、配置方向で見た幅が、前記重なる部分よりも狭幅であり、
前記P側電極及びN側電極は、光出射面とは反対側の面にあり、
前記P側電極及び前記N側電極のうちの一方の電極は、前記P型半導体層及び前記N型半導体層のうちの一方の表面であって、前記重なる部分に設けられており、
他方の電極は、前記重ならない部分において、他方の半導体層の上に設けられ、前記一方の半導体層及び前記一方の電極から絶縁ギャップにより電気絶縁されており、
前記一方の電極は、前記絶縁ギャップを除き、前記一方の半導体層の前記表面のほぼ全面を覆っている、
発光素子。
A light-emitting device including a PN semiconductor stacked structure in which a P-type semiconductor layer and an N-type semiconductor layer are stacked, a P-side electrode of the P-type semiconductor layer, and an N-side electrode of the N-type semiconductor layer,
The PN semiconductor multilayer structure has a portion where the P-type semiconductor layer and the N-type semiconductor layer overlap, and a portion where they do not overlap,
The non-overlapping part is disposed on the side of the overlapping part, and the width seen in the arrangement direction is narrower than the overlapping part,
The P-side electrode and the N-side electrode are on the surface opposite to the light emitting surface,
One of the P-side electrode and the N-side electrode is provided on the overlapping portion on one surface of the P-type semiconductor layer and the N-type semiconductor layer,
The other electrode is provided on the other semiconductor layer in the non-overlapping portion, and is electrically insulated from the one semiconductor layer and the one electrode by an insulating gap,
The one electrode covers almost the entire surface of the one semiconductor layer except the insulating gap,
Light emitting element.
請求項1に記載された発光素子であって、前記配置方向で見て、前記重ならない部分の幅は、前記重なる部分の幅の1〜40%の範囲にある。   2. The light emitting device according to claim 1, wherein a width of the non-overlapping portion is in a range of 1 to 40% of a width of the overlapping portion when viewed in the arrangement direction. 請求項1又は2に記載された発光素子であって、前記光出射面は、3μm〜200μmの層厚を有するサファイアによって構成されている。   It is a light emitting element described in Claim 1 or 2, Comprising: The said light-projection surface is comprised with the sapphire which has a layer thickness of 3 micrometers-200 micrometers. 発光素子と、基板とを含む発光デバイスであって、
前記発光素子は、請求項1乃至3の何れかに記載されたものであり、
前記基板は、一面に発光素子搭載領域を有し、前記発光素子搭載領域の面内に厚み方向に設けられた第1電極及び第2電極の端面が露出しており、前記第1電極は、端面の面積が前記一方の電極の電極面積に合わせられており、
前記発光素子は、前記発光素子搭載領域に搭載され、前記一方の電極が前記第1電極に接合され、前記他方の電極が前記第2電極に接合されている、
発光デバイス。
A light emitting device including a light emitting element and a substrate,
The light emitting element is described in any one of claims 1 to 3,
The substrate has a light emitting element mounting region on one surface, and end surfaces of the first electrode and the second electrode provided in the thickness direction in the surface of the light emitting element mounting region are exposed, and the first electrode is The area of the end face is matched to the electrode area of the one electrode,
The light emitting element is mounted on the light emitting element mounting region, the one electrode is bonded to the first electrode, and the other electrode is bonded to the second electrode.
Light emitting device.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10209494A (en) * 1997-01-24 1998-08-07 Rohm Co Ltd Semiconductor light emitting device
JP2004006468A (en) * 2002-05-31 2004-01-08 Matsushita Electric Ind Co Ltd Semiconductor light emitting device
JP2004063732A (en) * 2002-07-29 2004-02-26 Matsushita Electric Ind Co Ltd Light-emitting element
JP2008004689A (en) 2006-06-21 2008-01-10 Noda Screen:Kk Light-emitting diode package
JP2008098442A (en) * 2006-10-12 2008-04-24 Sony Corp Method of forming wiring of light-emitting element, light-emitting element mounting board, display, backlight, illuminator and electronic instrument
JP2009049342A (en) 2007-08-23 2009-03-05 Toyoda Gosei Co Ltd Light emitting device
JP2011181699A (en) 2010-03-01 2011-09-15 Seiko Instruments Inc Light emitting device
JP4778107B1 (en) * 2010-10-19 2011-09-21 有限会社ナプラ Light emitting device and manufacturing method thereof

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10209494A (en) * 1997-01-24 1998-08-07 Rohm Co Ltd Semiconductor light emitting device
JP2004006468A (en) * 2002-05-31 2004-01-08 Matsushita Electric Ind Co Ltd Semiconductor light emitting device
JP2004063732A (en) * 2002-07-29 2004-02-26 Matsushita Electric Ind Co Ltd Light-emitting element
JP2008004689A (en) 2006-06-21 2008-01-10 Noda Screen:Kk Light-emitting diode package
JP2008098442A (en) * 2006-10-12 2008-04-24 Sony Corp Method of forming wiring of light-emitting element, light-emitting element mounting board, display, backlight, illuminator and electronic instrument
JP2009049342A (en) 2007-08-23 2009-03-05 Toyoda Gosei Co Ltd Light emitting device
JP2011181699A (en) 2010-03-01 2011-09-15 Seiko Instruments Inc Light emitting device
JP4778107B1 (en) * 2010-10-19 2011-09-21 有限会社ナプラ Light emitting device and manufacturing method thereof

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