JP2013120787A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which can easily form high-aspect holes in an insulation film.SOLUTION: A semiconductor device manufacturing method comprises: a step of forming a first pattern 6 extending in a first direction by processing an interlayer insulation film 6a formed on a semiconductor substrate and forming a first sidewall film 21 composed of an LP carbon film on both sidewalls of the first pattern; a step of filling spaces formed among the first pattern by forming a first buried film 22 on an entire area; a step of forming a plurality of first holes 27 arranged at predetermined intervals in the first direction on the first sidewall film extending in the first direction by performing processing of forming a pattern in a second direction orthogonal to the first direction thereby to divide the first sidewall film with respect to the first direction; a step of filling the first holes by a second buried film 28 thereby to divide the first sidewall film with respect to the first direction; and a step of removing the remaining first sidewall film to form a plurality of second holes 11.

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  In the manufacture of semiconductor devices, various structures are created on a semiconductor substrate. As the degree of integration of semiconductor devices increases, the size of these structures decreases in the direction parallel to the substrate surface. Also, the size tends to increase in the vertical direction. The ratio of these dimensions is called the aspect ratio and means the ratio of the vertical dimension to the parallel dimension, that is, the aspect ratio. In general, as the aspect ratio increases, the difficulty of manufacturing a semiconductor device has increased dramatically. A good example is a capacitor used in a DRAM (Dynamic Random Access Memory).

  As the density of the DRAM increases, the area allowed for the capacitor, which is the main component of the DRAM, is inevitably reduced, making it difficult to secure the required capacity (Patent Document). 1).

JP 2006-120732 A JP 2008-10866 A

  In addition, as DRAM (Dynamic Random Access Memory) density increases, holes with high aspect ratios (hereinafter referred to as high aspect ratios) are used to form capacitors in insulating films such as silicon oxide films that make up the elements. (Referred to as Patent Document 2). Here, when the dry etching method is used for forming the high aspect hole, the etching gas collides with the side wall of the hole and the sputtering effect at the bottom of the hole is attenuated, so that the processing becomes more difficult as the aspect ratio increases.

  An object of the present invention is to provide a method of manufacturing a semiconductor device in which a high aspect hole can be easily formed in an insulating film.

  In the present invention, a carbon film having a high aspect ratio (hereinafter referred to as an LP carbon film) is formed in the insulating film, and finally, the LP carbon film is removed to form a high aspect hole in the insulating film. This is a method of manufacturing a semiconductor device that can be easily formed.

A method of manufacturing a semiconductor device according to the first aspect of the present invention includes:
An interlayer insulating film formed on the semiconductor substrate is processed by a first pattern forming process to form a first pattern extending in a first direction, and an LP carbon film is formed on both side walls of the first pattern. Forming a first sidewall film comprising:
Forming a first buried film on the entire surface and burying a space formed between the first patterns;
The first sidewall film extending in the first direction using a second pattern forming step of forming a pattern in a second direction that is a direction perpendicular to the first direction, Forming a plurality of first holes arranged at predetermined intervals in a first direction;
Dividing the first sidewall film with respect to the first direction by burying the first hole with a second buried film;
Removing the remaining first sidewall film to form a plurality of second holes.

A method of manufacturing a semiconductor device according to the second aspect of the present invention includes:
An interlayer insulating film formed on the semiconductor substrate is processed by a first pattern forming process to form a first pattern extending in a first direction, and an LP carbon film is formed on both side walls of the first pattern. Forming a first sidewall film comprising:
Forming a first buried film on the entire surface and burying a space formed between the first patterns;
The first sidewall film extending in the first direction using a second pattern forming step of forming a pattern in a second direction that is a direction perpendicular to the first direction, Dividing the first sidewall film with respect to the first direction by forming a plurality of high aspect holes arranged at predetermined intervals in the first direction;
Burying the high aspect hole with a conductive film to form a columnar lower electrode;
Removing the interlayer insulating film located around the lower electrode, the first buried film, and the remaining first sidewall film to expose the outer surface of the lower electrode.

A method for manufacturing a semiconductor device according to a third aspect of the present invention includes:
An interlayer insulating film formed on the semiconductor substrate is processed by a first pattern forming process to form a first pattern extending in a first direction, and an LP carbon film is formed on both side walls of the first pattern. Forming a first sidewall film comprising:
Forming a first buried film on the entire surface and burying a space formed between the first patterns;
The first sidewall film extending in the first direction using a second pattern forming step of forming a pattern in a second direction that is a direction perpendicular to the first direction, Dividing the first sidewall film with respect to the first direction by forming a plurality of high aspect holes arranged at predetermined intervals in the first direction;
Forming a conductive film on the inner wall of the high aspect hole as a lower electrode;
Removing the interlayer insulating film located around the lower electrode, the first buried film, and the remaining first sidewall film to expose the outer surface of the lower electrode.

  According to the method for manufacturing a semiconductor device of the present invention, a hole having a small opening width and a high aspect ratio can be formed, and a capacitor suitable for miniaturization is formed by using this as a cylinder hole for forming a capacitor. can do.

1 is a cross-sectional view showing a memory cell and peripheral circuit portions of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a plan view (FIG. A) and a cross-sectional view (FIG. B) for explaining the manufacturing process of the semiconductor device shown in FIG. FIG. 3 is a plan view (FIG. A) and a cross-sectional view (FIG. B) for explaining a manufacturing process subsequent to FIG. FIG. 4 is a plan view (FIG. A) and a sectional view (FIG. B) for explaining the manufacturing process subsequent to FIG. FIG. 5 is a plan view (FIG. A) and a cross-sectional view (FIG. B) for explaining a manufacturing process subsequent to FIG. FIG. 6 is a plan view (FIG. A) for explaining the manufacturing process subsequent to FIG. 5, a cross-sectional view between A-A 'in FIG. A (FIG. B), and a cross-sectional view between B-B' (FIG. C). FIG. 7 is a plan view (FIG. A) for explaining the manufacturing process subsequent to FIG. 6, a cross-sectional view between A-A ′ (FIG. B) and a cross-sectional view between B-B ′ (FIG. C) in FIG. FIG. 8 is a plan view (FIG. A) for explaining the manufacturing process subsequent to FIG. 7, a cross-sectional view between A-A 'in FIG. A (FIG. B), and a cross-sectional view between B-B' (FIG. C). FIG. 9 is a plan view (FIG. A) for explaining the manufacturing process subsequent to FIG. 8, a cross-sectional view between A-A 'in FIG. A (FIG. B), and a cross-sectional view between B-B' (FIG. C). FIG. 9 is a plan view (FIG. A) for explaining the manufacturing process, a cross-sectional view between AA ′ in FIG. A (FIG. B), a cross-sectional view between BB ′ (FIG. C), and CC. It is sectional drawing (FIG. D) between '. FIG. 10 is a plan view (FIG. A) for explaining the manufacturing process, a cross-sectional view between AA ′ in FIG. A (FIG. B), a cross-sectional view between BB ′ (FIG. C), and CC. It is sectional drawing (FIG. D) between '. FIG. 12 is a plan view (FIG. A) for explaining the manufacturing process subsequent to FIG. 11, a cross-sectional view between A-A 'in FIG. A (FIG. B), and a cross-sectional view between B-B' (FIG. C). It is sectional drawing which showed the semiconductor device concerning the 2nd Example of this invention about the memory cell and the peripheral circuit part. FIG. 14 is a plan view (FIG. A) and a sectional view (FIG. B) for explaining the manufacturing process of the semiconductor device shown in FIG. 13 from the middle thereof; FIG. 15 is a plan view (FIG. A) for explaining a manufacturing process subsequent to FIG. 14, a cross-sectional view between A-A ′ in FIG. A (FIG. B), and a cross-sectional view between B-B ′ (FIG. C). FIG. 15 is a plan view for explaining the manufacturing process (FIG. A), a cross-sectional view between AA ′ in FIG. A (FIG. B), a cross-sectional view between BB ′ (FIG. C), and CC. It is sectional drawing (FIG. D) between '. FIG. 16 is a plan view for explaining the manufacturing process (FIG. A), a sectional view taken along line AA 'in FIG. A (FIG. B), a sectional view taken along line BB' (FIG. C), and CC. It is sectional drawing (FIG. D) between '. FIG. 17 is a plan view (FIG. A) for explaining the manufacturing process, a cross-sectional view between AA ′ in FIG. A (FIG. B), a cross-sectional view between BB ′ (FIG. C), and CC. It is sectional drawing (FIG. D) between '. FIG. 18 is a plan view (FIG. A), a cross-sectional view taken along the line AA ′ in FIG. A (FIG. B), a cross-sectional view taken along the line BB ′ (FIG. C), and CC. It is sectional drawing (FIG. D) between '. It is sectional drawing which showed the semiconductor device which concerns on the 3rd Example of this invention about the memory cell and the peripheral circuit part. FIG. 20 is a plan view for explaining the manufacturing process of the semiconductor device shown in FIG. 20 (FIG. A), a sectional view taken along line AA ′ in FIG. A (FIG. B), and a sectional view taken along line BB ′. (FIG. C) and a sectional view (FIG. D) between CC ′. FIG. 21 is a plan view for explaining the manufacturing process (FIG. A), a cross-sectional view between AA ′ in FIG. A (FIG. B), a cross-sectional view between BB ′ (FIG. C), and CC. It is sectional drawing (FIG. D) between '. Plan view (FIG. A) for explaining the manufacturing process subsequent to FIG. 22, sectional view (FIG. B) between AA 'in FIG. A, sectional view (FIG. C) between BB' and CC It is sectional drawing (FIG. D) between '. 23 is a plan view (FIG. A) for explaining the manufacturing process subsequent to FIG. 23, a sectional view taken along line AA ′ in FIG. A (FIG. B), a sectional view taken along line BB ′ (FIG. C), and CC. It is sectional drawing (FIG. D) between '. FIG. 24 is a plan view (FIG. A) for explaining the manufacturing process, a cross-sectional view between AA ′ in FIG. A (FIG. B), a cross-sectional view between BB ′ (FIG. C), and CC. It is sectional drawing (FIG. D) between '. FIG. 25 is a plan view (FIG. A) for explaining the manufacturing process, a cross-sectional view between AA ′ in FIG. A (FIG. B), a cross-sectional view between BB ′ (FIG. C), and CC. It is sectional drawing (FIG. D) between '.

[First embodiment]
A semiconductor device according to a first embodiment of the present invention will be described with reference to FIG.

  A semiconductor substrate 1 (hereinafter referred to as a silicon substrate 1) is provided with a memory cell region surrounded by a broken line and a peripheral circuit region for driving the memory cell.

  Although not shown, a pair of impurity diffusion regions is provided in the active region divided by the element isolation region on the surface of the silicon substrate 1 in the memory cell region. On the silicon substrate 1, a gate insulating film and a gate electrode are further laminated to form a transistor. The transistor is covered with an interlayer insulating film 2 formed on the silicon substrate 1. A bit line is provided on the interlayer insulating film 2 and connected to one of the pair of impurity diffusion regions. The upper surface of the interlayer insulating film 2 is covered with the interlayer insulating film 3 so as to cover the bit lines. Contact plug 4 penetrating interlayer insulating film 3 and interlayer insulating film 2 is connected to the other of the pair of impurity diffusion regions.

  On the upper surface of the interlayer insulating film 3, a stopper film 5 and an interlayer insulating film 6a are laminated. A lower electrode 7 is provided in the stopper film 5 and the interlayer insulating film 6a in the memory cell region, and is connected to the contact plug 4 (4a). The surface of the lower electrode 7 is covered with a capacitive insulating film 8 and an upper electrode 9 to constitute a capacitor 10. The lower electrode 7 having a U-shaped cross section has an outer wall surface covered with an interlayer insulating film 6 a, whereas an inner surface and an upper end surface are covered with an upper electrode 9 through a capacitive insulating film 8. . A plate electrode (not shown) may be further provided on the upper electrode 9. The recess formed inside the lower electrode 7 may be embedded only by the upper electrode 9 with the capacitive insulating film 8 interposed therebetween. However, the recess of the lower electrode 7 provided in the high aspect hole 11 It is difficult to bury it alone. Therefore, after providing the upper electrode 9 that covers the inner surface of the recess, the remaining space may be embedded with a filling film (not shown), and a plate electrode may be provided on the filling film. An interlayer insulating film 12 is formed so as to cover the upper electrode 9, and a contact plug 13 penetrating the interlayer insulating film 12 is connected to the upper electrode 9.

  Similarly, on the silicon substrate 1 in the peripheral circuit region, a contact plug 15 connected to the contact plug 4 (4b) is provided in the high aspect hole 14 penetrating the stopper film 5, the interlayer insulating film 6a, and the interlayer insulating film 12. It has been. A wiring 16 is provided on the interlayer insulating film 12. The wiring 16 in the memory cell region is connected to the contact plug 13, and the wiring 16 in the peripheral circuit region is connected to the contact plug 15. The wiring 16 is covered with an interlayer insulating film 17.

  As described above, the capacitor 10 including the lower electrode 7, the capacitor insulating film 8, and the upper electrode 9 is connected to a transistor (not shown) in the memory cell region of the DRAM 100. Charges are taken in and out of the capacitor 10 by turning on / off a transistor (not shown). In the DRAM 100, since the charge amount stored in the capacitor 10 is stored information, it is necessary to store a charge amount of a certain value or more for stable operation. In such a memory cell, the size of the capacitor is reduced along with the miniaturization. Therefore, in order to secure a charge amount of a certain value or more, the capacitor 10 is formed in a high aspect hole with a small occupation area, and the miniaturization is performed. And ensuring the amount of charge.

  In the DRAM configured as described above, the high aspect hole manufacturing process is applied to the DRAM 100 according to the first embodiment. Below, the manufacturing method of the high aspect hole 11 is demonstrated, referring FIGS. 2-12. In the following description, the drawings of the memory cell region surrounded by the broken line portion of FIG. 1 are used, in each of which (a) is a plan view, (b) is a cross-sectional view between AA ′ in the plan view, (C) is sectional drawing between BB 'in a top view, (d) is sectional drawing between CC' in a top view.

  In FIG. 2, a MOS transistor (not shown) having a gate insulating film, a gate electrode, and a pair of impurity diffusion layers serving as a source / drain is formed on the surface of the silicon substrate 1 by a known method. The MOS transistor functions as a switching transistor of the memory cell. Next, an interlayer insulating film 2 is formed so as to cover the MOS transistor. Subsequently, a first contact plug (not shown) that penetrates the interlayer insulating film 2 and is connected to the impurity diffusion layer is formed. Bit lines (not shown) are formed on the top surfaces of some of the first contact plugs. Next, an interlayer insulating film 3 is formed so as to cover the bit line. Further, a memory cell contact plug 4 (4a) and a peripheral circuit contact plug 4 (4b) (see FIG. 1) are formed through the interlayer insulating film 3 and connected to the upper surface of the first contact plug.

Next, a stopper film 5 which is a silicon nitride film having a thickness of 50 nm is formed by plasma CVD (Chemical Vapor Deposition) so as to cover the interlayer insulating film 3 and the contact plug 4. Subsequently, an interlayer insulating film 6a that is a silicon oxide film having a thickness of 2 μm was formed by plasma CVD so as to cover the upper surface of the stopper film 5. Next, a mask film 18 which is an amorphous carbon film {Amorphous Carbon: hereinafter referred to as an AC film} having a thickness of 100 nm is formed by plasma CVD so as to cover the upper surface of the interlayer insulating film 6a. did. The deposition conditions for the mask film 18 were propylene (C ₃ H ₆ ) as a source gas, a flow rate of 600 sccm (Standard Cubic Centimeter per Minute), a high frequency power of 300 W, a heating temperature of 300 ° C., and a pressure of 5 Torr. Here, 400 sccm of helium (He) was supplied as a carrier gas.

  Next, referring to FIG. 3, a first pattern formation step was performed by photolithography and dry etching. First, a mask pattern 18 ′ extending in the Y direction and having a width X 2 was formed on the mask film 18. As a result, a part of the upper surface of the interlayer insulating film 6a is exposed. Next, the interlayer insulating film 6a whose upper surface is exposed is dry-etched using the mask pattern 18 'as a mask. Thereby, the first pattern 6 extending in the Y direction in a straight line is formed. The width X2 is, for example, 50 nm. At this time, a groove 19 having a width X1 of, for example, 150 nm is formed between the adjacent first patterns 6 so as to extend in the Y direction, and a partial upper surface of the stopper film 5 is exposed.

The dry etching conditions for the mask film 18 made of an AC film are parallel plate type plasma etching, using nitrogen (N ₂ ) and hydrogen (H ₂ ) as process gases, and flow rates of 100 sccm (N ₂ ) and 300 sccm (H ₂ ) The high frequency power was 400 W, the stage temperature was 20 ° C., and the pressure was 30 mTorr.

The dry etching conditions for the interlayer insulating film 6a are perfluorocyclobutane (C ₄ F ₈ ), argon (Ar), oxygen (O ₂ ), and tetrafluoromethane (CF ₄ ) using a two-frequency parallel plate plasma etching method. Is a process gas, the flow rates are 10 sccm (C ₄ F ₈ ), 300 sccm (Ar), 25 sccm (O ₂ ), and 15 sccm (CF ₄ ), the upper high-frequency power is 1500 W, the lower high-frequency power is 3500 W, the stage temperature is 40 ° C., The pressure was 40 mTorr and the treatment was performed for 350 seconds. At this time, the contact plug 4 (4a) is disposed below the stopper film 5 exposed on the bottom surface of the groove 19. The contact plugs 4 (4a) are respectively disposed at target positions on both sides in the X direction with the one first pattern 6 as the center.

Next, referring to FIG. 4, mask pattern 18 'used as a mask was removed by an ashing method. For ashing the mask pattern 18 ', oxygen (O ₂ ) and nitrogen (N ₂ ) are used as process gases, the flow rates are 3000 sccm (O ₂ ) and 300 sccm (N ₂ ), the stage temperature is 250 ° C., the pressure is 800 mTorr, and the high frequency Processing was performed for 10 seconds using isotropic etching conditions with a power of 2000 W.

Next, a carbon film having a thickness of 50 nm (hereinafter referred to as an LP carbon film) was formed by low pressure (LP) CVD so as to cover the first pattern 6 extending in the Y direction. The LP carbon film is formed by using ethylene (C ₂ H ₄ ) and propylene (C ₃ H ₆ ) as process gases, flow rates of 1000 sccm (C ₂ H ₄ ) and 2000 sccm (C ₃ H ₆ ), and a heating temperature. The pressure was 550 ° C. and the pressure was 120 Torr. As described above, the LP carbon film formed using thermal reaction without using plasma can be formed conformally. Although the mask film 18 used in FIG. 2 is the same amorphous carbon film, it cannot be formed conformally under the film formation conditions of the mask film 18 formed by using the plasma CVD method. By forming the LP carbon film, a new groove 20 having a width X3 of 50 nm is formed in the groove 19 so as to extend in the Y direction.

Next, by etching back the LP carbon film, first sidewall films 21 were formed on both side surfaces of the first pattern 6 extending in the Y direction. The LP carbon film is etched back using a parallel plate plasma etching apparatus, using nitrogen (N ₂ ) and hydrogen (H ₂ ) as process gases, flow rates of 100 sccm (N ₂ ) and 300 sccm (H ₂ ), and high frequency. The power was 400 W, the stage temperature was 20 ° C., and the pressure was 30 mTorr. At this time, the groove 20 remains without changing the width X 3, and a part of the stopper film 5 is exposed at the bottom of the groove 20. At this stage, the contact plug 4 a is positioned directly below the first sidewall film 21.

Next, referring also to FIG. 5, a first buried film 22, which is a silicon oxide film having a thickness of, for example, 100 nm, is formed by an ALD (Atomic Layer Deposition) method so as to fill the groove 20. In the ALD method, a silicon substrate kept at a predetermined temperature is
(1) Adsorption of source gas on the entire surface of the silicon substrate by supplying source gas,
(2) Discharge of surplus source gas by vacuum purge,
(3) Oxidation reaction of source gas by supplying oxidizing gas,
(4) Excess oxidizing gas discharged by vacuum purge,
The film formation is performed by repeating the one cycle process consisting of a plurality of cycles. Here, as an example of the film formation conditions of the first buried film 22 in one cycle, 300 sccm of trisdimethylaminosilane {TDMAS: SiH [N (CH ₃ ) ₂ ] ₃ } is used as a source gas in an atmosphere at 550 ° C. After supplying for 5 seconds and evacuating, ozone (O ₃ ) as an oxidizing gas is supplied at 1000 sccm for 5 seconds and evacuating. Since the ALD method is an excellent method for controlling the film thickness, the groove 20 can be easily embedded by forming the first embedded film 22 having a small film thickness in several steps.

  After planarizing the upper surface of the first embedded film 22 by a CMP (Chemical Mechanical Polishing) method, a mask film 23 which is an AC film having a thickness of 100 nm was formed by a plasma CVD method. The conditions for forming the mask film 23 are the same as the conditions for forming the mask film 18 in FIG.

  Next, referring to FIG. 6, a second pattern forming step was performed by photolithography and dry etching. In the second pattern formation step, sidewall double patterning (SWDPT) is used in which sidewalls are formed on both side walls of the core pattern to form twice as many masks.

  First, the mask film 23 was etched by a dry etching method to form a core pattern (second pattern) 23 ′ extending in the X direction and having a width Y 2. The X direction is a direction perpendicular to the Y direction. As a result, a part of the upper surface of the first buried film 22 is exposed. The pattern width Y2 of the core pattern 23 'is 50 nm, for example, and the pattern interval Y1 is 150 nm, for example. The dry etching conditions for the mask film 23 are the same as the dry etching conditions for the mask film 18 in FIG.

  Next, a coating film 25, which is a 50 nm thick silicon oxide film, was formed by ALD so as to cover the core pattern 23 'extending in the X direction. Here, the deposition conditions of the coating film 25 in one cycle of the ALD method are the same as the deposition conditions of the first buried film 22 in FIG. Since the ALD method is an excellent method for controlling the film thickness, the coating film 25 having a thin film thickness is formed in a plurality of times without completely filling the grooves between the core patterns 23 '. The surface of the core pattern 23 ′ can be conformally covered with the coating film 25. Accordingly, a new groove 24 having a width Y3 of, for example, 50 nm is formed to extend in the X direction between the adjacent core patterns 23 ′ covered with the coating film 25. .

Next, referring to FIG. 7, second sidewall films 25A were formed on both side surfaces of the core pattern 23 ′ by an etch back method. The etch-back condition of the coating film 25 uses a parallel plate type plasma etch method, with trifluoromethane (CHF ₃ ), argon (Ar), oxygen (O ₂ ), and tetrafluoromethane (CF ₄ ) as process gases, The treatment was performed at a flow rate of 100 sccm (CHF ₃ ), 500 sccm (Ar), 10 sccm (O ₂ ) and 200 sccm (CF ₄ ), a high frequency power of 600 W, a stage temperature of 40 ° C., and a pressure of 80 mTorr for 15 seconds. At this time, the groove 24 remains without changing the width Y 3, and a part of the first buried film 22 is exposed at the bottom of the groove 24.

  Next, referring to FIG. 8, the core pattern 23 'was removed by an ashing method. As a result, a new groove 24a (not shown, but from which the core pattern 23 'in FIG. 7c has been removed) is formed on the bottom surface where the first buried film 22 is exposed. The ashing conditions for the core pattern 23 'are the same as the ashing conditions for the mask pattern 18' in FIG. As a result, a new mask composed of the six second sidewall films 25A formed by SWDPT based on the three core patterns 23 'is formed. In other words, twice as many new mask patterns as the core pattern 23 'are formed.

Subsequently, the upper surface of the first sidewall film 21 is exposed from the first buried film 22 exposed on the bottom surfaces of the grooves 24 and 24a by a dry etching method using the second sidewall film 25A as a mask. The grooves 26 and 26a extending in the X direction were formed. As a result, a part of the upper surface of each of the first pattern 6 and the first buried film 22 composed of the first sidewall film 21 and the interlayer insulating film is alternately repeated on the bottom surfaces of the grooves 26 and 26a. Exposed. Further, since the grooves 26 and 26a and the first sidewall film 21 are orthogonal to each other in plan view, the first sidewall film 25A and the first sidewall film 25A that form the grooves 26 and 26a and extend in the X direction are formed. The embedded film 22 is in a state of covering the first sidewall film 21 extending in the Y direction at equal pitch intervals. The dry etching conditions for the first buried film 22 are trifluoromethane (CHF ₃ ), argon (Ar), oxygen (O ₂ ), and tetrafluoromethane (CF ₄ ) using a parallel plate plasma etch method. The flow rates were 100 sccm (CHF ₃ ), 500 sccm (Ar), 10 sccm (O ₂ ) and 200 sccm (CF ₄ ), the high frequency power was 600 W, the stage temperature was 40 ° C., and the pressure was 80 mTorr.

Next, referring to FIG. 9, the first sidewall film 21 whose upper surface is exposed is etched back by dry etching, and a rectangular first having a horizontal dimension X4 of 50 nm and a vertical dimension Y4 of 50 nm. Hole 27 was formed. For dry etching of the first sidewall film 21 made of LP carbon film, a dual frequency parallel plate type plasma etch method is used, using nitrogen (N ₂ ) and hydrogen (H ₂ ) as process gases and a flow rate of 100 sccm ( N ₂ ) and 300 sccm (H ₂ ), an anisotropic dry etching condition in which the upper high-frequency power is 700 W, the lower high-frequency power is 200 W, the stage temperature is 20 ° C., and the pressure is 30 mTorr.

  Under the above conditions, by applying a bias to the plasma generated by the application of the lower high-frequency power, that is, the application of the upper high-frequency power, the nitrogen ions and hydrogen ions existing in the plasma are accelerated and incident perpendicularly to the semiconductor substrate. Therefore, anisotropic dry etching can be realized. In this etching, a fluorine-containing gas necessary for dry etching the silicon oxide film or the silicon nitride film is not used. Furthermore, the silicon oxide film and the silicon nitride film are not dry etched by nitrogen plasma or hydrogen plasma. Therefore, in this anisotropic dry etching process, the first pattern 6 located in contact with the first sidewall film 21 made of the LP carbon film, the first buried film 22 and the stopper film 5 located on the bottom surface. Only the first sidewall film 21 can be removed with high selectivity without etching. This is the greatest advantage in using the LP carbon film as a sacrificial film for hole formation.

  Thereby, a part of the stopper film 5 is exposed on the bottom surface of the first hole 27. Further, the first buried film 22 and the first pattern 6 are exposed on the side surface of the first hole 27 facing the X direction, and the side surface facing the Y direction is divided by the first hole 27. The first sidewall film 21 is exposed. Here, the horizontal dimension X4 of the first hole 27 depends on the film thickness of the first sidewall film 21, and the vertical dimension Y4 depends on the width Y2 of the core pattern 23 ′ and the width Y3 of the groove 24. doing. In order to make the vertical dimension Y4 of all the first holes 27 the same and arrange them at equal pitch intervals, the interval Y1 of the core pattern 23 ′ is set to be three times the width Y2 of the core pattern 23 ′, Furthermore, the film thickness of the coating film 25 (second sidewall film 25A) may be set to the same value as the width Y2 of the core pattern 23 ′.

  Next, referring to FIG. 10, a second buried film 28 which is a silicon oxide film having a thickness of 100 nm is formed by ALD so as to fill the first hole 27. As a result, the first sidewall film 21 divided by the first hole 27 in the Y direction is divided by the second buried film 28. Here, the deposition conditions of the second buried film 28 in one cycle of the ALD method are the same as the deposition conditions of the first buried film 22 in FIG. By the ALD method, the first hole 27 having a high aspect ratio can be easily embedded. Next, the upper surface of the first pattern 6 is exposed by CMP so that the upper surfaces of the first sidewall film 21 and the first pattern 6 located under the second sidewall film 25A are exposed. The second sidewall film 25A, the first buried film 22 and the second buried film 28 formed above are removed. Thus, the top surfaces of the first sidewall film 21, the first pattern 6, the first buried film 22 and the second buried film 28 whose upper surfaces are exposed in the plan view of FIG. 10 (b), (c), and (d), which are flush with each other.

  Next, referring to FIG. 11, the first sidewall film 21 whose upper surface is exposed is removed by an ashing method, and a second high-aspect second having a horizontal dimension X5 of 50 nm and a vertical dimension Y5 of 50 nm. Hole 11 was formed. The ashing conditions for the first sidewall film 21 are the same as the ashing conditions for the mask pattern 18 'in FIG. At this stage, only the first pattern 6 made of a silicon oxide film, the first buried film 22, the second buried film 28, and the stopper film 5 made of a silicon nitride film are provided around the first sidewall film 21. Since it does not exist, an ashing method that is isotropic etching can be used. Instead of the ashing method, the dry etching method described in FIG. 9 can also be used.

  Thereby, a part of the stopper film 5 is exposed on the bottom surface of the second hole 11. Here, the horizontal dimension X5 of the second hole 11 depends on the film thickness of the first sidewall film 21, and the vertical dimension Y5 depends on the film thickness of the second sidewall film 25A. . Further, the X-direction interval X6 of the second holes 11 depends on the width X2 of the mask pattern 18 ′ (the first pattern 6 below) and the width X3 of the groove 20, and the Y-direction interval Y6 is This depends on the width Y2 of the core pattern 23 ′ and the width Y3 of the groove 24. In order to make all the second holes 11 have the same X-direction interval X6 and at equal pitch intervals, the interval X1 of the mask pattern 18 ′ (first pattern 6) is set to the width X2 of the mask pattern 18 ′. The film thickness of the first sidewall film 21 may be set to the same value as the width X2 of the mask pattern 18 ′.

Next, the stopper film 5 exposed on the bottom surface of the second hole 11 was removed by a dry etching method to expose at least a part of the contact plug 4a. The dry etching conditions for the stopper film 5 are a dual frequency parallel plate type plasma etch method using trifluoromethane (CHF ₃ ), argon (Ar), oxygen (O ₂ ), and tetrafluoromethane (CF ₄ ) as process gases. The flow rate is 100 sccm (CHF ₃ ), 500 sccm (Ar), 10 sccm (O ₂ ), and 200 sccm (CF ₄ ), the upper high-frequency power is 2000 W, the lower high-frequency power is 800 W, the stage temperature is 20 ° C., and the pressure is 80 mTorr. Processed for seconds.

  Next, referring to FIG. 12, titanium nitride (TiN) having a thickness of 10 nm is formed by CVD so as to cover the upper surface of first pattern 6 and first buried film 22 and the inner surface of second hole 11. A conductive film was formed. Further, the lower electrode 7 connected to the contact plug 4a is formed on the inner surface of the second hole 11 by removing the conductive film on the upper surface of the first pattern 6 and the first buried film 22 by etch back. . The lower electrode 7 has a U-shaped cross section and the inner surface is exposed. The lower electrode 7 is not limited to titanium nitride, and a metal such as ruthenium (Ru) or platinum (Pt) can be used.

After the capacitive insulating film 8 is formed by the CVD method or the ALD method so as to cover the exposed surface of the lower electrode 7, the upper electrode 9 made of titanium nitride is formed by the CVD method so as to further cover the surface of the capacitive insulating film 8. did. Here, when the lower electrode 7 and the upper electrode 9 are opposed to each other via the capacitive insulating film 8, they function as a capacitor 10. As the capacitor insulating film 8, a high dielectric film such as zirconium oxide (ZrO ₂ ), aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), or a laminated film thereof can be used. The upper electrode 9 is formed by forming titanium nitride with a thickness of about 10 nm, then laminating a polysilicon film doped with impurities, filling the cavity between the adjacent lower electrodes 7, and further tungsten ( A metal film such as W) may be formed in a plate shape to form a laminated structure. Further, a metal film such as ruthenium (Ru) or platinum (Pt) can be used instead of titanium nitride. Here, also in the peripheral circuit region, the capacitive insulating film and the upper electrode are laminated on the upper surface of the interlayer insulating film 6a. However, after the upper electrode 9 is formed, the capacitor insulating film and the upper electrode in the peripheral circuit region that are no longer needed are removed by photolithography and dry etching.

  Thus, the capacitor 10 is completed in the memory cell region.

  Next, returning to FIG. 1, the upper electrode 9 was covered with the interlayer insulating film 12 which is a silicon oxide film by the CVD method, and then the interlayer insulating film 12 was planarized by the CMP method. Subsequently, a third hole penetrating the interlayer insulating film 12 was formed in the memory cell region by photolithography and dry etching. Here, simultaneously with the formation of the third hole, the high aspect hole 14 penetrating the interlayer insulating film 12, the interlayer insulating film 6a, and the stopper film 5 was also formed in the peripheral circuit region.

  Next, the third hole and the high aspect hole 14 are filled with tungsten (W) by sputtering, and then excess tungsten on the upper surface of the interlayer insulating film 12 is removed by CMP to remove contact plugs in the memory cell region. 13 and the contact plug 15 in the peripheral circuit region were formed simultaneously. Further, wiring 16 is formed on the upper surface of the interlayer insulating film 12 so as to be connected to the contact plugs 13 and 15, and the wiring 16 is covered with the interlayer insulating film 17.

  Through the above steps, the DRAM 100 shown in FIG. 1 is completed.

In the first embodiment of the present invention, the interlayer insulating film 6a formed on the silicon substrate 1 is processed by the first pattern forming process to extend in the first direction (Y direction). Forming a first sidewall film 21 made of an LP carbon film serving as a sacrificial film on both side walls of the first pattern 6;
Forming a first buried film 22 on the entire surface and burying a space formed between the first patterns 6;
A first sidewall film extending in the first direction by using a second pattern forming step of forming a pattern in a second direction (X direction) which is a direction perpendicular to the first direction; 21. A step of dividing the first sidewall film 21 with respect to the first direction by forming a plurality of first holes 27 arranged in the first direction at predetermined intervals and extending in the film thickness direction; ,
Burying the first hole 27 with a second buried film 28;
Removing the remaining first sidewall film 21 and forming a plurality of second holes 11 extending in the film thickness direction, and using a double patterning process.

  Accordingly, the second hole 11 having a small opening width and a high aspect ratio can be formed, and a capacitor suitable for miniaturization can be formed by using the second hole 11 as a cylinder hole for forming a capacitor.

[Second Embodiment]
A semiconductor device according to a second embodiment of the present invention will be described in detail with reference to FIGS. Since the film forming conditions and etching conditions of each member in the second embodiment are the same as those in the first embodiment, the description of the common contents is omitted, and only the differences from the first embodiment are described. Describe.

  FIG. 13 is a partial sectional view showing a DRAM 200 as a semiconductor device according to the second embodiment.

  In the first embodiment, the lower electrode of the capacitor is formed to cover the inner surface of the cylinder hole (the second hole 11 having a high aspect ratio). On the other hand, in the second embodiment, the lower electrode 7A has a column shape. The bottom surface portion of the lower electrode 7A is connected to the upper surface of the contact plug 4 (4a), and a part of the upper side surface is connected to the support film 29. The support film 29 plays a role of supporting each other so that adjacent lower electrodes 7A are not in contact with each other. The side and top surfaces of the lower electrode 7A, excluding the connection with the support film 29, are covered with the capacitive insulating film 8A and the upper electrode 9A, and the capacitor 10A is formed by the lower electrode 7A, the capacitive insulating film 8A, and the upper electrode 9A. It is configured.

  When the area occupied by the capacitor 10 (FIG. 1) of the DRAM 100 and the capacitor 10A of the DRAM 200 is the same, the contact portion between the lower electrode 7A and the capacitor insulating film 8A in the capacitor 10A is almost the entire outer wall of the lower electrode 7A. . This is because the contact area between the lower electrode 7A and the capacitor insulating film 8A is larger than the contact area in the capacitor 10 (FIG. 1) in which the contact portion between the lower electrode 7 and the capacitor insulating film 8 is only the inner wall of the lower electrode 7. Also means increasing. Therefore, the capacity of the capacitor 10 </ b> A can be made larger than the capacity of the capacitor 10.

  Hereinafter, a method for manufacturing the DRAM 200 will be described by extracting a memory cell region surrounded by a broken line in FIG. 14A to 19B, (a) is a plan view, (b) is a cross-sectional view between AA ′ in the plan view, (c) is a cross-sectional view between BB ′ in the plan view, (d) ) Is a cross-sectional view taken along the line CC 'in the plan view.

  Referring to FIG. 14, an interlayer insulating film 6a was formed on silicon substrate 1 through the same steps as those described in FIG. Next, a first support film 29, which is a silicon nitride film having a thickness of 100 nm, was formed by plasma CVD so as to cover the upper surface of the interlayer insulating film 6a. Subsequently, a mask film 18, which is an AC film having a thickness of 100 nm, was formed by a CVD method so as to cover the upper surface of the first support film 29.

  Next, although not shown in FIG. 15, a mask pattern 18 'extending in the Y direction and an interlayer insulating film 6a is formed by the same process as the process of FIGS. 3 and 4 of the first embodiment. After forming the laminated film with the first pattern 6, the first sidewall film 21 made of LP carbon film is formed on both side walls of the first pattern 6. Subsequently, the first buried film 22 is formed so as to fill the groove 20 between the first sidewall films 21 by the same process as in FIG. The upper surface of the first support film 29 on the first pattern 6 is exposed, the second support film 30 is formed on the entire surface, and then the mask film 23 is formed.

  Next, after the core pattern 23 'extending in the Y direction and the second sidewall film 25A are formed on both side walls by the same process as in FIGS. 6 and 7 of the first embodiment, the same as in FIG. The core pattern 23 'was removed by the process. Next, using the second sidewall film 25A as a mask, the first buried film 22 is removed until the upper surface of the first sidewall film 21 is exposed, and grooves 26 and 26a extending in the X direction are formed. (FIG. 15). Thereafter, as in the step of FIG. 9, the first sidewall film 21 whose upper surface is exposed is etched back, and the stopper film 5 is further etched. Thus, a high aspect hole 11 (corresponding to the first hole 27 in the first embodiment) having a horizontal dimension X5 of 50 nm and a vertical dimension Y5 of 50 nm was formed. Further, the X-direction interval X6 and the Y-direction interval Y6 of the holes 11 are each 50 nm.

  As a result, the contact plug 4 is exposed on the bottom surface of the hole 11. Further, the first buried film 22 and the laminated film in which the support film 29 is formed on the first pattern 6 are exposed on the side surface facing the X direction of the hole 11, and on the side surface facing the Y direction. The first sidewall film 21 divided by the hole 11 is exposed.

  Next, referring to FIG. 16, a conductive film made of titanium nitride (TiN) was formed by CVD so as to fill hole 11 and grooves 26 and 26a. Further, by etching back, the conductive film is removed so that the upper surface of the conductive film coincides with the upper surface of the support film 29, thereby forming the lower electrode 7A composed of the conductive film in which the hole 11 is embedded. The lower electrode 7A is not limited to titanium nitride, and a metal such as ruthenium (Ru) can also be used. In addition, below the second sidewall film 25A and the second support film 30 extending in the X direction, the first buried film 22, the first pattern 6, and the first support film 29 are provided. The first sidewall film 21 remains.

  Next, referring to FIG. 17, the first embedded film 22, the first pattern 6, and the first pattern, both of which are silicon oxide films, are formed by wet etching using a chemical solution containing hydrofluoric acid (HF) as a main component. The second sidewall film 25A was removed. Since this wet etching method is isotropic etching, the first buried film 22 and the first pattern 6 below the second support film 30 can be easily removed. Since the silicon nitride film, titanium nitride, and AC film cannot be removed with hydrofluoric acid, the first support film 29, the second support film 30, the stopper film 5, the lower electrode 7A, and the sidewall film 21 made of the AC film remain. Yes. The interlayer insulating film 3, which is a silicon oxide film below the stopper film 5, remains because it is covered with the stopper film 5 and protected from the chemical solution. In FIG. 17C, a space is formed between the stopper film 5 and the first support film 29.

  Next, referring to FIG. 18, the remaining first sidewall film 21 was removed by ashing. The ashing conditions for the first sidewall film 21 are the same as the ashing conditions for the mask pattern 18 'in FIG. At this time, the lower electrode 7A that remains and the side surface portion is exposed is connected to the first support film 29 extending in the Y direction at a part of the side surface portion. It is connected to the second support film 30 extending in the direction. The lower electrode 7A is in a state of being self-supported on the contact plug 4, but is collapsed in any direction because it is supported by the second support film 30 from the X direction and the first support film 29 from the Y direction. Defects that are prevented are prevented. 18C and 18D, there is a space between the stopper film 5 and the second support film 30.

  Next, referring to FIG. 19, a capacitive insulating film 8A and an upper electrode 9A were formed in this order by CVD or ALD so as to cover the exposed surface of lower electrode 7A. Thus, a plurality of columnar lower electrodes 7A that are connected and supported by the first support film 29 in the Y direction and supported by the second support film 30 in the X direction, and the capacitive insulating film 8A that covers the outer surface of the lower electrode 7A, and A capacitor 10A composed of the upper electrode 9A is formed. Thereafter, the DRAM 200 shown in FIG. 13 is completed through steps similar to those described in the first embodiment.

In the second embodiment of the present invention, the interlayer insulating film 6a formed on the silicon substrate 1 is processed by the first pattern forming process to extend in the first direction (Y direction). Forming a first sidewall film 21 made of an LP carbon film serving as a sacrificial film on both side walls of the first pattern 6;
Forming a first buried film 22 on the entire surface and burying a space formed between the first patterns 6;
A first sidewall film extending in the first direction by using a second pattern forming step of forming a pattern in a second direction (X direction) which is a direction perpendicular to the first direction; 21, dividing the first sidewall film 21 in the first direction by forming a plurality of holes 11 arranged at predetermined intervals in the first direction;
Burying the hole 11 with a conductive film to form a columnar lower electrode 7A;
Removing the first pattern 6, the first buried film 22, and the remaining first sidewall film 21 remaining around the lower electrode 7A to expose the outer surface of the lower electrode 7A; The double patterning process including is used.

  Thereby, a hole 11 having a small opening width and a high aspect ratio can be formed. By using this as a hole for forming the lower electrode 7A, a capacitor suitable for miniaturization can be formed.

[Third embodiment]
A semiconductor device according to a third embodiment of the present invention will be described in detail with reference to FIGS. Since the film forming conditions and etching conditions of each member in the third embodiment are the same as those in the first and second embodiments, description of common contents is omitted, and the first and second embodiments are omitted. Only the differences are described.

  FIG. 20 is a partial cross-sectional view of a DRAM 300 as a semiconductor device according to the third embodiment.

  In FIG. 20, the lower electrode 7B constituting the capacitor 10B has a crown shape. The bottom surface portion of the lower electrode 7B is connected to the upper surface of the contact plug 4 (4a), and a part of the upper side surface is connected to the first support film 29. The first support film 29 serves to support each other so that adjacent lower electrodes 7B do not contact each other. The side surface and the upper surface of the lower electrode 7B are covered with the capacitive insulating film 8B and the upper electrode 9B, thereby constituting the capacitor 10B.

  When the area occupied by the capacitor 10A of the DRAM 200 according to the second embodiment and the capacitor 10B of the DRAM 300 according to the third embodiment is the same, the contact portion between the lower electrode 7B and the capacitor insulating film 8B in the capacitor 10B is the lower portion. It is almost the entire inner wall and outer wall of the electrode 7B. This is because the contact area between the lower electrode 7B and the capacitive insulating film 8B is larger than the contact area in the capacitor 10A in which the contact portion between the lower electrode 7A and the capacitive insulating film 8A is only the entire outer wall of the lower electrode 7A. It means to increase. Therefore, the capacity of the capacitor 10B can be increased more than the capacity of the capacitor 10A.

  In the DRAM configured as described above, the manufacturing method of the DRAM 300 according to the third embodiment is used in the manufacturing process of the high aspect hole. This will be described with reference to FIG. In this description, a drawing of a memory cell region surrounded by a broken line part in FIG. 20 is used, where (a) is a plan view, (b) is a cross-sectional view between AA ′ in the plan view, c) is a cross-sectional view taken along the line BB ′ in the plan view, and (d) is a cross-sectional view taken along the line CC ′ in the plan view.

  Up to the formation of the high aspect hole 11 is realized through the same steps as those shown in FIGS. 14 and 15 described in the second embodiment. Next, referring to FIG. 21, the CVD method is used to cover the upper surfaces of the first support film 29 and the first buried film 22 and the high aspect hole 11 and the inner wall of the groove 26 (FIG. 15). A conductive film 32 made of titanium nitride (TiN) was formed. Since the conductive film 32 is formed so as not to be embedded in the high aspect hole 11 and the grooves 26 and 26a, the inside of the conductive film 32 having a U-shaped cross section is a recessed space. The conductive film 32 is not limited to titanium nitride, and a metal such as ruthenium (Ru) can also be used.

  Next, a buried film 31 which is a silicon oxide film having a thickness of 100 nm was formed by ALD so as to fill the high aspect hole 11 and the grooves 26 and 26a. Here, the deposition conditions of the buried film 31 in one cycle are the same as the deposition conditions of the first buried film 22 in FIG. By the ALD method, the high aspect hole 11 having a high aspect ratio can be easily embedded.

  Next, referring to FIG. 22, the buried film 31, the conductive film 32, and the second sidewall film 25 </ b> A were removed by CMP so that the upper surface of the second support film 30 was exposed. At this time, the buried film 31 and the conductive film 32 are exposed on the silicon substrate 1 along with the second support film 30 so as to extend in the X direction.

  Next, referring to FIG. 23, the buried film 31 and the conductive film 32 are removed by the etch back method so that the first support film 29 is exposed, and the remaining conductive film 32 is formed as the lower electrode 7B. did. Here, the lower electrode 7 </ b> B has a U-shaped cross section so as to contact the side wall of the high aspect hole 11. A buried film 31 is buried inside the lower electrode 7B having a U-shaped cross section, and the lower electrode 7B and the second support film adjacent to the upper end of the buried film 31 extend in the X direction. It is exposed from between 30. In addition, below the second support film 30 extending in the X direction, the first support film 29, the first buried film 22, the first pattern 6, and the first sidewall film 21 are provided. It remains.

  Next, referring to FIG. 24, the first buried film 22, the first pattern 6, and the buried film 31 that are silicon oxide films are formed by a wet etching method using a chemical solution containing hydrofluoric acid (HF) as a main component. Was removed. Since this wet etching method is isotropic etching, the first buried film 22 and the first pattern 6 below the second support film 30 can be easily removed. Manufacturing methods other than those described here are the same as in FIG. In FIG. 24C, a space is formed between the stopper film 5 and the first support film 29. The same applies to FIG. 25C described later.

  Next, referring to FIG. 25, the remaining first sidewall film 21 was removed by ashing. The ashing conditions for the first sidewall film 21 are the same as the ashing conditions for the mask pattern 18 'in FIG. At this time, in the lower electrode 7A, the outer wall portion and the inner wall portion that remain to be exposed, the first support film 29 extending in the Y direction is connected to a part of the outer wall portion. The first support film 29 is connected to a second support film 30 extending in the X direction. The lower electrode 7A is in a state of being self-supported on the contact plug 4, but is supported by the second support film 30 from the X direction and the first support film 29 from the two directions of the Y direction. Failure to collapse is prevented. Also in FIG. 25D, a space is formed between the stopper film 5 and the first support film 29.

  Next, referring to FIG. 26, a capacitive insulating film 8A was formed by CVD or ALD so as to cover the exposed surface of lower electrode 7A. The steps after the formation of the capacitive insulating film 8A are the same as those described in the first embodiment and FIG.

  The DRAM 300 shown in FIG. 20 is completed by the manufacturing method described above.

  As described above, according to the method of manufacturing a semiconductor device of the present invention, the carbon film having a high aspect is formed on the interlayer insulating film 6a (first pattern 6) forming the lower electrode 7 (7A, 7B). The high aspect hole 11 is formed by forming the first sidewall film 21 and then removing the first sidewall film 21 by ashing or dry etching. According to the manufacturing method by ashing, since the interlayer insulating film is not processed by dry etching when the high aspect hole 11 is formed, the high aspect hole 11 can be easily formed.

  Also by the manufacturing method by dry etching, since the target film for dry etching is a carbon film, it is easier to form the high aspect hole 11 than the silicon oxide film.

  Further, the horizontal dimension X5 of the high aspect hole 11 depends on the film thickness of the first sidewall film 21, and the vertical dimension Y5 depends on the film thickness of the second sidewall film 25A. Further, the interval X6 in the X direction of the high aspect hole 11 depends on the width X2 of the mask pattern 18 '(first pattern 6) and the width X3 of the groove 20, and the interval Y6 in the Y direction is the width of the core pattern 23'. It depends on Y2 and the width Y3 of the groove 24. That is, the dimensions and spacing of the high aspect holes 11 depend on the film thickness of the film that can be easily adjusted and the dimensions of the rectangular patterns and grooves that can be formed relatively easily by dry etching. The dimension adjustment can be easily performed.

  The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2, 3, 6a, 12, 17 Interlayer insulating film 4, 4a, 13, 15 Contact plug 6 1st pattern 7, 7A, 7B Lower electrode 8 Capacitance insulating film 9, 9A, 9B Upper electrode 10 Capacitor 16 Wiring 20, 24, 26, 26a, 27 Groove 21 First sidewall film 22 First buried film 23 Mask film 23 'Core pattern 25 Cover film 25A Second sidewall film 28 Second buried film 29 Second 1 support film 30 second support film 100, 200, 300 DRAM

Claims (11)

An interlayer insulating film formed on the semiconductor substrate is processed by a first pattern forming process to form a first pattern extending in a first direction, and an LP carbon film is formed on both side walls of the first pattern. Forming a first sidewall film comprising:
Forming a first buried film on the entire surface and burying a space formed between the first patterns;
The first sidewall film extending in the first direction using a second pattern forming step of forming a pattern in a second direction that is a direction perpendicular to the first direction, Forming a plurality of first holes arranged at predetermined intervals in a first direction;
Dividing the first sidewall film with respect to the first direction by burying the first hole with a second buried film;
Removing the remaining first sidewall film to form a plurality of second holes;
A method for manufacturing a semiconductor device, comprising:   2. The method of manufacturing a semiconductor device according to claim 1, wherein an LP carbon film is formed as the first sidewall film by an LPCVD method. In the second pattern forming step, a second pattern extending in the second direction is formed on the first buried film, and second sidewalls are formed on both side walls of the second pattern. Forming a film,
In order to make all the first holes have the same dimension Y4 in the first direction and are arranged at equal pitch intervals, the interval Y1 of the second pattern is three times the width Y2 of the second pattern. 3. The method of manufacturing a semiconductor device according to claim 1, further comprising setting the film thickness of the second sidewall film to the same value as the width Y2 of the second pattern. .   In order to arrange all the second holes with the same interval X6 in the second direction and at equal pitch intervals, the interval X1 of the first pattern is three times the width X2 of the first pattern. The film thickness of the first sidewall film is set to the same value as the width X2 of the first pattern. A method for manufacturing a semiconductor device.   5. The semiconductor according to claim 1, further comprising a step of sequentially forming a lower electrode, a capacitor insulating film, and an upper electrode constituting a capacitor on an inner wall of the second hole. Device manufacturing method. An interlayer insulating film formed on the semiconductor substrate is processed by a first pattern forming process to form a first pattern extending in a first direction, and an LP carbon film is formed on both side walls of the first pattern. Forming a first sidewall film comprising:
Forming a first buried film on the entire surface and burying a space formed between the first patterns;
The first sidewall film extending in the first direction using a second pattern forming step of forming a pattern in a second direction that is a direction perpendicular to the first direction, Dividing the first sidewall film with respect to the first direction by forming a plurality of high aspect holes arranged at predetermined intervals in the first direction;
Burying the high aspect hole with a conductive film to form a columnar lower electrode;
Removing the interlayer insulating film located around the lower electrode, the first buried film, and the remaining first sidewall film to expose the outer surface of the lower electrode;
A method for manufacturing a semiconductor device, comprising:   The method of manufacturing a semiconductor device according to claim 6, wherein an LP carbon film is formed as the first sidewall film by an LPCVD method.   8. The method of manufacturing a semiconductor device according to claim 6, further comprising a step of sequentially forming a capacitor insulating film and an upper electrode constituting a capacitor on the exposed outer surface of the lower electrode. An interlayer insulating film formed on the semiconductor substrate is processed by a first pattern forming process to form a first pattern extending in a first direction, and an LP carbon film is formed on both side walls of the first pattern. Forming a first sidewall film comprising:
Forming a first buried film on the entire surface and burying a space formed between the first patterns;
The first sidewall film extending in the first direction using a second pattern forming step of forming a pattern in a second direction that is a direction perpendicular to the first direction, Dividing the first sidewall film with respect to the first direction by forming a plurality of high aspect holes arranged at predetermined intervals in the first direction;
Forming a conductive film on the inner wall of the high aspect hole as a lower electrode;
Removing the interlayer insulating film located around the lower electrode, the first buried film, and the remaining first sidewall film to expose the outer surface of the lower electrode;
A method for manufacturing a semiconductor device, comprising:   The method for manufacturing a semiconductor device according to claim 9, wherein an LP carbon film is formed as the first sidewall film by an LPCVD method.   11. The method of manufacturing a semiconductor device according to claim 9, further comprising a step of sequentially forming a capacitor insulating film and an upper electrode constituting a capacitor on the exposed outer surface of the lower electrode.

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