JP2013115109A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which can achieve an arbitrary logic while reducing a circuit scale.SOLUTION: A semiconductor integrated circuit of an embodiment comprises: first circuit groups each including at least one first logical block; second circuit groups each including second logical blocks larger than the first logical block in number; and an input/output part having a function of inputting input data to the first logical block or the second logical block and a function of outputting output data output from the first logical block or the second logical block to the outside. The first circuit groups include first switch blocks and first power supply control circuits. The first power supply control circuit commonly controls supply of power and interruption of power supply with respect to the first logical blocks included in the first circuit groups and the first switch blocks. The second circuit groups include second switch blocks and second power supply control circuits. The second power supply control circuit commonly controls supply of power and interruption of power supply with respect to the second logical blocks included in the second circuit groups and the second switch blocks.

Description

  Embodiments described herein relate generally to a semiconductor integrated circuit.

  Conventionally, a field-programmable gate array (FPGA) is known as an example of a semiconductor integrated circuit (IC) capable of realizing arbitrary logic. A general FPGA includes a logic block capable of realizing a specific logic, and a switch block including a plurality of switches for switching connection of a plurality of wirings used for connection between the logic blocks according to programmable control data; , And a plurality of tiles, each of which is arranged in a matrix. Various logics can be realized by supplying (writing) control data from the outside to each switch block.

  The FPGA can implement various logics, but since all the tiles are rarely used when realizing each logic, power supply to unused tiles is stopped. It is desirable to do.

T. Tuan, et al. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO.2, FEBRUARY 2007

  However, if a power supply control circuit is provided for each tile indicating a unit capable of realizing a specific logic, peripheral circuits such as circuit area and wiring required for installing the power supply control circuit increase. That is, there is a problem that the circuit scale increases. The problem to be solved by the present invention is to provide a semiconductor integrated circuit capable of realizing any logic while reducing the circuit scale.

  The semiconductor integrated circuit according to the embodiment includes a first circuit group including at least one first logic block, a second circuit group including a larger number of second logic blocks than the first logic block, and input data to the first logic block. And an input / output unit having a function of inputting to the block or the second logic block and a function of outputting output data output from the first logic block or the second logic block to the outside. The first circuit group includes a first switch block and a first power supply control circuit. The first switch block includes at least one of a connection between the first logic block or the second logic block and the input / output unit, a connection between the first logic blocks, and a connection between the first logic block and the second logic block. It includes a switch for switching the wiring connection used according to programmable control data. The first power supply control circuit controls in common the supply and stop of power to the first logic block and the first switch block included in the first circuit group. The second circuit group includes a second switch block and a second power supply control circuit. The second switch block includes at least one of a connection between the first logic block or the second logic block and the input / output unit, a connection between the second logic blocks, and a connection between the first logic block and the second logic block. It includes a switch for switching the wiring connection used according to programmable control data. The second power supply control circuit commonly controls supply and stop of power to the logic block and the second switch block included in the second circuit group.

The figure which shows the schematic structural example of FPGA of 1st Embodiment. The figure which shows the example of a path | route from the logic block of 1st Embodiment to an input-output part. The figure which shows the average value of the statistical distribution of Fermi-Dirac. The figure which shows the example of arrangement | positioning of the power supply control circuit of 1st Embodiment. The figure which shows the structural example of the power supply control circuit of 1st Embodiment. The figure which shows the example of arrangement | positioning of the power supply control circuit of the modification of 1st Embodiment. The figure which shows the example of arrangement | positioning of the power supply control circuit of 2nd Embodiment. The figure which shows the example of arrangement | positioning of the power supply control circuit of the modification of 2nd Embodiment. The figure which shows the example of arrangement | positioning of the power supply control circuit of 3rd Embodiment. The figure which shows the example of arrangement | positioning of the power supply control circuit of the modification of 3rd Embodiment. The figure which shows the example of arrangement | positioning of the power supply control circuit of 4th Embodiment. The figure which shows the example of the grouping in the modification 1 of 4th Embodiment. The figure which shows the example of the grouping in the modification 2 of 4th Embodiment. The figure which shows the example of the grouping in the modification 3 of 4th Embodiment. The figure which shows the example of the grouping in the modification 4 of 4th Embodiment. The figure which shows the example of arrangement | positioning of the power supply control circuit of 5th Embodiment. The figure which shows the example of arrangement | positioning of the power supply control circuit of the modification of 5th Embodiment. The figure which shows the example of the grouping of the modification of 5th Embodiment. The figure which shows the example of the grouping of the modification of 5th Embodiment. The figure which shows the example of the grouping of a modification. The figure which shows the structural example of the power supply control circuit of a modification. The figure which shows the structural example of the power supply control circuit of a modification. The figure which shows the structural example of the power supply control circuit of a modification. The figure which shows the structural example of the power supply control circuit of a modification. The figure which shows the structural example of the power supply control circuit of a modification.

  Embodiments of a semiconductor integrated circuit according to the present invention will be described below in detail with reference to the accompanying drawings. In the following embodiments, an FPGA is described as an example of a semiconductor integrated circuit, but the present invention is not limited to this.

(First embodiment)
FIG. 1 is a diagram illustrating a schematic configuration example of the FPGA 100 according to the present embodiment. As shown in FIG. 1, the FPGA 100 includes an array unit 20 in which a plurality of tiles 10 are arranged in a matrix, and a plurality of input / output units (I / O) 30 arranged so as to surround the array unit 20. .

  Each tile 10 of the present embodiment is a unit capable of realizing a specific logic, and includes a logical block LB and a switch block SB. The logic block LB includes at least one logic operation circuit, and specific logic is realized by the logic operation of the logic operation circuit. The logic that can be realized by each tile 10 can be set individually for each tile 10.

  The switch block SB can control (arbitrarily settable) control data for connecting a plurality of wirings (not shown) used to connect the logical block LB and the input / output unit 30 or the logical blocks LB. It includes a plurality of switches that switch depending on. For example, each switch may be formed of a field effect transistor, and its gate may be connected to a memory that stores bit data (control data) written from the outside. In this case, the bit data stored in the memory can be rewritten, and the on / off of each switch is switched according to the bit data written in the memory.

  Each of the plurality of input / output units 30 has a function of inputting input data to the logical block LB and a function of outputting output data output from the logical block LB to the outside.

  Here, due to the structure of the FPGA 100, in order for the output data output from the logical block LB of a certain tile 10 to reach the input / output unit 30, all the switches interposed between the tile 10 and the input / output unit 30 are used. Since the block SB must be passed, for example, as shown in FIG. 2, if the tile 10A separated from the input / output unit 30B for outputting the output data is arranged and wired so as to be used, the data transmission delay amount Will increase. For this reason, the tiles 10 are arranged and wired so as to use the tiles 10 close to the input / output unit 30 that inputs input data or outputs output data (hereinafter referred to as “used input / output unit 30”). .

Therefore, the tile 10 closer to the input / output unit 30 to be used has a higher operation probability value indicating the possibility of operation. The operation probability of the tile 10 can be expressed by Equation 1 below.
f (D) = 1 / [exp {(D−μ) / C} +1] (1)
In the above equation 1, f (D) represents the operation probability of the tile 10 arranged at a distance D from the input / output unit 30 to be used. μ indicates the distance from the input / output unit 30 when the logical block LB is used in the order of proximity to the input / output unit 30 to be used. Furthermore, μ is a fixed value (constant) determined by the size (for example, the number of tiles 10) of the FPGA (for example, an FPGA including 150 × 150 tiles 10) and the logic used by the user. On the other hand, D described above is a variable of a function for obtaining the motion probability f (D) of the tile 10, and the value of the motion probability f (D) is set variably according to the variable D. C is a constant indicating the ease of leaving the logical block LB from the input / output unit 30 to be used. That is, the motion probability f (D) follows the Fermi-Dirac statistical distribution. Note that the operation probability of the tile 10 can also be understood as indicating the possibility that the logical block LB included in the tile 10 operates.

  FIG. 3 is a diagram showing the average value of the Fermi-Dirac statistical distribution calculated when the FPGA width is 150 tiles for 20 circuits extracted from the MCNC benchmark circuit. It is assumed that the logical block in each tile is composed of a 4-input lookup table (LUT). As understood from FIG. 3, the value of the operation probability increases as the tile is closer to the input / output unit (I / O) to be used.

  As described above, in the FPGA, the value of the operation probability is higher in the tile 10 near the input / output unit 30 to be used. Of the array unit 20 in which the tiles 10 are arranged in a matrix, in a region having a high operation probability, it is considered that a plurality of tiles 10 included in the region are used simultaneously. It is considered that a power supply control circuit may be provided.

  Therefore, in the present embodiment, as shown in FIG. 4, the tiles 10 arranged at positions close to the side SD composed of the plurality of input / output units 30 to be used are grouped (set) for each of the plurality of tiles 10. Divided). In the example of FIG. 4, in the direction (column direction) orthogonal to the extending direction (row direction) of the side SD, one set P <b> 1 includes the first and second tiles 10 counted from the side closer to the side SD. Is configured. For each set P1, a common power supply control circuit 40 that controls supply and stop of power to each of the two tiles 10 belonging to the set P1 is provided. On the other hand, for the tiles 10 other than the tile 10 included in the set P1, a power control circuit 50 that controls supply and stop of power to the tile 10 is individually provided. In other words, the other tiles 10 arranged at positions farther from the side SD than the tiles 10 included in the set P1 are grouped for each tile 10, and for each group that has been grouped, It can also be understood that a power supply control circuit 50 that controls the supply and stop of power to one tile 10 belonging to the set is individually provided.

  That is, the FPGA 100 according to the present embodiment includes a first circuit group including at least one logical block LB (“first logical block”) (in this example, a unit grouped for each tile 10, that is, one unit Tile 10 itself) and a larger number of logical blocks LB ("second logical block") than the first logical block, and are arranged closer to the input / output unit 30 to be used than the first circuit group. It can be understood that the second circuit group (the set P1 in this example) is provided.

  The first circuit group includes at least one of a connection between the first logic block or the second logic block and the input / output unit 30, a connection between the first logic blocks, and a connection between the first logic block and the second logic block. A first switch block (in this example, one tile 10) including a switch (single or plural) for switching the connection of wiring (single or plural) used for one according to programmable control data. The switch block SB included), the first logic block included in the first circuit group (in this example, the logic block LB included in one tile 10) and the first switch block are supplied and stopped. It has the 1st power supply control circuit (this example power supply control circuit 50) controlled in common. The second circuit group includes at least one of a connection between the first logic block or the second logic block and the input / output unit 30, a connection between the second logic blocks, and a connection between the first logic block and the second logic block. A second switch block (in this example, included in the set P1) including a switch (single or plural) that switches connection of wiring (single or plural) used for one according to programmable control data A switch block SB included in each of the two tiles 10) and a second logical block included in the second circuit group (in this example, a logical block LB included in each of the two tiles 10 included in the set P1). And a second power supply control circuit (in this example, the power supply control circuit 40) for commonly controlling the supply and stop of power to the second switch block. It is possible.

  FIG. 5 is a diagram illustrating a configuration example of the power supply control circuit 40. Here, the power supply control circuit 40 (corresponding to the power supply control circuit 40 included in one set P1) provided corresponding to one set P1 will be described as an example, but it corresponds to another set P1. The power supply control circuit 40 provided in the same manner has the same configuration. As shown in FIG. 5, the power supply control circuit 40 includes a switch element 41 and a control circuit 42. The switch element 41 is disposed between the power supply line 101 to which the power supply potential VD is supplied and the set P1. In the example of FIG. 5, the switch element 41 is configured by a P-channel field effect transistor (P-type MOSFET). The gate of the switch element 41 is connected to the control circuit 42, and the switch element 41 is switched on and off in accordance with a switch control signal supplied from the control circuit 42. For example, the switch control signal may be 1-bit digital data, and the switch element 41 may be turned on / off according to the digital data. The control circuit 42 may be any means that can control the on / off of the switch element 41, and its configuration is arbitrary. For example, the control circuit 42 may be configured by a memory element that can store a switch control signal written from the outside.

  When the switch element 41 transitions to the ON state, a power supply path from the power supply line 101 to each of the two tiles 10 included in the set P1 is formed, and the power supply potential VD is applied to each of the two tiles 10. Supplied. On the other hand, when the switch element 41 transitions to the OFF state, a power supply path from the power supply line 101 to each of the two tiles 10 included in the set P1 is not formed, and thus the power supply potential VD for each of the two tiles 10 is not formed. Is not supplied. The basic configuration of the power supply control circuit 50 is the same as that of the power supply control circuit 40 shown in FIG. 5, but the power supply control circuit 50 is provided for each tile 10 other than the tiles 10 included in the set P1. Since they are provided individually, the same number of switch elements and control circuits as the other tiles 10 are required.

  As described above, in the present embodiment, the tiles 10 arranged at positions close to the input / output unit 30 (side SD) to be used are grouped into two tiles 10 and the unit is grouped. Since the common power supply control circuit 40 is provided every time (for each set P1), the circuit scale can be reduced as compared with the configuration in which the power supply control circuits 50 are individually provided for all the tiles 10. On the other hand, the tile 10 arranged at a position far from the input / output unit 30 to be used, that is, the tile 10 having a low possibility of being used (the value of the operation probability is small) is common to the plurality of tiles 10. The effect of reducing power is greater when the unit for controlling the supply and stop of power is made finer than when a power supply control circuit is provided. In the present embodiment, since the power supply control circuit 50 is individually provided for the tile 10 arranged at a position farther from the input / output unit 30 to be used than the tile 10 included in the set P1, power is supplied in units of tiles 10. Can be controlled and stopped. That is, since the unit for controlling the supply and stop of power can be made finer, the effect of reducing the power is greater than when a common power supply control circuit is provided for each of the plurality of tiles 10.

(Modification of the first embodiment)
In the array unit 20 described above, it can be understood that a set G of a plurality of tiles 10 arranged in parallel with the extending direction (row direction) of the side SD is arranged in parallel. As shown in FIG. 6, for a plurality of tiles 10 included in the first row set G counted from the side closer to the side SD, one set P <b> 2 may be configured for every two tiles 10. In the example of FIG. 6, a common power supply control circuit 40 is provided for each set P2. On the other hand, the power supply control circuits 50 are individually provided for the tiles 10 other than the plurality of tiles 10 included in the set G in the first row.

(Second Embodiment)
Next, a second embodiment will be described. The second embodiment is different from the first embodiment described above in that the number of tiles 10 belonging to a set formed in the vicinity of the input / output unit 30 (side SD) to be used is larger than two. The configuration is the same as in the first embodiment. Below, about the part which is common in 1st Embodiment, the same code | symbol is attached | subjected and description is abbreviate | omitted suitably.

  As described above, in the array unit 20, it can be understood that a set G of a plurality of tiles 10 arranged in parallel with the extending direction (row direction) of the side SD is arranged in parallel. In the present embodiment, as shown in FIG. 7, the plurality of tiles 10 included in each of the sets G of the first row and the second row counted from the side closer to the side SD is 2 rows × 2 One set P3 is configured for every four tiles 10 in the column. A common power supply control circuit 400 is provided for each set P3. The basic configuration of the power supply control circuit 400 is the same as that of the power supply control circuit 40 shown in FIG. 5, but the power supply control circuit 400 supplies and stops the power supply potential VD to each of the four tiles 10 included in the set P3. To control. On the other hand, for the tiles 10 other than the tiles 10 included in each of the first row and the second row set G, the power supply control circuits 50 are individually provided.

  In the present embodiment, the tiles 10 arranged at positions close to the input / output unit 30 (side SD) to be used are grouped into four tiles 10 for each grouped unit (for each group P3). ) Since the common power supply control circuit 400 is provided, the circuit scale can be further reduced as compared with the first embodiment.

(Modification of the second embodiment)
For example, as shown in FIG. 8, for a plurality of tiles 10 included in each of the sets G of the first row and the second row counted from the side closer to the side SD, one set P4 for every three tiles 10 May be configured. In the example of FIG. 8, a common power supply control circuit 410 is provided for each set P4. The basic configuration of the power supply control circuit 410 is the same as that of the power supply control circuit 40 shown in FIG. 5, but the power supply control circuit 410 supplies and stops the power supply potential VD to each of the three tiles 10 included in the set P4. To control. On the other hand, for the tiles 10 other than the tile 10 included in the set P4, the power supply control circuit 50 is individually provided.

(Third embodiment)
Next, a third embodiment will be described. The third embodiment is different from the above-described embodiments in that the number of tiles 10 belonging to a set formed near the input / output unit 30 (side SD) to be used is variably set for each set. . In the following, portions common to the above-described embodiments are denoted by the same reference numerals and description thereof is omitted as appropriate.

  In FIG. 9, description will be made by paying attention to three sets (P51, P52, P53) formed in the vicinity of the side SD. The number of tiles 10 included in each of the three sets (P51, P52, P53) illustrated in FIG. 9 is set individually. As in the second embodiment described above, the set P51 is any four of the plurality of tiles 10 included in each of the sets G of the first row and the second row counted from the side closer to the side SD. The tile 10 is composed of four tiles 10 (2 rows × 2 columns). The set P52 formed on the right side thereof is the first counted from the side closer to the side SD in the direction (column direction) orthogonal to the extending direction of the side SD, as in the first embodiment. Consists of the second tile 10. The set P53 formed on the right side is any of the tiles 10 included in the set G in the first row, counting from the side closer to the side SD, as in the modification of the first embodiment described above. Or two tiles 10. For each set (P51, P52, P53), a power supply control circuit that controls supply and stop of power to the tiles 10 included in the set is provided. In the present embodiment, in the vicinity of the side SD, the above-described three types of sets (P51, P52, P53) are repeatedly formed and included in any of the above-described three types of sets (P51, P52, P53). For the tiles 10 other than the tile 10 to be provided, the power supply control circuit 50 is individually provided.

  In the example of FIG. 9, for the set P51, a power supply control circuit 420 that controls supply and stop of power to the four tiles 10 included in the set P51 is provided. The basic configuration of the power supply control circuit 420 is the same as that of the power supply control circuit 40 shown in FIG. 5, but the power supply control circuit 420 supplies and stops the power supply potential VD to each of the four tiles 10 included in the set P51. Are controlled in common. Further, for the set P52, a power supply control circuit 430 that controls supply and stop of power to the two tiles 10 included in the set P52 is provided. The basic configuration of the power supply control circuit 430 is the same as that of the power supply control circuit 40 shown in FIG. Furthermore, for the set P53, a power supply control circuit 440 that controls supply and stop of power to the two tiles 10 included in the set P53 is provided. The basic configuration of the power supply control circuit 440 is the same as that of the power supply control circuit 40 shown in FIG.

(Modification of the third embodiment)
The number of tiles 10 included in the set formed in the vicinity of the side SD is not limited to the above-described content, and can be arbitrarily set. For example, as shown in FIG. 10, one tile P54 is formed by E (E ≧ 2) tiles 10 among the tiles 10 (tiles 10 whose operation probability is a predetermined value or more) arranged in the vicinity of the side SD. Further, on the right side of the set P54, one set P55 may be formed by F tiles (F is an integer of 2 or more different from E). Note that the tiles 10 included in the set P54 or the set P55 are not limited to the tiles 10 included in each of the set G in the first row and the set G in the second row. The tile 10 may be included.

  Also in the example of FIG. 10, for each set (P54, P55), a power supply control circuit that controls supply and stop of power to the tiles 10 included in the set is provided. In the present embodiment, in the vicinity of the side SD, the above-described two types of sets (P54, P55) are repeatedly formed, and other than the tiles 10 included in any of the above-described two types of sets (P54, P55). For the other tiles 10, a power supply control circuit 50 is individually provided.

  In the example of FIG. 10, for the set P54, a power supply control circuit 450 that controls supply and stop of power to the E tiles 10 included in the set P54 is provided. The basic configuration of the power supply control circuit 450 is the same as that of the power supply control circuit 40 shown in FIG. 5, but the power supply control circuit 450 supplies the power supply potential VD to each of the E tiles 10 included in the set P54. Common control of stopping. For the set P55, a power supply control circuit 460 that controls supply and stop of power to the F tiles 10 included in the set P55 is provided. The basic configuration of power supply control circuit 460 is the same as that of power supply control circuit 40 shown in FIG. 5, except that power supply control circuit 460 supplies power supply potential VD to each of F tiles 10 included in set P55. Common control of stopping.

  For example, if the logic implemented in the entire FPGA 100 is limited, the area that is frequently used (the area to which the tile 10 having a high operation probability belongs) is also limited. By forming a group having a large number and providing a power supply control circuit corresponding to the group, the circuit scale can be further reduced. On the other hand, for areas that are used infrequently, by forming a set with a small number of tiles (or a set with one tile) and providing a power supply control circuit corresponding to the set, power can be efficiently generated. Can be reduced.

(Fourth embodiment)
Next, a fourth embodiment will be described. In the fourth embodiment, the tiles 10 that share the power control circuit are grouped in stages, and the tiles 10 that are closer to the input / output unit 30 (side SD) to be used are included in the same set. Is different from the above-described embodiments in that the tiles 10 that are farther from the input / output unit 30 (side SD) to be used are grouped so that the number of tiles 10 included in the same group is smaller. . In the following, portions common to the above-described embodiments are denoted by the same reference numerals and description thereof is omitted as appropriate.

  In FIG. 11, the tiles 10 that are closer to the side SD are grouped so that the number of tiles 10 included in the same set is larger, and the tiles 10 that are farther from the side SD are smaller in number of tiles 10 included in the same set. Description will be made by paying attention to three sets (P61, P62, P63). The set P61 includes N tiles (N> 1) of the plurality of tiles 10 having an operation probability equal to or higher than the first reference value. The set P62 is configured by any M tiles (M> 1, M <N) of a plurality of tiles having an operation probability equal to or higher than the second reference value and lower than the first reference value. The set P63 includes L tiles (L ≧ 1, L <M) among a plurality of tiles having an operation probability less than the second reference value.

  In the example of FIG. 11, for the set P61, a power supply control circuit 470 that controls supply and stop of power to the N tiles 10 included in the set P61 is provided. The basic configuration of power supply control circuit 470 is the same as that of power supply control circuit 40 shown in FIG. 5, except that power supply control circuit 470 supplies power supply potential VD to each of N tiles 10 included in set P61. Common control of stopping. Further, for the set P62, a power supply control circuit 480 that controls supply and stop of power to the M tiles 10 included in the set P62 is provided. The basic configuration of the power supply control circuit 480 is the same as that of the power supply control circuit 40 shown in FIG. 5, but the power supply control circuit 480 supplies the power supply potential VD to each of the M tiles 10 included in the set P62. Common control of stopping. Further, for the set P63, a power supply control circuit 490 that controls supply and stop of power to the L tiles 10 included in the set P63 is provided. The basic configuration of power supply control circuit 490 is the same as that of power supply control circuit 40 shown in FIG. 5, except that power supply control circuit 490 supplies power supply potential VD to each of L tiles 10 included in set P63. Common control of stopping.

  That is, the FPGA of this embodiment includes a first circuit group (for example, the set P63) including at least one logical block LB (“first logical block”) and a larger number of logical blocks LB (“ A second circuit block (for example, the set P61) disposed closer to the input / output unit 30 to be used than the first circuit group, and more than the first logic block, It includes a smaller number of logical blocks LB (“third logical block”) than two logical blocks, and is arranged at a position farther from the input / output unit 30 than the second circuit group, and the input / output unit is more than the first circuit group. It can be understood that the third circuit group (for example, the set P62) arranged at a position close to 30 is provided.

  The first circuit group includes a connection between any one of the first logic block, the second logic block, and the third logic block and the input / output unit 30, a connection between the first logic blocks, a second logic block, or a third logic block. A switch (which may be singular or plural) for switching the connection of wiring (which may be singular or plural) used for at least one of the connections between the logical block and the first logical block according to programmable control data is included. The first switch block (in this example, the switch block SB included in each of the L tiles 10 included in the set P63) and the first logical block (in this example, the set P63 included in the set P63) The logic block LB) and the first switch block included in each of the included L tiles 10 and the first switch block are commonly controlled to supply and stop power. Power control circuit (in this example, the power control circuit 490) has a. The second circuit group includes a connection between the input / output unit 30 and any one of the first logic block, the second logic block, and the third logic block, a connection between the second logic blocks, a first logic block, or a third logic block. Includes a switch (single or plural) that switches connection of wiring (single or plural) used for at least one of the connections between the logical block and the second logical block according to programmable control data The second switch block (in this example, the switch block SB included in each of the N tiles 10 included in the set P61) and the second logic block (in this example, the set P61 included in the set P61) A second block for commonly controlling power supply and stop for the logical block LB) and the second switch block included in each of the N tiles 10 included. (In this example, the power control circuit 470) source control circuit having. Further, the third circuit group includes a connection between any one of the first logic block, the second logic block, and the third logic block and the input / output unit 30, a connection between the third logic blocks, the first logic block, or the second logic block. A switch (single or plural) for switching connection of wiring (single or plural) used for at least one of the connections between the logical block and the third logical block according to programmable control data is included. The third switch block (in this example, the switch block SB included in each of the M tiles 10 included in the set P62) and the third logic block (in this example, the set P62 included in the set P62) The logic block LB) and the third switch block included in each of the M tiles 10 included are commonly controlled to supply and stop power. Power control circuit (in this example, the power control circuit 480) can be regarded as having. Even in the above configuration, the circuit scale can be reduced as compared with the configuration in which the power supply control circuits 50 are individually provided for all tiles 10.

(Modification 1 of 4th Embodiment)
For example, when the user can freely specify the input / output unit 30 to be used, as shown in FIG. 12, four sides constituted by a plurality of input / output units 30 arranged so as to surround the array unit 20. The tiles 10 closer to (SD1 to SD4) have a larger number of tiles 10 included in the same set, and the tiles 10 farther from the four sides SD are grouped so that the number of tiles 10 included in the same set decreases. May be. That is, the set may be formed so that the size of the region where the set is formed is point-symmetric. In the example of FIG. 12, the input / output unit 30 arranged near the four corners of the substantially rectangular array unit 20 is used, and the logic is arranged and wired so that the tile 10 close to the input / output unit 30 is used. Is particularly effective in realizing the above, and can reduce the amount of power while reducing the circuit scale.

(Modification 2 of 4th Embodiment)
For example, it is assumed that two sides SD1 and SD3 facing each other are used among four sides (SD1 to SD4) configured by a plurality of input / output units 30 arranged so as to surround the array unit 20. To do. In this case, as shown in FIG. 13, the tile 10 closer to the two sides SD1 and SD3 has a larger number of tiles 10 included in the same set, and the tile 10 farther from the two sides SD1 and SD3 has the same value. Since the grouping is performed so that the number of tiles 10 included in the group is reduced, it is particularly effective in the case of realizing the logic of arranging and wiring so that the tiles 10 arranged in the vicinity of the side SD1 and the side SD3 are used. Thus, the amount of electric power can be reduced while reducing the circuit scale.

(Modification 3 of 4th Embodiment)
For example, it is assumed that the side SD1 is used among four sides (SD1 to SD4) configured by a plurality of input / output units 30 arranged so as to surround the array unit 20. In this case, as shown in FIG. 14, the tile 10 closer to the side SD1 has a larger number of tiles 10 included in the same set, and the tile 10 farther from the side SD1 has a smaller number of tiles 10 included in the same set. Therefore, it is particularly effective in the case of realizing a logic that is arranged and wired so that the tile 10 arranged in the vicinity of the side SD1 is used, and reduces the electric power while reducing the circuit scale. it can.

(Modification 4 of 4th Embodiment)
For example, among the four sides (SD1 to SD4) constituted by a plurality of input / output units 30 arranged so as to surround the array unit 20, the input / output unit 30 near the corner C1 between the sides SD1 and SD4 is Assume that it is used. In this case, as shown in FIG. 15, the tile 10 closer to the corner C1 has a larger number of tiles 10 included in the same set, and the tile 10 farther from the corner C1 has a smaller number of tiles 10 included in the same set. Therefore, it is particularly effective in the case of realizing logic that is arranged and wired so that the tile 10 arranged in the vicinity of the corner C1 is used, and reduces the amount of power while reducing the circuit scale. it can.

(Fifth embodiment)
Next, a fifth embodiment will be described. In the fifth embodiment, the number of tiles included in the set formed at a position close to the input / output unit 30 used is set to a set formed at a position farther from the input / output unit 30 used than the set. It differs from the above-described embodiments in that it is smaller than the number of tiles included. In the following, portions common to the above-described embodiments are denoted by the same reference numerals and description thereof is omitted as appropriate.

  In FIG. 16, the tile 10 closer to the side SD constituted by the plurality of input / output units 30 used has a smaller number of tiles 10 included in the same set, and the tile 10 farther from the side SD is included in the same set. Description will be made by paying attention to two sets (P71, P72) that are grouped so that the number of tiles 10 to be increased. The set P71 is configured by any i (i ≧ 1) tiles 10 among a plurality of tiles having an operation probability equal to or higher than the first reference value. The set P72 is configured with any number of tiles 10 (j> 1, j> i) among a plurality of tiles having an operation probability less than the first reference value.

  In the example of FIG. 16, for the set P71, a power control circuit 4000 that controls supply and stop of power to i tiles 10 included in the set P71 is provided. The basic configuration of power supply control circuit 4000 is the same as that of power supply control circuit 40 shown in FIG. 5, except that power supply control circuit 4000 supplies power supply potential VD to each of i tiles 10 included in set P71. Common control of stopping. Further, for the set P72, a power supply control circuit 4010 that controls supply and stop of power to the j tiles 10 included in the set P72 is provided. The basic configuration of power supply control circuit 4010 is the same as that of power supply control circuit 40 shown in FIG. 5, except that power supply control circuit 4010 supplies power supply potential VD to each of j tiles 10 included in set P72. Common control of stopping.

  That is, the FPGA of the present embodiment includes a first circuit group (for example, the set P71) including at least one logic block LB and a larger number of logic blocks LB than the first circuit group, and more than the first circuit group, It can be understood that the second circuit group (for example, the set P72) disposed at a position far from the input / output unit 30 to be used is provided. The first circuit group includes a first switch block (in this example, a switch block SB included in each of the i tiles 10 included in the set P71), a logical block LB included in the first circuit group, and A first power supply control circuit (in this example, a power supply control circuit 4000) for commonly controlling supply and stop of power to the first switch block. The second circuit group includes a second switch block (in this example, a switch block SB included in each of the j tiles 10 included in the set P72), a logical block LB included in the second circuit group, and It can be understood that the second switch block has a second power supply control circuit (in this example, a power supply control circuit 4010) that controls the supply and stop of power in common.

(Modification of the fifth embodiment)
For example, it can be understood that there is no other set (circuit group) between the first set (the input / output unit 30 and the first set) formed at the position closest to the input / output unit 30 to be used. The number of tiles 10 included in the second set formed in a position farther from the input / output unit 30 than the first set is smaller than the number of tiles 10 included in the second set. The number of tiles 10 included in the third set formed at a position far from the output unit 30 may be set to be smaller than the number of tiles 10 included in the second set. That is, for the tiles 10 other than the tiles 10 included in the first set, the tiles 10 that are closer to the side SD, the number of tiles 10 that are included in the same set is larger, and the tiles 10 that are farther from the side SD are the same. The groups may be grouped so that the number of tiles 10 included in the group is small.

  In FIG. 17, the set P73 formed at a position closest to the side SD constituted by the plurality of input / output units 30 to be used is adjacent to the set P73 in the orthogonal direction of the side SD and is closer to the side SD than the set P73. Description will be made by paying attention to the set P74 formed at a far position and the set P75 which is adjacent to the set P74 in the orthogonal direction of the side SD and is further away from the side SD than the set P74. The set P73 is configured by any q tiles 10 among the plurality of tiles 10 having an operation probability equal to or higher than the first reference value. The set P74 is configured by any r tiles 10 among the plurality of tiles 10 having an operation probability equal to or higher than the second reference value and lower than the first reference value. The set P75 includes any s tiles 10 among the plurality of tiles 10 having an operation probability less than the second reference value. The number q of tiles 10 included in the set P73 is 1 or more and is smaller than the number r of tiles 10 included in the set P74. The number r of tiles 10 included in the set P74 is greater than one. The number s of tiles included in the set P75 is 1 or more and is smaller than the number r of tiles 10 included in the set P74.

  In the example of FIG. 17, for the set P73, a power control circuit 4020 that controls supply and stop of power to the q tiles 10 included in the set P73 is provided. The basic configuration of power supply control circuit 4020 is the same as that of power supply control circuit 40 shown in FIG. 5, except that power supply control circuit 4020 supplies power supply potential VD to each of q tiles 10 included in set P73. Common control of stopping. Further, for the set P74, a power control circuit 4030 for controlling the supply and stop of power to the r tiles 10 included in the set P74 is provided. The basic configuration of power supply control circuit 4030 is the same as that of power supply control circuit 40 shown in FIG. 5, except that power supply control circuit 4030 supplies power supply potential VD to each of r tiles 10 included in set P74. Common control of stopping. Further, for the set P75, a power supply control circuit 4040 for controlling power supply to the s tiles 10 included in the set P75 is provided. The basic configuration of the power supply control circuit 4040 is the same as that of the power supply control circuit 40 shown in FIG. 5, but the power supply control circuit 4040 supplies the power supply potential VD to each of the s tiles 10 included in the set P75. Common control of stopping.

  That is, the FPGA of the present embodiment includes a first circuit group (for example, the set P73) including at least one logical block LB (“first logical block”) and a larger number of logical blocks LB (“ 2nd logic block "), and the 2nd circuit group (for example, set P74) arrange | positioned in the position far from the input / output part 30 used rather than the 1st circuit group, and a number smaller than a 2nd logic block A logic block LB (“third logic block”) is included, and is considered to include a fourth circuit group (for example, a set P75) disposed farther from the input / output unit 30 to be used than the second circuit group. Can do.

  The first circuit group includes a connection between any one of the first logic block, the second logic block, and the fourth logic block and the input / output unit 30, a connection between the first logic blocks, a second logic block, or a fourth logic block. A switch (which may be singular or plural) for switching the connection of wiring (which may be singular or plural) used for at least one of the connections between the logical block and the first logical block according to programmable control data is included. The first switch block (in this example, the switch block SB included in each of the q tiles 10 included in the set P73) and the first logical block (in this example, the set P73 included in the set P73) The logic block LB) and the first switch block included in each of the q tiles 10 included are commonly controlled to supply and stop power. Power control circuit (in this example, the power supply control circuit 4020) having a. In addition, the second circuit group includes a connection between any one of the first logic block, the second logic block, and the fourth logic block and the input / output unit 30, a connection between the second logic blocks, a first logic block, or a fourth logic block. Includes a switch (single or plural) that switches connection of wiring (single or plural) used for at least one of the connections between the logical block and the second logical block according to programmable control data The second switch block (in this example, the switch block SB included in each of the r tiles 10 included in the set P74) and the second logic block (in this example, the set P74 included in the set P74) A second block for commonly controlling power supply and stop for the logical block LB) and the second switch block included in each of the r tiles 10 included. (In this example, the power supply control circuit 4030) source control circuit having. Further, the fourth circuit group includes a connection between the first logic block, the second logic block, and the fourth logic block and the input / output unit 30, a connection between the fourth logic blocks, the first logic block, Switch (single or plural) for switching the connection of wiring (single or plural) used for at least one of the connections between the second logical block and the fourth logical block according to programmable control data (In this example, the switch block SB included in each of the s tiles 10 included in the set P75) and the fourth logic block (in this example, the set Power supply and stop are commonly controlled for the logical block LB) and the fourth switch block included in each of the s tiles 10 included in P75. (In this example, the power supply control circuit 4040) fourth power supply control circuit can be regarded as having.

  Further, the FPGA 100 according to the present embodiment includes a first circuit group (for example, the set P75) including at least one logical block LB (“first logical block”) and a larger number of logical blocks LB (“ 2nd logic block "), and the 2nd circuit group (for example, set P74) arrange | positioned in the position near the input / output part 30 used rather than the 1st circuit group, and a smaller number than a 2nd logic block A logic block LB (“fifth logic block”) is included, and is considered to include a fifth circuit group (for example, a set P73) disposed closer to the input / output unit 30 to be used than the second circuit group. You can also.

  The first circuit group includes a connection between any one of the first logic block, the second logic block, and the fifth logic block and the input / output unit 30, a connection between the first logic blocks, a second logic block, Switch (single or plural) for switching the connection of wiring (single or plural) used for at least one of the connections between the fifth logical block and the first logical block according to programmable control data (In this example, the switch block SB included in each of the s tiles 10 included in the set P75) and the first logic block (in this example, the set block) included in the first circuit group. Power supply and stop are commonly controlled for the logical block LB) and the first switch block included in each of the s tiles 10 included in P75. (In this case, the power supply control circuit 4040) the first power control circuit having a. The second circuit group includes a connection between any one of the first logic block, the second logic block, and the fifth logic block and the input / output unit 30, a connection between the second logic blocks, the first logic block, Switch (single or plural) for switching the connection of wiring (single or plural) used for at least one of the connections between the fifth logical block and the second logical block according to programmable control data Including a second switch block (in this example, a switch block SB included in each of the r tiles 10 included in the set P74) and a second logic block (in this example, the set Power supply and stop are commonly controlled for the logical block LB) and the second switch block included in each of the r tiles 10 included in P74. (In this example, the power supply control circuit 4030) 2 power supply control circuit having a. Further, the fifth circuit group includes a connection between any of the first logic block, the second logic block, and the fifth logic block and the input / output unit 30, a connection between the fifth logic blocks, the first logic block, Switch (single or plural) for switching the connection of wiring (single or plural) used for at least one of the connections between the second logical block and the fifth logical block according to programmable control data (In this example, the switch block SB included in each of the q tiles 10 included in the set P73) and the fifth logic block (in this example, the set P73) included in the fifth circuit group. The logic block LB) and the fifth switch block included in each of the q tiles 10 included in the first tile 10 are commonly controlled to supply and stop power. Power control circuit (in this example, the power supply control circuit 4020) can be regarded as having.

  For example, when four sides (SD1 to SD4) composed of a plurality of input / output units 30 arranged so as to surround the array unit 20 are used, a set may be formed as shown in FIG. (Grouping may be performed).

  For example, when the side SD1, the side SD2, and the side SD4 are used, a set may be formed as shown in FIG. In the example of FIG. 19, the logical block LB included in the rectangular area Tx in the vicinity of the side SD1 is used, and the side SD2 extends from the corner C2 between the side SD1 and the side SD2 by a predetermined distance along the side SD2. It is assumed that the existing part PSD2 is used and the part PSD4 extending from the corner C1 between the side SD1 and the side SD4 by a predetermined distance is used from the corner C1. More specifically, it is assumed that the input / output unit 30 configuring PSD2 and PSD4 is used in addition to the side SD1, while the logical block LB used is only the logical block LB in the region Tx. That is, in this example, PSD2 and PSD4 are used as wirings, and a plurality of sets formed at positions closest to the partial PSD2 are formed so that a wiring path from the logical block LB in the region Tx to the partial PSD2 is formed. Each of the tiles 10 (switch block SB) included in each of them operates. Similarly, the tiles 10 included in each of the plurality of sets formed at positions closest to the partial PSD4 operate so that a wiring path from the logical block LB in the region Tx to the partial PSD4 is formed.

  In the example of FIG. 19, the number of tiles 10 included in the set (referred to as “first set”) formed at the position closest to the input / output unit 30 used is adjacent to the first set. Since the number of tiles 10 included in the second set formed at a position farther from the input / output unit 30 than the first set is smaller than the number of tiles 10 included in the first set, the number of tiles 10 included in the first set is another set. Compared to the case where the number of tiles 10 included in the group is larger than the number of tiles 10 included in the first group (when the number of tiles 10 included in the first group is the largest), the power consumption is reduced. Can be reduced. That is, in the example of FIG. 19, by reducing the number of tiles 10 included in the first set formed at the position closest to PSD2 (PSD4) used as wiring, the number of tiles 10 used as wiring is reduced. The number is decreasing. Thereby, power consumption can be reduced.

  As mentioned above, although each embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  In short, the FPGA to which the present invention is applied has two sets ("first circuit group") in which the number of tiles 10 (the number of logic blocks LB that can realize a specific logic) with which the power supply control circuit is shared is different. , “Second circuit group”). Thereby, the circuit scale can be reduced as compared with the case where the power supply control circuit is provided individually for each unit capable of realizing the specific logic.

  Further, in each of the above embodiments and modifications, each set formed in the FPGA is divided by a plurality of straight lines extending in the row direction and a plurality of straight lines extending in the column direction. Not limited to this, for example, as shown in FIG.

  Further, in the example of FIG. 5 described above, the switch element 41 is configured by a P-type MOSFET, but the configuration of the switch element 41 is not limited to this and is arbitrary. In short, the power supply control circuit 40 may have any configuration that can control the supply and stop of power to the corresponding set P1, and the configuration is not limited to the configuration in FIG. In the following variation examples, a case where the number of tiles 10 included in the set P1 corresponding to the switch element 41 is three will be described as an example.

  For example, as shown in FIG. 21, the switch element 41 may be configured by an N-type MOSFET. Further, when the switch element 41 is composed of an N-type MOSFET, for example, as shown in FIG. 22, a power supply line (not shown) to which a power supply potential VD is supplied and a ground potential GND (for example, 0 V) are supplied. The configuration may be such that the set P1 is disposed between the ground line 102 and the power supply control circuit 40 is disposed between the set P1 and the ground line 102.

  For example, as shown in FIGS. 23 and 24, a switch element 41 formed of a P-type MOSFET or an N-type MOSFET is provided between each of the three tiles 10 included in the set P1 and the power supply line 101. May be provided individually. In this configuration, the gates of the three switch elements 41 are commonly connected to the control circuit 42, and the on / off states of the three switch elements 41 are controlled simultaneously according to the switch control signal from the control circuit 42. Even with this configuration, only one control circuit 42 is provided corresponding to the set P1, so that the circuit scale can be reduced as compared with the case where the control circuit 42 is provided for each tile 10 individually. However, as in the above-described embodiments and modifications, the switch element 41 that switches the supply and stop of power to each of the three tiles 10 included in the set P1 is shared, thereby further reducing the circuit scale. It becomes possible.

  Further, for example, as shown in FIG. 25, the switch element 41 formed of an N-type MOSFET is individually provided between each of the three tiles 10 included in the set P1 and the ground line 102. May be.

10 tile 20 array unit 30 input / output unit 40 power control circuit 41 switch element 42 control circuit 50 power control circuit 101 power line 102 ground line

Claims (9)

A first circuit group including at least one first logic block;
A second circuit group including a larger number of second logic blocks than the first logic block;
An input / output unit having a function of inputting input data to the first logic block or the second logic block, and a function of outputting output data output from the first logic block or the second logic block to the outside; Including,
The first circuit group includes:
At least one of the connection between the first logic block or the second logic block and the input / output unit, the connection between the first logic blocks, and the connection between the first logic block and the second logic block. A first switch block including a switch for switching the wiring connection used according to programmable control data;
A first power supply control circuit for commonly controlling supply and stop of power to the first logic block and the first switch block included in the first circuit group,
The second circuit group includes:
At least one of the connection between the first logic block or the second logic block and the input / output unit, the connection between the second logic blocks, and the connection between the first logic block and the second logic block. A second switch block including a switch for switching the wiring connection used according to programmable control data;
A second power supply control circuit for commonly controlling supply and stop of power to the second logic block and the second switch block included in the second circuit group,
Semiconductor integrated circuit. The second circuit group is disposed closer to the input / output unit for inputting the input data or outputting the output data than the first circuit group.
The semiconductor integrated circuit according to claim 1. The input / output that includes the number of third logic blocks that is greater than the first logic block and less than the second logic block, and that inputs the input data or outputs the output data from the second circuit group. A third circuit group disposed at a position far from the input unit, and disposed closer to the input / output unit for inputting the input data or outputting the output data than the first circuit group,
The third circuit group includes
Connection between any of the first logic block, the second logic block, and the third logic block and the input / output unit, connection between the third logic blocks, the first logic block, or the second logic block And a third switch block including a switch for switching the connection of the wiring used for at least one of the connections to the third logic block according to programmable control data;
A third power supply control circuit for commonly controlling supply and stop of power to the third logic block and the third switch block included in the third circuit group,
The semiconductor integrated circuit according to claim 2. The first circuit group is disposed closer to the input / output unit for inputting the input data or outputting the output data than the second circuit group.
The semiconductor integrated circuit according to claim 1. There is no circuit group including other logic blocks between the input / output unit that inputs the input data or outputs the output data and the first circuit group.
The semiconductor integrated circuit according to claim 4. The fourth logic block includes a smaller number of fourth logic blocks than the second logic block, and is arranged at a position farther from the input / output unit that inputs the input data or outputs the output data than the second circuit group. Further comprising four circuit groups,
The fourth circuit group includes:
Connection between any one of the first logic block, the second logic block, and the fourth logic block and the input / output unit, connection between the fourth logic blocks, the first logic block, or the second A fourth switch block including a switch for switching connection of wiring used for at least one of the connection between the logic block and the fourth logic block according to programmable control data;
A fourth power supply control circuit for commonly controlling supply and stop of power to the fourth logic block and the fourth switch block included in the fourth circuit group,
The semiconductor integrated circuit according to claim 5. The fifth logic block includes a smaller number of fifth logic blocks than the second logic block, and is arranged closer to the input / output unit that inputs the input data or outputs the output data than the second circuit group. Further comprising five circuit groups,
The fifth circuit group includes:
Connection between any of the first logic block, the second logic block, and the fifth logic block and the input / output unit, connection between the fifth logic blocks, the first logic block, or the second A fifth switch block including a switch for switching connection of wiring used for at least one of the connection between the logic block and the fifth logic block according to programmable control data;
A fifth power supply control circuit for commonly controlling supply and stop of power to the fifth logic block and the fifth switch block included in the fifth circuit group,
4. The semiconductor integrated circuit according to claim 2 or 3. The logic block included in the second circuit group has a higher operation probability indicating the possibility that the logic block included in the first circuit group operates by being supplied with power.
The semiconductor integrated circuit according to claim 2. The motion probability is represented by the following equation:
The semiconductor integrated circuit according to claim 7.
f (D) = 1 / [exp {(D−μ) / C} +1]
Here, f (D) indicates the operation probability of the logical block arranged at a distance D from the input / output unit that inputs the input data or outputs the output data, and μ indicates the logical block , Indicates the distance from the input / output unit when used in order from the closest to the input / output unit, and C is a constant indicating the ease of leaving the logic block from the input / output unit.