JP2013114446A - Semiconductor device, optical disk device, and testing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of accurately generating a reference current while reducing a cost, and further to provide an optical disk device and a testing method of the semiconductor device.SOLUTION: A semiconductor device 100 includes: a current generation circuit which generates a reference current; an external terminal T1 through which the generated reference current is outputted to a tester 300; an external terminal T2 to which current control data for controlling a current value of the reference current is set by the tester 300 in accordance with the reference current outputted through the external terminal T1; and a current control unit 14 which adjusts the reference current generated by the current generation circuit to a prescribed value in accordance with the current control data set by the tester 300.

Description

  The present invention relates to a semiconductor device, an optical disc device, and a semiconductor device test method, and more particularly to a semiconductor device having a current generation circuit that generates a predetermined current, an optical disc device, and a semiconductor device test method.

  In recent years, in various electronic devices such as an optical disk device, the operation speed has been rapidly increased with an increase in the amount of information to be handled. For this reason, in order to operate stably at higher speed, it is strongly desired to reduce variation in characteristics of semiconductor devices mounted on electronic equipment.

  For example, the semiconductor device is provided with an oscillation circuit that generates an oscillation clock having a frequency corresponding to a supplied reference current, and a filter circuit having a frequency characteristic corresponding to the supplied reference current. In order to stabilize the characteristics of the oscillation clock and the filter, it is necessary to suppress fluctuations in the characteristics of a constant current circuit (reference current circuit) that generates a constant reference current.

  As a semiconductor device provided with a conventional constant current circuit, for example, the configurations of FIGS. 10 and 11 are known.

  As shown in FIG. 10, a conventional semiconductor device 900 includes a constant current circuit 910 inside the semiconductor device, and a resistor 918 is connected to the outside of the semiconductor device. The constant current circuit 910 includes a constant voltage source (VBG) 911, an operational amplifier 912, PMOS transistors 913 and 914, and NMOS transistors 915 and 916.

  The operational amplifier 912 has a non-inverting (normal) input terminal connected to the constant voltage source 911 and an output terminal commonly connected to the gate of the PMOS transistor 913 and the gate of the PMOS transistor 914. The source of the PMOS transistor 913 and the source of the PMOS transistor 914 are commonly connected to the power supply potential VCC, and the inverting input terminal of the operational amplifier 912 and the drain of the PMOS transistor 913 are connected to the external terminal 917.

  The NMOS transistor 915 and the NMOS transistor 916 have their drains and gates commonly connected to the drain of the PMOS transistor 914 and their sources commonly connected to the ground potential GND. The source of the PMOS transistor 916 is connected to the output destination circuit of the output current Iout. Then, outside the semiconductor device 900, a resistor 918 is connected between the external terminal 917 and the ground potential GND.

  In the constant current circuit 910 of the conventional semiconductor device 900, a current I0 corresponding to the voltage of the constant voltage source 911 and the resistance value of the external resistor 918 is generated. An output current Iout equal to the current I0 is output to another circuit via the PMOS transistors 913, 914 and the NMOS transistors 915, 916.

  As shown in FIG. 11, the conventional semiconductor device 901 includes a constant current circuit 920 inside the semiconductor device. The constant current circuit 920 includes a constant voltage source (VBG) 921, an operational amplifier 922, PMOS transistors 923 and 924, an NMOS transistor 925, and a resistor 926.

  The operational amplifier 922 has a non-inverting input terminal connected to the constant voltage source 921 and an output terminal connected to the inverting input terminal and the gate of the NMOS transistor 925. A resistor 926 is connected between the source of the NMOS transistor 925 and the ground potential GND.

  The sources of the PMOS transistor 923 and the PMOS transistor 924 are commonly connected to the power supply potential VCC, and the gates of the PMOS transistor 923 and the PMOS transistor 924 are commonly connected to the drain of the PMOS transistor 924 and the source of the PMOS transistor 925. The drain of the PMOS transistor 923 is connected to the output destination circuit of the output current Iout.

  In the constant current circuit 920, a current I0 corresponding to the voltage determined from the voltage of the constant voltage source 921 and the threshold voltage Vth of the NMOS transistor 925 and the resistance value of the resistor 926 is generated. Then, an output current Iout equal to the current I0 is output to another circuit via the PMOS transistors 924 and 923.

  Patent Document 1 describes a constant current circuit that trims a current using a trimming circuit.

JP 2010-217963 A

  In the conventional semiconductor device 900 shown in FIG. 10, a resistor 918 is externally attached to the outside of the semiconductor device. The constant current generated by the constant current circuit 910 in the semiconductor device 900 is determined by the voltage of the constant voltage source 911 and the resistance value of the resistor 918. Therefore, by connecting a high-precision resistor with small characteristic variation as the resistor 918, fluctuations in the output current of the constant current circuit 910 can be suppressed. Since the resistor 918 does not change in characteristics due to manufacturing variations of semiconductor devices, a constant current can be generated even when the manufacturing process (fab) is changed.

  However, the conventional semiconductor device 900 requires an external terminal for connecting an external resistor. If an external terminal dedicated to an external resistor is provided in the semiconductor device, the number of external terminals increases, which hinders downsizing and cost reduction of the semiconductor device. In particular, in recent years, the number of external terminals has been decreasing with the miniaturization of semiconductor devices, so it has become difficult to provide external terminals dedicated to external resistors. Further, in the conventional semiconductor device 900, it is necessary to prepare a highly accurate resistor with little characteristic variation as a resistor to be connected to the outside, and since such a resistor is generally high in cost, there is a problem that the cost increases. .

  On the other hand, the conventional semiconductor device 901 illustrated in FIG. 11 does not require an external terminal and does not need to provide an external resistor as compared with the conventional semiconductor device 900, so that the cost is lower than that of the semiconductor device 900. It is possible.

  However, in the conventional semiconductor device 901, the resistance 926 is affected by characteristic fluctuations due to manufacturing variations and the like, so that the characteristic fluctuations when the manufacturing process is changed are large, and the output current of the constant current circuit 920 is large. There's a problem. For example, if the absolute value variation of the resistance in the semiconductor device is ± 20%, the output current of the constant current circuit also varies ± 20%.

  As described above, the conventional semiconductor device has a problem that it is difficult to accurately generate the reference current while reducing the cost.

  The semiconductor device according to the present invention includes a current generation circuit (corresponding to the current generation unit 11, the current switching unit 13, and the current output unit 17 in FIG. 3), a first external terminal (corresponding to the external terminal T1 in FIG. 3), a first 2 external terminals (corresponding to the external terminal T2 in FIG. 3) and a current control circuit (corresponding to the current control unit 14 in FIG. 3). The current generation circuit is a current generation circuit that generates a reference current (corresponding to Iout and IREF). The first external terminal is a terminal for outputting the reference current generated by the current generation circuit to the tester. The second external terminal is a terminal set by the tester according to the reference current output from the first external terminal, with current control data for controlling the current value of the reference current generated by the current generation circuit. It is. Further, the current control circuit adjusts the reference current generated by the current generation circuit to a predetermined value according to the current control data set by the tester via the second external terminal. With the above configuration, the current value of the reference current can be trimmed to a constant predetermined value, so that current variations caused by resistance and the like can be prevented and a highly accurate reference current can be generated. In addition, since it is not necessary to prepare a high-precision resistor separately outside, the cost can be reduced.

  Here, the current generation circuit may include a resistance current generation unit (corresponding to the current generation unit 11 in FIG. 3) and a current switching unit (corresponding to the current switching unit 13 in FIG. 3). The resistance current generator generates a resistance current corresponding to the constant voltage by using the resistance. The current switching unit generates the reference current by switching the mirror ratio of the first current mirror circuit that mirrors the resistance current generated by the resistance current generation unit according to the current control data input from the current control circuit. .

  The current generation circuit may further include a current output unit (corresponding to the current output unit 17 in FIG. 3). The current output unit mirrors and outputs the reference current generated by the current switching unit by the second current mirror circuit.

  Further, a cascode transistor (corresponding to the cascode transistor group 20 and the cascode transistor group 21 in FIG. 5) may be connected to the first current mirror circuit or the second current mirror circuit. As a result, the accuracy of the current mirror of the current mirror circuit is improved, so that a more accurate reference current can be generated.

  Further, the semiconductor device may include a current measurement circuit (corresponding to the ammeter in FIG. 6) that measures the reference current generated by the current generation circuit. After the current control data is set by the tester, the current control circuit further adjusts the reference current generated by the current generation circuit to a predetermined value according to the measurement result of the reference current by the current measurement circuit. May be. The semiconductor device may include a temperature sensor (corresponding to the temperature sensor 23 in FIG. 7) that measures temperature. Then, after the current control data is set by the tester, the current control circuit further adjusts the reference current generated by the current generation circuit to the predetermined value according to the temperature measurement result by the temperature sensor. May be. Thus, even after current trimming by a tester, the reference current can be set to a predetermined value in the semiconductor device, so that current variations caused by temperature or the like can be prevented and a more accurate reference current can be generated.

  In the semiconductor device, the tester may perform the memory test and the reference current test in the same process. That is, the tester measures the reference current output from the first external terminal in the memory test process for relieving a defect in the memory included in the semiconductor device, and the second external device is measured according to the measurement result of the reference current. Current control data may be set to the terminals. Thereby, since the test and trimming of the memory and the reference current can be performed together, the test and trimming can be performed efficiently, and the test cost can be reduced.

  An optical disc apparatus according to the present invention includes a pickup that irradiates an optical disc with laser light, and a semiconductor device that controls the operation of the pickup. The semiconductor device includes a current generation circuit, a first external terminal, a second external terminal, a current control circuit, and a signal processing circuit (RF system circuit 113, wobble detection circuit 114, write PLL 115, servo system circuit 116 in FIG. Equivalent). The configurations of the current generation circuit, the first external terminal, the second external terminal, and the current control circuit are the same as those of the semiconductor device. The signal processing circuit processes the signal output from the pickup based on the reference current of the current generation circuit adjusted by the current control circuit. With the above configuration, in the optical disc apparatus, the current value of the reference current can be trimmed to a constant predetermined value, and current variations caused by resistance or the like can be prevented and a highly accurate reference current can be generated. In addition, since it is not necessary to prepare a high-precision resistor separately outside, the cost can be reduced. Then, by stabilizing the reference current, it is possible to suppress the characteristic variation of the signal processing circuit in the optical disc apparatus, and to operate with high accuracy even in the double speed mode or the like.

  A test method for a semiconductor device according to the present invention is a test method for a semiconductor device having a current generation circuit for generating a reference current, a current control circuit for adjusting the generated reference current, and first and second external terminals. . In the method for testing a semiconductor device, first, the tester connects a probe to the first and second external terminals, electrically connects to the current generation circuit via the first external terminal, and connects the second external terminal to the first external terminal. And electrically connected to the current control circuit. Next, the tester determines an initial value of the current control data for controlling the current value of the reference current, and changes the current control data determined as the initial value to the current control circuit via the second external terminal. Set as possible. Next, the current control circuit adjusts the reference current generated by the current generation circuit in accordance with the set current control data. Next, the current generation circuit outputs the reference current adjusted by the current control data to the tester via the first external terminal. Next, the tester measures the current value of the output reference current, and determines the optimum value of the current control data according to the comparison result between the reference current measurement result and the predetermined value. Next, the tester sets the current control data determined as the optimum value to the current control circuit through the second external terminal so as not to be changed. With the above operation, the current value of the reference current can be trimmed to a constant predetermined value, so that a current variation caused by resistance or the like can be prevented and a highly accurate reference current can be generated. In addition, since it is not necessary to prepare a high-precision resistor separately outside, the cost can be reduced.

  According to the present invention, it is possible to provide a semiconductor device, an optical disk device, and a test method for a semiconductor device that can generate a reference current with high accuracy while reducing costs.

1 is a block diagram showing a configuration of an optical disc device according to Embodiment 1 of the present invention. 3 is a graph showing signal characteristics of the optical disc device according to Embodiment 1 of the present invention. 1 is a circuit diagram showing a circuit configuration of a semiconductor device according to a first embodiment of the present invention. 3 is a flowchart showing a test method (trimming method) for a semiconductor device according to the first embodiment of the present invention; It is a circuit diagram which shows the circuit structure of the semiconductor device which concerns on Embodiment 2 of this invention. It is a circuit diagram which shows the circuit structure of the semiconductor device which concerns on Embodiment 3 of this invention. It is a circuit diagram which shows the circuit structure of the semiconductor device which concerns on Embodiment 4 of this invention. It is a block diagram which shows the test structure of the semiconductor device which concerns on Embodiment 5 of this invention. It is a flowchart which shows the test method (trimming method) of the semiconductor device which concerns on Embodiment 5 of this invention. It is a circuit diagram which shows the circuit structure of the conventional semiconductor device. It is a circuit diagram which shows the circuit structure of the conventional semiconductor device.

(Embodiment 1 of the present invention)
Embodiment 1 of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of an optical disc apparatus (optical disc system) 1 according to Embodiment 1 of the present invention. As shown in FIG. 1, the optical disc apparatus 1 includes a semiconductor device 100 and a pickup 200.

  The pickup 200 is an optical pickup that irradiates the optical disc with laser light in accordance with control from the semiconductor device 100. The pickup 200 includes a photoelectric conversion circuit OEIC 201, a front monitor diode FMD 202, and a laser diode driver LDD 203. In addition, the pickup 200 is provided with a laser diode that irradiates the optical disk with laser light, a servo mechanism (actuator) that aligns in the focus direction and the tracking direction, and the like (not shown).

  The laser diode driver LDD 203 is a drive circuit that drives the laser diode. The front monitor diode FMD 202 is a detection circuit that detects reflected light from the optical disk in order to adjust the emission intensity of the laser diode.

  The photoelectric conversion circuit OEIC 201 is a conversion circuit that converts light reflected from an optical disk into an electrical signal. For example, a detection circuit (photodetector) for detecting reflected light from an optical disk is divided into four areas A, B, C, and D in a square shape. The photoelectric conversion circuit OEIC 201 outputs signals A, B, C, and D detected in each of the four regions as electric signals. In addition to the signals A, B, C, and D, it is also possible to output an RF (Radio Frequency) signal indicating data.

  The semiconductor device 100 includes an AFE (Analog Front End) unit 110 and a DSP (Digital Signal Processor) unit 120. In addition, the semiconductor device 100 has external terminals T1 and T2 for connecting to an external device. As will be described later, the external terminals T1 and T2 are used as test terminals only during testing (trimming), and can be used as normal external terminals for each internal circuit to perform input / output with the outside during normal operation. It is.

  The AFE unit 110 is an analog circuit that converts each signal input from the pickup 200 into a signal that can be processed by the DSP unit 120. The DSP unit 120 is a digital circuit that performs arithmetic processing based on each signal of the pickup 200 input via the AFE unit 110 and performs data read / write, servo control, and the like.

  For example, the semiconductor device 100 is a SoC (System on Chip) or SiP (System in Package) semiconductor device. The semiconductor chip may include one semiconductor chip including the AFE unit 110 and the DSP unit 120, the semiconductor chip of the AFE unit 110 and the semiconductor chip of the DSP unit 120 may be configured as one package, or the semiconductor of the AFE unit 110. The chip, the semiconductor chip of the DSP unit 120, and the semiconductor chip of the memory 127 may be configured as one package.

  The AFE unit 110 includes a reference current generation circuit 10, a reference voltage generation circuit 111, an interface IF 112, an RF system circuit 113, a wobble detection circuit 114, a write PLL 115, a servo system circuit 116, and an APC circuit (automatic power control circuit) 117. ADC (A / D converter) 118 is provided. The AFE unit 110 also includes an analog register 128 a that is a part of the register 128.

  The reference current generation circuit 10 is a constant current circuit that generates a constant reference current IREF (constant current) and supplies the reference current IREF (bias current) to each circuit of the AFE unit 110 and the DSP unit 120 in the semiconductor device 100. is there. As will be described later, the reference current generation circuit 10 can variably set the reference current IREF in accordance with the current code value (current control data) held in the register 128. The reference current generation circuit 10 is connected to the external terminal T1, and outputs the generated reference current IREF to an external tester via the external terminal T1 during the test.

  The reference voltage generation circuit 111 is a constant voltage circuit that generates a constant reference voltage VREF (constant voltage) and supplies the reference voltage VREF (bias voltage) to each circuit of the AFE unit 110 and the DSP unit 120 in the semiconductor device 100. is there. The reference voltage generation circuit 111 is a band gap voltage generation circuit that generates a band gap voltage VBG with little variation due to temperature or the like as the reference voltage VREF.

  The interface IF 112 is an interface with the pickup 200. Each signal that has been photoelectrically converted by the photoelectric conversion circuit OEIC 201 of the pickup 200 is input to the RF system circuit 113 that processes each signal by performing level conversion and the like, and a wobble detection circuit. 114, and output to the servo system circuit 116. That is, the interface IF 112 outputs an RF signal, a wobble signal, a focus error signal, a tracking error signal, and the like from the signals A, B, C, and D to each circuit. When an RF signal is input from the pickup 200, the interface IF 112 outputs the input RF signal to the RF system circuit 113.

  The RF system circuit 113 generates a reproduction data signal indicating data from the RF signal. The RF circuit 113 uses the input signal when an RF signal is input from the interface IF 112, and calculates the signal (A + B + C + D) when the signals A, B, C, and D are input, for example. An RF signal is generated from The RF circuit 113 includes a filter that operates according to the reference current IREF. The RF system circuit 113 removes a predetermined frequency component from the RF signal using a filter, extracts an envelope, and generates a reproduction data signal.

  The wobble detection circuit 114 detects a wobble indicating an address and synchronization timing on the optical disc from a signal input from the interface IF 112 and generates a wobble signal. The wobble detection circuit 114 includes a filter that operates in accordance with the reference current IREF. For example, the wobble detection circuit 114 calculates a signal (A + D) − (B + C), removes a predetermined frequency component from the calculated signal by a filter, extracts an envelope, and generates a wobble signal.

  The write PLL 115 generates a write clock for writing on the optical disc based on the wobble signal generated by the wobble detection circuit 114. The write PLL 115 has an oscillation circuit that operates according to the reference current IREF. When the wobble signal is input, the write PLL 115 repeatedly oscillates by the oscillation circuit to be locked and generates a write clock.

The servo system circuit 116 generates a servo control signal for servo control from the signal input by the interface IF 112. The servo system circuit 116 has a DPD circuit that detects a phase difference. For example, the servo system circuit 116 generates a tracking error signal TE for controlling in the tracking direction from the calculation of the signal (A + B) − (C + D), and controls in the focus direction from the calculation of the signal (A + C) − (B + D). A focus error signal FE is generated, a DPD signal for servo control is generated from the phase difference between the signals (A + C) and (B + D), and is output as a servo control signal.
The APC circuit (automatic power control circuit) 117 receives a laser diode emission intensity detected by the front monitor diode FMD202, and a laser diode driver so that the laser diode has a predetermined emission intensity according to the detected emission intensity. A light emission control signal for controlling light emission is output to the LDD 203.

  The ADC 118 converts a servo control signal from the servo system circuit 116 and an analog signal output from the APC circuit 117 into a digital signal, and outputs the digital signal to the servo DSP 125 and the CPU 126 of the DSP unit 120. Note that the data processing of the ADC 118 can be configured by an analog circuit or a digital circuit, and therefore may be provided in the AFE unit 110 or the DSP unit 120.

  The DSP unit 120 includes a data strobe circuit 121, a decoder 122, an encoder 123, an ATIP / ADIP circuit 124, a servo DSP 125, a CPU 126, a memory 127, and a register 128.

  The data strobe circuit 121 generates a data strobe signal indicating the timing for decoding data from the reproduction data signal generated by the RF system circuit 113. Based on the timing of the data strobe signal generated by the data strobe circuit 121, the decoder 122 decodes the reproduction data signal by decompression / decoding processing or the like to generate read data. The read data is stored in the memory 127 and output to an external data processing device or the like.

  The encoder 123 encodes write data stored in the memory 127 from an external data processing device or the like by compression / encoding processing or the like, and generates write data. The write data is output to the pickup 200 via the interface IF 112 and written to the optical disc based on the write clock generated by the write PLL 115.

  The ATIP / ADIP circuit 124 performs ATIP demodulation and ADIP demodulation on the wobble signal generated by the wobble detection circuit 114 to generate address information and absolute position information. Write data is written based on the address information and absolute position information.

  The servo DSP 125 controls the servo of the pickup 200 based on the servo control signal input via the ADC 118 and adjusts the position of the pickup 200. The servo DPS 125 performs arithmetic processing based on the tracking error signal TE, the focus error signal FE, the DPD signal, etc., and controls the tracking servo and the focus servo to align the pickup 200.

  The CPU 126 is an arithmetic processing unit that executes a program stored in the memory 127 and performs arithmetic processing according to the program to control the operation of the entire system. The memory 127 is composed of a flash memory, SDRAM, or the like, stores various programs and data, and stores optical disk read data, write data, and the like.

  The register 128 holds data used for arithmetic processing in the CPU 126 and data necessary for each circuit. The register 128 includes an analog register 128a configured with an analog circuit and a digital register 128b configured with a digital circuit.

  In such a semiconductor device 100, in this embodiment, the reference current IREF generated by the reference current generation circuit 10 is mainly supplied to the RF system circuit 113, the wobble detection circuit 114, the write PLL 115, and the servo system circuit 116. Yes. By supplying the reference current IREF to these circuits and controlling the current of the circuit operation, it is possible to cope with a wide dynamic range and to reduce the necessary power supply voltage as compared with the case of voltage control.

  In the RF system circuit 113 and the wobble detection circuit 114, the reference current IREF is supplied to the internal filter. This filter is, for example, a gmc filter, which operates according to an input reference current IREF, and changes frequency characteristics such as a boost amount, a boost frequency, and a cutoff frequency by switching a filter setting using the reference current IREF. be able to.

  FIG. 2 shows the frequency characteristics of the RF signal in the RF system circuit 113. In the optical disc apparatus, the reading speed can be selected, and the frequency characteristics of the RF signal differ depending on the selected reading speed. For example, FIG. 2 (a) is an RF signal before boosting, FIG. 2 (b) is an RF signal when reading in a 4 × speed mode of a certain optical disk, and FIG. 2 (c) is an RF signal when reading in an 8 × speed mode. It is a frequency characteristic of a signal.

  The RF system circuit 113 sets the filter characteristics in accordance with the frequency characteristics of the RF signal. That is, as shown in FIGS. 2B and 2C, in the double speed mode, the filter is set to boost the frequency according to the double speed number. In other double speed modes, it is necessary to boost or cut other frequencies.

  Accordingly, the RF circuit 113 and the wobble detection circuit 114 need to boost or cut the filter characteristics depending on the double speed mode, and more accurate characteristics are required. Therefore, it is necessary to suppress variations in the reference current IREF supplied to the filter. There is.

  In the servo system circuit 116, offset adjustment of the DC signal input from the pickup, bias adjustment of the input buffer, and the like are performed according to the reference current IREF. Therefore, in order for the servo system circuit 116 to generate the servo control signal from the input signal with high accuracy, it is necessary to suppress variations in the reference current IREF.

  Note that the ADC 118 may not normally perform A / D conversion if the level varies for each of a plurality of servo control signals output from the servo system circuit 116, so that the level of the servo control signal is kept constant. However, it is necessary to suppress variations in the reference current IREF supplied to the servo system circuit 116.

  The write PLL circuit 115 generates a write clock having a predetermined frequency based on the wobble signal in accordance with the reference current IREF. Therefore, in order for the write PLL circuit 115 to accurately generate a write clock synchronized with the wobble signal, it is necessary to suppress variations in the reference current IREF.

  For this reason, in this embodiment, in order to improve the accuracy of the reference current IREF and stably operate the RF system circuit 113, the wobble detection circuit 114, the write PLL 115, the servo system circuit 116, etc., the following configuration is adopted. did. FIG. 3 shows the circuit configuration of the reference current generation circuit 10 according to the first embodiment of the present invention and the connection state of the tester 300 during the test.

  As shown in FIG. 3, the reference current generation circuit 10 in the semiconductor device 100 includes a current generation unit 11, a current switching unit 13, a current control unit 14, and a current output unit 17. For example, the current generation unit 11, the current switching unit 13, and the current output unit 17 are current generation circuits that generate the reference current IREF, and the current control unit 14 sets the reference current IREF to a predetermined value according to the current code value. It is a current control circuit that adjusts so that.

  The current generation unit (resistance current generation unit) 11 generates a current I0 mainly including variations due to resistance based on the constant voltage VBG and the resistance. The current generator 11 includes a constant voltage source 12, an operational amplifier OP1, a PMOS transistor P0, and a resistor R1.

  The constant voltage source 12 is a band gap voltage generation circuit that generates a constant voltage (band gap voltage) VBG as a constant voltage. The constant voltage source 12 has a circuit configuration such that voltage fluctuation due to manufacturing variations is small and voltage fluctuation is small even with respect to temperature change. For example, the constant voltage source 12 corresponds to the reference voltage generation circuit 111 of FIG. 1, and the constant voltage VBG is the reference voltage VREF itself generated by the reference voltage generation circuit 111 or a predetermined voltage based on the reference voltage VREF. Voltage.

  The operational amplifier OP1 is a differential amplifier circuit that outputs an output signal obtained by differentially amplifying input signals input to the non-inverting input terminal and the inverting input terminal from the output terminal. The operational amplifier OP1 receives the band gap voltage VBG from the constant voltage source 12 at the non-inverting input terminal. The PMOS transistor P0 has a source connected to the power supply potential VCC, a gate connected to the output terminal of the operational amplifier OP1, and a drain (node ND1) connected to the inverting input terminal of the operational amplifier OP1 and one end of the resistor R1.

  The other end of the resistor R1 is connected to the ground potential GND. The resistor R1 is a polysilicon resistor formed of polysilicon. The resistance value of the resistor R1 has an absolute value variation mainly caused by the manufacturing process, and also has a variation due to a temperature change.

  In the operational amplifier OP1, since a feedback signal is input from the node ND1 to the inverting input terminal, the operational amplifier OP1, the PMOS transistor P0, and the resistor R1 constitute a negative feedback amplifier circuit. Then, the operational amplifier OP1 is in an imaginary short state, the voltages at the non-inverting input terminal and the inverting input terminal are the same, and the voltage at the node ND1 between the PMOS transistor P0 and the resistor R1 is equal to the constant voltage VBG. Therefore, a current I0 (resistance current) corresponding to the constant voltage VBG and the resistance value of the resistor R1 flows through the resistor R1 and the PMOS transistor P0. For example, if the constant voltage VBG = 1.25 V and the resistance R1 = 12.5 KΩ, the current I0 = 100 μA.

  The current switching unit (current selection unit) 13 switches the current value according to the current code value based on the current I0 generated by the current generation unit 11, and generates the output current Iout. The current switching unit 13 generates the output current Iout by switching the mirror ratio of the current mirror circuit that mirrors the current I0 according to the current code value. The current switching unit 13 is also a current DAC (D / A converter) that outputs an analog current corresponding to the digital value of the current code value. The current switching unit 13 includes PMOS transistors P1 to P5 and switches SW1 to SW5.

  In the PMOS transistors P1 to P5, the sources are commonly connected to the power supply potential VCC, the gates are commonly connected to the gate of the PMOS transistor P0, and the drains are nodes ND2 that generate the output current Iout via the switches SW1 to SW5, respectively. (Reference current generation node).

  The PMOS transistor P0 and the PMOS transistors P1 to P5 constitute a first current mirror circuit connected in a current mirror. Therefore, currents I1 to I5 corresponding to the transistor size ratio between the PMOS transistor P0 and the PMOS transistors P1 to P5 are generated in the PMOS transistors P1 to P5 with respect to the current I0 of the PMOS transistor P0. Then, the current obtained by adding the currents I1 to I5 at the node ND2 becomes the output current Iout. For this reason, the output current Iout can be varied by switching the on / off of the switches SW1 to SW5 and selecting the total currents I1 to I5.

  Here, the switch SW1 is always on, and the switches SW2 to SW5 can be switched. Each bit of the 4-bit current code value is associated with the switches SW2 to SW5 and the PMOS transistors P2 to P5, and the switches SW2 to SW5 are turned on / off according to the current code value to switch the output current Iout. The switch SW1 may be switchable.

  The MSB (most significant bit) of the current code value corresponds to the switch SW2 and the PMOS transistor P2, and the LSB (lowest bit) of the current code value corresponds to the switch SW5 and the PMOS transistor P5. The size ratio (current mirror ratio) of the PMOS transistors P2: P3: P4: P5 is 8: 4: 2: 1, and the ratio of currents I2: I3: I4: I5 is also 8: 4: 2: 1. . Thereby, the current Iout corresponding to the numerical value of each bit of the current code value is generated.

  For example, the currents of the PMOS transistors P0 to P5 are I0 = 100 μA, I1 = 78 μA, I2 = 24 μA, I3 = 12 μA, I4 = 6 μA, and I5 = 3 μA. The W / L size of the reference PMOS transistor P5 is set as a reference size, and the PMOS transistors P0 to P4 are set according to the current ratio with respect to the PMOS transistor P5. In this case, Iout = 78 μA + (current code value × 3) μA. Therefore, when current code value = (0001), Iout = 78 + 3 = 81 μA, when current code value = (0111), Iout = 78 + 12 + 6 + 3 = 99 μA, and when current code value = (1111), Iout = 78 + 24 + 12 + 6 + 3 = 123 μA.

  The current control unit 14 controls the current value of the current Iout generated by the current switching unit 13 according to the current code value of the fuse register 15 or the interrupt register 16. The current control unit 14 is connected to the switches SW1 to SW5, the fuse register 15 and the interrupt register 16. The current control unit 14 is configured by a logic circuit, generates a control signal corresponding to the current code value held in the fuse register 15 or the interrupt register 16, and switches the switches SW1 to SW5 on / off.

  It can be selected which current code value of the fuse register 15 or the interrupt register 16 is used for current control. For example, a selection control signal for controlling which one to select may be supplied from the CPU to the current control unit 14 and the current code value may be selected according to the selection control signal. Further, the current code value of the fuse register 15 may be set with priority, or the current code value of the interrupt register 16 may be set with priority. In this case, when current code values are set in both registers, the current code value of the priority register is used.

  Further, current control may be performed by the current code values of both the fuse register 15 and the interrupt register 16. For example, the current control may be performed by adding or subtracting the reference value and the correction value using the current code value of the fuse register 15 as a reference value and the current code value of the interrupt register as a correction value.

  The fuse register 15 holds the current code value in a state in which the current code value cannot be fixedly changed by cutting the fuse, and the interrupt register 16 has a state in which the current code value can be dynamically changed by input from a CPU, a tester, or the like. Hold. The fuse register 15 and the interrupt register 16 are connected to the external terminal T2, and a current control value can be written from the tester 300 through the external terminal T2. The external terminal T2 is a register control terminal that controls register writing from the tester 300. The fuse register 15 and the interrupt register 16 correspond to the analog register 128a or the digital register 128b of the register 128 in FIG.

  The current output unit 17 outputs the output current Iout (reference current IREF) generated by the current switching unit 13 to each circuit in the semiconductor device 100 and also outputs it to the outside for testing. The current output unit 17 includes NMOS transistors N1 to N4.

  The drain of the NMOS transistor N1 is connected to the node ND2 and commonly connected to the gates of the NMOS transistors N1 to N4. The sources of the NMOS transistors N1 to N4 are commonly connected to the ground potential GND. The drains of the NMOS transistors N2 to N4 are connected to the output destination circuit of the output current Iout, respectively.

  The NMOS transistor N1 and the NMOS transistors N2 to N4 constitute a second current mirror circuit connected in a current mirror. Therefore, a current corresponding to the transistor size ratio between the NMOS transistor N1 and the NMOS transistors N2 to N4 flows to the NMOS transistors N2 to N4 with respect to the current Iout of the NMOS transistor N1. Here, the NMOS transistors N1 to N4 are all transistors of the same size, and the same output current Iout (reference current IREF) as the current of the NMOS transistor N1 also flows to the NMOS transistors N2 to N4, and enters each connected circuit. Is output. Note that the current based on the output current Iout can be output to each circuit by changing the size of the NMOS transistors N2 to N4.

  The NMOS transistors N2 and N3 are output circuits that output a current Iout (reference current IREF) to the internal circuit of the semiconductor device 100. That is, the current Iout is output to the RF system circuit 113, the wobble detection circuit 114, the write PLL 115, the servo system circuit 116, and the like.

  The NMOS transistor N4 is an output circuit that outputs a current Iout (reference current IREF) to the tester 300 outside the semiconductor device 100. The NMOS transistor N4 is connected to the external terminal T1 through the multiplexer 18 and the internal buffer 19.

  In addition to the NMOS transistor N4, the multiplexer 18 is connected to an internal circuit that performs input / output with an external device during normal operation. The connection between the multiplexer 18 and the external terminal T1, and the connection between the internal buffer 19 and the external terminal T1 are switched by switches SW11 and SW12.

  During normal operation, the multiplexer 18 selects connection with the internal circuit, the switch SW11 is on, and the switch SW12 is off. For this reason, the internal circuit and the external terminal T1 are connected, and the internal circuit and the external device are electrically connected via the external terminal T1. At the time of testing (trimming), when a test selection signal is input to the multiplexer 18 and the switches SW11 and SW12, the multiplexer 18 selects connection with the NMOS transistor N4, the switch SW11 is turned off, and the switch SW12 is turned on. To do. Therefore, the NMOS transistor N4 and the external terminal T1 are connected, and the NMOS transistor N4 and the tester 300 are electrically connected via the external terminal T1, and the output current Iout (reference current IREF) is supplied to the tester 300. Is output.

  Similarly, the connection of the external terminal T1 is switched between the normal operation and the test by the test selection signal, and the fuse register 15 and the interrupt register 16 and the tester 300 are connected via the external terminal T1 only during the test. The

  The tester 300 is a device for testing the operation of the semiconductor device 100, and is a device that measures the output current Iout (reference current IREF) of the reference current generation circuit 10 and performs trimming to obtain a predetermined current. It is.

  The tester 300 has a plurality of probes and connects the probes to the external terminals T1 and T2 of the semiconductor device 100 at the time of a probe test. The tester 300 includes an ammeter 301 and measures the current of the output current Iout output from the NMOS transistor N4 via the external terminal T1. The tester 300 determines a current code value according to the measurement result of the output current Iout so that the output current Iout becomes a predetermined value, and writes the current code value to the fuse register 15 or the interrupt register 16 via the external terminal T2.

  Various methods can be adopted as a method of measuring the output current Iout. For example, a high-precision resistor with little characteristic variation provided on the test board of the tester 300 may be connected to the external terminal T1, and current measurement may be performed using a voltage-converted value. Further, the current Iout may be directly measured by an ammeter included in the tester 300.

  FIG. 4 shows the flow of the test method according to the first embodiment of the present invention. This test method is a method in which the tester 300 trims the reference current IREF of the semiconductor device 100 with the configuration of FIG.

  First, the tester 300 initializes the LSI (S101). In order to trim the reference current IREF, the tester 300 connects the probe to the external terminals T1 and T2, sets the semiconductor device 100 to the test mode, and performs necessary initial settings. Here, the initial value of the current code value is determined. As a 4-bit initial value, a minimum value (0000), a maximum value (1111), a center value (0111 or 1000), or the like can be used. Starting the measurement from the center value is the most efficient test, so the center value is determined as the initial value. Further, when the test of the other semiconductor device 100 is already completed, the current code value trimmed and set in the other semiconductor device 100 may be determined as the initial value.

  Next, the tester 300 sets the current code value in the interrupt register 16 (S102). The tester 300 writes to the interrupt register 16 via the external terminal T2 in order to verify the current code value determined by the determination in S101 or S104. When setting again after the current determination in S104, the current code value is added or subtracted by 1 (1 LSB) in accordance with the magnitude of the measured current measured and the target current, and the currents are sequentially compared. A numerical value greater than 1 may be added or subtracted, or the center value may be selected sequentially to perform a binary search. A value corresponding to the difference from the target value may be added or subtracted. Further, when the test of another semiconductor device 100 has already been completed, the setting may be made based on the value added or subtracted by the other semiconductor device 100.

  Next, the tester 300 measures the current of the reference current IREF of the semiconductor device 100 (S103). The tester 300 measures the reference current IREF output via the external terminal T2 using an ammeter or the like.

  Next, the tester 300 determines the magnitude of the measured reference current IREF (S104). The tester 300 compares the measured current value of the reference current IREF with a target current value to determine whether the reference current IREF is within a target range. For example, it is determined whether the range is ± 1 LSB. That is, if 1LSB is 3 μA, it is determined whether it is in the range of ± 3 μA. If it is within the range of ± 1LSB, the current current code value is determined as the optimum value, and the process proceeds to S105. If it is outside the range of ± 1LSB, S102 and the subsequent steps are repeated to obtain the optimum value of the current code value.

  Next, the tester 300 stores the current code value in the fuse register (trimming memory) 15 (S105) and executes trimming (S106). The tester 300 writes the current code value determined as the optimum value by current measurement into the fuse register 15 via the external terminal T2. As a result, the current code value is fixedly set, and the reference current IREF is trimmed to a current having no absolute value variation.

  As described above, in this embodiment, the reference current of the semiconductor device is measured by the tester, the current code value is determined so that the reference current becomes a predetermined value, and the current code value is set in the semiconductor device. As a result, it is possible to trim current fluctuations caused by variations in the absolute value of resistance, and therefore it is possible to generate an accurate reference current. Since the current is trimmed based on the reference current that is actually output, trimming can be performed including variations in VBG as well as variations in resistance. Further, since it is not necessary to connect a resistor to the outside via an external terminal, it is not necessary to prepare an effective resistor, and an external terminal is not necessary, so that the cost can be reduced.

  In the conventional circuit, for example, when there is ± 20% current variation, it is necessary to increase the power by 20% in consideration of the -20% characteristic in order to secure the required dynamic range and bandwidth. In the embodiment, by trimming and stabilizing the current, the bias current of each block can be minimized, so that power can be reduced.

(Embodiment 2 of the present invention)
The second embodiment of the present invention will be described below with reference to the drawings. FIG. 5 shows a circuit configuration of the reference current generating circuit 10 according to the second embodiment of the present invention, and other configurations are the same as those in the first embodiment.

  In the reference current generation circuit 10 of FIG. 5, in addition to the circuit configuration of FIG. 3, a cascode transistor group 20 including PMOS transistors P11 to P15 (first cascode transistors), NMOS transistors N11 to N12 (second cascode transistors) The cascode transistor group 21 is included.

  As shown in FIG. 5, in the reference current generating circuit 10, PMOS transistors P11 to P15 are connected between the PMOS transistors P1 to P5 and the switches SW1 to SW5, respectively. That is, the PMOS transistors P11 to P15 have their sources connected to the drains of the PMOS transistors P1 to P5, their gates connected to the bias input terminal, and their drains connected to one end of the switches SW1 to SW5, respectively. Yes.

  Therefore, a cascode current mirror circuit is formed that is cascode-connected by the PMOS transistor P0, the PMOS transistors P1 to P5, and the PMOS transistors P11 to P15. Due to the effect of the cascode current mirror circuit, the output resistances of P1 to P5 and P11 to P15 as viewed from ND2 increase, and even when ND2 fluctuates, currents I0 to I5 corresponding to the current mirror ratio can be generated with high accuracy.

  Similarly, in the reference current generation circuit 10, NMOS transistors N11 to N12 are connected between the NMOS transistors N1 to N2 and ND2, respectively. That is, a cascode current mirror circuit is formed which is cascode-connected by NMOS transistors N1 and N2 and NMOS transistors N11 and N12. Therefore, a current corresponding to the current mirror ratio can be generated with high accuracy, and here, the same current Iout as that of the NMOS transistors N1 and N11 is generated in the NMOS transistors N2 and N12. The NMOS transistors N3 and N4 are not shown, but are similarly cascode-connected.

  As described above, in the present embodiment, the current mirror circuit of the reference current generation circuit is a cascode current mirror circuit connected in cascode. Thereby, since the accuracy of the current copy ratio of the current mirror is improved, the reference current IREF can be kept more constant.

(Embodiment 3 of the present invention)
The third embodiment of the present invention will be described below with reference to the drawings. FIG. 6 shows a circuit configuration of the semiconductor device 100 including the reference current generation circuit 10 according to the third embodiment of the present invention, and other configurations are the same as those of the first embodiment. In FIG. 6, as in FIGS. 3 and 4, current trimming has already been performed by the tester, and the current code value is set in the fuse register 15.

  The semiconductor device 100 in FIG. 6 includes an ammeter 22 in addition to the circuit configuration in FIG. 3, and the ammeter 22, ADC 118, CPU 126, and interrupt register 16 are connected in this order.

  The ammeter 22 measures the current value of the current I0 generated by the current generator 11. As a method for measuring the current I0, the current I0 may be directly measured by an ammeter, or the current may be measured using a high-precision resistor with little characteristic variation.

  The measured value of the ammeter 22 is A / D converted by the ADC 118, and the CPU 126 performs arithmetic processing on the A / D converted measured value. The CPU 126 (current calculation processing unit) determines the current code value so that the reference current IREF becomes constant according to the fluctuation of the current value of the current I0, and sets the current code value in the interrupt register 16. The initial value of the current I0 after completion of trimming is compared with the current current I0, and the current code value is determined according to the magnitude of the current value. In addition, you may comprise not only CPU126 but another logic circuit.

  Although the current I0 is measured here, other currents and the like may be measured. For example, the current Iout may be measured and the current may be controlled according to the fluctuation of the current Iout. Further, the characteristic fluctuation of the filter or the oscillation circuit to which the reference current IREF (current Iout) is supplied may be detected, and current control may be performed according to the characteristic fluctuation.

  As described above, in this embodiment, after trimming is completed by the tester, the current is measured inside the semiconductor device and the current is controlled according to the fluctuation of the current value. Thus, even when the current varies due to a temperature change or the like after completion of trimming, the reference current IREF can be kept constant.

(Embodiment 4 of the present invention)
Embodiment 4 of the present invention will be described below with reference to the drawings. FIG. 7 shows a circuit configuration of the semiconductor device 100 including the reference current generation circuit 10 according to the fourth embodiment of the present invention, and the other configurations are the same as those in the first and third embodiments. . In FIG. 6, as in the third embodiment, the current trimming has already been performed by the tester, and the current code value is set in the fuse register 15.

  The semiconductor device 100 of FIG. 7 includes a temperature sensor 23 instead of the ammeter 22 as compared with the configuration of FIG. The temperature sensor 23 can be composed of a diode or the like. Further, as the temperature sensor 23, a temperature sensor built in the constant voltage source 12 may be used.

  The temperature sensor 23 measures the temperature of the semiconductor device 100, and the measurement result is input to the CPU 126 via the ADC 118. The CPU 126 (temperature calculation processing unit) determines the current code value so that the reference current IREF becomes constant according to the temperature variation detected by the temperature sensor 23, and sets the current code value in the interrupt register 16. For example, the temperature code of the resistor R1 is set in advance, and the current code value is determined by obtaining the fluctuation of the resistor R1 from the temperature characteristic according to the detected temperature.

  As described above, in this embodiment, after trimming is completed by the tester, the temperature is measured inside the semiconductor device, and the current is controlled in accordance with the temperature fluctuation. Thus, even when the current varies due to a temperature change after completion of trimming, the reference current IREF can be kept constant.

(Embodiment 5 of the present invention)
Hereinafter, a fifth embodiment of the present invention will be described with reference to the drawings. FIG. 8 shows a connection state between the semiconductor device 100 according to the fifth embodiment of the present invention and the tester 300 during the test. The internal configuration of the semiconductor device 100 is the same as in the first to fourth embodiments.

  As shown in FIG. 8, in the present embodiment, the external terminals T <b> 1 to T <b> 3 of the semiconductor device 100 are connected to the semiconductor device 100 during a probe test of the semiconductor device 100. The reference current generation circuit 10 and the tester 300 are connected via the external terminal T1, the register 128 (interrupt register and fuse register) and the tester 300 are connected via the external terminal T2, and the external terminal T3. The memory 127 and the tester 300 are connected. Then, the tester 300 performs a test of the memory 127 and also performs a trimming test of the reference current IREF of the reference current generation circuit 10 as in FIG.

  FIG. 9 shows a flow of a test method according to the fifth embodiment of the present invention. As shown in FIG. 9, in the memory test process, first, the tester 300 performs a memory test on the semiconductor device 100 (S201) and trims the memory (S202). The tester 300 connects the probe to the external terminals T1 to T3, and sets the semiconductor device 100 to the test mode. The tester 300 performs a test to verify the presence / absence of a defect in the memory 127 via the external terminal T3. When the tester 300 finds a defect in the memory 127, the tester 300 sets memory repair information in the memory 127 to repair the defective memory cell, and performs trimming of the memory.

  Next, the tester 300 performs a reference current test on the semiconductor device 100 (S203), and trims the reference current (S204). Similar to S101 to S106 in FIG. 4, the tester 300 measures the reference current IREF via the external terminal T1, determines the current code value, and determines the optimum current code value via the external terminal T2 in the register 128 ( The reference current is trimmed by setting the fuse register 15).

  In the test method of FIG. 9, the current trimming of S203 to S204 may be performed first, and then the memory trimming of S201 to S202 may be performed. Further, current trimming and memory trimming may be performed simultaneously.

  As described above, in this embodiment, the memory test and trimming and the reference current test and trimming are performed by the same probe test. Since the memory test is a test process that is always necessary for repairing a defect in the memory, it is not necessary to perform a test for the reference current in a separate process, and the test and trimming can be performed efficiently.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention. For example, in the above example, the optical disk device has been described, but other electronic devices having a constant current circuit may be used.

DESCRIPTION OF SYMBOLS 1 Optical disk apparatus 10 Reference current generation circuit 11 Current generation part 12 Constant voltage source 13 Current switching part 14 Current control part 15 Fuse register 16 Interrupt register 17 Current output part 18 Multiplexer 19 Internal buffer 20 Cascode transistor group 21 Cascode transistor group 22 Ammeter 23 Temperature Sensor 100 Semiconductor Device 110 AFE (Analog Front End) Unit 111 Reference Voltage Generation Circuit 112 Interface IF
113 RF system circuit 114 Wobble detection circuit 115 Write PLL circuit 116 Servo system circuit 117 APC circuit 118 ADC
120 DSP (Digital Signal Processor) 121 Data Strobe Circuit 122 Decoder 123 Encoder 124 ATIP / ADIP Circuit 125 Servo DSP
126 CPU
127 Memory 128 Register 128a Analog register 128b Digital register 200 Pickup 201 Photoelectric conversion circuit OEIC
202 Front monitor diode FMD
203 Laser diode driver LDD
300 tester 301 ammeter OP1 operational amplifier R1 resistors P0 to P5, P11 to P15 PMOS transistors N1 to N4, N11 to N12 NMOS transistors SW1 to SW5, SW11 to SW12 switches T1 to T3 external terminals

Claims (20)

A current generation circuit for generating a reference current;
A first external terminal for outputting the generated reference current to a tester;
Current control data for controlling the current value of the reference current, a second external terminal set by the tester according to the reference current output from the first external terminal;
A current control circuit for adjusting a reference current generated by the current generation circuit to a predetermined value according to the current control data set by the tester;
A semiconductor device comprising: A register for storing the current control data;
The second external terminal is a register control terminal that controls writing of the register from the tester.
The semiconductor device according to claim 1. The current generation circuit includes:
A resistance current generator that generates a resistance current according to a constant voltage using a resistor;
A current switching unit that generates the reference current by switching a mirror ratio of the first current mirror circuit that mirrors the generated resistance current according to current control data input from the current control circuit; The semiconductor device according to claim 1. The resistance current generator is
An operational amplifier in which the constant voltage is input to one input terminal;
A control terminal connected to the output terminal of the operational amplifier, and a first terminal connected to a first power source via the resistor,
The current switching unit is
Each control terminal is commonly connected to the control terminal of the first transistor, each first terminal is commonly connected to the first power supply, and a plurality of second transistors constituting the first current mirror circuit ,
A plurality of switches connected between each second terminal of the plurality of second transistors and a reference current generation node for generating the reference current, each being turned on / off according to the current control data; With
The semiconductor device according to claim 3. The resistor is a polysilicon resistor;
The semiconductor device according to claim 3 or 4. Each transistor included in the plurality of second transistors has a different transistor size.
The semiconductor device according to claim 4 or 5. The transistor size of each transistor included in the plurality of second transistors corresponds to each bit of the current control data.
The semiconductor device according to claim 6. A plurality of first cascode transistors connected to each of the plurality of second transistors and the plurality of switches, and each control terminal being commonly connected;
The semiconductor device according to claim 4. An arithmetic processing unit for performing predetermined arithmetic processing;
The current switching unit generates the reference current according to the current control data set by an interrupt signal output from the arithmetic processing unit based on the arithmetic processing;
The semiconductor device according to claim 3. The current generation circuit includes:
A current output unit that outputs the reference current generated by the current switching unit by mirroring with a second current mirror circuit;
The semiconductor device according to claim 3. The current generation circuit includes:
A third transistor having a first terminal and a control terminal connected to the reference current generation node and a second terminal connected to the second power supply;
Each control terminal is commonly connected to the control terminal of the third transistor, each first terminal is connected to an output destination circuit, each second terminal is commonly connected to the second power source, and second A plurality of fourth transistors constituting the current mirror circuit of
The semiconductor device according to claim 4. Each transistor included in the third transistor and the plurality of fourth transistors has the same transistor size.
The semiconductor device according to claim 11. A plurality of second cascode transistors each connected between the reference current generation node and each first terminal of the third transistor and the plurality of fourth transistors and each control terminal being commonly connected Having
The semiconductor device according to claim 11 or 12. A current measuring circuit for measuring a reference current generated by the current generating circuit;
After the current control data is set by the tester, the current control circuit sets the reference current generated by the current generation circuit to the predetermined value according to the measurement result of the reference current by the current measurement circuit. To further adjust,
The semiconductor device according to claim 1. A current calculation processing unit for performing calculation processing on the measurement result by the current measurement circuit;
The current control circuit adjusts a reference current of the current generation circuit according to an interrupt signal output from the current calculation processing unit based on the measurement result;
The semiconductor device according to claim 14. Having a temperature sensor to measure the temperature,
After the current control data is set by the tester, the current control circuit is further configured so that a reference current generated by the current generation circuit becomes the predetermined value according to a temperature measurement result by the temperature sensor. adjust,
The semiconductor device according to claim 1. A temperature calculation processing unit that performs calculation processing on the measurement result of the temperature sensor;
The current control circuit adjusts a reference current of the current generation circuit according to an interrupt signal output from the temperature calculation processing unit based on the measurement result;
The semiconductor device according to claim 16. The tester measures a reference current output from the first external terminal in a memory test process for repairing a defect in a memory included in the semiconductor device, and the second tester determines the second current according to the measurement result of the reference current. Set the current control data to the external terminal of
The semiconductor device according to claim 1. An optical disc apparatus comprising a pickup for irradiating an optical disc with laser light, and a semiconductor device for controlling the operation of the pickup,
The semiconductor device includes:
A current generation circuit for generating a reference current;
A first external terminal for outputting the generated reference current to a tester;
Current control data for controlling the current value of the reference current, a second external terminal set by the tester according to the reference current output from the first external terminal;
A current control circuit for adjusting a reference current generated by the current generation circuit to a predetermined value according to the current control data set by the tester;
A signal processing circuit for processing a signal output from the pickup based on the adjusted reference current of the current generation circuit;
An optical disc device comprising: A test method for a semiconductor device, comprising: a current generation circuit for generating a reference current; a current control circuit for adjusting the generated reference current; and first and second external terminals,
The tester connects a probe to the first and second external terminals, electrically connects to the current generation circuit via the first external terminal, and controls the current control via the second external terminal. Electrically connected to the circuit,
The tester determines an initial value of current control data for controlling the current value of the reference current, and transmits the current control data determined as the initial value to the current control circuit via the second external terminal. Set to changeable,
The current control circuit adjusts a reference current generated by the current generation circuit according to the set current control data,
The current generation circuit outputs the reference current adjusted by the current control data to the tester via the first external terminal,
The tester measures a current value of the output reference current, determines an optimum value of the current control data according to a comparison result between the measurement result of the reference current and the predetermined value,
The tester sets the current control data determined as the optimum value to the current control circuit through the second external terminal so as not to be changed.
A method for testing a semiconductor device.

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