JP2013110338A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To ensure electromigration resistance which is important for achieving micro bump pitch and lead-free bumps because flip-chip mounting is executed in various configurations with increase in the number of terminals per chip.SOLUTION: A flip-chip semiconductor integrated circuit device of an embodiment comprises a metal barrier which is provided in the middle of each of solder bumps respectively provided on a plurality of UBM pads formed on a first principal surface of a chip, which divides the solder bump into two in a vertical direction, and which is composed of a material different from that of the solder bump.

Description

  The present invention relates to a technique effective when applied to a bump electrode technique in a semiconductor integrated circuit device (or a semiconductor device).

  Japanese Patent Application Laid-Open No. 2010-251741 (Patent Document 1) or US Patent Publication No. 2010-258335 (Patent Document 2) corresponding thereto discloses a current concentration at an UBM (Under Bump Metal) portion in solder bump connection. In order to avoid this, a technique of inserting a relatively thick copper layer between the adhesion layer and the barrier layer of the UBM portion is disclosed.

  In Japanese Unexamined Patent Publication No. 2006-295109 (Patent Document 3), in order to avoid the weak point that the stress of the non-melting type metal bump formed by columnar metal such as copper or nickel is easily transmitted to a semiconductor substrate or the like. A technique for covering the periphery of a non-melting type metal bump with a solder bump is disclosed.

  Chih-ming Chen and one other, "Electromigration effect up the the Sn-0.7wt% Cu / Ni and Sn-3.5w% Ag / Ni interfacial reactions", Journal of Applied Physics, V. 90, no. 3,1 August 2001, pp1208-1214 (Non-Patent Document 1) discusses the relationship between the formation of an intermetallic compound and electromigration at the interface between a lead-free solder and a nickel layer.

J. et al. Two names other than Shen, “Growth mechanism of Ni ₃ Sn ₄ in a Sn / Ni liquid / solid interface reaction”, Acta Materialia 57 (2009), pp5196-5206, lead layer (Non-Patent Document 2) Various discussions have been made on the growth of intermetallic compounds at the interface.

  In Minhua Lu 3 names, “Blech effect in Pb-free flip chip solder joint”, Applied Physics Letters 94, 011912 (2009) (Non-patent Document 3), a stress gradient is generated in the direction opposite to the electron flow direction. Discussions have been made on the effect of suppressing electromigration that occurs as a force.

JP 2010-251741 A US Patent Publication No. 2010-258335 JP 2006-295109 A

Chih-ming Chen and one other, "Electromigration effect up the the Sn-0.7wt% Cu / Ni and Sn-3.5w% Ag / Ni interfacial reactions", Journal of Applied Physics, V. 90, no. 3,1 August 2001, pp1208-1214 J. et al. Two people outside of Shen, “Growth mechanism of Ni3Sn4 in a Sn / Ni liquid / solid interface reaction”, Acta Materialia 57 (2009), pp 5196-5206 Minhua Lu 3 people, “Blech effect in Pb-free flip chip solder joint”, Applied Physics Letters 94, 011912 (2009)

  As the number of terminals per chip increases, flip chip mounting is implemented in various forms. However, it is increasingly important to ensure electromigration resistance by reducing the bump pitch and making the bump lead-free.

  The present invention has been made to solve these problems.

  An object of the present invention is to provide a highly reliable semiconductor integrated circuit device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, according to one aspect of the present invention, in the flip-chip type semiconductor integrated circuit device, an intermediate portion of the solder bumps provided on each of a large number of UBM pad shapes formed on the first main surface of the chip includes: A metal partition made of a material different from the solder bumps that divide the upper and lower sides is provided.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, in the flip-chip type semiconductor integrated circuit device, the solder bumps divided into upper and lower parts are arranged in the middle part of the solder bumps provided on each of a large number of UBM pads formed on the first main surface of the chip. Since the metal partition made of a material different from the above is provided, generation of voids due to electromigration or the like in the solder bumps can be reduced.

1 is a schematic cross-sectional view of a semiconductor wafer or chip showing an example of a device structure of a semiconductor integrated circuit device according to an embodiment of the present application. It is a process block flowchart for demonstrating the outline of the manufacturing process regarding the semiconductor integrated circuit device of the said one Embodiment of this application. FIG. 3 is a partial schematic cross-sectional view of a semiconductor wafer (at the time when the formation of the wiring layer WS on the semiconductor substrate is completed) for explaining a bump formation process and the like related to the semiconductor integrated circuit device of the embodiment of the present application. FIG. 3 is a partial schematic cross-sectional view of a semiconductor wafer (at the time of completion of opening of an inorganic final passivation film) for explaining a bump formation process and the like related to the semiconductor integrated circuit device of the one embodiment of the present application. FIG. 3 is a partial schematic cross-sectional view of a semiconductor wafer (at the time of completion of opening of an organic final passivation film) for explaining a bump formation process and the like related to the semiconductor integrated circuit device of the embodiment of the present application. It is a partial schematic cross section (at the time of completion of UBM film formation) of a semiconductor wafer for explaining the bump formation process etc. concerning the semiconductor integrated circuit device of the one embodiment of the present application. FIG. 3 is a partial schematic cross-sectional view (at the time of completion of solder plating) of a semiconductor wafer for explaining a bump formation process and the like related to the semiconductor integrated circuit device of the one embodiment of the present application. It is a partial schematic cross section (at the time of completion of UBM film bottom layer film processing) for explaining the bump formation process etc. concerning the semiconductor integrated circuit device of the one embodiment of the present application. It is a partial schematic cross section (at the time of reflow completion) of the semiconductor wafer for demonstrating the bump formation process etc. regarding the semiconductor integrated circuit device of the said one Embodiment of this application. FIG. 3 is an overall top view of the wafer showing an arrangement that can be placed on the wafer in a chip region (at the time of completion of the bump formation process) corresponding to the semiconductor integrated circuit device of the embodiment of the present application. FIG. 11 is a partially enlarged top view of FIG. 10. It is a schematic cross section of FCBGA (Flip Chip Ball Grid Array) which is an example of a completed form corresponding to the semiconductor integrated circuit device of the one embodiment of the present application. FIG. 7 is a schematic cross-sectional view of a semiconductor wafer or chip showing a modification (multilayer laminated solder bump) relating to the device structure of the semiconductor integrated circuit device of the embodiment of the present application corresponding to FIG. 1. FIG. 7 is a partial schematic cross-sectional view of a semiconductor wafer (solder plating completed) for explaining a bump forming process and the like of a modified example (multilayer laminated solder bump) related to the device structure of the semiconductor integrated circuit device of the embodiment of the present application corresponding to FIG. Time). FIG. 8 is a partial schematic cross-sectional view of a semiconductor wafer (UBM film top view) for explaining a bump formation process and the like of a modification (multilayer laminated solder bump) related to the device structure of the semiconductor integrated circuit device of the embodiment of the present application corresponding to FIG. (When the underlayer processing is completed). FIG. 9 is a partial schematic cross-sectional view of a semiconductor wafer for explaining a bump formation process and the like of a modified example (multilayer laminated solder bump) related to the device structure of the semiconductor integrated circuit device of the embodiment of the present application corresponding to FIG. ). Solder bumps for explaining the flow of ions, etc. on the intermetallic compound layer and the solder interface on the UBM (Under Bump Metal) side nickel layer on the chip for explaining the principle of each embodiment (including modifications) of the present application FIG. 2 is a schematic cross-sectional view of a chip end portion (without a metal partition wall at a bump intermediate portion and before completion of growth of an intermetallic compound layer). Solder bumps for explaining the flow of ions, etc. on the intermetallic compound layer and the solder interface on the UBM (Under Bump Metal) side nickel layer on the chip for explaining the principle of each embodiment (including modifications) of the present application FIG. 2 is a schematic cross-sectional view of a chip end portion (without a metal partition wall at a bump intermediate portion and after completion of growth of an intermetallic compound layer). Solder bumps for explaining the flow of ions, etc. on the intermetallic compound layer and the solder interface on the UBM (Under Bump Metal) side nickel layer on the chip for explaining the principle of each embodiment (including modifications) of the present application FIG. 2 is a schematic cross-sectional view of a chip end portion (having a metal partition wall at a bump intermediate portion and after completion of growth of an intermetallic compound layer). It is a curve graph which shows the relationship between bump diameter and critical solder thickness from which the electromigration suppression effect of each embodiment (a modification is included) of this application becomes remarkable.

[Outline of Embodiment]
First, an outline of a typical embodiment of the invention disclosed in the present application will be described.

1. Semiconductor integrated circuit devices including:
(A) a semiconductor substrate having a first main surface;
(B) a number of UBM pads provided on the first main surface of the semiconductor substrate;
(C) a substantially spherical solder bump provided on each UBM pad of the multiple UBM pads and mainly composed of a solder member;
(D) A first metal partition made of a material different from the solder bump, which divides the solder bump into an upper part and a lower part in an intermediate part of the solder bump.

  2. In the semiconductor integrated circuit device according to Item 1, the first metal partition includes a first partition metal film having solder wettability, a main component constituting the partition metal film, and tin as main components. It is basically composed of one intermetallic compound layer.

  3. In the semiconductor integrated circuit device according to Item 2, the main component of the first partition wall metal film is nickel or copper.

  4). In the semiconductor integrated circuit device according to Item 2, the main component of the first partition metal film is nickel.

  5. In the semiconductor integrated circuit device according to any one of Items 1 to 4, the solder member of the solder bump is lead-free solder.

  6). In the semiconductor integrated circuit device according to Item 5, the lead-free solder is a tin-silver based lead-free solder.

  7). In the semiconductor integrated circuit device according to any one of Items 1 to 6, the semiconductor substrate is a semiconductor chip.

  8). In the semiconductor integrated circuit device according to any one of Items 1 to 6, the semiconductor substrate is a semiconductor wafer.

  9. In the semiconductor integrated circuit device according to any one of Items 1 to 7, the solder bump is an internal bump of a BGA.

10. The semiconductor integrated circuit device according to any one of Items 1 to 9, further including:
(E) A second metal partition made of the same material as the first metal partition, which further divides the upper part in the middle part of the upper part of the solder bump.

[Description format, basic terms, usage in this application]
1. In the present application, the description of the embodiment may be divided into a plurality of sections for convenience, if necessary, but these are not independent from each other unless otherwise specified. Each part of a single example, one part is the other part of the details, or part or all of the modifications. Moreover, as a general rule, the same part is not repeated. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

  Further, in the present application, the term “semiconductor device” or “semiconductor integrated circuit device” mainly refers to various transistors (active elements) alone, and a plurality of resistors, capacitors, etc. on a semiconductor chip or wafer, centering on them. That are integrated on a chip region or the like (for example, a single crystal silicon substrate). Here, as a representative of various transistors, a MISFET (Metal Insulator Semiconductor Effect Transistor) typified by a MOSFET (Metal Oxide Field Effect Transistor) can be exemplified. At this time, as a typical integrated circuit configuration, a CMIS (Complementary Metal Insulator Semiconductor) integrated circuit represented by a CMOS (Complementary Metal Oxide Semiconductor) integrated circuit combining an N-channel MISFET and a P-channel MISFET. Can be illustrated.

  A semiconductor process of today's semiconductor integrated circuit device, that is, a LSI (Large Scale Integration) wafer process, is usually performed by carrying a silicon wafer as a raw material to a premetal process (an interlayer insulating film between the lower end of the M1 wiring layer and the gate electrode structure). Etc., a contact hole formation, a tungsten plug, a process consisting of embedding, etc.) and an M1 wiring layer formation, and formation of a pad opening to the final passivation film on the pad electrode It can be roughly divided into a BEOL (Back End of Line) process. Note that flip chip products and wafer level package processes include UBM (Under Bump Metal) forming processes, bump forming processes, and the like.

  2. Similarly, in the description of the embodiment and the like, the material, composition, etc. may be referred to as “X consisting of A”, etc., except when clearly stated otherwise and clearly from the context, except for A It does not exclude what makes an element one of the main components. For example, as for the component, it means “X containing A as a main component”. For example, “silicon member” is not limited to pure silicon, but also includes SiGe alloys, other multi-component alloys containing silicon as a main component, and members containing other additives. Needless to say. Similarly, “silicon oxide film”, “silicon oxide insulating film”, etc. are not only relatively pure undoped silicon oxide (FS), but also FSG (Fluorosilicate Glass), TEOS-based silicon oxide ( Thermal oxide films such as TEOS-based silicon oxide), SiOC (Silicon Oxicarbide) or Carbon-doped Silicon oxide or OSG (Organosilicate glass), PSG (Phosphorus Silicate Glass), BPSG (Borophosphosilicate Glass), CVD Oxide film, SOG (Spin ON Glass), nano-clustering silica (Nano-Clustering Silica: NCS) and other coating-type silicon oxide, silica-based low-k insulating film (porous insulating) Needless to say, a film) and a composite film with other silicon-based insulating films including these as main constituent elements are included.

  In addition to silicon oxide insulating films, silicon nitride insulating films that are commonly used in the semiconductor field include silicon nitride insulating films. Materials belonging to this system include SiN, SiCN, SiNH, SiCNH, and the like. Here, “silicon nitride” includes both SiN and SiNH unless otherwise specified. Similarly, “SiCN” includes both SiCN and SiCNH, unless otherwise specified.

  Note that SiC has similar properties to SiN, but SiON is often rather classified as a silicon oxide insulating film.

  A silicon nitride film is frequently used as an etch stop film in SAC (Self-Aligned Contact) technology, that is, CESL (Contact Etch-Stop Layer), and also as a stress applying film in SMT (Stress Measurement Technique). .

  3. Similarly, suitable examples of graphics, positions, attributes, and the like are given, but it is needless to say that the present invention is not strictly limited to those cases unless explicitly stated otherwise, and unless otherwise apparent from the context.

  4). In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

  5. “Wafer” usually refers to a single crystal silicon wafer on which a semiconductor integrated circuit device (same as a semiconductor device and an electronic device) is formed, but an insulating substrate such as an epitaxial wafer, an SOI substrate, an LCD glass substrate and the like. Needless to say, a composite wafer such as a semiconductor layer is also included.

  6). The “flip chip type semiconductor device” usually has bump electrodes formed on the upper layer of a substantially circular (circular, octagonal, hexagonal, etc.) metal pad (shifted horizontally when using rewiring). As this metal pad, an “aluminum metal pad” (aluminum metal pad method) or a “non-aluminum metal pad method” (non-aluminum metal pad method) is mainly used. The “aluminum-based metal pad method” has the merit that the wire bonding product and the wafer can be shared, but the process is complicated accordingly. On the other hand, the “non-aluminum-based metal pad method” has an advantage that the structure can be simplified on a copper-based embedded wiring, and in particular, a method using a UBM (Under Bump Metal) itself as a metal pad (referred to as “UBM pad method”). The structure becomes very simple. In the following embodiments, the UBM pad method will be mainly described. However, it goes without saying that the present invention can be applied to an aluminum metal pad method and a non-aluminum metal pad method other than the UBM pad method.

  The flip chip type semiconductor element includes a WLP (Wafer Level Package) type and a bare chip type which will be mainly described below, but it goes without saying that the present invention can also be applied to the WLP type.

  Further, in this application, FCBGA (Flip Chip Ball Grid Array) is mainly a semiconductor chip on the upper surface of a main wiring board of BGA (Ball Grid Array) and flip chip bonded via a bump electrode. . At this time, when it is particularly necessary to distinguish, the bump electrodes on the semiconductor chip are called “internal bumps”, and the bump electrodes on the lower surface of the main wiring board are called external bumps.

  7). "Solder" is a metal material having a low melting point (less than about 250 degrees Celsius) generally containing tin as one of main components. “Solder” includes “lead-containing solder” containing lead and “lead-free solder” not containing lead. In the present application, lead-free solder containing tin as a main component is particularly referred to as “tin-based lead-free solder”.

  Tin-based lead-free solder includes silver-added tin-based lead-free solder, bismuth-added tin-based lead-free solder, silver-copper-added tin-based lead-free solder, silver-antimony-bismuth-added tin-based lead-free solder, bismuth- Silver-copper-added tin-based lead-free solder. In the following embodiments, as an example, a silver-added tin-based lead-free solder (melting point: about 221 degrees Celsius) added with about 1.5% by weight of silver will be specifically described as an example. Needless to say, lead-free solder (addition of about 3.5% by weight of silver), other binary tin-based lead-free solder, ternary tin-based lead-free solder, or quaternary tin-based lead-free solder may be used. Nor. It should be noted that even if “lead-free” is used, in practice, a small amount of lead is usually contained.

[Details of the embodiment]
The embodiment will be further described in detail. In the drawings, the same or similar parts are denoted by the same or similar symbols or reference numerals, and description thereof will not be repeated in principle.

  In the accompanying drawings, hatching or the like may be omitted even in a cross section when it becomes complicated or when the distinction from the gap is clear. In relation to this, when it is clear from the description etc., the contour line of the background may be omitted even if the hole is planarly closed. Furthermore, even if it is not a cross section, it may be hatched to clearly indicate that it is not a void.

1. Description of an example of a device structure of a semiconductor integrated circuit device according to an embodiment of the present application (mainly FIG. 1)
In this section, a CMIS type integrated circuit in which a large number of 40 nm technology node MISFETs and the like are integrated will be specifically described as an example of a semiconductor integrated circuit chip. However, the following embodiments are not limited to MIS type integrated circuits. Needless to say, it may be a bipolar integrated circuit or a single device. In addition, the following example is not limited to a device of a 40 nm technology node, but can be applied to a device of a technology node smaller than this, and can also be applied to a device of a technology node smaller than this. Yes. Note that these semiconductor integrated circuit chips correspond to, for example, SOC (System on Chip) type chips, microcomputers, and peripheral chips thereof as circuit systems.

  In this section, an integrated circuit having eight layers of copper-based embedded wiring will be described as an example, but the embodiment of the present application is also applicable to an integrated circuit having a wiring system having a different number of layers. Needless to say, you can.

  FIG. 1 is a schematic cross-sectional view of a semiconductor wafer or chip showing an example of a device structure of a semiconductor integrated circuit device according to an embodiment of the present application. Based on this, an example of the device structure of the semiconductor integrated circuit device according to the embodiment of the present application will be described.

  As shown in FIG. 1, for example, a device surface 1a (on the back surface 1b) of a P-type single crystal silicon substrate 1s (wafer 1 or semiconductor chip 2) separated by an STI (Shallow Trench Isolation) type element isolation field insulating film 37. A P-channel MOSFET or an N-channel MOSFET (8) is formed on the opposite surface. A silicon nitride liner film 4 (for example, about 30 nm) which is an etch stop film is formed thereon. On top of this, for example, a premetal made of an ozone TEOS silicon oxide film (for example, about 200 nm) as a lower layer by a thermal CVD method and a plasma TEOS silicon oxide film (for example, about 270 nm) as an upper layer is much thicker than the silicon nitride liner film 4. A (Premetal) interlayer insulating film 5 is formed. A tungsten plug 3 is formed through these premetal insulating films. A layer in which the silicon nitride liner film 4 and the premetal interlayer insulating film 5 are present is a premetal region PM.

  The first wiring layer M1 thereabove is formed on, for example, an insulating barrier film 14 such as a lower SiC film (for example, about 50 nm), a plasma silicon oxide film 15 (for example, about 150 nm) which is a main interlayer insulating film, and the like. The copper wiring 13 is embedded in the wiring groove formed. This layer is a copper-based embedded wiring having a so-called single damascene structure.

  The second to sixth wiring layers M2, M3, M4, M5, and M6 on the second wiring layer have substantially the same structure as each other, and are copper-based embedded wirings having a so-called dual damascene structure. Each layer is made of, for example, an insulating barrier film (liner film) 24, 34, 44, 54, 64 made of a lower SiC film (for example, about 50 nm) or the like, and main interlayer insulating films 25, 35 occupying most of the upper layer region. , 45, 55, 65, etc. The main interlayer insulating films 25, 35, 45, 55, 65 are made of, for example, a carbon-doped silicon oxide film, that is, a SiOC film (for example, about 400 nm). Copper embedded wirings 23, 33, 43, 53, 63 including copper plugs and copper wirings are formed through these interlayer insulating films. Note that the first to sixth wiring layers M1, M2, M3, M4, M5, and M6 are local wirings in this example, for example.

  The seventh wiring layer M8 to the eighth wiring layer M8 on the seventh wiring layer M7 and M8 have substantially the same structure as each other, and are copper-based embedded wirings having a so-called dual damascene structure. That is, the global lower wiring layer interlayer insulating film 19 is made of, for example, an insulating barrier film 74 such as a lower SiC film (for example, about 70 nm), an upper plasma TEOS silicon oxide film 75a, 85a (for example, about 850 nm), or the like. A copper buried wiring 73 including a copper plug and a copper wiring is formed through these interlayer insulating films. Although not described here, the side surface and the bottom surface of the copper embedded wiring 73 are surrounded by a barrier metal film such as a TaN film (including a laminated film with a Ta film), for example (the following copper embedded) Same for wiring).

  On the other hand, global upper wiring layer interlayer insulating film 18 is made of, for example, an insulating barrier film 84 such as a lower SiC film (for example, about 70 nm), an upper plasma TEOS silicon oxide film 85 (for example, about 1200 nm), or the like. A copper buried wiring 83 including a copper plug and a copper wiring is formed through these interlayer insulating films. The copper embedded wiring 83 is capped with a buried-type eighth wiring layer barrier metal film (for example, a TiN film having a thickness of about 200 nm). Up to this point is the embedded multilayer wiring layer DW. In this example, the global wiring has two layers. However, the number of global wiring layers may be three or more as needed, or may be one layer.

  On top of this, for example, a lower inorganic final passivation film 11 (for example, a SiON film having a thickness of about 300 nm) and an upper organic final passivation film 9 (for example, a polyimide having a thickness of about 1.5 micrometers) This is a final passivation film 17 composed of a system film) or the like. The inorganic final passivation film is not limited to the SiON film, but other silicon oxide insulating films, silicon nitride insulating films, composite films of these, and the like are suitable. Further, as the organic final passivation film, in addition to the polyimide insulating film, for example, a heat-resistant polymer resin film such as a BCB (Bencyclocyclene) insulating film is preferable.

  A lower UBM film 16a (for example, a TiW film having a thickness of about 200 nm) is provided in an opening and an upper surface of these final passivation films 17, and a lower copper film 16b (for example, a thickness of 200 nm is formed thereon). Degree) is provided. As the lower UBM film, in addition to the TiW film, chromium, titanium, tungsten, or a composite film thereof is preferable.

  On the lower copper film 16b, a nickel film 16c (for example, about 3 micrometers in thickness) is provided as a barrier film against solder. In addition, an upper copper film (for example, a thickness of about 400 nm) may be further provided thereon as a connection surface with solder. The lower UBM film 16 a, the lower copper film 16 b and the nickel film 16 c constitute the UBM film 16, which is also the metal pad 12.

  Furthermore, solder bumps 7 are formed on the metal pads 12. In this example, the bump height H is, for example, about 80 micrometers (approximately equal to the bump diameter). Here, the solder bump 7 is a lead-free solder. For example, as an example of a tin-based lead-free solder, Sn-Ag-based lead-free solder (specifically, the composition is, for example, 98.5 wt. %, Silver 1.5% by weight; melting point is about 221 degrees Celsius). The tin-based lead-free solder is not limited to a binary system such as a Sn-Ag system and a Sn-Bi system. In this example, any Sn-Ag-Cu solder having a melting point of 200 degrees Celsius or more is used. It may be a ternary system such as a quaternary system or a quaternary system such as a Sn-Bi-Ag-Cu system or a Sn-Ag-Bi-Sb system. Here, lead-free solder is mainly described, but lead-containing solder may be used if there is no environmental problem.

In the middle portion of the solder bump 7, the solder bump is partitioned into an upper portion and a lower portion by a metal partition wall 38 (first metal partition wall) made of a material different from the solder bump for suppressing electromigration. The first metal partition wall includes a first partition wall metal film having solder wettability, a main component constituting the partition wall metal film, and tin as main components, and the first metal partition wall covering the periphery of the metal partition wall 38. It is basically composed of an intermetallic compound layer (for example, Ni ₃ Sn ₄ layer). As a main component of the first partition metal film, nickel can be exemplified as a suitable component. This is because the amount consumed as an intermetallic compound is smaller than that of copper or the like. In addition, as a main component of the first partition wall metal film, copper or the like can be raised in addition to nickel.

  As a thickness of the first partition metal film, for example, about 3 micrometers (as a range, about 1.5 micrometers to 7 micrometers) can be exemplified as a preferable one. In addition, the thickness here is a thickness before reflow for convenience. The lower limit of the thickness of the first partition wall metal film is a condition that a nickel film as a core remains sufficiently even after a plurality of reflows. On the other hand, the upper limit is determined from the condition that the volume reduction of about 10% due to the formation of the intermetallic compound layer is kept within an allowable range. In this example, the number of the metal partition walls 38 is singular, but it goes without saying that the number may be plural. However, the singular has higher structural stability. The metal partition 38 is preferably arranged so that the solder layers that can be divided have the same thickness.

  As described above, in this example, the metal pad 12 is a non-aluminum metal pad, and the UBM film 16 has no gold film. Of course, an aluminum metal pad may be formed instead of the non-aluminum metal pad. Further, a gold film may be provided in the UBM film 16. However, using a non-aluminum metal pad has the advantage that the device structure becomes very simple. Also, not using an expensive gold film is a cost advantage.

2. Description of manufacturing process outline and bump formation process and the like related to the semiconductor integrated circuit device of the embodiment of the present application (mainly FIGS. 2 to 12)
The solder bump formation method includes a so-called SMD (Solder Mask Defined) type in which both sides of the bump are defined by the edge of the polyimide final passivation film (organic final passivation film), and both sides of the bump at the edge of the polyimide final passivation film. There is a non-SMD (non-Solder Mask Defined) type. In this section, a non-SMD type will be described as an example, but it goes without saying that the embodiment of the present application can also be applied to an SMD type.

  FIG. 2 is a process block flow diagram for explaining the outline of the manufacturing process relating to the semiconductor integrated circuit device according to the embodiment of the present application. FIG. 3 is a partial schematic cross-sectional view of a semiconductor wafer (at the time when the formation of the wiring layer WS on the semiconductor substrate is completed) for explaining a bump formation process and the like related to the semiconductor integrated circuit device according to the embodiment of the present application. FIG. 4 is a partial schematic cross-sectional view of a semiconductor wafer (at the time when the opening of the inorganic final passivation film is completed) for explaining a bump forming process and the like related to the semiconductor integrated circuit device of the one embodiment of the present application. FIG. 5 is a partial schematic cross-sectional view of a semiconductor wafer (at the time of completing the opening of the organic final passivation film) for explaining a bump formation process and the like related to the semiconductor integrated circuit device according to the embodiment of the present application. FIG. 6 is a partial schematic cross-sectional view (at the time of completion of UBM film formation) of the semiconductor wafer for explaining a bump formation process and the like related to the semiconductor integrated circuit device of the one embodiment of the present application. FIG. 7 is a partial schematic cross-sectional view of a semiconductor wafer (at the time of completion of solder plating) for explaining a bump forming process and the like related to the semiconductor integrated circuit device of the one embodiment of the present application. FIG. 8 is a partial schematic cross-sectional view of a semiconductor wafer (at the time of completion of UBM film bottom layer film processing) for explaining a bump formation process and the like related to the semiconductor integrated circuit device according to the embodiment of the present application. FIG. 9 is a partial schematic cross-sectional view (at the time of reflow completion) of a semiconductor wafer for explaining a bump formation process and the like related to the semiconductor integrated circuit device of the embodiment of the present application. Based on these drawings, an outline of a manufacturing process and a bump forming process regarding the semiconductor integrated circuit device according to the embodiment of the present application will be described.

  For example, a 300-phi P-type single crystal silicon wafer 1 (see FIG. 1) is prepared (the diameter of the wafer may be 450 phi, 220 phi, or other as required). As shown in FIG. 2, an FEOL process 201 such as forming a large number of MISFETs (8) is performed on the wafer 1. Subsequently, for example, a BEOL process 202 for forming an eight-layer copper embedded wiring (wiring layer WS on the semiconductor substrate 1s) is executed.

  FIG. 3 shows a cross-sectional structure when the buried eighth wiring layer M8 is formed in this way. As shown in FIG. 3, an embedded eighth wiring layer M8 is formed on the embedded seventh wiring layer M7, and is composed of, for example, an SiC-based insulating barrier film 84 and a plasma TEOS-based main interlayer insulating film 85. An eighth-layer copper embedded wiring 83 is embedded in the global wiring upper-layer wiring interlayer insulating film 18. Here, on the device surface 1a (first main surface) side of the wafer, the eighth-layer copper buried wiring 83 is covered with the buried-type eighth wiring layer barrier metal film 10 (for example, TiN). Membrane).

  Next, as shown in FIG. 4, an inorganic final passivation film 11 (for example, a SiON film) is formed on almost the entire surface on the device surface 1a side of the wafer by, for example, plasma CVD (Chemical Vapor Deposition). The inorganic final passivation film 11 is patterned by, for example, ordinary lithography to form the lower final passivation opening 30.

  Next, as shown in FIG. 5, for example, a photosensitive polyimide film or the like is applied and patterned on almost the entire surface of the wafer on the device surface 1 a side, thereby forming an organic final passivation film 9 (for example, a polyimide film) and Upper final passivation opening 31 is formed. The inorganic final passivation film 11 and the upper final passivation opening 31 constitute a final passivation film 17. The final passivation film 17 can have various other configurations, but the organic final passivation film is effective in absorbing stress during reflow processing or the like.

  Next, the solder bump forming process 203 (FIG. 2) will be described. As shown in FIG. 6, a lower UBM film 16a (for example, a TiW film) is formed as an adhesive layer (Adhesion Layer) on almost the entire surface of the wafer on the device surface 1a side by, for example, sputtering. Next, a lower copper film 16b is formed as a seed layer on almost the entire surface of the lower UBM film 16a by, for example, sputtering. Next, a UBM plating resist film 36 is formed on the device surface 1a side of the wafer by, for example, ordinary lithography. Next, for example, a nickel film 16c is selectively formed as a barrier film on the lower copper film 16b by, for example, electroplating. Thereafter, the resist film 36 that is no longer needed is entirely removed by, for example, ashing. Next, the lower copper film 16b is patterned in a self-aligning manner, for example, by wet etching (for example, a mixed solution of sulfuric acid and hydrogen peroxide solution) (see FIG. 7).

  Next, as shown in FIG. 7, a solder plating resist film 32 is formed on the device surface 1a side of the wafer by, for example, ordinary lithography. Next, the lower part 7a (before reflow) of the solder bump is formed by, for example, electroplating. Next, a nickel film (for example, a thickness of about 3 micrometers) to be the first metal partition wall 38 is formed on the lower portion 7a of the solder bump by, for example, electroplating. Next, the upper part 7b of the solder bump is formed by, for example, electroplating. Thereafter, the resist film 32 that has become unnecessary is entirely removed by, for example, ashing. The solder bumps can be formed by various printing methods in addition to the plating method. However, the plating method is advantageous in reducing the bump pitch.

  Next, as shown in FIG. 8, the lower UBM film 16a is patterned in a self-aligning manner, for example, by wet etching (for example, a hydrogen peroxide-based etching solution such as a mixed solution of ammonia and hydrogen peroxide solution). .

  Next, as shown in FIG. 9, by performing a first reflow process (for example, about 240 to 260 degrees Celsius), the solder bumps 7 (for example, lead-free solder) are substantially spherical (mainly made of a solder member). (Spherical solder bump). Since the TiW film 16a does not get wet with the solder, and the copper film 16b and the nickel films 16c and 38 get wet with the solder, the shaping is performed autonomously.

3. Description after the wafer probe test process in the outline of the manufacturing process relating to the semiconductor integrated circuit device according to the embodiment of the present application (mainly refer to FIGS. 10 to 12 and FIG. 2)
In this section, a standard individual resin sealing method will be specifically described as an example of the packaging process. However, the present invention is not limited to this, and the ceramic sealing method, the can sealing method, etc. Of course, the present invention can also be applied to a MAP (Mold Array Package) method in which the entire device is sealed with resin and then separated into individual devices by package dicing.

  In addition, here, an example in which die bonding (flip chip bonding) is directly performed on the upper surface of the package wiring board by the flip chip method has been specifically described, but die bonding (flip chip bonding) is performed on the lower surface of the package wiring board. Also good. Further, die bonding (flip chip bonding) may be performed on a device surface or the like of another chip die bonded to the upper surface of the package wiring board.

  FIG. 10 is an overall top view of the wafer showing the arrangement of the chip region (at the time of completion of the bump formation process) corresponding to the semiconductor integrated circuit device of the embodiment of the present application that can be placed on the wafer. FIG. 11 is a partially enlarged top view of FIG. FIG. 12 is a schematic cross-sectional view of an FCBGA (Flip Chip Ball Grid Array) which is an example of a completed form corresponding to the semiconductor integrated circuit device according to the embodiment of the present application. Based on these, the wafer probe test process and subsequent steps in the outline of the manufacturing process relating to the semiconductor integrated circuit device of the one embodiment of the present application will be described.

  FIG. 10 shows an overall top view of the wafer 1 after the solder bump forming step 203 of FIG. 2 is completed. As shown in FIG. 10, for example, a large number of chip regions 2 are formed in a lattice shape on the upper surface 1a or device surface (first main surface) of the silicon single crystal wafer 1 having the notches 21. Although the wafer having the notch 21 is illustrated here, it goes without saying that the wafer may have an orientation flat.

  FIG. 11 shows a partially enlarged view of FIG. As shown in FIG. 11, solder bumps 7 are arranged in each chip area 2 in a matrix, for example, and the chip areas 2 are separated from each other by a dicing area 20 (scribe area). In this state, the product may be shipped as a product. Next, in this state, for example, the wafer probe test process 204, the bump height inspection process 205 (omitted if necessary) and the wafer dicing process 206 shown in FIG. Is done.

  Next, as shown in FIG. 12, the flip chip bonding step 211, the underfill step 212, the resin sealing step 213, and the external solder bump forming step 214 shown in FIG. That is, as shown in FIG. 12, for example, an epoxy organic wiring board, which has an internal bump metal land 40 (Ni land) on the upper surface and an external bump metal land portion 27 on the lower surface, is a main body for BGA. A wiring board 26 is prepared. Here, as the internal bump metal land 40, for example, a copper-based metal land coated with a nickel film or the like can be exemplified as a suitable one.

  Next, the chip 2 is mounted on the upper surface of the BGA main wiring board 26 with the internal bumps 7 facing downward. At this time, as shown in FIG. 12, the horizontal position of each internal bump 7 substantially coincides with the horizontal position of each internal bump metal land 40. In this state, the second reflow process is performed at, for example, about 240 degrees Celsius to 260 degrees Celsius. This completes the flip chip bonding step 211.

  Next, as shown in FIG. 12, an underfill resin 28 is filled between the chip 2 and the upper surface of the BGA main wiring board 26 (underfill process 212 in FIG. 2).

  Next, as shown in FIG. 12, the upper surfaces of the chip 2 and the BGA main wiring board 26 are sealed with, for example, an epoxy sealing resin body 29 (resin sealing step 213 in FIG. 2).

  Next, as shown in FIG. 12, external solder bumps 22 (external solder bump forming step 214 in FIG. 2) are formed. As a material of the solder bump 22, the same material as that of the internal solder bump 7 can be exemplified as a suitable material. Needless to say, different materials may be used. In addition, since the diameter of the external solder bump 22 is much larger than the diameter of the internal solder bump 7, application of a metal partition is generally unnecessary. However, it may be applied if necessary.

4). Description of Modifications Related to Semiconductor Integrated Circuit Device of One Embodiment of the Present Application (Mainly FIGS. 13 to 16)
In this section, variations on the device structure of section 1 and corresponding changes to the manufacturing process of section 2 are described. Basically, there is no difference from FIG. 1 to FIG. 9, so in this section, only different parts will be described in principle.

  FIG. 13 is a schematic cross-sectional view of a semiconductor wafer or chip showing a modification (multilayer laminated solder bump) relating to the device structure of the semiconductor integrated circuit device of the embodiment of the present application corresponding to FIG. FIG. 14 is a partial schematic cross-sectional view of a semiconductor wafer for explaining a bump forming process and the like of a modified example (multilayer laminated solder bump) related to the device structure of the semiconductor integrated circuit device of the embodiment of the present application corresponding to FIG. (When solder plating is completed). FIG. 15 is a partial schematic cross-sectional view of a semiconductor wafer for explaining a bump forming process and the like of a modified example (multilayer laminated solder bump) relating to the device structure of the semiconductor integrated circuit device of the embodiment of the present application corresponding to FIG. (When the UBM film bottom layer film processing is completed). FIG. 16 is a partial schematic cross-sectional view of a semiconductor wafer for explaining a bump forming process and the like of a modified example (multilayer laminated solder bump) related to the device structure of the semiconductor integrated circuit device of the embodiment of the present application corresponding to FIG. When reflow is completed). Based on these, a modification of the semiconductor integrated circuit device according to the embodiment of the present application will be described.

  The bump structure of the modified example is basically the same as that shown in FIG. 1, but as shown in FIG. 13, a metal partition (first metal partition 38, second partition) that divides the solder bump 7 in the vertical direction. The difference is that there are a plurality of metal partitions 39). This is because the effect of suppressing electromigration in the solder by inserting the metal partition wall increases as the solder layer thickness decreases.

  Next, the bump formation process will be described with reference to FIGS.

  3 to 6 are the same as those in section 2, and the wafer in the state shown in FIG. 6 is processed as shown in FIG. 14 (corresponding to FIG. 7). That is, a resist film 32 for solder plating is formed on the device surface 1a side of the wafer by, for example, ordinary lithography. Next, the lower portion 7a of the solder bump is formed by, for example, electroplating. Next, a nickel film (for example, a thickness of about 2.5 micrometers) to be the first metal partition wall 38 is formed on the lower portion 7a of the solder bump by, for example, electroplating. Next, the central portion 7b of the solder bump is formed by electroplating, for example. Next, a nickel film (for example, a thickness of about 2.5 micrometers) to be the second metal partition 39 is formed on the central portion 7b of the solder bump by, for example, electroplating. Next, the upper part 7c of the solder bump is formed by, for example, electroplating. Thereafter, the resist film 32 that has become unnecessary is entirely removed by, for example, ashing.

  Next, as shown in FIG. 15, the lower UBM film 16a is patterned in a self-aligning manner, for example, by wet etching (for example, a hydrogen peroxide-based etchant such as a mixed solution of ammonia and hydrogen peroxide solution). .

  Next, as shown in FIG. 16, the first reflow process (for example, about 240 to 260 degrees Celsius) is performed to shape the solder bump 7 (for example, lead-free solder) into a substantially spherical shape. Since the TiW film 16a is not wetted by the solder, and the copper film 16b and the nickel films 16c, 38, and 39 are wetted by the solder, the shaping is performed autonomously.

5. Supplementary explanation about the above-described embodiment (including modifications) and general consideration (mainly FIGS. 17 to 20)
FIG. 17 illustrates the flow of ions between the intermetallic compound layer on the surface of the nickel layer on the UBM (Under Bump Metal) side on the chip and the solder interface, for explaining the principle of each embodiment of the present application (including modifications). FIG. 2 is a schematic cross-sectional view of a chip end portion of a solder bump (having no metal partition wall in the bump middle portion and before completion of growth of an intermetallic compound layer). FIG. 18 illustrates the flow of ions, etc., between the intermetallic compound layer on the surface of the nickel layer on the UBM (Under Bump Metal) side on the chip and the solder interface for explaining the principle of each embodiment (including modifications) of the present application. FIG. 3 is a schematic cross-sectional view of a chip end portion of a solder bump (after a growth of an intermetallic compound layer is completed without a metal partition wall at a bump intermediate portion). FIG. 19 illustrates the flow of ions, etc., between the intermetallic compound layer on the surface of the nickel layer on the UBM (Under Bump Metal) on the chip and the solder interface for explaining the principle of each embodiment (including modifications) of the present application. FIG. 3 is a schematic cross-sectional view of a chip end portion of a solder bump (having a metal partition wall at the bump intermediate portion and after completion of growth of an intermetallic compound layer). FIG. 20 is a curve graph showing the relationship between the bump diameter and the critical solder thickness at which the electromigration suppression effect of each embodiment (including the modification) of the present application becomes significant. Based on these, a supplementary explanation regarding the above-described embodiment (including modifications) and a general consideration will be given.

  In an in-vehicle electronic device or the like, it is necessary to install and operate a semiconductor device near the engine. In this case, it is essential to satisfy sufficient reliability at a high temperature. However, when lead-free solder for reducing the environmental load is used, it is difficult to ensure the target joint reliability. On the other hand, the number of product terminals tends to increase with the progress of integration. In order to increase the number of terminals with the same chip size, flip-chip mounting technology is widely used, but there are many reliability problems. One of them is securing electromigration resistance. Since the solder bumps connecting the chip and the substrate tend to be reduced in diameter to ensure the number of terminals, the current density when transmitting an electrical signal tends to increase. Electromigration is an atomic transport phenomenon whose driving force is momentum exchange caused by collision of electrons conducted in a metal with a metal atom, and therefore is accelerated as the current density increases. Furthermore, since a metal having a lower melting point tends to cause atomic transport, the necessity of ensuring electromigration resistance of solder bumps using lead-free solder is greatly increased.

  Even when the chip and the substrate are connected with a general structure, the risk of long-term reliability is low if the opening diameter of the polyimide and the diameter of the solder bump are sufficiently large. However, as the circuit scale and functions increase due to the need for miniaturization, the number of signals arranged per unit chip area and the number of input / output terminals of the power supply, that is, the number of connection parts to the substrate by solder bumps tend to increase. . At that time, the polyimide opening diameter and the solder bump diameter are reduced, but the signal flowing to the input / output terminal, in other words, the current value does not decrease so much. Therefore, the current flowing per unit area, that is, the current density is increased.

In general, wiring used in LSI has a small cross-sectional area with respect to a current path, and is used in a state of excessive current density as compared with wiring used in daily life. For example, a commercially available electric wire used for supplying electric power to a home is used with a current density of about 10 ³ A / cm ² as an upper limit, and actually a much lower current density. On the other hand, the wiring of the LSI is 10 ³ to 10 ⁴ A / cm 2 when the bump bonding portion is regarded as the wiring, and 10 ⁵ to 10 ⁶ A / cm ² in the wiring formed of Cu or Al in the Si chip. It is often used at a current density of. This is because the LSI wiring is very fine and has a high surface area ratio, and the surrounding area is covered with a material with good heat dissipation such as silicon dioxide, so temperature rise due to Joule heat generation is suppressed, resulting in fusing It is because it is hard to generate | occur | produce.

  However, it is known that an atomic transport phenomenon called electromigration occurs when the current density is high. In general, the phenomenon of flowing a current through a metal is caused by a potential difference in the field of atomic groups forming a metal-bonded state, so that the emitted outermost electrons become free electrons and change from the cathode side to the anode side. It is a phenomenon that moves to. At this time, the electrons accelerated by the electric field collide with a metal atom (which is in an ionic state since the outermost electrons are emitted), thereby suppressing the acceleration and averaging the moving speed. At this time, the average value of the movement distance of electrons from collision to collision is called the mean free path, and the shorter the distance, the higher the electric resistance. At the same time, this collision between electrons and metal atoms involves momentum exchange. When an electron that has moved at a relatively high speed collides with a metal atom that is considered to be stationary at almost the same location, the momentum of the electron is transferred to the metal atom. Since the size of electrons and metal atoms differ by several orders of magnitude, the exchange of momentum per collision is not very large. Therefore, when the number of collisions per unit time is small, in other words, when the current density is low, the momentum for moving the metal atoms cannot be achieved. However, as the current density increases, the number of collisions per unit time increases, thereby increasing the momentum received by the metal atoms, which can be a driving force for atom transport. Moreover, since this momentum works in the direction of the electron flow, the metal atoms move from the cathode side toward the anode side. This force is called electronic wind.

As described above, the solder bumps 7 are formed by solder such as SnAg and UBM (16) such as Ni. However, in the combination of Sn and Ni, or Sn and Cu, an intermetallic compound is formed by thermal diffusion. . For example, Cu ₃ Sn, Cu ₆ Sn ₅ , Ni ₃ Sn _4, etc., with volume shrinkage of 7.7%, 5.1%, and 11.4%, respectively. Due to the above-described atomic transport by electromigration and the formation of an intermetallic compound, a defect called a void occurs in a portion where atoms are sparse. As this grows, the resistance of the connecting portion increases, and eventually disconnection occurs.

This transport of atoms will be described with reference to the drawings. FIG. 17 illustrates the initial state in which mounting on the substrate is completed and current starts to flow, and atom transport. UBM (16) was Ni and the solder was SnAg. Ni ₃ Sn ₄ is formed as an intermetallic compound at the joint between Ni and SnAg (solder layer 7). That is, formation of the intermetallic compound layer 41. It is known that voids are generated and grow at the interface between the intermetallic compound layer 41 and SnAg (7), and atoms move to this interface by some driving force. The + symbol represents the inflow of atoms to the interface, and the − symbol represents the outflow of atoms from the interface. The case where Ni is the cathode side and Sn is the anode side is shown. On the solder side, since the volume is relatively large, the outflow of Sn and Ni from the interface is the main atomic transport. At this time, the atomic vacancy moves in the opposite direction in exchange for the moved atom. This transport is called Jem. On the other hand, in the intermetallic compound layer 41, Ni moves toward the interface using diffusion due to the concentration gradient as a driving force. This transport is called Jchem. At the same time, Ni moves toward the interface by electromigration caused by electronic wind. This transport is J'em. At this time, inside the intermetallic compound layer 41, atoms are dense on the anode side and atoms are sparse on the cathode side. As a result, since the cathode side is in a tensile stress state and the anode side is in a compressive stress state, the stress gradient becomes a driving force in the direction opposite to the electron flow direction, and transport occurs. This transport is Js. These atomic transport balances Jimc / sn are as shown in FIG.

  When time elapses from the state of FIG. 17, the production of the intermetallic compound is almost saturated. Atom transport in this state will be described with reference to FIG. 18 (for example, a state after mounting on a substrate or the like). Since the diffusion due to the concentration gradient disappears, the atomic transport balance Jimc / sn is as shown in FIG. The intermetallic compound is formed by heat treatment such as primary reflow, secondary reflow, and subsequent mounting on a substrate or the like.

  In other words, since the atomic transport using the chemical potential due to the concentration gradient as a driving force does not contribute, the contribution of outflow increases. Therefore, it is explained that the place where the void starts to grow becomes the interface between the intermetallic compound layer 41 and SnAg (solder layer 7).

  Through the above-described process, a structure in which the solder and the intermetallic compound layer 41 are stacked in the bump is realized. As a result, by laminating with the intermetallic compound layer 41, a significant stress gradient and resulting backflow J's are also generated in the SnAg layer 7a. FIG. 19 shows the concept. Compared with the atomic flux at the interface shown in FIGS. 17 and 18, the total flux is reduced by the amount of reverse flow in SnAg (solder layer 7 a). For example, the atomic transport balance Jimc / sn at the interface between the UBM (16) and the solder is as shown in FIG. 19 (lower part). 19 is the same as FIG. 18, and the intermetallic compound layer 41 is formed by heat treatment such as primary reflow, secondary reflow, and subsequent mounting on a substrate or the like. Therefore, at least after the first reflow, the first metal partition wall 38, the second metal partition wall 39, the internal bump metal land 40 (Ni land), and the metal pad in FIGS. 1, 9, 12, and 16 are used. As shown in FIG. 19, an intermetallic compound layer 41 is formed between 12 and the solder layer.

  Further, the balance at the interface between the intermetallic compound layer 41 in the bump and the solder on the anode side is as shown in FIG. 19 (upper part). Compared with FIG. 18 etc., it turns out that the atomic transport of a backflow arises. That is, it is expected that void generation and growth due to accumulation of vacancies are suppressed. This is because a concentration gradient, in other words, a stress gradient, is generated in a single film due to atoms that have moved in the direction of electron flow due to electromigration. This is an application of moving driving force. In solder bumps that have been widely used so far, the solder portion such as SnAg (solder layer) has a large volume, and therefore the backflow due to this stress gradient is negligibly small. Therefore, by stacking a solder layer such as SnAg (solder layer) and a metal layer such as Ni multiple times, a stress gradient caused by electromigration is also induced in the SnAg portion (solder layers 7, 7a, 7b, 7c). The expected suppression effect is obtained. What is necessary is just to optimize the film thickness of each layer in the case of lamination | stacking to the film thickness from which a back flow stress becomes significant.

The threshold value for the occurrence of electromigration due to the backflow stress is considered to be about 30 A / cm from various data. This shows the condition that the atom transport due to electromigration from the cathode to the anode by electron wind and the back flow from the anode to the cathode due to the stress gradient are balanced and that effective atom transport does not occur. . Specifically, when the product of the wiring length and the current density is smaller than this value, void generation and growth do not occur. For example, consider a case where a current of 500 mA flows. Considering the bump as a cylinder having a diameter of about 80 micrometers, the cross-sectional area is about 5 × 10 ⁻⁵ cm ² . Therefore, the current density is about 10,000 A / cm2. In order to satisfy the threshold condition of 30 A / cm, the wiring length needs to be ³ × 10 ⁻³ cm, in other words, the solder length. Therefore, the solder layer may be laminated a plurality of times so that the thickness of the solder layer is 30 micrometers or less. Also, when the bump diameter is reduced and the solder sandwiched between the UBM (16) and the intermetallic compound layer 41 at the solder interface and the intermetallic compound layer 41 at the substrate and the solder interface is less than the thickness obtained as described above. Is considered to have a similar effect.

  If it is assumed that a current of 500 mA flows, the relationship between the bump diameter and the thickness of the solder layer expected to have a backflow effect is as shown in FIG. Since the current flowing through the bumps is determined by the ability of the input / output terminals on the chip side, it does not change depending on the manufacturing process technology on the chip side, so it can be considered that the current value does not change. At this time, since the current density increases, the solder thickness at which the backflow stress becomes significant is also reduced. Accordingly, as the bumps become finer, the thickness of the solder sandwiched between the UBM (16), the intermetallic compound layer 41 at the solder interface, and the intermetallic compound layer 41 at the substrate and the solder interface is equivalent to the numerical value shown in FIG. Alternatively, it is effective to adjust the thickness so as to be smaller than this.

6). Summary The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.

  For example, in the above-described embodiment, the description has been given specifically for the device mainly having the copper-based embedded wiring. However, the present invention is not limited thereto, and the aluminum-based non-embedded wiring, the silver-based embedded wiring, and the like. Needless to say, the present invention can also be applied to a device having a metal embedded wiring.

  Further, as a barrier metal against copper, a tantalum nitride-based barrier metal has been specifically described as an example, but the present invention is not limited thereto, and a titanium nitride-based barrier metal (including a Ti / TiN multilayer barrier), It goes without saying that other barrier metals such as ruthenium-based barrier metals may be used. In addition, although an example of a TaN film single-layer barrier metal has been specifically described here, it is needless to say that the present invention is not limited thereto and may be a Ta / TaN multilayer barrier.

  Furthermore, although the example which mainly used SiC etc. was specifically demonstrated as an insulating copper diffusion barrier film, this invention is not limited to it, Other films, such as SiCN and SiN, may be sufficient Needless to say.

  In the above embodiment, an example in which a semiconductor integrated circuit device is formed mainly using a single crystal silicon wafer as a starting material has been described. However, the present invention is not limited thereto, and an SOI wafer, an epitaxy wafer, or the like is used as a star material. Needless to say, the present invention can also be applied to forming a semiconductor integrated circuit device as a ting material. Needless to say, the base material of the wafer can be applied to a compound semiconductor such as SiGe, GaAs, SiC, GaN, InP as well as a silicon-based semiconductor.

1 Semiconductor wafer (semiconductor substrate)
1a Device surface of substrate or wafer (first main surface)
1b Back surface of substrate or wafer (second main surface)
1s P-type single crystal silicon substrate portion of substrate or wafer 2 Semiconductor substrate or integrated circuit chip (semiconductor chip region)
3 Tungsten plug 4 Silicon nitride liner film (etch stop film)
5 Premetal interlayer insulating film 6 Substrate contact area 7 Solder bump (on chip) 7a Lower part of solder bump (on chip) 7b Upper part (or center part) of solder bump (on chip)
7c Upper part of solder bump (on chip) 8 MISFET
9 Organic final passivation film (polyimide film)
10 Barrier metal film (TiN film) on embedded type 8th wiring layer
11 Inorganic final passivation film (SiON film)
12 Metal Pad 13 Embedded Copper Wiring 14 SiC Insulating Barrier Film 15 Plasma TEOS Main Interlayer Insulating Film 16 UBM Film (UBM Pad)
16a Lower UBM film (TiW film)
16b Lower copper film 16c Nickel film 17 Final passivation film 18 Global wiring upper layer wiring interlayer insulating film 19 Global wiring lower layer wiring interlayer insulating film 20 Dicing region (scribe region)
21 Notch 22 External solder bump 23 Copper embedded wiring 24 SiC insulating barrier film 25 SiOC main interlayer insulating film 26 Package wiring board 27 External bump metal land 28 Underfill resin 29 Sealing resin body 30 Lower final passivation opening 31 Upper final passivation opening 32 Resist film for solder plating 33 Copper embedded wiring 34 SiC insulating barrier film 35 SiOC main interlayer insulating film 36 UBM plating resist film 37 Element isolation region (STI insulating film region)
38 1st metal partition wall 39 2nd metal partition wall 40 Metal land for internal bump (Ni land) on wiring board
41 Intermetallic compound layer 43 Copper embedded wiring 44 SiC-based insulating barrier film 45 SiOC main interlayer insulating film 53 Copper embedded wiring 54 SiC-based insulating barrier film 55 SiOC main insulating interlayer 63 Copper embedded wiring 64 SiC-based insulating Barrier film 65 SiOC main interlayer insulating film 73 Seventh layer copper embedded wiring 74 SiC insulating barrier film 75 Plasma TEOS main interlayer insulating film 83 Eighth layer copper embedded wiring 84 SiC insulating barrier film 85 Plasma TEOS main Interlayer insulating film 201 FEOL process 202 BEOL process 203 Solder bump formation process 204 Wafer probe inspection process 205 Bump height inspection process 206 Wafer dicing process 211 Flip chip bonding process 212 Underfill process 213 Resin sealing process 214 External solder bump Formation process H Bump height Jchem Flow due to concentration gradient in intermetallic compound layer Jem Flow due to electromigration in solder Jim / sn Flow rate balance at intermetallic compound layer / solder interface Js Flow due to stress gradient in intermetallic compound layer J'em Flow due to electromigration in intermetallic compound layer J's Flow due to stress gradient in solder M1 Embedded first wiring layer M2 Embedded second wiring layer M3 Embedded third wiring layer M4 Embedded fourth wiring layer M5 Embedded type 5th wiring layer M6 Embedded type 6th wiring layer M7 Embedded type 7th wiring layer M8 Embedded type 8th wiring layer PM Premetal region WS The wiring layer on a semiconductor substrate

Claims (10)

Semiconductor integrated circuit devices including:
(A) a semiconductor substrate having a first main surface;
(B) a number of UBM pads provided on the first main surface of the semiconductor substrate;
(C) a substantially spherical solder bump provided on each UBM pad of the multiple UBM pads and mainly composed of a solder member;
(D) A first metal partition made of a material different from the solder bump, which divides the solder bump into an upper part and a lower part in an intermediate part of the solder bump.     2. The semiconductor integrated circuit device according to claim 1, wherein the first metal partition includes a first partition metal film having solder wettability, and main components and tin constituting the partition metal film as main components. It is basically composed of one intermetallic compound layer.     3. The semiconductor integrated circuit device according to claim 2, wherein the main component of the first partition wall metal film is nickel or copper.     3. The semiconductor integrated circuit device according to claim 2, wherein the main component of the first partition wall metal film is nickel.     5. The semiconductor integrated circuit device according to claim 4, wherein the solder member of the solder bump is lead-free solder.     6. The semiconductor integrated circuit device according to claim 5, wherein the lead-free solder is tin-silver based lead-free solder.     7. The semiconductor integrated circuit device according to claim 6, wherein the semiconductor substrate is a semiconductor chip.     7. The semiconductor integrated circuit device according to claim 6, wherein the semiconductor substrate is a semiconductor wafer.     8. The semiconductor integrated circuit device according to claim 7, wherein the solder bumps are BGA internal bumps. 10. The semiconductor integrated circuit device according to claim 9, further comprising:
(E) A second metal partition made of the same material as the first metal partition, which further divides the upper part in the middle part of the upper part of the solder bump.

Images