JP2013110276A - Semiconductor substrate evaluation method and semiconductor substrate for evaluation - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor substrate evaluation method and a semiconductor substrate for evaluation, which can evaluate, with high accuracy, junction leakage current characteristics regarding a high quality wafer used for products such as a CCD and a CMOS sensor which require high yield.SOLUTION: A semiconductor substrate evaluation method comprises: forming on an evaluation target semiconductor substrate 1, a plurality of PN junctions 5, an isolation oxide film 6 for isolating the PN junctions 5 from each other and a channel stop layer 3 positioned under the isolation oxide film 6; and measuring junction leakage currents at the PN junctions 5 to perform evaluation.

Description

  The present invention relates to a semiconductor substrate evaluation method and an evaluation semiconductor substrate, and more particularly, to a semiconductor substrate evaluation method and an evaluation semiconductor substrate by junction leakage current.

  With the miniaturization and high performance of semiconductor devices such as solid-state image sensors such as memories and CCDs, in order to improve the product yield, silicon wafers as materials are required to have high quality, and this has been dealt with. Various silicon wafers have been developed. In the solid-state imaging device, the quality of the silicon substrate has a great influence, and in particular, the crystallinity of the wafer surface layer portion, which is presumed to directly affect the product characteristics, is important. As measures for improving surface layer quality, 1) high-temperature treatment in an atmosphere containing inert gas or hydrogen, 2) reduction of grown-in defects by improving pulling conditions, and 3) epitaxial growth wafers have been developed. ing.

  As a conventional method for evaluating the electrical characteristics of the surface quality of a silicon wafer, oxide film breakdown voltage (GOI) evaluation has been used. In this method, a gate oxide film is formed on a silicon surface by thermal oxidation, and an electrode is formed thereon to apply an electrical stress to the silicon oxide film as an insulator, and the silicon surface quality is evaluated based on the degree of insulation. Is. That is, if defects or metal impurities are present on the original silicon surface, these are taken into the silicon oxide film by thermal oxidation, or an oxide film according to the surface shape is formed. Therefore, the silicon surface quality is evaluated.

  In actual devices, this is the reliability of the gate oxide film of the MOSFET, and various wafers have been developed to improve this. In particular, research related to Grown-in defects related to COP has greatly contributed to the improvement of wafers and devices.

  However, even if there is no problem with the GOI, it is naturally possible that the device yield decreases, and in particular, in recent years, such events have become more and more accompanied with the higher integration of devices. In particular, in a solid-state imaging device, it is necessary to reduce the junction leakage current caused by the wafer in view of the principle, such as the influence of the diffusion current from the neutral region outside the depletion layer.

Faced with the above problems, the silicon wafer substrate is being further developed and improved, but there is a problem that the effect cannot be determined unless a device such as a solid-state imaging device is actually fabricated and evaluated. It was. Paying attention to the structure of the light receiving portion that can be said to be the heart of the solid-state imaging device, a PN junction is formed in the wafer surface, and this junction leakage current is measured.
For silicon wafer evaluation, a structure with a guard ring is disclosed in Patent Document 1 as an example of the structure, and its relationship with substrate deposition is introduced. However, in the guard ring structure, the stability of the voltage applied to the guard ring side is very important. Especially in recent devices, high integration and high performance have progressed, and very minute defects and minute contamination are affected. I want to keep the fluctuation as small as possible. Therefore, the structure which does not use a guard ring has been examined.

The details of the junction leakage current measurement related to the evaluation of a silicon substrate or the like are described in, for example, Patent Document 2. Regarding the structure, it is described that a PN junction is formed in a well region.
However, it is necessary to evaluate the junction leakage current at the pA level in order to improve the problem of white scratches and dark current of the solid-state imaging device, and the above evaluation method is insufficient in terms of accuracy.

JP-A-6-97247 JP 2001-77168 A

  The present invention has been made in view of the above problems. For example, it is possible to evaluate junction leakage current characteristics with high accuracy with respect to high quality wafers used in products requiring high yield such as CCD and CMOS sensors. An object of the present invention is to provide a semiconductor substrate evaluation method and an evaluation semiconductor substrate.

  In order to achieve the above object, the present invention is a method for evaluating a semiconductor substrate by a junction leakage current, and includes a plurality of PN junctions and an isolation oxide film that separates the plurality of PN junctions from each other. And a channel stop layer positioned under the isolation oxide film, and measuring and evaluating junction leakage current at the plurality of PN junctions. .

With such a method for evaluating a semiconductor substrate, the channel stop layer used in the manufacture of an actual solid-state imaging device or the like can be used to evaluate the junction leakage current due to the influence of the isolation oxide film or the surface interface level. It is possible to prevent the generation of parasitic depletion capacitance around the well region where the junction is formed.
Therefore, the junction leakage current can be evaluated with high accuracy, and the semiconductor substrate can be evaluated with higher accuracy.
In addition, since a plurality of PN junctions are formed and the junction leakage current is measured and evaluated, the in-plane distribution of the junction leakage current can be grasped, and the cause of the occurrence of the junction leakage current can be examined in detail.

At this time, the area of each of the plurality of PN junctions can be set to 0.5 to 4 mm ² .
In the junction leakage current measurement in the present invention, for example, a voltage is applied by bringing a probe (needle) into contact with an electrode or the like formed on a PN junction. At this time, by setting the area of the PN junction to 4 mm ² or less, it is possible to prevent the application of a uniform electric field in the electrode surface due to the influence of the sheet resistance.

In actual devices, there are products in the order of microns, and in principle it is possible to produce a PN junction of that size, but it is not necessary to make it so small from the viewpoint of semiconductor substrate evaluation, and 0.5 mm ² should be minimized. it can. This is also to prevent the probe from being able to come into contact with a measurement device having a smaller area due to the accuracy of the measuring instrument, so that the defect sensitivity cannot be sufficiently obtained.

  Further, when forming the plurality of PN junctions, the isolation oxide film, and the channel stop layer, an oxide film is formed on the surface of the semiconductor substrate, and a part of the formed oxide film is removed. An opening is formed, and the remaining oxide film is used as an isolation oxide film. A dopant having the same conductivity type as that of the semiconductor substrate is ion-implanted from the plurality of openings and the isolation oxide film thus formed, A well region is formed in each of the openings, a channel stop layer is formed under the isolation oxide film, and a dopant having a conductivity type different from that of the well region is diffused into each well region. A plurality of PN junctions can be formed by forming a diffusion layer.

In this way, in particular, it is possible to easily form a channel stop layer.
Further, the junction leakage current can be increased by forming the well region, and the evaluation can be performed with high accuracy.

In the well region, the concentration of a dopant having the same conductivity type as that of the semiconductor substrate can be set to 1 × 10 ¹⁷ atoms / cm ³ or less.

  In particular, when the well region is formed by ion implantation of boron, if the concentration is too high, dislocations are formed by the ion implantation and defects are formed in the well region. If it is the said range which this inventor discovered, generation | occurrence | production of a dislocation | rearrangement does not occur and stable measurement is possible.

In the well region, a dopant concentration of the same conductivity type as that of the semiconductor substrate is set to 1 × 10 ¹⁶ to 1 × 10 ¹⁷ atoms / cm ³ and a depth is set to 2 μm or less. The dopant concentration of the conductivity type different from the conductivity type of the well region is 1 × 10 ^{18 to} 5 × 10 ²⁰ atoms / cm ³ , the depth is 1 μm or less, and in the channel stop layer, the conductivity type of the semiconductor substrate The concentration of the dopant of the same conductivity type can be 1 × 10 ¹⁶ to 1 × 10 ¹⁷ atoms / cm ³ and the depth can be 0.5 μm or less.

First, the well region can have an effect as a well region by setting the concentration to 1 × 10 ¹⁶ atoms / cm ³ or more (if it is lower than this, the impurity concentration is comparable to that of the semiconductor substrate). By setting it to 1 × 10 ¹⁷ atoms / cm ³ or less, it is possible to prevent the introduction of defects during ion implantation.
Further, by setting the depth to 2 μm or less, it is possible to prevent the introduction of defects due to an increase in the ion implantation acceleration voltage in order to form deeper than that.

The diffusion layer has a higher concentration than the well region for forming a PN junction. For example, the maximum concentration obtained by ion implantation or phosphorus glass diffusion is set as the upper limit (5 × 10 ²⁰ atoms / cm ³ ), and the lower limit (1 × 10 ¹⁸ atoms / cm ³ ) is one digit higher than the well region to form a PN junction. Concentration.
The depth can be within the range of the well region, for example, 1 μm or less.

The channel stop layer is more easily formed when the concentration is the same as that of the well region, and no carrier gradient occurs in the periphery.
Further, the depth does not need to be deep and can be in the above-described range that can be controlled by ion implantation.

  Further, the present invention is a semiconductor substrate for evaluation for evaluating by junction leakage current, wherein a plurality of PN junctions, an isolation oxide film separating the plurality of PN junctions, and a position below the isolation oxide film An evaluation semiconductor substrate is provided in which a channel stop layer is formed.

In such an evaluation semiconductor substrate, the channel stop layer can prevent the generation of parasitic depletion capacitance around the well region where the PN junction is formed even in the evaluation of the junction leakage current. The leakage current can be evaluated with high accuracy, and further, the semiconductor substrate can be evaluated with high accuracy.
In addition, it is possible to measure and evaluate junction leakage current by forming multiple PN junctions, to understand the in-plane distribution of junction leakage current, and to investigate the cause of junction leakage current in detail. It becomes possible.

At this time, each of the plurality of PN junctions may have an area of 0.5 to ⁴ mm ² .
When the voltage is 4 mm ² or less, a uniform electric field is generated in the electrode surface due to the influence of the sheet resistance when the probe is brought into contact with the electrode or the like formed on the PN junction in the measurement of the junction leakage current. It is possible to prevent the application from being impossible.
Further, from the viewpoint of evaluation of the semiconductor substrate, 0.5 mm ² or more is sufficient, and it is preferably more than that in terms of contact with the probe.

  The PN junction is formed in a well region into which a dopant having the same conductivity type as that of the semiconductor substrate is ion-implanted, and a dopant having a conductivity type different from the conductivity type of the well region. It can consist of a diffused diffusion layer.

  In such a case, the junction leakage current can be increased by the well region, and the evaluation can be performed with high accuracy.

The well region may have a dopant concentration of the same conductivity type as that of the semiconductor substrate of 1 × 10 ¹⁷ atoms / cm ³ or less.

  In particular, when a well region is formed by ion implantation of boron, if the concentration is too high, dislocations are formed by ion implantation and defects are formed in the well region. Stable measurement is possible.

The well region has a dopant concentration of 1 × 10 ¹⁶ to 1 × 10 ¹⁷ atoms / cm ³ of the same conductivity type as the conductivity type of the semiconductor substrate, a depth of 2 μm or less, and the diffusion layer has The dopant concentration of the conductivity type different from the conductivity type of the well region is 1 × 10 ^{18 to} 5 × 10 ²⁰ atoms / cm ³ , the depth is 1 μm or less, and the channel stop layer is formed on the semiconductor substrate. The concentration of a dopant having the same conductivity type as that of the first conductive layer may be 1 × 10 ¹⁶ to 1 × 10 ¹⁷ atoms / cm ³ and the depth may be 0.5 μm or less.

With respect to the well region, by setting the concentration to 1 × 10 ¹⁶ atoms / cm ³ or more, an effect as a well region can be obtained, and by setting the concentration to 1 × 10 ¹⁷ atoms / cm ³ or less, defects are caused during ion implantation Can be prevented from being introduced.
Further, by setting the depth to 2 μm or less, it is possible to prevent a defect from being introduced due to a high acceleration voltage for ion implantation.

For the diffusion layer, for example, the maximum concentration obtained by ion implantation or phosphorus glass diffusion is set as the upper limit (5 × 10 ²⁰ atoms / cm ³ ), and the lower limit (1 × 10 ¹⁸ atoms / cm ³ ) is used to form a PN junction. The density can be one digit higher in the area.
The depth can be within the range of the well region, for example, 1 μm or less.

The channel stop layer is more easily formed when the concentration is the same as that of the well region, and no carrier gradient occurs in the periphery.
Further, the depth does not need to be deep and can be in the above-described range that can be controlled by ion implantation.

  As described above, according to the semiconductor substrate evaluation method and the semiconductor substrate for evaluation according to the present invention, it is possible to prevent the generation of parasitic depletion capacitance around the well region where the PN junction is formed by the channel stop layer. The junction leakage current can be measured with higher accuracy and the semiconductor substrate can be evaluated.

It is the schematic which shows an example of the semiconductor substrate for evaluation of this invention. It is a figure which shows an example of the flow of the evaluation method of the semiconductor substrate of this invention. It is explanatory drawing which shows the state of the depletion layer in an Example. It is a graph which shows the relationship between the junction leakage current in an Example and Comparative Examples 1 and 2, and an applied voltage. 6 is an explanatory diagram showing a state of a depletion layer in Comparative Example 1. FIG. 10 is an explanatory diagram showing a state of a depletion layer in Comparative Example 2. FIG.

  As described above, Patent Document 2 describes the measurement of junction leakage current, but only describes the formation of a PN junction in the well region, but is insufficient in terms of measurement level accuracy. It was. Patent Document 2 does not describe the formation of a channel stop layer for preventing the generation of parasitic depletion capacitance around the well region, which is used in the manufacture of an actual solid-state imaging device. It is only measured with an evaluation element, and the parasitic depletion capacitance around the well region is not taken into consideration.

  However, it is necessary to evaluate the junction leakage current at the pA level in order to improve the problem of white scratches and dark current of the solid-state imaging device, and also in the evaluation of the junction leakage current, the generation of parasitic depletion capacitance around the well is prevented. It is considered necessary. As a result of considering and examining the above, the present inventor has found that the junction leak current detection accuracy can be improved by combining the structure described in Patent Document 2 with the formation of a channel stop layer in the measurement of a minute junction leak current. The present invention has been completed.

Hereinafter, although an embodiment of the present invention is described in detail, referring to drawings, the present invention is not limited to this.
First, the semiconductor substrate for evaluation of the present invention will be described.
FIG. 1 shows an outline of an example of a semiconductor substrate for evaluation according to the present invention. As shown in FIG. 1, in the semiconductor substrate for evaluation 1 of the present invention, a well region 2 in which a dopant having the same conductivity type as that of the semiconductor substrate 1 ′ is ion-implanted is formed in the semiconductor substrate 1 ′ to be evaluated. Yes. A channel stop layer 3 in which a dopant having the same conductivity type as that of the semiconductor substrate 1 ′ is ion-implanted is also formed around the well region 2. A diffusion layer 4 in which a dopant having a conductivity type different from that of the well region 2 is diffused is formed in the well region 2, and a PN junction 5 is formed in the well region.

  Here, the semiconductor substrate 1 ′, the well region 2, and the channel stop layer 3 are doped with a P-type dopant (boron or the like), while the diffusion layer 4 is doped with an N-type dopant (phosphorus or the like). Yes. However, it is naturally not limited to this aspect, and the reverse aspect is also possible.

A plurality of well regions 2 and diffusion layers 4 as described above are formed in the surface of the semiconductor substrate 1 ′, and a plurality of PN junctions 5 are formed.
An isolation oxide film 6 is formed on the surface of the semiconductor substrate 1 ′ to separate the PN junctions. The channel stop layer 3 is located immediately below the isolation oxide film 6.

  Here, although an example is given and demonstrated about the dopant concentration, depth, etc. of each area | region and layer, naturally it is not limited to this, It is possible to set to an appropriate numerical value each time. It can be determined appropriately according to the purpose and cost.

First, in the well region 2, when the dopant concentration is formed by ion implantation of the dopant, for example, dislocations are formed by ion implantation due to the high concentration, and defects are formed in the well region. In order to prevent this, it can be set to 1 × 10 ¹⁷ atoms / cm ³ or less. In particular, when the dopant is boron, attention should be paid to the tendency of the above-described defect formation.
In particular, when the dopant concentration is 1 × 10 ¹⁶ atoms / cm ³ or more, an effect as a well region can be provided. This is because if it is lower than this, the dopant concentration will be comparable to that of the semiconductor substrate 1 ′.

Further, by setting the depth to 2 μm or less, it is possible to prevent the introduction of defects due to the high acceleration voltage for ion implantation.
Note that if it is too shallow, the width of the depletion layer that can be evaluated becomes small, and sensitivity is lowered as an evaluation of the semiconductor substrate 1 ′.

In the diffusion layer 4, for example, the maximum concentration obtained by ion implantation or phosphorous glass diffusion is set as the upper limit (5 × 10 ²⁰ atoms / cm ³ ), and the lower limit (1 × 10 ¹⁸ atoms / cm ³ ) forms a PN junction. Therefore, the concentration can be increased by an order of magnitude in the well region.
Regarding the depth, since it is naturally formed in the well, it can be, for example, 1 μm or less.

Next, the channel stop layer 3 is more easily formed when the dopant concentration is the same as that of the well region 2 and no carrier gradient occurs in the periphery. Therefore, it can be set to 1 * 10 < ¹⁶ > -1 * 10 < ¹⁷ > atoms / cm < ³ >.
The depth does not need to be deep and can be 0.5 μm or less which can be controlled by ion implantation.

Next, the isolation oxide film 6 will be described.
The formation method and thickness of the isolation oxide film 6 are not particularly limited, and can be determined each time. For example, a thermal oxide film or a CVD film may be used. Regarding the thickness, in particular, in the case where the channel stop layer 3 is formed by ion implantation from above the isolation oxide film, it can be in the range of, for example, 100 to 500 nm. In such a range, it is possible to form the channel stop layer 3 immediately below the isolation oxide film 6 by appropriately passing a part of the dopant during ion implantation.

In addition, regarding the PN junction 5, the individual area (here, the area of the portion (opening 7) surrounded by the isolation oxide film 6) can be set to 0.5 to 4 mm ² .
In the measurement of the junction leakage current, the probe is brought into point contact with the diffusion layer 4 and a voltage is applied. By making the area of the PN junction 4 mm ² or less, a uniform electric field can be applied due to the influence of the sheet resistance. It can be prevented from disappearing.
Furthermore, 0.5 mm ² or more is sufficient from the viewpoint of evaluation of the semiconductor substrate, and 0.5 mm ² or more is preferable from the viewpoint of probe contact and the like.

  If a plurality of PN junctions 5 are formed, the in-plane distribution of the junction leakage current of the semiconductor substrate 1 ′ can be measured as desired, but the specific number is not particularly limited. The number of the PN junctions 5 can be appropriately determined in consideration of the area of the PN junction 5, the target data amount, the measurement effort, the cost and the like.

  Furthermore, as necessary, an electrode 8 made of aluminum, polycrystalline silicon, or the like is further formed on the plurality of PN junctions 5 by photolithography. The junction leakage current can be measured by applying a voltage with a probe in contact with the electrode 8.

Next, a method for evaluating a semiconductor substrate according to the present invention will be described.
FIG. 2 shows an example of the flow of the semiconductor substrate evaluation method of the present invention. Note that the present invention is not limited to the flow of FIG. 2, and after forming a plurality of PN junctions, an isolation oxide film separating the PN junctions, and a channel stop layer located under the isolation oxide film, What is necessary is just to measure and evaluate the junction leakage current in junction, and it can determine suitably about each specific process. As will be described later, the channel stop layer can be particularly easily formed with the flow of FIG.
(Step 1) Formation of Oxide Film First, an oxide film 9 serving as a mask is formed on the prepared semiconductor substrate 1 ′ to be evaluated. The oxide film 9 may be formed by thermal oxidation or CVD, but attention should be paid to the following points.

In a later step, ion implantation is performed to form the well region 2, and the thickness can be made such that ions at this time slightly pass through the oxide film 9. Since this thickness depends on the element, acceleration voltage, etc., it is necessary to find a value suitable for the process and equipment.
For example, the thickness can be set to 100 nm or more so as to function appropriately as a mask at the time of ion implantation and so that the pattern becomes thin and pattern recognition becomes impossible at the time of actual measurement.
Further, for example, if it is thicker than 500 nm, the ion-implanted ions are completely masked, and the channel stop layer 3 is hardly formed immediately below the oxide film 9.

  Of course, the thickness of the oxide film is not particularly limited, but as a practical range, it can be in the range of about 100 to 500 nm.

(Process 2) Window opening process (formation of opening and isolation oxide film)
As described above, photolithography is performed on the oxide film 9 formed in the step 1, and a part of the oxide film 9 is subjected to windowing processing by dry etching or wet etching. As described above, the area of the windowed portion (opening 7) at this time corresponds to the area of the PN junction. Therefore, in forming the opening 7, as described above, it can be set to 0.5 to ⁴ mm ² , for example. A plurality of openings 7 are formed so that the in-plane distribution of the junction leakage current can be obtained, but the specific number of formation is not particularly limited and can be determined each time.
Note that the oxide film 9 remaining in the portion other than the opening 7 corresponds to the isolation oxide film 6.

(Step 3) Ion implantation process (formation of well region and channel stop layer)
Next, in this state, an ion implantation process is performed from above the opening 7 and the isolation oxide film 6. By this ion implantation process, a dopant having the same conductivity type as that of the semiconductor substrate 1 ′ is implanted to form the well region 2 at the opening 7. At this time, the channel stop layer 3 is formed immediately below the isolation oxide film 6. Such a method is particularly convenient because not only the well region 2 but also the channel stop layer 3 can be formed simultaneously.

As described above, for example, the dopant concentration of the well region 2 can be set to 1 × 10 ¹⁶ to 1 × 10 ¹⁷ atoms / cm ³ and the depth can be set to 2 μm or less. In the channel stop layer 3, the dopant concentration can be set to 1 × 10 ¹⁶ to 1 × 10 ¹⁷ atoms / cm ³ and the depth can be set to 0.5 μm or less.

In particular, the ion implantation process conditions (dose amount, acceleration voltage, etc.) at this time take into account the thickness of the isolation oxide film 6 and a desired depth (thickness) immediately below the isolation oxide film 6. Care must be taken to form the channel stop layer 3). It is preferable to conduct an experiment or the like in advance and investigate an appropriate combination of oxide film thickness and ion implantation treatment conditions.
Thereafter, recovery heat treatment is performed.

(Step 4) Formation of Diffusion Layer and PN Junction Thereafter, a dopant having a conductivity type different from that of the well region 2 is diffused to form the diffusion layer 4 in order to form a PN junction. The diffusion at this time may be an ion implantation process or a solid diffusion process. Further, when the ion implantation process is used, it can also serve as a recovery heat treatment when the well region 2 is formed.
As described above, a PN junction can be formed, and the semiconductor substrate 1 for evaluation can be obtained.

As described above, for example, in the diffusion layer 4, the dopant concentration of the conductivity type different from the conductivity type of the well region 2 is 1 × 10 ^{18 to} 5 × 10 ²⁰ atoms / cm ³ and the depth is 1 μm or less. be able to.

(Step 5) Measurement of Junction Leakage Current and Evaluation of Semiconductor Substrate The evaluation semiconductor substrate 1 obtained as described above is made of aluminum, polycrystalline silicon, or the like by photolithography on a plurality of PN junctions as necessary. Each of the electrodes 8 is further formed, a probe is brought into contact with the electrodes 8, a voltage is applied, and a junction leakage current is measured.
In the present invention, since the channel stop layer 3 is formed around the well region 2, that is, immediately below the isolation oxide film 6, it is possible to prevent the occurrence of parasitic depletion capacitance around the well region 2, thereby preventing junction leakage. Current detection accuracy can be improved.
Then, it is possible to evaluate the semiconductor substrate with high accuracy by using the high-accuracy junction leakage current characteristic thus obtained.

EXAMPLES Hereinafter, although an Example and a comparative example are shown and this invention is demonstrated more concretely, this invention is not limited to these.
(Example)
The semiconductor substrate evaluation method of the present invention was carried out.
A silicon wafer having a resistivity of 10 Ω · cm, boron dope (concentration of 1 × 10 ¹⁵ atoms / cm ³ ), and a diameter of 200 mm was prepared as a material. First, this was subjected to a heat treatment at 1000 ° C. for 90 minutes in a Pyro atmosphere to form an oxide film of 200 nm.

Thereafter, a resist is applied and photolithography is performed. This time I chose negative resist. The mask was devised so that a plurality of openings of an oxide film with an area of 4 mm ² could be obtained in the wafer surface. The resist-coated wafer was etched with an oxide film with a buffered HF solution, and the resist was removed with a sulfuric acid / hydrogen peroxide mixture, followed by RCA cleaning.

Boron is ion-implanted into the wafer in which the opening is formed at an acceleration voltage of 55 KeV and a dose of 2 × 10 ¹² atoms / cm ² to form a well region and a channel stop layer, and recovered at 1000 ° C. in a nitrogen atmosphere. Annealing was performed.
Thereafter, phosphorus glass was applied and diffused, and phosphorus was diffused from the surface to form a diffusion layer in the well region to form a PN junction.
Under this condition, the well region has a boron concentration of 1 × 10 ¹⁷ atoms / cm ³ and a depth of 1 μm, and the channel stop layer has a concentration immediately below the oxide film of 1 × 10 ¹⁷ atoms / cm ³ and a depth of 0.5 μm. The diffusion layer had a concentration of 1 × 10 ¹⁹ atoms / cm ³ and a depth of 0.4 μm.

  Then, an electrode made of polycrystalline silicon was formed in the opening, and a probe was applied to apply a voltage to measure the junction leakage current. The state of the depletion layer at this time is shown in FIG.

An example of the measurement result of the junction leakage current of this structure is shown in FIG. As shown in FIG. 4, it can be seen that the junction leakage current of about 1 × 10 ⁻¹¹ to 1 × 10 ⁻¹² A, that is, the picoampere level can be detected. If measurement is possible at such a level, acquisition of temperature characteristics and the like is easy.
In this way, using a plurality of PN junctions formed in the wafer surface, the distribution of junction leakage current in the wafer surface could be obtained.

The junction leakage current was measured in the same manner as described above except that the dose amount during ion implantation was 1 × 10 ¹³ atoms / cm ² so that the boron concentration in the well region was 1 × 10 ¹⁸ atoms / cm ³ . .
As a result, the value of the junction leakage current increased by an order of magnitude, compared to when the boron concentration was 1 × 10 ¹⁷ atoms / cm ³ , and became about 1 × 10 ⁻¹⁰ to 1 × 10 ⁻¹¹ A. . This is presumably due to defects introduced at the time of ion implantation.

(Comparative Example 1)
Unlike the semiconductor substrate evaluation method of the present invention, the semiconductor substrate was evaluated by measuring the junction leakage current without forming the well region and the channel stop layer.
A wafer having an opening formed therein was prepared in the same manner as in Example 1, phosphorus glass was applied and diffused, and phosphorus was diffused from the surface to form a diffusion layer in the wafer, thereby forming a PN junction. The diffusion layer had a concentration of 1 × 10 ¹⁹ atoms / cm ³ and a depth of 0.4 μm.

  Then, an electrode made of polycrystalline silicon was formed in the opening, and a probe was applied to apply a voltage to measure the junction leakage current. The state of the depletion layer at this time is shown in FIG. Unlike the embodiment, a depletion layer is also generated around the well region.

An example of the measurement result of the junction leakage current is also shown in FIG. As shown in FIG. 4, a junction leakage current of about 1 × 10 ⁻³ to 1 × 10 ⁻⁵ A was detected. That is, even a microampere level junction leakage current cannot be detected, and such a level is insufficient in terms of sensitivity and inappropriate for wafer analysis.

(Comparative Example 2)
Unlike the method for evaluating a semiconductor substrate of the present invention, the junction leakage current was measured without forming a channel stop layer to evaluate the semiconductor substrate.
A silicon wafer similar to that prepared in Example 1 was heat-treated at 1000 ° C. for 300 minutes in a Pyro atmosphere to form an 800 nm oxide film.

Thereafter, a resist is applied and photolithography is performed. This time I chose negative resist. The mask was devised so that a plurality of openings of an oxide film with an area of 4 mm ² could be obtained in the wafer surface. The resist-coated wafer was etched with an oxide film with a buffered HF solution, and the resist was removed with a sulfuric acid / hydrogen peroxide mixture, followed by RCA cleaning.

Boron was ion-implanted into the wafer with the opening formed at an acceleration voltage of 55 KeV and a dose of 2 × 10 ¹² atoms / cm ² to form a well region. At this acceleration voltage, boron could not pass through the 800 nm oxide film, and no channel stop layer was formed around the well region. Then, recovery annealing was performed at 1000 ° C. in a nitrogen atmosphere.
Thereafter, phosphorus glass was applied and diffused, and phosphorus was diffused from the surface to form a diffusion layer in the well region to form a PN junction.
Under these conditions, the well region had a boron concentration of 1 × 10 ¹⁷ atoms / cm ³ and a depth of 1 μm, and the diffusion layer had a concentration of 1 × 10 ¹⁹ atoms / cm ³ and a depth of 0.4 μm.

  Then, an electrode made of polycrystalline silicon was formed in the opening, and a probe was applied to apply a voltage to measure the junction leakage current. The state of the depletion layer at this time is shown in FIG. Even in this case, unlike the embodiment, a depletion layer is also generated around the well region.

An example of the measurement result of the junction leakage current is also shown in FIG. As shown in FIG. 4, only the junction leakage current of about 1 × 10 ⁻⁸ to 1 × 10 ⁻⁹ A can be detected, that is, the sub-picoampere level can be detected. Although improved compared to Comparative Example 1, since the channel stop layer is not formed, a depletion layer is generated around the well region, and the detection accuracy of the extremely high junction leakage current as in the example is obtained. I can't understand.

  The present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and the present invention has substantially the same configuration as the technical idea described in the claims of the present invention, and any device that exhibits the same function and effect is the present invention. It is included in the technical scope of the invention.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate for evaluation of this invention, 1 '... Semiconductor substrate, 2 ... Well area | region,
3 ... channel stop layer, 4 ... diffusion layer, 5 ... PN junction,
6 ... isolation oxide film, 7 ... opening, 8 ... electrode, 9 ... oxide film.

Claims (10)

A method for evaluating a semiconductor substrate by junction leakage current,
Forming a plurality of PN junctions, an isolation oxide film separating the plurality of PN junctions, and a channel stop layer located under the isolation oxide film on the semiconductor substrate to be evaluated; A method for evaluating a semiconductor substrate, comprising measuring and evaluating a junction leakage current in the semiconductor substrate. The method for evaluating a semiconductor substrate according to claim 1, wherein an area of each of the plurality of PN junctions is set to 0.5 to 4 mm ² . When forming the plurality of PN junctions, the isolation oxide film, and the channel stop layer,
Forming an oxide film on the surface of the semiconductor substrate;
By removing a part of the formed oxide film, a plurality of openings are formed, and the remaining oxide film is used as an isolation oxide film.
A dopant having the same conductivity type as that of the semiconductor substrate is ion-implanted from above the plurality of openings and the isolation oxide film to form a well region in each of the plurality of openings, and below the isolation oxide film Forming a channel stop layer on the
2. The plurality of PN junctions are formed in each of the well regions by diffusing a dopant having a conductivity type different from that of the well region to form a diffusion layer. Item 3. A method for evaluating a semiconductor substrate according to Item 2. 4. The concentration of a dopant having the same conductivity type as that of the semiconductor substrate in the well region is set to 1 × 10 ¹⁷ atoms / cm ³ or less. 5. Evaluation method of semiconductor substrate. In the well region, the concentration of a dopant having the same conductivity type as that of the semiconductor substrate is set to 1 × 10 ¹⁶ to 1 × 10 ¹⁷ atoms / cm ³ , and the depth is set to 2 μm or less.
In the diffusion layer, the concentration of a dopant having a conductivity type different from the conductivity type of the well region is 1 × 10 ^{18 to} 5 × 10 ²⁰ atoms / cm ³ , and the depth is 1 μm or less.
In the channel stop layer, a dopant concentration of the same conductivity type as that of the semiconductor substrate is set to 1 × 10 ¹⁶ to 1 × 10 ¹⁷ atoms / cm ³ and a depth is set to 0.5 μm or less. The method for evaluating a semiconductor substrate according to any one of claims 1 to 4. An evaluation semiconductor substrate for evaluating by junction leakage current,
A semiconductor substrate for evaluation, comprising: a plurality of PN junctions; an isolation oxide film that separates the plurality of PN junctions; and a channel stop layer positioned under the isolation oxide film. The semiconductor substrate for evaluation according to claim 6, wherein each of the plurality of PN junctions has an area of 0.5 to ⁴ mm ² .   The PN junction is formed in a well region in which a dopant of the same conductivity type as that of the semiconductor substrate is ion-implanted, and a dopant of a conductivity type different from the conductivity type of the well region is diffused. The evaluation semiconductor substrate according to claim 6, wherein the evaluation semiconductor substrate comprises a diffusion layer. 9. The well region according to claim 6, wherein a concentration of a dopant having the same conductivity type as that of the semiconductor substrate is 1 × 10 ¹⁷ atoms / cm ³ or less in the well region. The semiconductor substrate for evaluation as described in 2. The well region has a dopant concentration of the same conductivity type as that of the semiconductor substrate of 1 × 10 ¹⁶ to 1 × 10 ¹⁷ atoms / cm ³ and a depth of 2 μm or less.
The diffusion layer has a dopant concentration of 1 × 10 ^{18 to} 5 × 10 ²⁰ atoms / cm ³ different from that of the well region and a depth of 1 μm or less.
The channel stop layer has a dopant concentration of the same conductivity type as that of the semiconductor substrate of 1 × 10 ¹⁶ to 1 × 10 ¹⁷ atoms / cm ³ and a depth of 0.5 μm or less. The evaluation semiconductor substrate according to claim 6, wherein the evaluation semiconductor substrate is a semiconductor substrate for evaluation.

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