JP2013105911A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device of a compact size, which is applicable to any wiring design and includes paired resistive elements having a highly accurate resistance ratio therebetween.SOLUTION: In a semiconductor device 100, when defining a length of an outer edge of each of resistive elements R1f, R2f as L; a length of each outer edge of the resistive elements R1f, R2f directly above distribution lines 4a, 4b as a length-on-distribution-line H; outer-edge-distribution-line coverage V as V=H/2L; an outer edge length of the resistive element R2f directly above reflection correction pads Pa, Pb formed from a wiring layer the same with the distribution lines 4a, 4b at least under the resistive element R2f which has smaller outer-edge-distribution-line coverage V among two resistive elements R1f, R2f and which is arranged directly below the outer edge of the resistive element R2f as a length-on-correction-pad P; and outer-edge-wiring-layer coverage W of the R1f, R2f as W=(H+P)/2L, a difference of the outer-edge-wiring-layer coverage W between the resistive elements R1f, R2f is set smaller than a difference of the outer-edge-distribution-line coverage V between the resistive elements R1f, R2f.

Description

  The present invention relates to a semiconductor device in which two resistors made of a thin film are disposed adjacent to each other above a wiring in a semiconductor substrate via an insulating film.

  In a semiconductor device in which a large number of semiconductor elements are integrated on a small semiconductor substrate and connected by wiring, a thin film resistor is disposed above the semiconductor substrate (semiconductor chip) via an insulating film. There is. In particular, in a semiconductor device configured with an analog circuit, a pair resistor connected in series used for voltage division requires a highly accurate resistance ratio in order to ensure good circuit characteristics, and is insulated above the semiconductor substrate. Two rectangular resistors made of a thin film are arranged adjacent to each other through the film.

Conventionally, the pair resistance by the thin film resistor is arranged not on an element region of a semiconductor substrate on which a semiconductor element or wiring is formed but on a flat field region on which no semiconductor element or wiring is formed. This is because, when arranged on the element region, the resistance value of the thin film resistor is shifted due to the step of the semiconductor element or the wiring, and the resistance ratio of the pair resistor is shifted from the design. On the other hand, in order to reduce the size of the semiconductor device and reduce the cost, it is preferable that the pair resistance by the thin film resistor can be arranged not only on the field region but also on the element region.

  For example, Japanese Patent Application Laid-Open No. 2002-124039 (Patent Document 1) and US Pat. No. 7,208,388 (Patent Document) disclose a method for solving the above-described problem of resistance deviation when a thin film resistor is disposed on an element region. Document 2).

  In the semiconductor device and the manufacturing method disclosed in Patent Document 1, in order to dispose the thin film resistor above the stepped semiconductor element and wiring, the interlayer insulating film is planarized by CMP (Chemical Mechanical Polishing), A thin film resistor is formed thereon. Also, in Patent Document 2, as in Patent Document 1, a structure in which a thin film resistor is formed on an interlayer insulating film flattened by CMP is employed. Furthermore, in Patent Document 2, in order to prevent a dish-like dent due to over-grinding of the surface of the interlayer insulating film that occurs during CMP, a dummy filling layer composed of parallel strip lines and a dielectric layer is disposed under the interlayer insulating film. In addition, the flatness of the surface of the interlayer insulating film at the position where the thin film resistor is formed after CMP is ensured.

JP 2002-124039 A US Pat. No. 7,208,388

  When the thin film resistor is disposed on the element region, the method of planarizing the surface of the interlayer insulating film forming the thin film resistor by CMP is based on the design of the resistance value of the thin film resistor caused by the step of the semiconductor element or wiring. This is an effective method for preventing the deviation. However, the method of disposing the dummy filling layer under the interlayer insulating film as in Patent Document 2 has an influence on the wiring (wiring design) of the wiring connected to the semiconductor element when the thin film resistor is disposed on the element region. In general, it cannot be adopted. Further, planarization of the interlayer insulating film by CMP is a cost increase factor, so it is more preferable if it can be eliminated.

  Further, when the thin film resistor is disposed on the element region, there are the following problems in patterning the thin film resistor as well as the resistance value deviation caused by the step of the semiconductor element or the wiring. That is, in the case where there is silicon (Si) of the substrate directly below the thin film resistor and the case of aluminum (Al) of the wiring, the reflectance of the exposure light transmitted through the thin film resistor layer in the photolithography process is Different for both wirings. Therefore, when the substrate and the wiring are mixed directly under the thin film resistor, the reflection ratio of the exposure light transmitted through the thin film resistor layer in the photolithography process varies depending on the presence ratio of the substrate and the wiring. For this reason, the resist pattern width varies depending on the arrangement position of the thin film resistor, and the resistance value of the obtained thin film resistor deviates from the design. In particular, for a pair of thin film resistors that require a high-precision resistance ratio, such as a pair resistor used for voltage division, a good circuit can be obtained only by a resistance ratio deviation caused by a photolithography process. It becomes difficult to ensure the characteristics.

  Accordingly, the present invention provides a semiconductor device in which two thin film resistors are disposed adjacent to each other above a wiring in a semiconductor substrate via an insulating film, and an arbitrary wiring design for connecting to a semiconductor element is provided. It is an object of the present invention to provide a small-sized semiconductor device including two resistors having a highly accurate resistance ratio.

  The invention according to claim 1 is a semiconductor device in which two rectangular resistors made of a thin film are arranged adjacent to each other via an insulating film above a wiring in a semiconductor substrate. The length of the resistor defined by L is L, the length of the outer side of the resistor directly above the wiring is the length H on the wiring, and the outer wiring coverage V of the resistor is V = H / When defined by 2L, a reflection correction pad formed from the same wiring layer as the wiring is at least below the resistor having a small outer-side wiring coverage V of the two resistors, and the outer edge of the resistor. The length of the outer side of the resistor directly above the reflection correction pad is defined as a correction pad upper length P, and the outer-side wiring layer coverage W of the resistor is expressed as W = (H + P ) / 2L, the outer-side wiring layer coverage W for the two resistors. Difference, is characterized by comprising set smaller than the difference between the perimeter wire coverage V.

  The semiconductor device is a semiconductor device in which two rectangular resistors made of thin films are arranged adjacent to each other.

  In a semiconductor device in which a large number of semiconductor elements are integrated on a small semiconductor substrate and connected by wiring, the thin film is formed above the semiconductor substrate (semiconductor chip) via an insulating film as in the semiconductor device described above. There is a thing which arranges the resistor which becomes. In particular, in a semiconductor device configured with an analog circuit, a pair resistor connected in series used for voltage division requires a highly accurate resistance ratio in order to ensure good circuit characteristics, and is insulated above the semiconductor substrate. Two rectangular resistors made of a thin film are arranged adjacent to each other through the film.

  In the semiconductor device, the two resistors made of a thin film are not on the field region around the semiconductor substrate (semiconductor chip), which is a conventional general arrangement position, but on a semiconductor substrate on which semiconductor elements and wirings are formed. Is disposed above the wiring via an insulating film. For this reason, compared with the conventional semiconductor device which arrange | positions two resistors on a field area | region, the said semiconductor device can be made into a small and low-cost semiconductor device.

  On the other hand, when two resistors made of thin films are arranged on the element region as in the semiconductor device described above, a resistance value deviation occurs due to a step difference between the semiconductor element and the wiring. There is a problem that the resistance ratio of the individual resistors deviates from the design value. The problem of the shift in resistance value due to the step of the semiconductor element or the wiring is that, for example, the insulating film used between the layers is planarized by CMP (Chemical Mechanical Polishing), and then two resistors are formed thereon. Can be solved. However, planarization of the insulating film by CMP is a cost increase factor, and is preferably eliminated if possible.

  Furthermore, in the case where two thin-film resistors are arranged on the element region, not only the resistance value deviation caused by the step of the semiconductor element or the wiring but also the following problems are involved in the patterning of the resistors. is there. That is, the reflection of exposure light in the photolithography process is different between the substrate made of silicon (Si) and the wiring generally made of aluminum (Al) and usually having an antireflection film formed on the surface. Therefore, it differs between the substrate and the wiring. For this reason, when seeing directly under the position where the resistor is formed, the exposure light reflected through the thin film resistor layer in the photolithography process is reflected between the position where the substrate is located and the position where the wiring is located. There are different positions. Therefore, when the substrate and the wiring are mixed directly under the resistor, the reflection ratio of the exposure light transmitted through the resistor layer made of a thin film in the photolithography process from the base varies depending on the presence ratio of the substrate and the wiring. For this reason, the width of the rectangular resist pattern varies depending on the arrangement position of the resistor, and the resistance of the obtained resistor deviates from the design value. In particular, for a pair of resistors that require a highly accurate resistance ratio, such as a pair resistance used for voltage division, a good circuit characteristic can be obtained only by a resistance ratio shift caused by the photolithography process. It becomes difficult to ensure.

  In the semiconductor device described above, when two resistors are arranged on the element region, the resistance ratio difference between the two resistors due to the difference in the reflection state between the substrate and the wiring immediately below in the photolithography process is eliminated. To do. For this reason, in the above semiconductor device, the cause of the deviation of the resistance ratio is analyzed, and for two rectangular resistors, the length of the resistor is L, and the length of the outer side of the resistor directly above the wiring Is the length H on the wiring, and the outer side wiring coverage V of the resistor is defined as V = H / 2L, and attention is paid to the difference in the outer side wiring coverage V between the two resistors.

  The variation in the resist pattern width of the resistor in the photolithography process described above can be quantified by the outer-side wiring coverage V of the resistor defined above, and the resistance value change due thereto is also proportional to the outer-side wiring coverage V. On the other hand, the pattern of the semiconductor element and the wiring connected thereto is determined prior to the arrangement position of the two resistors in consideration of the characteristics of the entire circuit. For this reason, when two resistors are arranged on the element region, the wiring pattern immediately below the resistors varies depending on the arrangement position, and the outer-side wiring coverage V also varies depending on the arrangement position. . Therefore, the resistance value change of the resistors also varies, and the resistance ratio deviation between the two resistors cannot be controlled by any means.

  Therefore, in the semiconductor device, a reflection correction pad formed from the same wiring layer as the wiring is provided at least under the resistor having a small outer side wiring coverage V of the two resistors. It is arranged immediately below. The reflection correction pad may be, for example, an isolated region that does not affect the circuit current flowing through the wiring, or may flow through the wiring in a convex region in which a part of the wiring protrudes and the wiring width is wider than the surroundings. It may be a region where the influence on the circuit current is small. This reflection correction pad corrects the data of the initial wiring pattern connected to the previously determined semiconductor element, and can be automatically generated with a predetermined condition by CAD. Due to the arrangement of the reflection correction pad, in the semiconductor device, the length of the outer side of the resistor immediately above the reflection correction pad is set to the correction pad upper length P, and the outer side wiring layer coverage W of the resistor is set to W. When defined as = (H + P) / 2L, the difference in the outer wiring layer coverage W is set to be smaller than the difference in the outer wiring coverage V for the two resistors.

  From the definition, the outer side wiring layer coverage W quantifies the width variation of the resist pattern of the resistor in the photolithography process when a reflection correction pad is added to the initial wiring pattern. After the reflection correction pad is arranged, the difference in the outer side wiring layer coverage W between the two resistors is set to be smaller than the difference in the previous outer side wiring coverage V. As a result, the difference in the reflection ratio of the exposure light from the ground in the photolithography process is reduced for the two resistors, and the resist pattern width variation and the resistance value change of the two resistors approach the same ratio. It is possible to suppress a resistance ratio shift between the two resistors. In particular, when an antireflection film is formed on the upper surface of the wiring layer, it is possible to reduce changes in resistance values of the two resistors by arranging the reflection correction pads.

  As described above, the semiconductor device is a semiconductor device in which two resistors made of a thin film are arranged adjacent to each other via an insulating film above a wiring in a semiconductor substrate. The invention can be applied to any wiring design to be connected, and a resistance ratio shift caused by a photolithography process is suppressed, so that a small semiconductor device including two resistors having a highly accurate resistance ratio can be obtained. it can.

  In the semiconductor device, as described in claim 2, the length of the outer side of the wiring immediately below the resistor is a wiring outer side length T, and the wiring outer side coverage X by the resistor is X = T / L, and the length of the outer side of the reflection correction pad immediately below the resistor is defined as the reflection correction pad outer side length Q, and the wiring layer outer side coverage Y by the resistor is defined as Y When defined as = (T + Q) / L, it is preferable that the difference in the wiring layer outer side coverage Y is set smaller than the difference in the wiring outer side coverage X for the two resistors.

  In the semiconductor device described above, when two resistors are arranged on the element region, the resistance ratio shift between the two resistors due to the step difference of the wiring connected to the semiconductor element is eliminated. For this reason, in the semiconductor device, the cause of the deviation of the resistance ratio is analyzed, and the length of the outer periphery of the wiring immediately below the resistors is defined as the outer periphery length T of the two rectangular resistors. The wiring outer side coverage X by the resistor is defined as X = T / L, and attention is paid to the difference in the wiring outer side coverage X for the two resistors.

  The difference in resistance ratio between the two resistors due to the level difference of the wiring can be quantified by the wiring outer side coverage X by the resistance defined above. The wiring outer side coverage X indicates the existence ratio of the step due to the wiring immediately below the resistor, and the resistance value change due thereto is also proportional to the wiring outer side coverage X. Similar to the outer side wiring coverage V described above, when two resistors are arranged at desired positions on the element region, the respective wiring outer side coverages X by the two resistors vary depending on the arrangement positions. Value.

  Therefore, in the semiconductor device, the pattern shape of the reflection correction pad introduced in the semiconductor device of claim 1 is set so that the following relationship is satisfied, thereby causing a step difference in the wiring connected to the semiconductor element. The resistance ratio deviation between the two resistors is reduced. That is, in the semiconductor device, the length of the outer side of the reflection correction pad immediately below the resistor is the reflection correction pad outer side length Q, and the wiring layer outer side coverage Y by the resistor is Y = (T + Q). When defined by / L, the difference in the wiring layer outer side coverage Y is set to be smaller than the difference in the wiring outer side coverage X for the two resistors.

  As described above, after the arrangement of the reflection correction pad having the pattern shape that satisfies the above relationship, the difference in the wiring layer outer side coverage Y between the two resistors is equal to the previous wiring outer side coverage X. It is set to be smaller than the difference. As a result, for the two resistors, the difference in the existence ratio of the step due to the wiring immediately below the resistor is also reduced, and the resistance value change of the two resistors due to the step of the wiring approaches the same ratio, The resistance ratio deviation between the two resistors can be suppressed.

  As described above, the semiconductor device described above is a small semiconductor device including two resistors having a more accurate resistance ratio by suppressing a resistance ratio shift caused by a step of a wiring connected to the semiconductor element. It can be.

  As described above, the reflection correction pad in the semiconductor device can be an isolated region that does not affect the circuit current flowing through the wiring. According to a fourth aspect of the present invention, the reflection correction pad may be a convex region in which a part of the wiring protrudes and the wiring width is wider than the surrounding area.

  Further, as described in claim 5, the wiring layer in the semiconductor device may be composed of two or more layers.

  When the wiring layers are composed of two or more layers, the outer wiring coverage V and the outer wiring coverage W described in claim 1 are all projected on one surface. Then, the length H on the wiring and the length P on the correction pad are calculated. Further, the wiring outer edge coverage X and the wiring layer outer edge covering ratio Y described in claim 2 are calculated by adding all the wiring outer edge length T and the reflection correction pad outer edge length Q in each wiring layer. To do.

  In the semiconductor device, it is preferable that an antireflection film is formed on the upper surface of the wiring layer. As described above, in this case, not only can the resistance ratio shift between the two resistors be suppressed by the arrangement of the reflection correction pad, but also the respective resistance value changes in the two resistors can be reduced.

  In the semiconductor device, the upper surface of the insulating film, as described in claim 7, if the cost is within an acceptable range in suppressing resistance value deviation caused by steps of semiconductor elements and wirings, It is preferable that the surface is planarized by CMP (Chemical Mechanical Polishing).

  Further, the insulating film in the semiconductor device may be SOG (Spin On Glass) as described in claim 8, for example. An insulating film made of SOG can obtain a flatter surface compared to an insulating film such as TEOS (Tetra-Ethyl Ortho-Silicate) formed by CVD even when planarization by CMP is not performed. .

  As described above, the above-described semiconductor device is a semiconductor device in which two resistors made of a thin film are disposed adjacent to each other via an insulating film above a wiring in a semiconductor substrate. This can be applied to any wiring design connected to the semiconductor device, and a small semiconductor device including two resistors having a highly accurate resistance ratio can be obtained.

  Therefore, as described in claim 9, in the semiconductor device, the pair resistors connected in series used for voltage division are configured by the two resistors, and high accuracy is ensured in securing good circuit characteristics. It is suitable as a semiconductor device that requires a high resistance ratio.

1 is a diagram schematically illustrating a semiconductor device 10 as an example of a semiconductor device having a pair resistance. FIG. FIG. 2 is a view showing different arrangement forms of resistors made of thin films, in which the surface of the interlayer insulating film 2 is not flattened by CMP, (a) is a top view, and (b) is an alternate long and short dash line A in FIG. It is sectional drawing in -A. FIG. 2 is a view showing different arrangement forms of resistors made of thin films, in which the surface of the interlayer insulating film 2 is planarized by CMP, (a) is a top view, and (b) is an alternate long and short dash line B in (a). It is sectional drawing in -B. It is a figure explaining the problem at the time of patterning when arrange | positioning a pair resistance on an element area | region, (a) is a top view of the pair resistance PRe in the conventional semiconductor device 90, (b) is (a). It is sectional drawing in the dashed-two dotted line CC. Further, (c) is a diagram showing the state of exposure light in the photolithography process in forming the pair resistor PRe in (b). 4A and 4B are diagrams illustrating definitions of terms and a semiconductor device according to the present invention. FIG. 4A is a top view of a conventional semiconductor device 91 similar to FIG. 4A, and FIG. 1 is a top view of a semiconductor device 100 as an example of a device. Several prototypes of resistors R1e and R2e having the same length were produced in a state where the substrate 1 and the wiring 4 directly below were different, and the relationship between the difference in the outer wiring coverage V (V1−V2) and the resistance ratio R1e / R2e was examined. It is a result. It is a figure which shows the example of another semiconductor device which concerns on this invention, (a) is a top view of the same conventional semiconductor device 90 as Fig.4 (a), (b)-(d) is this, respectively. It is a top view of the semiconductor devices 101-103 which have the structure of the said outer periphery wiring layer coverage W based on invention. FIGS. 5A and 5B are diagrams showing examples of another semiconductor device according to the present invention, and FIGS. 5A and 5B are top views of the semiconductor devices 104 and 105 having the configuration of the outer peripheral wiring layer coverage W according to the present invention, respectively. FIG. 5A and 5B are diagrams illustrating definitions of terms, in which FIG. 5A is a top view of the same semiconductor device 91 as FIG. 5A, and FIG. 5B is a top view of the same semiconductor device 100 as FIG. . 2A and 2B are diagrams illustrating an example of a semiconductor device according to the present invention in a case where a wiring layer is composed of two or more layers, wherein FIG. 1A is a top view of a conventional semiconductor device 92, and FIGS. These are top views of the semiconductor devices 111 to 113 each having the configuration of the outer wiring layer coverage W according to the present invention.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

  First, problems of the present invention and problems of the conventional semiconductor device will be described.

  2. Description of the Related Art Some semiconductor devices in which a large number of semiconductor elements are integrated on a small semiconductor substrate and connected by wirings include a thin film resistor disposed above a semiconductor substrate via an insulating film. In particular, in a semiconductor device in which an analog circuit is configured, a pair resistor connected in series used for voltage division requires a highly accurate resistance ratio in order to ensure good circuit characteristics.

  FIG. 1 is a diagram schematically illustrating a semiconductor device 10 as an example of a semiconductor device having a pair resistance.

  In the semiconductor device 10 of FIG. 1, a pair resistor PR composed of resistors R1 and R2 connected in series used for voltage division is formed on one semiconductor substrate (semiconductor chip) 1 together with an amplifier (AMP), and an analog power supply circuit is formed. It is configured. In order to obtain a highly accurate output voltage Vcc as designed in the power supply circuit, the pair resistor PR requires a highly accurate resistance ratio R1 / R2.

  FIG. 2 and FIG. 3 are diagrams showing different arrangement forms of resistors made of thin films, respectively. FIG. 2 shows a case where the surface of the interlayer insulating film 2 is not flattened by CMP (Chemical Mechanical Polishing). Reference numeral 3 denotes a case where the surface of the interlayer insulating film 2 is planarized by CMP. 2 and 3, (a) is a top view, and (b) is a cross-sectional view taken along one-dot chain lines AA and BB in (a). As shown in FIGS. 2 and 3, the resistors R1a to R1d and R2a to R2d made of a thin film having a coarse cross-coating pattern are provided at both ends with aluminum (Al ) Etc. are formed.

  Like the pair resistor PR in the semiconductor device 10 shown in FIG. 1, a pair resistor that requires a highly accurate resistance ratio R1 / R2 is insulated above the semiconductor substrate 1 as shown in FIGS. It is configured as two rectangular resistors R1a to R1d and R2a to R2d made of a thin film and arranged adjacent to each other with the film 2 interposed therebetween. As a material of the resistors R1a to R1d and R2a to R2d, for example, a chromium-silicon (Cr—Si) alloy or the like is used.

  The pair resistance by the thin film resistor is conventionally used in the semiconductor substrate 1 on which the semiconductor element 3 and the wiring 4 are arranged as illustrated in the pair resistance PRa in FIG. It has been arranged not on the element region but on a flat field region in which a wide LOCOS region is formed below in the periphery of the semiconductor substrate 1 where the semiconductor element 3 and the wiring 4 are not arranged. This is because the thin film resistors R1b and R2b are deformed due to the steps of the semiconductor element 3 and the wiring 4 when arranged on the element region, as illustrated in the pair resistor PRb of FIG. This is because the resistance ratio R1b / R2b is deviated from the design. On the other hand, in order to reduce the size of the semiconductor device and reduce the cost, it is preferable that the pair resistance by the thin film resistor can be arranged not only on the field region but also on the element region.

  In the arrangement form of the pair resistor illustrated in FIG. 3, the thin film resistor is disposed above the semiconductor element 3 and the wiring 4 in the element region having a step, and therefore, after the interlayer insulating film 2 is planarized by CMP, A thin film resistor is formed thereon. As a result, as exemplified by the pair resistor PRd in FIG. 3, thin film resistors R1d and R2d without deformation can be formed on the interlayer insulating film 2, and the thin film resistors caused by the steps of the semiconductor element 3 and the wiring 4 can be formed. Deviation from the design of the resistance values of the bodies R1d and R2d can be suppressed. However, planarization of the interlayer insulating film 2 by CMP illustrated in FIG. 3 is a cost increase factor, so it is more preferable if it can be eliminated.

  Further, when the thin film resistors R1d and R2d are disposed on the element region as in the pair resistor PRd illustrated in FIG. 3, unlike the pair resistor PRc disposed on the field region, the semiconductor element 3 and the wiring 4 There are the following problems in patterning the thin film resistors R1d and R2d as well as the resistance value deviation caused by the step.

  FIG. 4 is a diagram for explaining a problem in the patterning when the pair resistor is arranged on the element region. FIG. 4A is a top view of the pair resistor PRe in the conventional semiconductor device 90. FIG. 4 (b) is a cross-sectional view taken along the two-dot chain line CC in FIG. FIG. 4C is a diagram showing the state of exposure light in the photolithography process when the pair resistor PRe in FIG. 4B is formed.

  The pair resistor PRE shown in FIGS. 4A and 4B is formed on the element region, and a substrate made of silicon (Si) indicated by a dot coating pattern when seen directly below the thin film resistors R1e and R2e. 1 and wirings 4a and 4b indicated by hatching patterns are mixed. 4 (a) and 4 (b), the alternate long and short dash line indicates the rectangular design pattern of the thin film resistors R1e and R2e, but in the pattern of the thin film resistors R1e and R2e indicated by the solid lines actually patterned, The portion immediately above the wirings 4a and 4b is in accordance with the design pattern, but the portion immediately above the substrate 1 is thinner than the design pattern. For this reason, the resistance values of the thin film resistors R1e and R2e are deviated from the design. Therefore, when the pair resistor PRe is used as a pair resistor for voltage division, the resistance ratio R1e / R2e deviates from the design.

  The deviation from the design pattern of the thin film resistors R1e and R2e after the patterning is caused by the state of exposure light in the photolithography process shown in FIG. That is, the exposure light transmitted through the thin film resistor layer 5 in the photolithography process when the substrate 1 is directly below the mask M processed into the design pattern of the thin film resistors R1e and R2e and when the wirings 4a and 4b are present. Is different between the substrate 1 and the wirings 4a and 4b. The wirings 4a and 4b are generally made of aluminum (Al), but an antireflection film (not shown) is usually formed on the upper surface of the Al. Therefore, as shown in FIG. 4C, the exposure light transmitted through the thin film resistor layer 5 is reflected on the surface of the substrate 1 made of Si, but is not reflected on the surfaces of the wirings 4a and 4b. Accordingly, the portions where the wirings 4a and 4b are located immediately below the outer periphery of the mask M have no reflected light, so that the resist 6 is exposed according to the pattern shape of the mask M. On the other hand, in the portion where the substrate 1 is directly under the outer periphery of the mask M, the resist 6 is overexposed to the inside of the outer periphery of the mask M by reflected light, and the pattern shape of the resist 6 after the photolithography process is It becomes thinner than the pattern shape. The thin shape of the pattern of the resist 6 is transferred to the etching of the thin film resistor layer 5, and the portion of the thin film resistor R1e, R2e in the pattern immediately above the substrate 1 becomes thinner than the design pattern.

  As described above, when the substrate and the wiring coexist directly under the resistor, the reflection ratio of the exposure light transmitted through the resistor layer made of a thin film in the photolithography process differs from the presence ratio of the substrate and the wiring. . For this reason, the width of the rectangular resist pattern varies depending on the arrangement position of the resistor, and the resistance of the obtained resistor deviates from the design value. In particular, for a pair of resistors that require a high-precision resistance ratio, such as a pair resistor used for voltage division, the voltage as designed can be obtained only by a resistance ratio shift caused by the photolithography process. It cannot be obtained, and it becomes difficult to ensure good circuit characteristics.

  In view of this, the semiconductor device according to the present invention includes two on the element region, in which two rectangular resistors made of a thin film are arranged adjacent to each other above the wiring in the semiconductor substrate via an insulating film. In order to suppress a resistance ratio shift caused by the photolithography process, a semiconductor device having the following configuration is provided.

  That is, the length of the resistor defined between the electrodes is L, the length of the outer side of the resistor directly above the wiring is the length H on the wiring, and the outer side wiring coverage V of the resistor is V When defined as = H / 2L, a reflection correction pad formed from the same wiring layer as the wiring is at least below the resistor having a small outer-side wiring coverage V among the two resistors. The length of the outer side of the resistor directly above the reflection correction pad is the correction pad upper length P, and the outer-side wiring layer coverage W of the resistor is W = When defined as (H + P) / 2L, the difference in the outer wiring layer coverage W is set to be smaller than the difference in the outer wiring coverage V for the two resistors.

  FIG. 5 is a diagram for explaining the definition of terms in the above configuration and the semiconductor device according to the present invention. FIG. 5A is a top view of a conventional semiconductor device 91 similar to FIG. FIG. 5B is a top view of the semiconductor device 100 as an example of the semiconductor device according to the present invention. Note that, in each semiconductor device exemplified below, only two design patterns and their arrangement positions are indicated by alternate long and short dash lines for two rectangular resistors made of thin films arranged adjacent to each other. Further, the two resistors R1e and R2e in the semiconductor device 90 in FIG. 4A have the same length, but the two resistors in the semiconductor devices 91 and 100 in FIGS. 5A and 5B. R1f and R2f have different general lengths.

  In the semiconductor device 100 of FIG. 5B, compared with the semiconductor device 91 of FIG. 5A, the reflection correction pads Pa and Pb formed from the same wiring layer as the wirings 4a and 4b are connected to the wirings 4a and 4b. As an isolated region that does not affect the circuit current flowing through the resistor R2f, it is additionally arranged immediately below the outer side of the resistor R2f.

  In the semiconductor device 91 of FIG. 5A, for the resistor R1f, the length L = L1 of the resistor defined between the electrodes, and the length on the wiring H of the outer side of the resistor directly above the wiring 2 · (H11 + H12). Therefore, the outer side wiring coverage V (= H / 2L) of the resistor R1f is V1 = 2 · (H11 + H12) / 2 · L1. On the other hand, for the resistor R2f, L = L2 and H = 2 · H21. Therefore, the outer side wiring coverage V of the resistor R2f is V2 = 2 · H21 / 2 · L2. As is apparent from FIG. 5A, the outer side wiring coverage V2 of the resistor R2f is smaller than the outer side wiring coverage V1 of the resistor R1f.

  Therefore, as described above, in the semiconductor device 100 of FIG. 5B, the reflection is performed below the resistor R2f having a small outer side wiring coverage V among the two resistors R1f and R2f of FIG. Correction pads Pa and Pb are additionally arranged immediately below the outer side of the resistor R2f.

  In the semiconductor device 100 of FIG. 5B, the correction pad length P = 0 for the resistor R1f because no reflection correction pad is arranged. Accordingly, the outer peripheral wiring layer coverage W (= (H + P) / 2L) of the resistor is W1 = 2 · (H11 + H12) / 2 · L1 = V1, and the outer peripheral wiring coverage V1 in FIG. The same value as On the other hand, the resistor R2f has the correction pad length P = 2 (P21 + P22) on the outer side of the resistor directly above the reflection correction pad due to the arrangement of the reflection correction pads Pa and Pb. Therefore, the outer peripheral wiring layer coverage W of the resistor is W2 = 2 · (H21 + P21 + P22) / 2 · L2.

  As is clear from FIGS. 5A and 5B, the difference (W1−W2) in the outer-side wiring layer coverage W in the semiconductor device 100 in FIG. 5B is (W1) for the two resistors R1f and R2f. The difference is set to be smaller than the difference (V1−V2) in the outer side wiring coverage V in the semiconductor device 91 of a).

  The semiconductor device 100 of the present invention shown in FIG. 5B is caused by the photolithography process in the conventional semiconductor device 91 of FIG. 5A when two resistors R1f and R2f are arranged on the element region. This eliminates the deviation of the resistance ratio R1f / R2f. Therefore, in the semiconductor device 100 of FIG. 5B, the cause of the deviation of the resistance ratio R1e / R2e in the semiconductor device 90 described in FIG. 4 is analyzed, and the two resistors in the semiconductor device 91 of FIG. Attention is paid to the difference in the outer side wiring coverage V between the bodies R1f and R2f.

  In the semiconductor device 90 of FIG. 4, the resist pattern width variation of the resistors R1e and R2e in the photolithography process is the same as that of the semiconductor device 91 of FIG. The resistance V can be quantified by the rate V, and the change in the resistance value is proportional to the outer wiring coverage V.

  FIG. 6 shows several prototypes of resistors R1e and R2e having the same length as in FIG. 4 in a state where the substrate 1 and the wiring 4 are different from each other, and the difference in the outer side wiring coverage V (V1−V2) and the resistance. It is the result of investigating the relationship of the ratio R1e / R2e. As shown in FIG. 6, the resistance ratio R1e / R2e is shifted from 100% of the same resistance value as the difference (V1−V2) in the outer side wiring coverage V becomes larger.

  The pattern of the semiconductor element and the wiring connected to it is determined prior to the arrangement position of the two resistors in consideration of the characteristics of the entire circuit. For this reason, when two resistors are arranged on the element region, the wiring pattern immediately below the resistors varies depending on the arrangement position, and the outer-side wiring coverage V also varies depending on the arrangement position. . Therefore, the resistance value change of the resistors also varies, and in the semiconductor device 91 of FIG. 5A, the deviation of the resistance ratio R1f / R2f between the two resistors R1f and R2f cannot be controlled in a random manner.

  Therefore, in the semiconductor device 100 of FIG. 5B according to the present invention, the same as the wirings 4a and 4b, at least below the resistor R2f having a small outer-side wiring coverage V, out of the two resistors R1f and R2f. The reflection correction pads Pa and Pb formed from the wiring layer are arranged immediately below the outer side of the resistor R2f. These reflection correction pads Pa and Pb are for correcting the pattern data of the initial wirings 4a and 4b connected to the semiconductor element previously determined in the semiconductor device 91 of FIG. 5A, and are defined by CAD in FIG. It is possible to automatically generate the predetermined conditions regarding the outer peripheral wiring coverage V, the outer wiring layer coverage W, and the like. Due to the arrangement of the reflection correction pads Pa and Pb, in the semiconductor device 100 of FIG. 5B, the difference (W1−W2) in the outer wiring layer coverage W between the two resistors R1f and R2f is shown in FIG. It is set to be smaller than the difference (V1−V2) in the outer side wiring coverage V in the semiconductor device 91 of 5 (a).

  From the definition, the outer side wiring layer coverage W quantifies the width variation of the resist pattern of the resistor in the photolithography process when a reflection correction pad is added to the initial wiring pattern. After the reflection correction pad is arranged, the difference in the outer side wiring layer coverage W between the two resistors is set to be smaller than the difference in the previous outer side wiring coverage V. As a result, the difference in the reflection ratio of the exposure light from the ground in the photolithography process is reduced for the two resistors, and the resist pattern width variation and the resistance value change of the two resistors approach the same ratio. It is possible to suppress a resistance ratio shift between the two resistors. In particular, when an antireflection film is formed on the upper surface of the wiring layer, it is possible to reduce changes in resistance values of the two resistors by arranging the reflection correction pads.

  As described above, the semiconductor device according to the present invention exemplified by the semiconductor device 100 in FIG. 5B has two thin films formed above the wirings 4a and 4b in the semiconductor substrate 1 via the insulating film. A semiconductor device in which resistors R1f and R2f are arranged adjacent to each other, which can be applied to any wiring design connected to a semiconductor element, and suppresses a deviation of the resistance ratio R1f / R2f caused by a photolithography process. Thus, a small semiconductor device including two resistors having a highly accurate resistance ratio can be obtained.

  7 and 8 are diagrams showing another example of the semiconductor device according to the present invention. FIG. 7A is a top view of the same conventional semiconductor device 90 as FIG. 4A, and FIG. FIGS. 8B and 8B are top views of the semiconductor devices 101 to 105 having the configuration of the outer peripheral wiring layer coverage W according to the present invention, respectively.

  In the semiconductor device 101 shown in FIG. 7B, a reflection correction pad Pc is additionally arranged immediately below the outer side of the resistor R2e, as compared with the conventional semiconductor device 90 shown in FIG. Further, in the semiconductor device 102 shown in FIG. 7C, the reflection correction pad Pd is additionally arranged immediately below the outer sides of the resistors R1e and R2e, as compared with the semiconductor device 100 shown in FIG. 7B. Yes.

  The two resistors R1e and R2e having the same length in the semiconductor devices 101 and 102 of FIGS. 7B and 7C are arranged with the reflection correction pad Pc as compared with that of the semiconductor device 90 of FIG. As a result, the patterns of the substrate 1 and the wirings 4a and 4b immediately below the resistors R1e and R2e have the same shape (therefore, the outer wiring layer coverage W is the same value), and the resistance ratio R1e resulting from the photolithography process. / R2e deviation can be suppressed. In addition, the two resistors R1e and R2e in the semiconductor device 102 of FIG. 7C are compared with those of the semiconductor device 101 of FIG. The shape of the pattern of the substrate 1 immediately below R1e and R2e is small (thus, the outer wiring layer coverage W is high). Therefore, the resistance values of the two resistors R1e and R2e in the semiconductor device 102 can be reduced from the design as compared with those of the semiconductor device 101.

  Also in the semiconductor device 103 shown in FIG. 7D, the reflection correction pads Pe1 and Pe2 are arranged immediately below the outer side of the resistor R2e, as compared with the conventional semiconductor device 90 shown in FIG. ing. The reflection correction pads Pc and Pd in the semiconductor devices 101 and 102 in FIGS. 7B and 7C are formed as isolated regions that do not affect the circuit current flowing through the wirings 4a and 4b. On the other hand, the reflection correction pads Pe1 and Pe2 in the semiconductor device 103 of FIG. 7D are formed from convex regions in which a part of the wirings 4a and 4b shown in FIG. Become. In this way, the reflection correction pad formed from the same wiring layer as the wiring may be formed as an isolated region that does not affect the circuit current flowing through the wiring, or as a convex region that has a small effect on the circuit current. May be.

  Further, in the semiconductor device 104 shown in FIG. 8A, the elongated reflection correction pads Pf1 and Pf2 are arranged immediately below the outer side of the resistor R2e. The outer side wiring layer coverage W of the resistors R1e and R2e in the semiconductor device 104 of FIG. 8A is the same value as those in the semiconductor devices 101 and 103 of FIG. 7B and FIG. Deviations from the design of R1f / R2f can be similarly suppressed. On the other hand, the reflection correction pads Pf1 and Pf2 in the semiconductor device 104 of FIG. 8A are only directly under the vicinity of the outer side of the resistor R2f, compared with the reflection correction pad Pc of the semiconductor device 101 of FIG. Between them, a long space Sf is provided in the vertical direction in the figure. For this reason, the semiconductor device 104 in FIG. 8A has a structure in which a short circuit between the wirings 4a and 4b due to the arrangement of the reflection correction pad is less likely to occur than the semiconductor device 101 in FIG. 7B.

  Further, in the semiconductor device 105 shown in FIG. 8B, a large number of small square-shaped reflection correction pads Pg are arranged immediately below the outer side of the resistor R2e, and in the meantime, a lattice-like pattern is formed in the vertical and horizontal directions in the figure. A space Sg is provided. For this reason, the semiconductor device 105 in FIG. 8B has a structure in which a short circuit between the wirings 4a and 4b due to the arrangement of the reflection correction pads is less likely to occur than the semiconductor device 104 in FIG. .

  Comparing the semiconductor device 104 in FIG. 8A and the semiconductor device 101 in FIG. 7B, the resistance ratio R1e / R2e shift caused by the photolithography process can be similarly suppressed as described above. . On the other hand, as exemplified by the resistor R2b in FIG. 2, when the surface of the interlayer insulating film 2 is not polished by CMP or the like, the resistor R2e in the semiconductor device 104 in FIG. Compared with the resistor R2e in the semiconductor device 101 of b), the deviation from the design of the resistance value due to the step between the reflection correction pads Pf1 and Pf2 becomes large.

  Therefore, in the semiconductor device of the present invention described above, when the surface of the insulating film is not polished by CMP or the like, in order to suppress a deviation from the design of the resistance value due to the step of the additionally disposed reflection correction pad, the following A semiconductor device having a structure is preferable.

  That is, the length of the outer side of the wiring immediately below the resistor is defined as a wiring outer side length T, and the wiring outer side coverage X by the resistor is defined as X = T / L. Is defined as Y = (T + Q) / L, where the length of the outer edge of the reflection correction pad is defined as the reflection correction pad outer edge length Q and the wiring layer outer edge coverage Y by the resistor is defined as Y = (T + Q) / L. The resistor is configured such that the difference in the wiring layer outer side coverage Y is set smaller than the difference in the wiring outer side coverage X.

  9A and 9B are diagrams illustrating definitions of terms in the above configuration. FIG. 9A is a top view of the same semiconductor device 91 as FIG. 5A, and FIG. It is a top view of the same semiconductor device 100 as b).

  In the semiconductor device 91 of FIG. 9A, the resistor R1f has a wiring outer side length T = 3 · T1 immediately below the resistor. Accordingly, the wiring outer side coverage X (= T / L) by the resistor R1f is X1 = 3 · T1 / L1. On the other hand, T = 2 · T2 for the resistor R2f. Therefore, the wiring outer side coverage X by the resistor R2f is X2 = 2 · T2 / L2.

  Further, in the semiconductor device 100 in which the reflection correction pads Pa and Pb are additionally arranged below the resistor R2f shown in FIG. 9B, the reflection correction pad is not arranged for the resistor R1f. The side length Q = 0. Therefore, the wiring layer outer side coverage Y (= (T + Q) / L) by the resistor Rf1 is Y1 = 3 · T1 / L1 = X1, which is the same value as the wiring outer side coverage X1 in FIG. become. On the other hand, for the resistor R2f, the reflection correction pad outer side length Q = 2 · T2 due to the arrangement of the reflection correction pads Pa and Pb. Therefore, the wiring layer outer side coverage Y by the resistor Rf2 is Y2 = 4 · T2 / L2.

  The configuration of the semiconductor device eliminates the resistance ratio shift between the two resistors due to the step difference of the wiring connected to the semiconductor element when the two resistors are arranged on the element region. For this reason, in the semiconductor device, the cause of the deviation of the resistance ratio is analyzed, and the length of the outer periphery of the wiring immediately below the resistors is defined as the outer periphery length T of the two rectangular resistors. The wiring outer side coverage X by the resistor is defined as X = T / L, and attention is paid to the difference in the wiring outer side coverage X for the two resistors.

  The difference in resistance ratio between the two resistors due to the level difference of the wiring can be quantified by the wiring outer side coverage X by the resistance defined above. The wiring outer side coverage X indicates the existence ratio of the step due to the wiring immediately below the resistor, and the resistance value change due thereto is also proportional to the wiring outer side coverage X. Similar to the outer side wiring coverage V described above, when two resistors are arranged at desired positions on the element region, the respective wiring outer side coverages X by the two resistors vary depending on the arrangement positions. Value.

  Therefore, in the semiconductor device described above, the pattern shape of the reflection correction pad introduced to suppress the deviation of the resistance ratio due to the photolithography process is further set to satisfy the following relationship, so that The resistance ratio shift between the two resistors due to the step of the wiring to be connected is reduced. That is, in the configuration of the semiconductor device, the length of the outer side of the reflection correction pad immediately below the resistor is the reflection correction pad outer side length Q, and the wiring layer outer side coverage Y by the resistor is Y = ( When defined as T + Q) / L, the difference in the wiring layer outer side coverage Y is set to be smaller than the difference in the wiring outer side coverage X for the two resistors.

  As described above, after the arrangement of the reflection correction pad having the pattern shape that satisfies the above relationship, the difference in the wiring layer outer side coverage Y between the two resistors is equal to the previous wiring outer side coverage X. It is set to be smaller than the difference. As a result, for the two resistors, the difference in the existence ratio of the step due to the wiring immediately below the resistor is also reduced, and the resistance value change of the two resistors due to the step of the wiring approaches the same ratio, The resistance ratio deviation between the two resistors can be suppressed.

  For example, in the semiconductor device 101 of FIG. 7B, the outer peripheral wiring of the two resistors R1e and R2e is compared with the semiconductor device 90 of FIG. 7A due to the additional arrangement of the reflection correction pad Pc. Not only does the difference in the layer coverage W become zero, but the difference in the wiring layer outer side coverage Y between the two resistors R1e and R2e also becomes zero. Therefore, the reflection correction pad Pc in the semiconductor device 101 of FIG. 7B is not only the resistance ratio shift caused by the photolithography process, but also the two resistors R1e, as compared with the semiconductor device 90 of FIG. , R2e, when the surface of the insulating film is not polished by CMP or the like, it is possible to suppress the resistance ratio shift caused by the steps of the wirings 4a and 4b.

  On the other hand, in the semiconductor device 104 of FIG. 8A, the reflection correction pads Pf1 and Pf2 are additionally arranged, so that, as described above, compared to the semiconductor device 90 of FIG. The difference between the outer wiring layer coverages W of R1e and R2e is zero. However, the difference in the wiring layer outer side coverage Y between the two resistors R1e and R2e is large because a step between the reflection correction pads Pf1 and Pf2 and the space Sf is newly formed immediately below the resistor R2e. turn into. Therefore, as in the semiconductor devices 103 to 105 shown in FIG. 7D and FIGS. 8A and 8B, the difference in the wiring layer outer edge coverage Y from the semiconductor device 90 in FIG. When the reflection correction pads Pe1, Pe2, Pf1, Pf2, and Pg that are to be enlarged are disposed, it is preferable to polish the surface of the insulating film on which the two resistors R1e and R2e are disposed by CMP or the like.

  It should be noted that a predetermined condition regarding the wiring outer edge coverage X and the wiring layer outer edge coverage Y defined in FIG. it can.

  As described above, the semiconductor device having the above configuration includes two resistors having a more accurate resistance ratio by suppressing a resistance ratio shift caused by a step of a wiring connected to the semiconductor element. A small semiconductor device can be obtained.

  Further, the wiring layer in the semiconductor device described above may be composed of two or more layers.

  FIG. 10 is a diagram showing an example of a semiconductor device according to the present invention when the wiring layer is composed of two or more layers. FIG. 10A is a top view of a conventional semiconductor device 92. FIG. (B)-(d) is a top view of the semiconductor devices 111-113 which respectively have the structure of the said outer periphery wiring layer coverage W based on this invention.

  In each of the semiconductor devices 92 and 111 to 113 shown in FIG. 10, the wirings 4a and 4b indicated by the lower right oblique line painting pattern are formed on the first layer, and the lower left oblique line painting pattern is provided on the second layer. The shown wirings 7a and 7b are formed. And two resistors R1g and R2g shown with the dashed-dotted line are arrange | positioned adjacently through them via the insulating film.

  In the semiconductor device 111 shown in FIG. 10B, compared to the conventional semiconductor device 92 shown in FIG. 10A, the reflection of the isolated region formed from the same wiring layer as the first-layer wirings 4a and 4b is reflected. The correction pad Ph is additionally arranged immediately below the outer side of the resistor R2g. In the semiconductor device 112 shown in FIG. 10C, as compared with the semiconductor device 92 in FIG. 10A, reflection correction of a convex region formed of the same wiring layer as the second-layer wirings 7a and 7b is performed. Pads Pi1 and Pi2 are additionally arranged directly below the outer side of the resistor R2g. For example, when a reflection correction pad is formed in the first wiring layer as shown in FIG. 10B, it is easy to place a short circuit between the wirings, as shown in FIG. 10C. The reflection correction pad may be formed of a layer. On the other hand, when the reflection correction pad is formed in the second wiring layer as shown in FIG. 10C, it is easy to place a short circuit between the wirings, as shown in FIG. 10B. A reflection correction pad is formed in the wiring layer. Further, in the semiconductor device 113 shown in FIG. 10D, as compared with the semiconductor device 112 in FIG. 10C, the reflection correction pad Pj in the convex region formed from the first wiring layer is It is additionally arranged directly below the outer side of the resistor R2g.

  As shown in the semiconductor devices 92 and 111 to 113 in FIG. 10, when the wiring layers immediately below the two resistors R1g and R2g are composed of two or more layers, the outer wiring coverage V described in FIG. For the outer wiring layer coverage W, the wiring length H and the correction pad length P are calculated in a state where all the wiring layers are projected onto one surface. Further, the wiring outer edge coverage X and the wiring layer outer edge covering ratio Y described in FIG. 9 are calculated by adding all the wiring outer edge length T and the reflection correction pad outer edge length Q in each wiring layer. .

  In the semiconductor device, as described in FIG. 4, it is preferable that an antireflection film is formed on the upper surface of the wiring layer. As described above, in this case, not only can the resistance ratio shift between the two resistors be suppressed by the arrangement of the reflection correction pad, but also the respective resistance value changes in the two resistors can be reduced.

  In the above-described semiconductor device, as described above, if the resistance value deviation caused by the step difference of the semiconductor element or the wiring is suppressed, the insulation in which the two resistors are arranged as described above is within the allowable range. The upper surface of the film is preferably planarized by CMP.

  The insulating film in the semiconductor device may be, for example, SOG (Spin On Glass). An insulating film made of SOG can obtain a flatter surface compared to an insulating film such as TEOS (Tetra-Ethyl Ortho-Silicate) formed by CVD even when planarization by CMP is not performed. .

  As described above, the semiconductor device according to the present invention described above is a semiconductor device in which two resistors made of a thin film are disposed adjacent to each other above a wiring in a semiconductor substrate via an insulating film. Thus, it can be applied to any wiring design connected to a semiconductor element, and a small semiconductor device including two resistors having a highly accurate resistance ratio can be obtained.

  Therefore, in the semiconductor device, a pair resistor connected in series used for voltage division is configured by the two resistors, and a semiconductor that requires a high-precision resistance ratio in order to ensure good circuit characteristics. It is suitable as a device.

  In each of the semiconductor devices 101 to 105 and 111 to 113 in FIGS. 7, 8, and 10, two resistors R1e, R2e, R1g, and R2g arranged adjacent to each other are the same for the sake of simplicity. It was a length. However, the present invention is not limited to this, and the two resistors arranged in the semiconductor device according to the present invention are two resistors R1f and R2f arranged in the semiconductor device 100 illustrated in FIGS. It can be of different lengths.

10, 90-92, 100-105, 111-113 Semiconductor device 1 Substrate 2 Insulating film 4, 4a, 4b, 7a, 7b Wiring R1, R2, R1a-R1g, R2a-R2g Resistor PR, PRa-PRe Pair resistance

Claims (9)

A semiconductor device in which two rectangular resistors made of a thin film are arranged adjacent to each other above a wiring in a semiconductor substrate via an insulating film,
The length of the resistor defined between the electrodes is L, the length of the outer side of the resistor directly above the wiring is the length H on the wiring, and the outer wiring coverage V of the resistor is V = H / 2L when defined
A reflection correction pad formed from the same wiring layer as the wiring is disposed directly below the outer side of the resistor, at least below the resistor having a small outer side wiring coverage V of the two resistors. Become
When the length of the outer side of the resistor directly above the reflection correction pad is the correction pad upper length P, and the outer side wiring layer coverage W of the resistor is defined as W = (H + P) / 2L,
The semiconductor device, wherein the difference between the outer wiring layer coverages W of the two resistors is set to be smaller than the difference between the outer wiring coverages V. The length of the outer side of the wiring immediately below the resistor is defined as a wiring outer side length T, and the wiring outer side coverage X by the resistor is defined as X = T / L,
When the length of the outer side of the reflection correction pad directly under the resistor is defined as the reflection correction pad outer side length Q, and the wiring layer outer side coverage Y by the resistor is defined as Y = (T + Q) / L ,
2. The semiconductor device according to claim 1, wherein the difference in the wiring layer outer side coverage Y is set to be smaller than the difference in the wiring outer side coverage X for the two resistors.   The semiconductor device according to claim 1, wherein the reflection correction pad is an isolated region that does not affect a circuit current flowing through the wiring.   The semiconductor device according to claim 1, wherein the reflection correction pad is a convex region in which a part of the wiring protrudes and a wiring width is formed wider than a surrounding area.   The semiconductor device according to claim 1, wherein the wiring layer includes two or more layers.   6. The semiconductor device according to claim 1, wherein an antireflection film is formed on an upper surface of the wiring layer.   The semiconductor device according to claim 1, wherein an upper surface of the insulating film is planarized by CMP.   The semiconductor device according to claim 1, wherein the insulating film is made of SOG.   9. The semiconductor device according to claim 1, wherein the two resistors constitute a pair resistor connected in series used for voltage division.

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