JP2013105848A - Soldering apparatus - Google Patents

Soldering apparatus Download PDF

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JP2013105848A
JP2013105848A JP2011247774A JP2011247774A JP2013105848A JP 2013105848 A JP2013105848 A JP 2013105848A JP 2011247774 A JP2011247774 A JP 2011247774A JP 2011247774 A JP2011247774 A JP 2011247774A JP 2013105848 A JP2013105848 A JP 2013105848A
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weight
semiconductor element
soldering
substrate
solder
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JP5712903B2 (en
Inventor
Gen Funabashi
元 舟橋
Takayuki Tominaga
隆行 冨永
Yasuhide Sonoda
靖秀 園田
Hikari Sano
光 佐野
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Denso Corp
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Denso Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

Abstract

PROBLEM TO BE SOLVED: To prevent deterioration of bonding strength of wire bonding in a soldering apparatus which performs reflow soldering while pressurizing a semiconductor element toward a substrate.SOLUTION: In the soldering apparatus which performs reflow soldering while pressurizing a semiconductor element 2 toward a substrate 1 by a weight 12, a pressure contact surface 121a of the weight 12, which comes into contact with the semiconductor element 2, is mirror-finished. Accordingly, a wire bonding execution surface 2a of the semiconductor element 2 can be prevented from being damaged in a reflow soldering process, and deterioration of bonding strength of wire bonding can thus be prevented.

Description

本発明は、半導体素子を基板側に向かって加圧しつつリフローはんだ付けを行うはんだ付け装置に関するものである。   The present invention relates to a soldering apparatus that performs reflow soldering while pressing a semiconductor element toward a substrate side.

従来、半導体素子と基板を接合する装置として、半導体素子の上に重りを載せて半導体素子を基板側に向かって加圧しつつ、リフローはんだ付けを行うものが提案されている（例えば、特許文献１〜４参照）。   Conventionally, as an apparatus for joining a semiconductor element and a substrate, an apparatus that performs reflow soldering while placing a weight on the semiconductor element and pressurizing the semiconductor element toward the substrate side has been proposed (for example, Patent Document 1). To 4).

特開２００２−１８４７９１号公報JP 2002-184791 A 特開２００８−１５９８７８号公報JP 2008-159878 A 特許第３６１４０７９号明細書Japanese Patent No. 3614079 特開平７−２９７２０９号公報JP 7-297209 A

しかしながら、半導体素子におけるワイヤボンディングが実施される面に重りが接触するため、リフローはんだ付け工程でワイヤボンディング実施面に傷が付き、ワイヤボンディングの接合強度が低下する虞があった。   However, since the weight comes into contact with the surface of the semiconductor element where wire bonding is performed, the wire bonding surface may be damaged during the reflow soldering process, and the bonding strength of the wire bonding may be reduced.

本発明は上記点に鑑みて、半導体素子を基板側に向かって加圧しつつリフローはんだ付けを行うはんだ付け装置において、ワイヤボンディングの接合強度の低下を防止することを目的とする。   In view of the above points, an object of the present invention is to prevent a reduction in bonding strength of wire bonding in a soldering apparatus that performs reflow soldering while pressing a semiconductor element toward a substrate.

上記目的を達成するため、請求項１に記載の発明では、基板（１）と半導体素子（２）との間にはんだ（３）を介在させ、重り（１２）により半導体素子（２）を基板（１）側に向かって加圧しつつリフローはんだ付けを行うはんだ付け装置であって、重り（１２）における半導体素子（２）に接触する加圧接触面（１２１ａ）は、鏡面仕上げされていることを特徴とする。   In order to achieve the above object, according to the first aspect of the present invention, solder (3) is interposed between the substrate (1) and the semiconductor element (2), and the semiconductor element (2) is mounted on the substrate by the weight (12). (1) A soldering apparatus that performs reflow soldering while applying pressure toward the side, and the pressure contact surface (121a) that contacts the semiconductor element (2) in the weight (12) is mirror-finished. It is characterized by.

これによると、リフローはんだ付け工程で半導体素子（２）におけるワイヤボンディング実施面（２ａ）に傷が付くことを防止することができ、ひいてはワイヤボンディングの接合強度の低下を防止することができる。   According to this, it is possible to prevent the wire bonding implementation surface (2a) of the semiconductor element (2) from being damaged in the reflow soldering process, and thus to prevent a reduction in the bonding strength of the wire bonding.

請求項２に記載の発明では、請求項１に記載のはんだ付け装置において、加圧接触面（１２１ａ）の中心線平均粗さは、０．２μｍ以下であることを特徴とする。   According to a second aspect of the present invention, in the soldering apparatus according to the first aspect, the center line average roughness of the pressure contact surface (121a) is 0.2 μm or less.

これによると、リフローはんだ付け工程で半導体素子（２）におけるワイヤボンディング実施面（２ａ）に傷が付くことを確実に防止することができる。   According to this, it can prevent reliably that the wire bonding implementation surface (2a) in a semiconductor element (2) is damaged in a reflow soldering process.

請求項３に記載の発明では、請求項１または２に記載のはんだ付け装置において、加圧接触面（１２１ａ）は、フッ素樹脂にて覆われていることを特徴とする。   According to a third aspect of the present invention, in the soldering apparatus according to the first or second aspect, the pressure contact surface (121a) is covered with a fluororesin.

これによると、加圧接触面（１２１ａ）への異物（ダスト、油分等）の付着が防止されるため、加圧接触面（１２１ａ）に付着していた異物がリフローはんだ付け工程で半導体素子（２）におけるワイヤボンディング実施面（２ａ）に付着することを防止することができ、ひいてはワイヤボンディングの接合強度の低下を防止することができる。   According to this, since foreign matter (dust, oil, etc.) is prevented from adhering to the pressure contact surface (121a), the foreign matter adhering to the pressure contact surface (121a) is removed from the semiconductor element (reflow soldering process). Adhering to the wire bonding execution surface (2a) in 2) can be prevented, and as a result, a decrease in the bonding strength of the wire bonding can be prevented.

請求項４に記載の発明のように、請求項３に記載のはんだ付け装置において、重り（１２）は、フッ素樹脂を含浸させたアルミニウムにて形成することができる。   As in the invention described in claim 4, in the soldering apparatus described in claim 3, the weight (12) can be formed of aluminum impregnated with a fluororesin.

請求項５に記載の発明では、請求項１ないし４のいずれか１つに記載のはんだ付け装置において、重り（１２）は、アルマイト処理されたアルミニウムよりなることを特徴とする。   According to a fifth aspect of the present invention, in the soldering apparatus according to any one of the first to fourth aspects, the weight (12) is made of anodized aluminum.

これによると、重り（１２）の耐食性や耐摩耗性を向上させて、リフローはんだ付け工程で半導体素子（２）におけるワイヤボンディング実施面（２ａ）に傷が付くことを継続して防止することができる。   According to this, it is possible to improve the corrosion resistance and wear resistance of the weight (12) and continuously prevent the wire bonding surface (2a) in the semiconductor element (2) from being damaged in the reflow soldering process. it can.

なお、この欄および特許請求の範囲で記載した各手段の括弧内の符号は、後述する実施形態に記載の具体的手段との対応関係を示すものである。   In addition, the code | symbol in the bracket | parenthesis of each means described in this column and the claim shows the correspondence with the specific means as described in embodiment mentioned later.

本発明の第１実施形態に係るはんだ付け装置を示す断面図である。It is sectional drawing which shows the soldering apparatus which concerns on 1st Embodiment of this invention. 図１のはんだ付け装置によるはんだ付け工程を示す図である。It is a figure which shows the soldering process by the soldering apparatus of FIG. 本発明の第２実施形態に係るはんだ付け装置を示す断面図である。It is sectional drawing which shows the soldering apparatus which concerns on 2nd Embodiment of this invention. 本発明の第３実施形態に係るはんだ付け装置を示す断面図である。It is sectional drawing which shows the soldering apparatus which concerns on 3rd Embodiment of this invention. 本発明の第４実施形態に係るはんだ付け装置を示す断面図である。It is sectional drawing which shows the soldering apparatus which concerns on 4th Embodiment of this invention. 本発明の第５実施形態に係るはんだ付け装置を示す断面図である。It is sectional drawing which shows the soldering apparatus which concerns on 5th Embodiment of this invention. 本発明の第６実施形態に係るはんだ付け装置におけるはんだ溶融前の状態を示す断面図である。It is sectional drawing which shows the state before the solder melting in the soldering apparatus which concerns on 6th Embodiment of this invention. 図７の装置におけるはんだ溶融後の状態を示す断面図である。It is sectional drawing which shows the state after the solder melting in the apparatus of FIG.

以下、本発明の実施形態について図に基づいて説明する。なお、以下の各実施形態相互において、互いに同一もしくは均等である部分には、図中、同一符号を付してある。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are denoted by the same reference numerals in the drawings.

（第１実施形態）
本発明の第１実施形態について説明する。図１は第１実施形態に係るはんだ付け装置を示す断面図、図２はそのはんだ付け装置によるはんだ付け工程を示す図である。 (First embodiment)
A first embodiment of the present invention will be described. FIG. 1 is a sectional view showing a soldering apparatus according to the first embodiment, and FIG. 2 is a view showing a soldering process by the soldering apparatus.

図１に示すように、本実施形態に係るはんだ付け装置１０は、基板１と半導体素子２との間にはんだ３を介在させ、リフローはんだ付けにより基板１と半導体素子２との接合を行うものである。なお、基板１は、ガラスエポキシまたはセラミックからなる板状の部材、もしくはアルミニウムからなるリードフレームである。   As shown in FIG. 1, a soldering apparatus 10 according to the present embodiment interposes a solder 3 between a substrate 1 and a semiconductor element 2 and joins the substrate 1 and the semiconductor element 2 by reflow soldering. It is. The substrate 1 is a plate-like member made of glass epoxy or ceramic, or a lead frame made of aluminum.

はんだ付け装置１０は、半導体素子２を位置決めするガイド治具１１と、半導体素子２を基板１側に向かって加圧するアルミニウム製の重り１２と、重り１２を摺動自在に支持する支持治具１３とを備えている。なお、ガイド治具１１および支持治具１３は、耐熱性を考慮してカーボン製としている。   The soldering apparatus 10 includes a guide jig 11 for positioning the semiconductor element 2, an aluminum weight 12 for pressing the semiconductor element 2 toward the substrate 1, and a support jig 13 for slidably supporting the weight 12. And. The guide jig 11 and the support jig 13 are made of carbon in consideration of heat resistance.

ガイド治具１１は、直方体であり、天地方向（鉛直方向）に貫通した収容空間１１０を備え、この収容空間１１０に半導体素子２が挿入される。ガイド治具１１を天地方向に沿って見たとき、収容空間１１０と半導体素子２は相似形状（具体的には矩形）であり、かつ、半導体素子２を位置決めするために収容空間１１０の壁面と半導体素子２の外周側面との隙間は小さく設定されている。   The guide jig 11 is a rectangular parallelepiped and includes an accommodation space 110 penetrating in the vertical direction (vertical direction), and the semiconductor element 2 is inserted into the accommodation space 110. When the guide jig 11 is viewed along the top-and-bottom direction, the accommodation space 110 and the semiconductor element 2 have a similar shape (specifically, a rectangle), and a wall surface of the accommodation space 110 for positioning the semiconductor element 2 The gap with the outer peripheral side surface of the semiconductor element 2 is set small.

ガイド治具１１は、下端面に下端切り欠き１１１を備え、上端面に上端切り欠き１１２を備えている。そして、下端切り欠き１１１に基板１を挿入してガイド治具１１と基板１との位置決めを行い、上端切り欠き１１２に支持治具１３を挿入してガイド治具１１と支持治具１３との位置決めを行うようになっている。   The guide jig 11 includes a lower end notch 111 on the lower end surface and an upper end notch 112 on the upper end surface. Then, the substrate 1 is inserted into the lower notch 111 to position the guide jig 11 and the substrate 1, and the support jig 13 is inserted into the upper notch 112 to connect the guide jig 11 and the support jig 13. Positioning is performed.

重り１２は、支持治具１３の摺動孔１３０に摺動自在に支持される軸部１２０と、この軸部１２０の下端に設けられて半導体素子２に接触する下端板部１２１と、軸部１２０が摺動孔１３０に挿入された後に軸部１２０の上端側に圧入等にて固定される上端板部１２２とを備えている。そして、支持治具１３の摺動孔１３０は天地方向に貫通しており、したがって、重り１２は天地方向に移動可能である。   The weight 12 includes a shaft portion 120 that is slidably supported by the slide hole 130 of the support jig 13, a lower end plate portion 121 that is provided at the lower end of the shaft portion 120 and contacts the semiconductor element 2, and a shaft portion. After the 120 is inserted into the sliding hole 130, an upper end plate portion 122 fixed to the upper end side of the shaft portion 120 by press fitting or the like is provided. The sliding hole 130 of the support jig 13 penetrates in the vertical direction, and therefore the weight 12 can move in the vertical direction.

重り１２は、下端板部１２１の下端面１２１ａが半導体素子２の上端面２ａに接触するようになっている。なお、半導体素子２の上端面２ａは、リフローはんだ付け後にワイヤボンディングが実施される面であり、以下、半導体素子２の上端面２ａを、ワイヤボンディング実施面２ａという。また、ワイヤボンディング実施面２ａに接触する下端板部１２１の下端面１２１ａを、以下、加圧接触面１２１ａという。   The weight 12 is configured such that the lower end surface 121 a of the lower end plate portion 121 is in contact with the upper end surface 2 a of the semiconductor element 2. The upper end surface 2a of the semiconductor element 2 is a surface on which wire bonding is performed after reflow soldering. Hereinafter, the upper end surface 2a of the semiconductor element 2 is referred to as a wire bonding execution surface 2a. In addition, the lower end surface 121a of the lower end plate portion 121 that contacts the wire bonding implementation surface 2a is hereinafter referred to as a pressure contact surface 121a.

この加圧接触面１２１ａは、マシニングセンタ等を用いて切削加工のみで鏡面仕上げされている。切削加工のみのため、重り１２を多数用いる場合も対応が容易である。また、重り１２は、フッ素樹脂を含浸させ且つアルマイト処理されたアルミニウムよりなる。したがって、加圧接触面１２１ａは、フッ素樹脂にて覆われている。   The pressure contact surface 121a is mirror-finished only by cutting using a machining center or the like. Since only the cutting process is performed, it is easy to deal with a case where a large number of weights 12 are used. The weight 12 is made of aluminum impregnated with a fluororesin and anodized. Therefore, the pressure contact surface 121a is covered with the fluororesin.

次に、はんだ付け装置１０によるはんだ付け工程について、図２に基づいて説明する。まず、図２（ａ）に示すように、基板１にペースト状のはんだ３をスクリーン印刷する。なお、以降の工程で基板１にガイド治具１１をセットした際に、はんだ３がガイド治具１１の収容空間１１０に臨むように、基板１の所定位置にはんだ３が印刷される。   Next, the soldering process by the soldering apparatus 10 is demonstrated based on FIG. First, as shown in FIG. 2A, paste-like solder 3 is screen-printed on the substrate 1. Note that when the guide jig 11 is set on the substrate 1 in the subsequent steps, the solder 3 is printed at a predetermined position on the substrate 1 so that the solder 3 faces the accommodation space 110 of the guide jig 11.

続いて、図２（ｂ）に示すように、基板１の上にガイド治具１１をセットする。このとき、ガイド治具１１の下端切り欠き１１１に基板１を挿入してガイド治具１１と基板１との位置決めを行う。   Subsequently, as shown in FIG. 2B, the guide jig 11 is set on the substrate 1. At this time, the substrate 1 is inserted into the lower end notch 111 of the guide jig 11 to position the guide jig 11 and the substrate 1.

続いて、図２（ｃ）に示すように、半導体素子２をガイド治具１１の収容空間１１０に挿入し、半導体素子２をはんだ３の上に載せる。   Subsequently, as shown in FIG. 2C, the semiconductor element 2 is inserted into the accommodation space 110 of the guide jig 11, and the semiconductor element 2 is placed on the solder 3.

続いて、図２（ｄ）に示すように、ガイド治具１１の収容空間１１０に重り１２を挿入してガイド治具１１の上に支持治具１３をセットする。このとき、ガイド治具１１の上端切り欠き１１２に支持治具１３を挿入してガイド治具１１と支持治具１３との位置決めを行う。この位置決めにより、重り１２と半導体素子２との相対位置が決められる。   Subsequently, as shown in FIG. 2D, the weight 12 is inserted into the accommodation space 110 of the guide jig 11 and the support jig 13 is set on the guide jig 11. At this time, the support jig 13 is inserted into the upper end notch 112 of the guide jig 11 to position the guide jig 11 and the support jig 13. By this positioning, the relative position between the weight 12 and the semiconductor element 2 is determined.

続いて、図２（ｄ）に示す状態のワークをリフロー炉に入れ、はんだ３を溶かして基板１と半導体素子２のはんだ付けを行う。このはんだ付けを行っている間、重り１２の加圧接触面１２１ａが半導体素子２のワイヤボンディング実施面２ａに接触し、重り１２により半導体素子２が基板１側に向かって加圧されるため、図２（ｅ）に示すようにはんだ３が押しつぶされ、これにより、表面張力の大きい鉛フリーはんだを使用してもボイド率が低減され、冷却時のはんだ引けが少なくなる。   Subsequently, the workpiece in the state shown in FIG. 2D is put in a reflow furnace, the solder 3 is melted, and the substrate 1 and the semiconductor element 2 are soldered. During this soldering, the pressure contact surface 121a of the weight 12 is in contact with the wire bonding execution surface 2a of the semiconductor element 2, and the semiconductor element 2 is pressed toward the substrate 1 by the weight 12, As shown in FIG. 2 (e), the solder 3 is crushed. As a result, even when a lead-free solder having a large surface tension is used, the void ratio is reduced and solder shrinkage during cooling is reduced.

なお、はんだ付けの際にはんだ３が押しつぶされて重り１２が下降しても、重り１２の上端板部１２２は支持治具１３に当接しないようになっている。したがって、重り１２の重量により、リフローはんだ付け後のはんだ３の厚みを制御することができる。   Even when the solder 3 is crushed and the weight 12 is lowered during soldering, the upper end plate portion 122 of the weight 12 does not come into contact with the support jig 13. Therefore, the thickness of the solder 3 after reflow soldering can be controlled by the weight of the weight 12.

続いて、ガイド治具１１、重り１２、および支持治具１３を取り外すことにより、基板１と半導体素子２とを接合した半導体組付体が完成する（図２（ｆ）参照）。   Subsequently, by removing the guide jig 11, the weight 12, and the support jig 13, a semiconductor assembly in which the substrate 1 and the semiconductor element 2 are joined is completed (see FIG. 2F).

本実施形態では、重り１２の加圧接触面１２１ａを鏡面仕上げしているため、はんだ付け工程において加圧接触面１２１ａが半導体素子２のワイヤボンディング実施面２ａに接触しても、ワイヤボンディング実施面２ａに傷が付くことを防止することができ、ひいてはワイヤボンディングの接合強度の低下を防止することができる。ここで、加圧接触面１２１ａの中心線平均粗さを０．２μｍ以下にした場合、リフローはんだ付け工程でワイヤボンディング実施面２ａに傷が付くことを確実に防止することができる。   In this embodiment, since the pressure contact surface 121a of the weight 12 is mirror-finished, even if the pressure contact surface 121a contacts the wire bonding execution surface 2a of the semiconductor element 2 in the soldering process, the wire bonding implementation surface. It is possible to prevent the 2a from being scratched and, in turn, to prevent a reduction in the bonding strength of the wire bonding. Here, when the center line average roughness of the pressure contact surface 121a is 0.2 μm or less, it is possible to reliably prevent the wire bonding execution surface 2a from being damaged in the reflow soldering process.

また、加圧接触面１２１ａはフッ素樹脂にて覆われているため、加圧接触面１２１ａへの異物の付着が防止される。したがって、加圧接触面１２１ａに付着していた異物がはんだ付け工程でワイヤボンディング実施面２ａに付着することを防止することができ、ひいてはワイヤボンディングの接合強度の低下を防止することができる。   Further, since the pressure contact surface 121a is covered with the fluororesin, the adhesion of foreign matter to the pressure contact surface 121a is prevented. Therefore, it is possible to prevent the foreign matter adhering to the pressure contact surface 121a from adhering to the wire bonding execution surface 2a in the soldering process, and to prevent a decrease in the bonding strength of the wire bonding.

さらに、重り１２はアルマイト処理されているため、重り１２の耐食性や耐摩耗性を向上させて、はんだ付け工程でワイヤボンディング実施面２ａに傷が付くことを継続して防止することができる。   Furthermore, since the weight 12 is anodized, the corrosion resistance and wear resistance of the weight 12 can be improved, and the wire bonding surface 2a can be continuously prevented from being damaged during the soldering process.

（第２実施形態）
本発明の第２実施形態について説明する。図３は第２実施形態に係るはんだ付け装置を示す断面図である。以下、第１実施形態と異なる部分についてのみ説明する。 (Second Embodiment)
A second embodiment of the present invention will be described. FIG. 3 is a sectional view showing a soldering apparatus according to the second embodiment. Only the parts different from the first embodiment will be described below.

本実施形態のはんだ付け装置は、基板１が複数に分かれている場合に用いられるもので、図３に示すように、はんだ付け装置１０は、基板１が収容される収容孔１４０が複数個形成されたカーボン製のセット治具１４を備えている。   The soldering apparatus of the present embodiment is used when the substrate 1 is divided into a plurality of parts. As shown in FIG. 3, the soldering apparatus 10 has a plurality of receiving holes 140 in which the substrate 1 is accommodated. The carbon setting jig 14 is provided.

そして、複数の基板１をセット治具１４の収容孔１４０に挿入して位置決めし、複数の半導体素子２をガイド治具１１により位置決めし、重り１２および支持治具１３をセットした後、その状態のワークをリフロー炉に入れ、はんだ３を溶かして基板１と半導体素子２のはんだ付けを行う。   Then, the plurality of substrates 1 are inserted and positioned in the accommodation holes 140 of the setting jig 14, the plurality of semiconductor elements 2 are positioned by the guide jig 11, and the weight 12 and the supporting jig 13 are set, and then the state The workpiece is placed in a reflow furnace, the solder 3 is melted, and the substrate 1 and the semiconductor element 2 are soldered.

本実施形態では、半導体素子２および基板１の位置は、ガイド治具１１の壁の厚みやセット治具１４の収容孔１４０の位置を変えることで調整される。また、はんだ３の厚みは重り１２の重量で決定されるため、半導体素子２および基板１の形状は問わない。   In the present embodiment, the positions of the semiconductor element 2 and the substrate 1 are adjusted by changing the wall thickness of the guide jig 11 and the position of the accommodation hole 140 of the setting jig 14. Further, since the thickness of the solder 3 is determined by the weight of the weight 12, the shapes of the semiconductor element 2 and the substrate 1 are not limited.

（第３実施形態）
本発明の第３実施形態について説明する。図４は第３実施形態に係るはんだ付け装置を示す断面図である。以下、第１実施形態と異なる部分についてのみ説明する。 (Third embodiment)
A third embodiment of the present invention will be described. FIG. 4 is a sectional view showing a soldering apparatus according to the third embodiment. Only the parts different from the first embodiment will be described below.

図４に示すように、支持治具１３は、リフロー炉内と収容空間１１０とを連通させる複数の連通孔１３１を備えている。これにより、リフロー炉内雰囲気を連通孔１３１を介して収容空間１１０内に取り込むことができるため、収容空間１１０の温度を上げやすく、はんだ付けを短時間で行うことができる。   As shown in FIG. 4, the support jig 13 includes a plurality of communication holes 131 that allow the inside of the reflow furnace and the accommodation space 110 to communicate with each other. Thereby, since the atmosphere in the reflow furnace can be taken into the accommodating space 110 through the communication hole 131, the temperature of the accommodating space 110 can be easily raised and soldering can be performed in a short time.

（第４実施形態）
本発明の第４実施形態について説明する。図５は第４実施形態に係るはんだ付け装置を示す断面図である。以下、第１実施形態と異なる部分についてのみ説明する。 (Fourth embodiment)
A fourth embodiment of the present invention will be described. FIG. 5 is a sectional view showing a soldering apparatus according to the fourth embodiment. Only the parts different from the first embodiment will be described below.

図５に示すように、支持治具１３の摺動孔１３０は、下方に向かって径が小さくなるテーパになっている。   As shown in FIG. 5, the sliding hole 130 of the support jig 13 has a taper whose diameter decreases downward.

重り１２は、上端板部１２２が廃止され、重り１２の軸部１２０は、下方に向かって径が小さくなるテーパになっている。また、軸部１２０が摺動孔１３０に挿入された後に軸部１２０の下端側に下端板部１２１が圧入等にて固定される。   In the weight 12, the upper end plate portion 122 is abolished, and the shaft portion 120 of the weight 12 is tapered such that the diameter decreases downward. Further, after the shaft portion 120 is inserted into the slide hole 130, the lower end plate portion 121 is fixed to the lower end side of the shaft portion 120 by press-fitting or the like.

そして、はんだ付けの際に重り１２の重量によりはんだ３が押しつぶされて重り１２が所定位置まで下降すると、軸部１２０が摺動孔１３０に当接し、重り１２はその位置で停止する。したがって、重り１２の停止位置を調整することにより、リフローはんだ付け後のはんだ３の厚みを制御することができる。   When the solder 3 is crushed by the weight of the weight 12 during soldering and the weight 12 is lowered to a predetermined position, the shaft portion 120 comes into contact with the sliding hole 130 and the weight 12 stops at that position. Therefore, by adjusting the stop position of the weight 12, the thickness of the solder 3 after reflow soldering can be controlled.

（第５実施形態）
本発明の第５実施形態について説明する。図６は第５実施形態に係るはんだ付け装置を示す断面図である。以下、第１実施形態と異なる部分についてのみ説明する。 (Fifth embodiment)
A fifth embodiment of the present invention will be described. FIG. 6 is a sectional view showing a soldering apparatus according to the fifth embodiment. Only the parts different from the first embodiment will be described below.

図６に示すように、はんだ付けの際にはんだ３が押しつぶされて重り１２が下降すると、重り１２の上端板部１２２が支持治具１３に当接し、重り１２はその位置で停止するようになっている。したがって、重り１２の停止位置を調整することにより、リフローはんだ付け後のはんだ３の厚みを制御することができる。   As shown in FIG. 6, when the solder 3 is crushed and the weight 12 is lowered during soldering, the upper end plate portion 122 of the weight 12 comes into contact with the support jig 13, and the weight 12 stops at that position. It has become. Therefore, by adjusting the stop position of the weight 12, the thickness of the solder 3 after reflow soldering can be controlled.

（第６実施形態）
本発明の第６実施形態について説明する。図７は第６実施形態に係るはんだ付け装置におけるはんだ溶融前の状態を示す断面図、図８は図７の装置におけるはんだ溶融後の状態を示す断面図である。以下、第１実施形態と異なる部分についてのみ説明する。 (Sixth embodiment)
A sixth embodiment of the present invention will be described. FIG. 7 is a cross-sectional view showing a state before the solder is melted in the soldering apparatus according to the sixth embodiment, and FIG. 8 is a cross-sectional view showing a state after the solder is melted in the apparatus of FIG. Only the parts different from the first embodiment will be described below.

本実施形態では、重り１２の線膨張係数が支持治具１３の線膨張係数よりも大である。そして、図７に示すように、はんだ３の溶融温度未満の温度域では、軸部１２０と摺動孔１３０との間に隙間があって、重り１２は天地方向に移動可能である。また、図８に示すように、はんだ３の溶融温度に達すると、軸部１２０と摺動孔１３０との間の隙間がなくなって重り１２は移動不可能になり、はんだ３はそれ以上押しつぶされなくなる。   In this embodiment, the linear expansion coefficient of the weight 12 is larger than the linear expansion coefficient of the support jig 13. As shown in FIG. 7, in the temperature range below the melting temperature of the solder 3, there is a gap between the shaft portion 120 and the sliding hole 130, and the weight 12 can move in the vertical direction. Further, as shown in FIG. 8, when the melting temperature of the solder 3 is reached, the gap between the shaft portion 120 and the sliding hole 130 disappears and the weight 12 cannot move, and the solder 3 is further crushed. Disappear.

（他の実施形態）
上記各実施形態では、ペースト状のはんだ３を用いたが、固形状のはんだ３を用いてもよい。具体的には、基板１の上にガイド治具１１をセットした後、基板１の上に固形状のはんだ３を載せ、さらにそのはんだ３の上に半導体素子２を載せる（図２（ｃ）の状態）。以下、第１実施形態と同様に、図２（ｄ）以降の工程を実行する。 (Other embodiments)
In each of the above embodiments, the paste-like solder 3 is used, but a solid solder 3 may be used. Specifically, after setting the guide jig 11 on the substrate 1, the solid solder 3 is placed on the substrate 1, and further the semiconductor element 2 is placed on the solder 3 (FIG. 2 (c)). State). Thereafter, similarly to the first embodiment, the processes after FIG. 2D are executed.

また、ペースト状のはんだ３または固形状のはんだ３を基板１の上に載せた状態、すなわち、はんだ３の上に半導体素子２を載せる前の状態（図２（ａ）の状態）で、はんだ３を一度溶融させてもよい。そして、はんだ３が固まった後に目視等にて検査し、ボイドが多いワークは廃却するようにしてもよい。   Further, in the state where the paste-like solder 3 or the solid solder 3 is placed on the substrate 1, that is, the state before the semiconductor element 2 is placed on the solder 3 (the state shown in FIG. 2A), the solder 3 may be melted once. Then, after the solder 3 is hardened, it may be inspected by visual inspection or the like, and the workpiece having many voids may be discarded.

なお、上記各実施形態は、実施可能な範囲で任意に組み合わせが可能である。   In addition, each said embodiment can be arbitrarily combined in the range which can be implemented.

１ 基板
２ 半導体素子
３ はんだ
１２ 重り
１２１ａ 加圧接触面 DESCRIPTION OF SYMBOLS 1 Board | substrate 2 Semiconductor element 3 Solder 12 Weight 121a Pressure contact surface

Claims (5)

基板（１）と半導体素子（２）との間にはんだ（３）を介在させ、重り（１２）により前記半導体素子（２）を前記基板（１）側に向かって加圧しつつリフローはんだ付けを行うはんだ付け装置であって、
前記重り（１２）における前記半導体素子（２）に接触する加圧接触面（１２１ａ）は、鏡面仕上げされていることを特徴とするはんだ付け装置。 Solder (3) is interposed between the substrate (1) and the semiconductor element (2), and reflow soldering is performed while pressing the semiconductor element (2) toward the substrate (1) by a weight (12). A soldering device to perform,
The pressure contact surface (121a) which contacts the said semiconductor element (2) in the said weight (12) is mirror-finished, The soldering apparatus characterized by the above-mentioned. 前記加圧接触面（１２１ａ）の中心線平均粗さは、０．２μｍ以下であることを特徴とする請求項１に記載のはんだ付け装置。   2. The soldering apparatus according to claim 1, wherein the center line average roughness of the pressure contact surface (121 a) is 0.2 μm or less. 前記加圧接触面（１２１ａ）は、フッ素樹脂にて覆われていることを特徴とする請求項１または２に記載のはんだ付け装置。   The soldering apparatus according to claim 1, wherein the pressure contact surface (121 a) is covered with a fluororesin. 前記重り（１２）は、フッ素樹脂を含浸させたアルミニウムよりなることを特徴とする請求項３に記載のはんだ付け装置。   The soldering apparatus according to claim 3, wherein the weight (12) is made of aluminum impregnated with a fluororesin. 前記重り（１２）は、アルマイト処理されたアルミニウムよりなることを特徴とする請求項１ないし４のいずれか１つに記載のはんだ付け装置。   The soldering device according to any one of claims 1 to 4, wherein the weight (12) is made of anodized aluminum.
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002166423A (en) * 2000-11-30 2002-06-11 Chisso Corp Polypropylene resin moldings with high transparency and rigidity and manufacturing method therefor
JP2002184791A (en) * 2000-12-14 2002-06-28 Yamaha Motor Co Ltd Semiconductor device
JP2006073839A (en) * 2004-09-03 2006-03-16 Oki Electric Ind Co Ltd Semiconductor device holder and semiconductor device manufactured using the same
JP2008112955A (en) * 2006-10-06 2008-05-15 Toyota Industries Corp Semiconductor device, metal bonding material, soldering method, and manufacturing method of electronic apparatus
JP2008226981A (en) * 2007-03-09 2008-09-25 Omron Corp Reflow device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002166423A (en) * 2000-11-30 2002-06-11 Chisso Corp Polypropylene resin moldings with high transparency and rigidity and manufacturing method therefor
JP2002184791A (en) * 2000-12-14 2002-06-28 Yamaha Motor Co Ltd Semiconductor device
JP2006073839A (en) * 2004-09-03 2006-03-16 Oki Electric Ind Co Ltd Semiconductor device holder and semiconductor device manufactured using the same
JP2008112955A (en) * 2006-10-06 2008-05-15 Toyota Industries Corp Semiconductor device, metal bonding material, soldering method, and manufacturing method of electronic apparatus
JP2008226981A (en) * 2007-03-09 2008-09-25 Omron Corp Reflow device

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