JP2013102237A - Particle adhesion restraining method and substrate processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a particle adhesion restraining method capable of restraining particles from being adhered to a substrate.SOLUTION: A wafer W processing device comprises: a chamber 11 that houses a wafer W and in which plasma is generated; a susceptor 12 for locating the housed wafer W; a first high frequency power source 19 for applying bias power to the susceptor 12; a second high frequency power source 31 for applying plasma generation power to the susceptor 12; and a second direct-current power source 15 for supplying direct-current power to an upper electrode 33 opposed to the susceptor 12. After completing dry-etching processing, the second direct-current power source 15 immediately finishes application of the direct-current power. While the second high-frequency power 31 reduces the plasma generation power from 2700 W to 200 W and maintains its application for a subsequent predetermined short time (Δt), the first high frequency power source 19 maintains application of the bias power of 4500 W for a predetermined short time (Δt).

Description

  The present invention relates to a particle adhesion suppression method and a substrate processing apparatus, and more particularly to a particle adhesion suppression method in a substrate processing apparatus that performs plasma processing on a substrate mounted on a mounting table to which bias power is applied.

  In a substrate processing apparatus including a storage chamber for storing a semiconductor wafer (hereinafter simply referred to as a “wafer”) as a substrate and a mounting table placed in the storage chamber for mounting the wafer, plasma processing is performed on the wafer. At this time, plasma (electrons and positive ions) is drawn into the wafer placed on the mounting table by generating plasma in the accommodation chamber and applying bias power to the mounting table.

  Usually, a semiconductor device is manufactured from a wafer. However, if particles in the accommodation chamber adhere to the wafer during plasma processing, the semiconductor device is defective. Therefore, there is a conventional technique for removing particles from the accommodation chamber before plasma processing. Some have been developed.

  However, particles may be generated during plasma processing due to wear of some of the components arranged in the storage chamber, and these particles are positively or negatively charged. On the other hand, when the plasma disappears after the plasma processing, a negative self-bias potential is generated on the wafer. Therefore, there is a possibility that particles that are positively charged after the plasma treatment are attracted to and attached to the wafer by electrostatic force.

  Therefore, when a plurality of plasma treatments are performed on the wafer, the plurality of plasma treatments are performed without interruption to keep generating plasma, thereby preventing the wafer from generating a self-bias potential, and positively charged particles A technique for preventing the wafer from being attracted has been developed (see, for example, Patent Document 1).

Further, the negatively charged particles P are mainly subjected to gravitational force F _G , force F _E received from an electric field caused by bias power applied to the mounting table, and accommodation during the plasma processing, as shown in FIG. viscous force F _n of the gas flowing through the chamber to act.

Since the bias power from the bias power source 101 to the mounting table 100 is applied a negative bias potential occurs when the stage 100 is the lower electrode, the force F _E applied from gravity F _G and the electric field is acting in opposite directions. When the particle P moves away from the mounting table 100 to some extent, the gravity F _G and the force F _E received from the electric field become substantially equal, so that the particle P stays there, and as indicated by the broken line in the figure due to the viscous force F _n of the gas. It floats near the boundary surface of the sheath 102 on the wafer W (FIG. 4B).

JP 2003-68708 A

However, after the plasma treatment, no longer a force F _E received from the field in the application of the bias power from the bias power supply 101 is completed the particles P, as shown in FIG. 4 (C), fall by gravity F _G There is a problem that it adheres to the wafer W.

  An object of the present invention is to provide a particle adhesion suppressing method and a substrate processing apparatus capable of suppressing particle adhesion to a substrate.

  In order to achieve the above object, a particle adhesion suppressing method according to claim 1 includes a storage chamber for storing a substrate and generating plasma therein, a mounting table for mounting the stored substrate, and a mounting table. A first power source for applying a bias power for drawing the plasma; a second power source for applying an electron density control power for controlling the electron density on the substrate; and a counter electrode facing the mounting table. And the second power source is a particle adhesion suppressing method in a substrate processing apparatus that applies DC power to the counter electrode, wherein 0.5 second to 1.0 second after completion of the plasma processing, The second power source has an electron density lowering step for controlling the electron density control power so that the electron density on the substrate is lower than the electron density at the time of processing by the plasma, In the step of decreasing the electron density, the first power source maintains the application of the bias power, and the second power source reduces the DC power to be lower than the DC power during the plasma processing. .

  The particle adhesion suppression method according to claim 2 is the particle adhesion suppression method according to claim 1, wherein the second power source applies high-frequency power having a frequency higher than the frequency of the bias power in addition to the DC power. In the electron density lowering step, the second power supply further reduces the high-frequency power to be lower than the high-frequency power at the time of processing with the plasma.

  The particle adhesion suppressing method according to claim 3 is the particle adhesion suppressing method according to claim 2, wherein in the electron density lowering step, the second power source converts the high-frequency power into the high-frequency power during processing by the plasma. It is characterized by being reduced to 40% or less.

  In order to achieve the above object, a substrate processing apparatus according to a fourth aspect of the present invention includes a storage chamber for storing a substrate and generating plasma therein, a mounting table for mounting the stored substrate, and a mounting table on the mounting table. A first power source for applying a bias power for drawing plasma, a second power source for applying an electron density control power for controlling the electron density on the substrate, and a counter electrode facing the mounting table. The second power source is a substrate processing apparatus for applying DC power to the counter electrode, and the second power source is the substrate in 0.5 to 1.0 seconds after the plasma processing is completed. The electron density control power is controlled so that the upper electron density is lower than the electron density at the time of processing by the plasma, and the first power source is the bias power in the period from 0.5 second to 1.0 second. Application of Maintaining said second power source is characterized in that to lower than the DC power during the treatment the DC power by the plasma.

  The substrate processing apparatus according to claim 5 is the substrate processing apparatus according to claim 4, wherein the electron density control power is power for generating plasma, and the electron density control power is applied to generate the plasma. The first region and the second region where the substrate is processed using the plasma are the same or adjacent to each other.

  The substrate processing apparatus according to claim 6 is the substrate processing apparatus according to claim 4 or 5, wherein the second power source applies high-frequency power having a frequency higher than the frequency of the bias power in addition to the DC power. In the period from 0.5 second to 1.0 second, the second power supply further reduces the high-frequency power to be lower than the high-frequency power during the treatment with the plasma.

  The substrate processing apparatus according to claim 7 is the substrate processing apparatus according to claim 6, wherein the second power source is configured to perform the high-frequency power during the processing with the plasma during the 0.5 second to 1.0 second. The high frequency power is reduced to 40% or less.

  According to the present invention, the electron density on the substrate becomes lower than the electron density at the time of processing using plasma after 0.5 to 1.0 second after the processing using plasma, and the application of bias power is performed. Is maintained. When the electron density is lowered in 0.5 seconds to 1.0 seconds, the negative bias potential due to the bias power applied to the mounting table rapidly decreases, and the force that the particles floating on the substrate receive from the electric field rapidly Since the force increases, the balance between the force received from the gravity and the electric field is lost, and the particles are removed from the substrate by the force received from the electric field. As a result, the adhesion of particles to the substrate can be suppressed.

  In addition, according to the present invention, the DC power applied to the counter electrode facing the mounting table is lower than the DC power during processing using plasma. When the direct current power is reduced, the emission of secondary electrons from the counter electrode is suppressed, and the electron density on the substrate is surely lower than the electron density during processing using plasma. As a result, since the force that the particles floating on the substrate receive from the electric field is reliably increased, the particles are reliably removed from the substrate by the force received from the electric field.

It is sectional drawing which shows schematically the structure of the substrate processing apparatus which concerns on embodiment of this invention. It is a chart figure which shows the power supply control sequence as a particle adhesion suppression method which concerns on this Embodiment. FIGS. 3A and 3B are diagrams for explaining the behavior of particles when the electron density on the wafer is lowered, FIG. 3A is a diagram showing vectors of each force acting on the particles, and FIG. It is a figure for demonstrating the mode of the removal of the particle from. FIG. 4A is a diagram for explaining the behavior of conventional particles during plasma processing, FIG. 4A is a diagram showing vectors of forces acting on the particles, and FIG. 4B is a diagram showing particles floating on the wafer. FIG. 4C is a diagram showing a state of falling particles after the plasma processing.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a cross-sectional view schematically showing a configuration of a substrate processing apparatus according to the present embodiment. The substrate processing apparatus is configured to perform a dry etching process on a wafer.

  In FIG. 1, a substrate processing apparatus 10 has, for example, a chamber 11 (accommodating chamber) that accommodates a wafer W having a diameter of 300 mm, and a cylindrical shape on which a semiconductor device wafer W is placed. A susceptor 12 (mounting table) is disposed. In the substrate processing apparatus 10, the side exhaust path 13 that functions as a flow path for discharging the gas above the susceptor 12 out of the chamber 11 is formed by the inner wall of the chamber 11 and the side surface of the susceptor 12. An exhaust plate 14 is disposed in the middle of the side exhaust path 13.

  The exhaust plate 14 is a plate-like member having a large number of holes, and functions as a partition plate that partitions the interior of the chamber 11 into an upper part and a lower part. Plasma is generated in an upper portion (hereinafter referred to as “reaction chamber”) 17 inside the chamber 11 partitioned by the exhaust plate 14. Further, an exhaust pipe 16 that exhausts gas in the chamber 11 is connected to a lower portion 18 (hereinafter referred to as “exhaust chamber (manifold)”) inside the chamber 11. The exhaust plate 14 captures or reflects the plasma generated in the reaction chamber 17 to prevent leakage to the manifold 18.

A TMP (Turbo Molecular Pump) and a DP (Dry Pump) (both not shown) are connected to the exhaust pipe 16, and these pumps evacuate and depressurize the inside of the chamber 11. Specifically, DP depressurizes the inside of the chamber 11 from atmospheric pressure to a medium vacuum state (for example, 1.3 × 10 Pa (0.1 Torr) or less), and TMP cooperates with the DP to medium vacuum in the chamber 11. The pressure is reduced to a high vacuum state (for example, 1.3 × 10 ⁻³ Pa (1.0 × 10 ⁻⁵ Torr or less)) that is lower than the state. The pressure in the chamber 11 is controlled by an APC valve (not shown).

  A first high frequency power source 19 (first power source) is connected to the susceptor 12 in the chamber 11 via a first matching unit 20, and a second power source having an electron density control function is used alone or a second power source described later. A second high-frequency power source 31 configured in cooperation with the two DC power sources 15 is connected via the second matching unit 30, and the first high-frequency power source 19 has a relatively low frequency, for example, 3.2 MHz. A bias power for drawing plasma into the susceptor 12 is applied to the susceptor 12, and the second high-frequency power source 31 generates a plasma having a relatively high frequency, for example, 40MHz. Electric power (electron density control power) (hereinafter referred to as “plasma generation power”) is applied to the susceptor 12. Thereby, the susceptor 12 functions as a lower electrode.

  An electrostatic chuck 22 having an electrostatic electrode plate 21 therein is disposed on the susceptor 12. The electrostatic chuck 22 has a shape in which an upper disk-shaped member having a diameter smaller than that of the lower disk-shaped member is stacked on a lower disk-shaped member having a certain diameter. The electrostatic chuck 22 is made of ceramics.

  In the electrostatic chuck 22, a first DC power source 23 is connected to the electrostatic electrode plate 21. When a positive DC voltage is applied to the electrostatic electrode plate 21, a negative potential is generated on the surface of the wafer W on the electrostatic chuck 22 side (hereinafter referred to as “back surface”), and the electrostatic electrode plate 21 and the wafer. A potential difference is generated between the back surfaces of W, and the wafer W is attracted and held on the upper disk-shaped member in the electrostatic chuck 22 by Coulomb force or Johnson-Rabeck force resulting from the potential difference.

  Further, a focus ring 24 which is a ring-shaped member is placed on the electrostatic chuck 22 so as to surround the wafer W held by suction. The focus ring 24 is made of the same single crystal silicon as the material constituting the conductor, for example, the wafer W. Since the focus ring 24 is made of a conductive material, the plasma distribution area is expanded not only on the wafer W but also on the focus ring 24 so that the plasma density on the peripheral portion of the wafer W is increased to the plasma on the central portion of the wafer W. Maintain the same density as. Thereby, the uniformity of the dry etching process performed on the entire surface of the wafer W can be maintained.

  Inside the susceptor 12, for example, an annular refrigerant chamber 25 extending in the circumferential direction is provided. A low temperature refrigerant such as cooling water or Galden (registered trademark) is circulated and supplied to the refrigerant chamber 25 through a refrigerant pipe 26 from a chiller unit (not shown). The susceptor 12 cooled by the low-temperature refrigerant cools the wafer W and the focus ring 24 via the electrostatic chuck 22.

  A plurality of heat transfer gas supply holes 27 are opened in a portion where the wafer W on the upper surface of the upper disk-shaped member of the electrostatic chuck 22 is held by suction (hereinafter referred to as “suction surface”). The plurality of heat transfer gas supply holes 27 are connected to a heat transfer gas supply unit (not shown) via a heat transfer gas supply line 28, and the heat transfer gas supply unit is helium (He) gas as the heat transfer gas. Is supplied to the gap between the adsorption surface and the back surface of the wafer W through the heat transfer gas supply hole 27. The helium gas supplied to the gap between the suction surface and the back surface of the wafer W effectively transfers the heat of the wafer W to the electrostatic chuck 22.

  A shower head 29 is disposed on the ceiling of the chamber 11 so as to face the susceptor 12. The shower head 29 includes an upper electrode 33 (counter electrode) that is a conductive disk-shaped member having a large number of gas holes 32, a cooling plate 34 that detachably supports the upper electrode 33, and the cooling plate 34. And a lid 35 covering the. A buffer chamber 36 is provided inside the cooling plate 34, and a processing gas introduction pipe 37 is connected to the buffer chamber 36. The upper electrode 33 is connected to a second DC power supply 15 that constitutes a second power supply having an electron density control function alone or in cooperation with the second high-frequency power supply 31, and the second DC power supply 15 is DC power (electron density control power) is applied to the upper electrode 33.

  In the substrate processing apparatus 10, the processing gas supplied from the processing gas introduction pipe 37 to the buffer chamber 36 is introduced into the reaction chamber 17 through the gas hole 32, and the introduced processing gas is supplied from the second high-frequency power source 31. Is excited by the plasma generation power applied to the inside of the reaction chamber 17 through the susceptor 12 to become plasma. The positive ions in the plasma are attracted toward the wafer W placed on the susceptor 12 by a negative bias potential resulting from the bias power applied to the susceptor 12, and the wafer W is subjected to a dry etching process.

  In the substrate processing apparatus 10, during the dry etching process, the second DC power supply 15 applies negative DC power to the upper electrode 33, and the upper electrode 33 emits secondary electrons. Since the amount of secondary electrons emitted depends on the value of the DC power applied to the upper electrode 33, the second DC power supply 15 changes the value of the DC power applied to change the amount of secondary electrons in the reaction chamber 17. The electron density, in particular, the electron density on the wafer W can be controlled. Further, since the amount of plasma generated depends on the value of the plasma generation power applied to the inside of the reaction chamber 17, the value of the plasma generation power applied to the second high-frequency power supply 31 is changed to change the amount of plasma generated in the reaction chamber 17. The electron density, in particular, the electron density on the wafer W can be controlled.

  The operation of each component of the substrate processing apparatus 10 described above, for example, the first high-frequency power supply 19, the second high-frequency power supply 31, and the second DC power supply 15, is performed by a control unit (not shown) provided in the substrate processing apparatus 10. The CPU performs control according to a program corresponding to the dry etching process.

  By the way, as described above, in the substrate processing apparatus 10, particles that are negatively charged on the wafer W during the dry etching process drift near the boundary surface of the sheath. These particles may fall by gravity and adhere to the wafer W when the application of the bias power from the first high frequency power supply 19 is completed after the dry etching process is completed. It is necessary to remove from W.

In this embodiment, in response to this, the charged particles negatively removed from the wafer W with a force F _E which receives from the electric field. Specifically, flick particles from the wafer W by impulsively a force F _E received from increased electric field to the particles.

  FIG. 2 is a chart showing a power supply control sequence as a particle adhesion suppressing method according to the present embodiment.

  In FIG. 2, during the dry etching process (up to time T) in the substrate processing apparatus 10, the second high-frequency power supply 31 applies a plasma generation power of 40 MHz to the susceptor 12 at 2700 W, and the first high-frequency power supply 19 A bias power of 3.2 MHz is applied to the susceptor 12 at 4500 W, and the second DC power supply 15 applies DC power to the upper electrode 33 at −300V.

  Next, after the dry etching process is completed, the second DC power supply 15 immediately ends the application of DC power, and the second high-frequency power supply 31 reduces the plasma generation power to 200 W over a predetermined short time (Δt). To maintain the application. When the application of the DC power from the second DC power supply 15 is completed, the emission of secondary electrons is stopped, and when the plasma generation power is reduced, the generation of plasma is suppressed. As a result, the electron density inside the reaction chamber 17, in particular, the electron density on the wafer W becomes lower than the electron density during the dry etching process. On the other hand, the first high-frequency power source 19 maintains the application of the bias power of 4500 W for a predetermined short time (Δt).

  FIG. 3 is a diagram for explaining the behavior of particles when the electron density on the wafer is lowered, and FIG. 3A is a diagram showing vectors of forces acting on the particles, and FIG. () Is a diagram for explaining how particles are removed from the wafer.

When the electron density is lowered, the effect of electrostatic shielding in the plasma is weakened, and therefore the influence of the negative bias potential on the susceptor 12 is increased. As shown in FIG. 3A, the force F _E that the particle P receives from the electric field. Increases rapidly. At this time, the force F _E received from the electric field increases and much than gravity F _G, unbalanced force F _E applied from gravity F _G and the electric field, from the wafer W by the force F _E particles P is received from the field Removed.

As described above, because a reduction in electron density on the wafer W is generated in a predetermined short time, the force F _E received from increased electric field impulsively act to the particles P, the particles P from the wafer W Played away. At this time, the particles P for viscous force F _n of some gas flowing along the surface of the wafer W is applied, the particles P, instead of being flicked vertically upwards to the surface of the wafer W, It is flipped off obliquely upward with respect to the surface of the wafer W (FIG. 3B). Therefore, the blown-off particles P hardly fall toward the wafer W again.

  Next, after the elapse of a predetermined short time (after T + Δt), the second high-frequency power supply 31 immediately ends the application of the plasma generation power, and the first high-frequency power supply 19 ends the application of the bias power. Exit.

  In order to change the electron density on the wafer W in response to the change in the plasma generation power, a certain response time is required, and if the time for reducing the plasma generation power is shorter than 0.5 seconds, The electron density does not decrease sufficiently. Further, after the plasma generation power is changed, if the changed state is maintained for 1.0 second or more, newly generated particles different from the particles P blown off from the wafer W reach the wafer W. Then, it begins to drift on the wafer W. Therefore, in the power supply control sequence described above, the predetermined short time for reducing the plasma generation power is set to 0.5 seconds to 1.0 seconds.

  In the power supply control sequence described above, removal of the particles P is greatly affected by a change in electron density. Therefore, the substrate processing apparatus 10 includes a device (not shown) that measures the electron density inside the processing chamber 17.

According to the power supply control sequence shown in FIG. 2, the application of DC power to the upper electrode 33 is immediately terminated after the dry etching process is completed, and the susceptor 12 is continued for 0.5 to 1.0 seconds. The plasma generation power applied to the susceptor 12 is maintained while being reduced from 2700 W to 200 W, while the bias power applied to the susceptor 12 is maintained at 4500 W. When the plasma generation power is reduced, the generation of plasma is suppressed, and when the application of the DC power is finished, the emission of secondary electrons from the upper electrode 33 is stopped, so that the electron density on the wafer W is the electron density during the dry etching process. Certainly lower than. Then, when the electron density on the wafer W becomes low during a short period of 0.5 seconds to 1.0 seconds, the negative bias potential due to the bias power applied to the susceptor 12 rapidly decreases, since the particles P floating on the wafer W is rapidly increases the force F _E received from the field, with the balance of forces F _E applied from gravity F _G and the electric field collapses quickly, the force F _E received from the electric field on the particles P impact It works in the same way. As a result, the particles P are blown off from the wafer W, so that the adhesion of the particles P to the wafer W can be suppressed.

In the power supply control sequence of FIG. 2 described above, after the dry etching process is finished, the application of DC power is finished and the plasma generation power is reduced, but only the application of DC power may be finished, or Only a reduction in plasma generation power may be performed. Since the electron density on the wafer W in any case is lower than the electron density of the dry etching process, particles P can be reliably increased force F _E received from the field, with, the particles P on the wafer W Can be reliably removed from. In particular, since the emission of secondary electrons is interrupted immediately after the application of the DC power is completed, it is preferable to execute the application of the DC power from the viewpoint of responsiveness in controlling the electron density.

  Further, instead of executing the application end of the DC power, the DC power may be reduced. In this case, emission of secondary electrons from the upper electrode 33 is suppressed, and the electron density on the wafer W can be made lower than the electron density during the dry etching process.

In the power supply control sequence of FIG. 2 described above, the application of DC power and the decrease of plasma generation power are executed. However, after the dry etching process is completed, the DC power and plasma generation power applied are not changed. The bias power may be increased. In this case, due to the increase of the bias power reduces the negative bias potential in the susceptor 12 (however, the absolute value of the potential difference is increased), it is possible to particles P to increase the force F _E which receives from the electric field.

In the substrate processing apparatus 10 described above, the reaction chamber 17 (first region), which is a region where plasma generation power is applied and plasma is generated, is on the wafer W, which is a region where the wafer W is processed using plasma. Therefore, the influence of the decrease in plasma generation power can be immediately reflected in the space on the wafer W. As a result, the electron density on the wafer W can be quickly reduced.

  Further, in the substrate processing apparatus 10 described above, a region where plasma generation power is applied and plasma is generated (hereinafter referred to as “plasma generation region”) is a region where the wafer W is processed using plasma (hereinafter referred to as “plasma generation region”). However, it is sufficient that the plasma generation region and the processing region are at least adjacent to each other. In this case as well, the effect of the decrease in plasma generation power in the plasma generation region is immediately reflected in the processing region. Therefore, the electron density in the space on the wafer W included in the processing region can be quickly reduced. That is, the power supply control sequence in FIG. 2 is not limited to the parallel plate etching apparatus such as the substrate processing apparatus 10 described above, but also, for example, an ECR (Electron Cyclotron Resonance) sputtering apparatus or an ICP (Inductive Coupling Plasma) apparatus, particularly a TCP ( It can also be applied to a Transformer Coupling Plasma) device.

  Further, in the substrate processing apparatus 10 described above, the plasma generation power is applied to the susceptor 12, but if the bias power is applied to the susceptor 12, the plasma generation power may be applied to the upper electrode 33. By reducing the plasma generation power, the electron density in the reaction chamber 17 can be reduced, and the negative bias potential in the susceptor 12 can be reduced.

  In the present embodiment described above, the substrate on which the dry etching process is performed is a semiconductor device wafer. However, the substrate on which the dry etching process is performed is not limited to this, for example, an LCD (Liquid Crystal Display). Or a glass substrate such as FPD (Flat Panel Display).

  Another object of the present invention is to supply a computer (for example, a control unit) with a storage medium storing software program codes for realizing the functions of the above-described embodiments, and the computer CPU is stored in the storage medium. It is also achieved by reading and executing the program code.

  In this case, the program code itself read from the storage medium realizes the functions of the above-described embodiments, and the program code and the storage medium storing the program code constitute the present invention.

  Examples of the storage medium for supplying the program code include RAM, NV-RAM, floppy (registered trademark) disk, hard disk, magneto-optical disk, CD-ROM, CD-R, CD-RW, DVD (DVD). -ROM, DVD-RAM, DVD-RW, DVD + RW) and other optical disks, magnetic tapes, non-volatile memory cards, other ROMs, etc., as long as they can store the program code. Alternatively, the program code may be supplied to the computer by downloading from another computer or database (not shown) connected to the Internet, a commercial network, a local area network, or the like.

  Further, by executing the program code read by the computer, not only the functions of the above-described embodiments are realized, but also an OS (operating system) running on the CPU based on the instruction of the program code. A case where part or all of the actual processing is performed and the functions of the above-described embodiments are realized by the processing is also included.

Further, after the program code read from the storage medium is written in a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer, the function expansion is performed based on the instruction of the program code. The case where the CPU or the like provided in the board or the function expansion unit performs part or all of the actual processing and the functions of the above-described embodiments are realized by the processing is included.

  The form of the program code may include an object code, a program code executed by an interpreter, script data supplied to the OS, and the like.

  Next, examples of the present invention will be described.

Examples 1 to 5
First, in the substrate processing apparatus 10, the surface of the wafer W when the power supply control sequence of FIG. 2 is executed for processes A to E having different recipes (reaction chamber 17 internal pressure, plasma generation power and bias power setting values). The number of particles having a size of less than 0.08 μm was counted and shown in Table 1 as Examples 1 to 5, respectively. At this time, the plasma generation power after the dry etching process in the power supply control sequence was reduced to 40% or less of the plasma generation power during the dry etching process.

Comparative Examples 1 to 5
Next, the substrate processing apparatus 10 counts the number of particles having a size smaller than 0.08 μm attached to the surface of the wafer W when the conventional power supply control sequence is executed for the processes A to E. To 5 are shown in Table 1 below. In the conventional power supply control sequence in this comparative example, the application of direct current power, application of plasma generation power, and application of bias power to the upper electrode 33 were terminated immediately after the dry etching process.

実施例６
基板処理装置１０において、上部電極３３への直流電力の印加及びプラズマ生成電力の印加のみが実行されるプロセスＦについて図２の電源制御シーケンスを実行した場合（但し、バイアス電力の印加は実行しない。）におけるウエハＷの表面に付着した大きさが０．０８μｍより小さいパーティクルの数をカウントし、実施例６として下記表２に示した。このときも電源制御シーケンスにおけるドライエッチング処理後のプラズマ生成電力を、ドライエッチング処理時のプラズマ生成電力の４０％以下まで低下させた。

Example 6
In the substrate processing apparatus 10, when the power supply control sequence of FIG. 2 is executed for the process F in which only application of DC power and plasma generation power to the upper electrode 33 is executed (however, application of bias power is not executed). The number of particles with a size smaller than 0.08 μm attached to the surface of the wafer W in FIG. Also at this time, the plasma generation power after the dry etching process in the power supply control sequence was reduced to 40% or less of the plasma generation power during the dry etching process.

Comparative Example 6
Next, in the substrate processing apparatus 10, the number of particles adhered to the surface of the wafer W when the conventional power supply control sequence is executed for the process F is counted, and the following table is shown as Comparative Example 6: It was shown in 2. In the conventional power supply control sequence in this comparative example, the application of the DC power and the plasma generation power to the upper electrode 33 were immediately terminated after the dry etching process.

実施例７，８
まず、基板処理装置１０において、プラズマ生成電力の印加及びバイアス電力の印加のみが実行されるプロセスＧ及びＨについて図２の電源制御シーケンスを実行した場合（但し、上部電極３３への直流電力の印加は実行しない。）におけるウエハＷの表面に付着した大きさが０．０８μｍより小さいパーティクルの数をカウントし、それぞれ実施例７，８として下記表３に示した。このときも電源制御シーケンスにおけるドライエッチング処理後のプラズマ生成電力を、ドライエッチング処理時のプラズマ生成電力の４０％以下まで低下させた。

Examples 7 and 8
First, in the substrate processing apparatus 10, when the power supply control sequence of FIG. 2 is executed for the processes G and H in which only the application of the plasma generation power and the application of the bias power is executed (however, the application of the DC power to the upper electrode 33) Are not executed.) The number of particles attached to the surface of the wafer W in less than 0.08 μm was counted, and the results are shown in Table 3 below as Examples 7 and 8, respectively. Also at this time, the plasma generation power after the dry etching process in the power supply control sequence was reduced to 40% or less of the plasma generation power during the dry etching process.

Comparative Examples 7 and 8
Next, the substrate processing apparatus 10 counts the number of particles having a size smaller than 0.08 μm attached to the surface of the wafer W when the conventional power supply control sequence is executed for the processes G and H, respectively. , 8 are shown in Table 3 below. In the conventional power supply control sequence in this comparative example, the application of the plasma generation power and the application of the bias power were finished immediately after the dry etching process.

実施例１乃至５及び比較例１乃至５の比較の結果、実施例６及び比較例６の比較の結果、並びに実施例７，８及び比較例７，８の比較の結果、図２の電源制御シーケンスを実行した場合にウエハＷの表面に付着したパーティクルの数を低減できることが分かった。これにより、プラズマ生成電力をドライエッチング処理時のプラズマ生成電力の４０％以下まで低下させると、ウエハＷ上の電子密度がドライエッチング処理時の電子密度よりも充分に低くなり、ウエハＷ上を漂うパーティクルが電界から受ける力Ｆ_Ｅを充分に大きくすることができ、ウエハＷの表面へのパーティクルの付着を抑制することができることが分かった。

As a result of comparison between Examples 1 to 5 and Comparative Examples 1 to 5, as a result of comparison between Example 6 and Comparative Example 6, and as a result of comparison between Examples 7 and 8 and Comparative Examples 7 and 8, the power supply control of FIG. It was found that the number of particles attached to the surface of the wafer W can be reduced when the sequence is executed. As a result, when the plasma generation power is reduced to 40% or less of the plasma generation power during the dry etching process, the electron density on the wafer W becomes sufficiently lower than the electron density during the dry etching process and floats on the wafer W. particles can be sufficiently large force F _E received from the field, it was found that the adhesion of particles to the surface of the wafer W can be suppressed.

W wafer
DESCRIPTION OF SYMBOLS 10 Substrate processing apparatus 12 Susceptor 15 2nd DC power supply 17 Reaction chamber 19 1st high frequency power supply 31 2nd high frequency power supply 33 Upper electrode

Claims (7)

A storage chamber for storing a substrate and generating plasma therein, a mounting table for mounting the stored substrate, a first power supply for applying a bias power for drawing the plasma into the mounting table, and the substrate A substrate comprising: a second power source for applying electron density control power for controlling the upper electron density; and a counter electrode facing the mounting table, wherein the second power source applies DC power to the counter electrode. A particle adhesion suppressing method in a processing apparatus,
In 0.5 second to 1.0 second after completion of the plasma treatment, the second power supply causes the electron density on the substrate to be lower than the electron density during the plasma treatment. An electron density lowering step for controlling the density control power;
In the electron density lowering step, the first power source maintains the application of the bias power, and the second power source lowers the direct-current power to be lower than the direct-current power during the plasma processing. Particle adhesion suppression method. The second power source applies high-frequency power having a frequency higher than the frequency of the bias power in addition to the DC power,
2. The particle adhesion suppressing method according to claim 1, wherein, in the electron density lowering step, the second power source further reduces the high-frequency power to be lower than the high-frequency power at the time of processing with the plasma.   3. The particle adhesion suppressing method according to claim 2, wherein, in the electron density lowering step, the second power source reduces the high-frequency power to 40% or less of the high-frequency power during the treatment with the plasma. A storage chamber for storing a substrate and generating plasma therein, a mounting table for mounting the stored substrate, a first power supply for applying a bias power for drawing the plasma into the mounting table, and the substrate A substrate comprising: a second power source for applying electron density control power for controlling the upper electron density; and a counter electrode facing the mounting table, wherein the second power source applies DC power to the counter electrode. In the processing device,
The second power supply supplies the electrons so that the electron density on the substrate is lower than the electron density during the plasma treatment for 0.5 to 1.0 seconds after the plasma treatment is completed. Control density control power,
In the 0.5 second to 1.0 second period, the first power source maintains the application of the bias power, and the second power source lowers the direct current power to be lower than the direct current power during the plasma processing. A substrate processing apparatus. The electron density control power is power for generating plasma,
5. The first region in which the electron density control power is applied to generate the plasma and the second region in which processing is performed on the substrate using the plasma are the same or adjacent to each other. Substrate processing equipment. The second power source applies high-frequency power having a frequency higher than the frequency of the bias power in addition to the DC power,
The said 2nd power supply further reduces the said high frequency electric power from the said high frequency electric power at the time of the process by the said plasma in the said 0.5 second thru | or 1.0 second. Substrate processing equipment.   7. The substrate according to claim 6, wherein the second power source reduces the high-frequency power to 40% or less of the high-frequency power during the treatment with the plasma in the 0.5 to 1.0 seconds. Processing equipment.

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