JP2013101635A - Printed circuit board design support program, printed circuit board design support method and printed circuit board design support apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To automatically arrange a via on a printed circuit board so as to satisfy a predetermined condition.SOLUTION: A printed circuit board design support program allows a computer to execute a ground conductive region identification step of identifying a conductive region available as a ground of a printed circuit board having a plurality of conductive layers, an extraction step of extracting an overlapped conductive region in which conductive areas identified by the ground conductive region identification step are overlapped in a two-dimensional manner, and a first arrangement step of arranging a layer connection member which electrically connects at least two of the plurality of conductive layers at an interval within a predetermined distance on the inside of the overlapped conductive region extracted by the extraction step. The first arrangement step includes a block division step of dividing the overlapped conductive region extracted by the extraction step into blocks, and a second arrangement step of arranging the layer connection member on the inside of the blocks divided by the block division step.

Description

  The present invention relates to a printed circuit board design support program, a printed circuit board design support method, and a printed circuit board design support apparatus. In particular, an interlayer connection member (via hole, hereinafter referred to as “via”) for electrically connecting a plurality of conductive layers stacked via an insulating layer is appropriately disposed.

  2. Description of the Related Art In recent years, unnecessary electromagnetic waves (hereinafter referred to as radiation noise) radiated from electronic devices have become a problem as the speed of signals transmitted in electronic devices such as information devices has increased. In order to solve this problem, various radiation noise suppression designs have been performed on the wiring on the printed board in the electronic device, the wire harness connected to the wiring, and the housing of the electronic device.

As one of the radiation noise suppression design methods, a technique for devising the arrangement of vias that electrically connect a plurality of conductive layers in a printed circuit board has been proposed (for example, see Patent Document 1 and Patent Document 2).
In the printed circuit board design support apparatus of Patent Document 1, a technique is disclosed in which the number of vias arranged within a predetermined range on a printed board is calculated, and notification is made that the number of vias arranged is less than the predetermined number. Further, this printed wiring board design support device discloses a technique for detecting whether or not vias are arranged at predetermined intervals and notifying them when the vias are not arranged at predetermined intervals.
In the board design support device of Patent Document 2, a location (hereinafter referred to as a checkpoint) where the necessity of changing the layer of a signal return current route is to be detected is detected, and a via is disposed within a specified distance from the checkpoint. A technique for displaying a composite region of a region that has not been performed is disclosed.

JP 2003-163467 A JP 2007-272342 A

As described above, the printed circuit board design support apparatus of Patent Document 1 notifies that the number of vias within a predetermined range is small or that vias are not arranged at predetermined intervals.
Further, in the board design support apparatus of Patent Document 2, a combined region of a place where the necessity of changing the layer of the return current route, such as a signal line layer changing part, should be determined and where there is no power supply or GND via is provided. calculate. Then, the necessity of changing the layer of the return current route is determined, and if the layer change is necessary, the composite region is visualized.

  However, when the user tries to satisfy the conditions of Patent Document 1 or when trying to add additional vias to the composite area where the layer of the return current route needs to be changed in Patent Document 2, it is possible to add vias at any position. It is necessary to visually determine whether or not. Therefore, the user needs a great deal of time to determine that the position where the via can be additionally arranged, and there is a possibility that a mistake in the determination or an oversight of the position where the via can be additionally arranged may occur.

  The present invention has been made in view of the above-described problems, and an object thereof is to automatically arrange vias on a printed circuit board so as to satisfy a predetermined condition. That is, in a printed circuit board in which a plurality of conductive layers are laminated via an insulating layer, a power supply or ground via is provided on a conductive region (hereinafter referred to as an overlapping conductive region) where the power supply or ground conductive region of the plurality of conductive layers overlaps. Enable automatic placement within a predetermined interval.

  The printed circuit board design support program according to the present invention includes a ground conductive area specifying step for specifying a conductive area that can be used as a ground of a printed board having a plurality of conductive layers, and the conductive area specified by the ground conductive area specifying step is two-dimensional. An extraction step for extracting overlapping conductive regions that overlap each other, and an interlayer connection member that electrically connects at least two of the plurality of conductive layers within the overlapping conductive region extracted by the extraction step A printed circuit board design support program for causing a computer to execute a first arrangement step that arranges at an interval within a distance of a predetermined distance, wherein the first arrangement step blocks an overlapping conductive region extracted by the extraction step Divided by the block dividing step and the block dividing step. A second placement step of placing the interlayer connection member in the lock, and having a.

  According to the present invention, by automatically arranging a power supply or ground (hereinafter, GND) via on a printed circuit board, it is possible to arrange a power supply or GND via in a short time and without any mistakes at the printed circuit board design stage. it can.

  Further, for example, according to the first invention, by automatically arranging the vias in the overlapped conductive region within a predetermined interval, it is possible to save the user's trouble of arranging the power supply or the GND via, and further, mistakes and leakages. There can be no power supply or GND vias.

  For example, according to the first aspect of the present invention, it is possible to prevent an excessively large number of power supply or GND vias from being arranged by arranging power supply or GND vias in a block obtained by dividing an overlapping conductive region.

  Further, for example, according to the second invention, the power supply or the GND via is automatically arranged within a predetermined distance within a predetermined distance from the peripheral edge and the inner edge of the overlapping conductive region. Accordingly, the user can save the trouble of checking the shape of the overlapping conductive region while looking at the plurality of conductive layers, and can arrange the power supply or the GND via without leaking or leaking near the periphery and inner edge of the overlapping conductive region. it can.

  For example, according to the third aspect, even when the shape of the overlapping conductive region is changed due to the wiring change, the power supply or the GND via based on the shape change of the overlapping conductive region is automatically rearranged. As a result, the user can eliminate unnecessary vias when changing the wiring, save the trouble of additionally arranging the necessary vias, and can rearrange the power supply or GND vias without any mistakes or leakage. it can.

  For example, according to the fourth aspect of the invention, the power supply outside the changed overlapping conductive region or the via of GND is automatically excluded. As a result, in addition to the effects of the third aspect of the invention, it is possible to eliminate the minimum necessary power supply or GND via and to save time for unnecessary additional arrangement when rearranging the power supply or GND via.

  For example, according to the fifth aspect of the present invention, the surrounding power supply or GND via is excluded according to the changed wiring. Thereby, in addition to the effect of the fourth invention, when the power supply or the GND via exists at the position where the user wants to change the wiring, it is possible to save the trouble of eliminating the power supply or the GND via. Further, the user can change the wiring without being aware of the existence of the GND via.

  For example, according to the sixth invention, the power supply or the GND via is automatically corrected and arranged in the changed overlapping conductive region. As a result, the power supply or the GND via can be arranged and arranged in the changed overlapping conductive region, and the user can easily recognize the arrangement state of the via.

  For example, according to the seventh aspect, the power supply or the GND via outside the changed overlapping conductive region is corrected and arranged in the overlapping conductive region. Thereby, in addition to the effect of the sixth invention, it is possible to save the trouble of eliminating the power supply or the GND via outside the overlapping conductive region.

  For example, according to the eighth aspect of the invention, even when components or wiring are changed on the printed circuit board, GND vias arranged in the arrangement prohibited area are automatically excluded. Thereby, the trouble of eliminating the power supply or the GND via can be saved.

It is a figure which shows the structure of a printed circuit board design assistance apparatus. It is a figure which shows the function structure of a printed circuit board design assistance apparatus. It is a flowchart which shows the operation | movement process of a printed circuit board design assistance apparatus. It is a flowchart which shows an example of the processing operation which concerns on 1st Embodiment. It is a flowchart which shows an example of the processing operation which concerns on 1st Embodiment. It is a schematic diagram of the printed circuit board for demonstrating the operation processing which concerns on 1st Embodiment. It is a figure for demonstrating the setting method of the via | veer automatic arrangement | positioning condition which concerns on 1st Embodiment. It is a flowchart which shows an example of the processing operation when a GND conductive region is specified using the GND attribute information according to the first embodiment. It is a figure which shows the state after the process of step S404 which concerns on 1st Embodiment. It is a figure which shows the state after the process of step S405 which concerns on 1st Embodiment. It is a figure for demonstrating step S408 which concerns on 1st Embodiment. It is a figure which shows the state after the process of step S410 which concerns on 1st Embodiment. It is a figure for demonstrating the process of step S411 to step S416 which concerns on 1st Embodiment. It is a figure for demonstrating the process of step S411 to step S416 which concerns on 1st Embodiment. It is a figure which shows the arrangement | positioning state of the GND via | veer after the process which concerns on 1st Embodiment. It is a figure which shows the arrangement | positioning state of the GND via | veer after the process which concerns on 1st Embodiment. It is a flowchart which shows an example of the processing operation which concerns on 2nd Embodiment. It is a schematic diagram of the printed circuit board for demonstrating the operation processing which concerns on 2nd Embodiment. It is a figure which shows the state after the process of step S405 which concerns on 2nd Embodiment. It is a figure for demonstrating the process of step S1600 to step S1602 which concerns on 2nd Embodiment. It is a figure which shows the state after the process of step S408 which concerns on 2nd Embodiment. It is a figure which shows the arrangement | positioning state of the GND via | veer after the process which concerns on 2nd Embodiment. It is a flowchart which shows an example of the processing operation which concerns on 3rd Embodiment. It is a flowchart which shows an example of the processing operation which concerns on 3rd Embodiment. It is a figure for demonstrating the process of step S411 to step S416 which concerns on 3rd Embodiment. It is a figure for demonstrating the process of step S411 to step S416 which concerns on 3rd Embodiment. It is a figure which shows the arrangement | positioning state of the GND via | veer after the process which concerns on 3rd Embodiment. It is a flowchart which shows an example of the processing operation which concerns on 4th Embodiment. It is a figure for demonstrating the process of step S2600 to step S2604 which concerns on 4th Embodiment. It is a figure for demonstrating the process of step S2600 to step S2604 which concerns on 4th Embodiment. It is a figure which shows the state after the process of step S2606 which concerns on 4th Embodiment. It is a figure for demonstrating the process of step S2608 and step S2609 which concerns on 4th Embodiment. It is a figure which shows the arrangement | positioning state of the GND via | veer after the process which concerns on 4th Embodiment. It is a schematic diagram of the printed circuit board for demonstrating the operation | movement process which concerns on 5th Embodiment. It is a flowchart which shows an example of the processing operation which concerns on 5th Embodiment. It is a flowchart which shows an example of the processing operation which concerns on 5th Embodiment. It is a figure which shows the state after the process of step S405 which concerns on 5th Embodiment. It is a figure which shows the state after the process of step S405 which concerns on 5th Embodiment. It is a figure which shows the state after the process of step S3300 which concerns on 5th Embodiment. It is a figure for demonstrating the process of step S3301 to step S3303 which concerns on 5th Embodiment. It is a figure for demonstrating the process of step S409 to step S410 which concerns on 5th Embodiment. It is a figure for demonstrating the process of step S411 to step S416 which concerns on 5th Embodiment. It is a figure which shows the arrangement | positioning state of the GND via | veer after the process which concerns on 5th Embodiment. It is a figure which shows the arrangement | positioning state of the GND via | veer after the process which concerns on 5th Embodiment. It is a flowchart which shows an example of the processing operation which concerns on 6th Embodiment. It is a figure for demonstrating the process of step S4301 which concerns on 6th Embodiment. It is a figure which shows the state after the process of step S4302 which concerns on 6th Embodiment. It is a figure which shows the arrangement | positioning state of the GND via | veer after the process which concerns on 6th Embodiment. It is a flowchart which shows an example of the processing operation which concerns on 7th Embodiment. It is a figure which shows the arrangement | positioning state of the GND via | veer after the process which concerns on 7th Embodiment. It is a figure which shows the state after the process of step S4703 which concerns on 7th Embodiment. It is a figure for demonstrating the process of step S4704 which concerns on 7th Embodiment. It is a figure which shows the state after the process of step S4707 which concerns on 7th Embodiment. It is a figure for demonstrating the process of step S4706 which concerns on 7th Embodiment. It is a figure which shows the state after the process of step S4707 which concerns on 7th Embodiment. It is a figure for demonstrating the process of step S4706 which concerns on 7th Embodiment. It is a figure which shows the state after the process of step S4707 which concerns on 7th Embodiment. It is a figure which shows the state after the process of step S4707 which concerns on 7th Embodiment. It is a figure which shows the state after the process of step S4709 which concerns on 7th Embodiment.

Hereinafter, an example of a preferred embodiment of a printed circuit board design support apparatus, a printed circuit board design support method, and a printed circuit board design support program according to the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description and embodiments, and it goes without saying that modifications and combinations can be made as appropriate within the scope of the gist of the present invention.
In the embodiment described below, the target of the conductive region in which the via is arranged is referred to only as the GND conductive region, but the power source region can be set as the arrangement target if necessary. Further, in the accompanying drawings, even when the embodiments and the drawings are different, the same reference numerals are used to indicate the same items.

(First embodiment)
FIG. 1 is a diagram illustrating an example of a schematic configuration of a computer apparatus including a printed circuit board design support apparatus according to the present embodiment. As shown in FIG. 1, the printed circuit board design support apparatus 100 includes a central processing unit (CPU) 10, a main storage device 11, a display device 12, an input device 13, an external storage device 14, and an output device 15.
The CPU 10 controls the entire apparatus. The main storage device 11 is a read-only storage device (ROM), a storage device (RAM) in which the CPU 10 temporarily reads and writes during calculation processing, and the like. The display device 12 is a cathode ray tube or a liquid crystal display. The input device 13 is a mouse, a keyboard, or the like. The external storage device 14 reads and writes data from and on a recording medium such as a hard disk, a floppy (registered trademark) disk, a CD, a DVD, and an MD. The output device 15 is a printer or the like for printing calculation results and the like output to the display device 12. These devices are connected to each other via a bus 16 for transmitting information such as an address bus, a data bus, and a control bus. It is configured such that necessary information such as control information and data information can be exchanged between devices via the bus 16 under the control of the CPU 10.
The external storage device 14 stores a processing program 141 and layout information 142 in advance. The processing program 141 is a program according to the present invention, and is installed in the external storage device 14 so that the CPU 10 can execute it.
The layout information 142 is information related to the printed circuit board. In other words, layout information refers to information related to the outer shape and layer configuration of the printed circuit board, component information such as the position coordinates of the components mounted on the printed circuit board and the shape and size of the conductor portion to which the terminals are connected, and wiring between components. It includes wiring information such as name and position coordinates of each point constituting the wiring figure.

FIG. 2 is a diagram illustrating an example of a mechanism configuration of the printed circuit board design support apparatus according to the present embodiment.
The functional configuration shown in FIG. 2 is realized by the CPU 10 executing the processing program 141. The printed circuit board design support apparatus 100 includes an input unit 20, an external storage information extraction unit 21, a graphic calculation unit 22, and a via automatic arrangement unit 23.
The input unit 20 reads out layout information input by the user via the input device 13, instruction information for execution of the processing program 141, and information on conditions used for execution of the processing program 141 in the printed circuit board design support apparatus. The function to input to. Hereinafter, conditions used for executing the processing program 141 and the like are referred to as via automatic arrangement conditions. The input information is stored in the main storage device 11 by the CPU 10 as necessary for processing or control.
When the execution of the processing program is input from the input unit 20, the external storage information extraction unit 21 extracts the processing program 141 stored in the external storage device 14 according to the input, and the extracted program is stored in the main storage device 11. To remember. When the external storage information extraction unit 21 receives an instruction to read layout information from the input unit 20, the external storage information extraction unit 21 extracts the layout information 142 stored in the external storage device 14, and the extracted layout information is stored in the main storage device 11. Remember in.
The graphic calculation unit 22 performs graphic calculation processing such as extracting a region in which two or more layers of two-dimensional graphics overlap while using a partial storage region of the main storage device 11. The graphic calculation unit 22 performs graphic calculation processing based on the via automatic arrangement conditions, the processing program 141, and the layout information 142 stored in the main storage device 11.
The via automatic arrangement unit 23 performs a calculation process for determining a via arrangement position and whether or not to arrange vias while using a partial storage area of the main storage device 11 and arranges vias.

FIG. 3 is a flowchart showing an example of a processing procedure performed by the printed circuit board design support apparatus according to the present embodiment based on a printed circuit board design support program (processing program). 4 and 5 are flowcharts showing in detail the operation of each step of the flowchart shown in FIG.
First, the operation of the printed circuit board design support apparatus according to the present embodiment will be described with reference to FIG. In step S <b> 101, when a processing program execution instruction is input from the input unit 20, the external storage information extraction unit 21 transfers the processing program 141 to the main storage device 11. Next, the graphic calculation unit 22 and the via automatic arrangement unit 23 execute the processing program 141, whereby the processing of the flowchart shown in FIG.

  In step S <b> 102, information input by the input unit 20 is transferred to the main storage device 11, or the external storage information extraction unit 21 extracts the layout information 142 and transfers it to the main storage device 11. That is, the input unit 20 and the external storage information extraction unit 21 acquire and set information necessary for via automatic arrangement described later.

In step S103, the graphic calculation unit 22 extracts a GND overlapping conductive area described later.
In step S104, the via automatic arrangement unit 23 automatically arranges GND vias, which will be described later, at intervals within a predetermined interval at the peripheral edge and the inner edge of the GND overlapping conductive region.
In step S <b> 105, the via automatic arrangement unit 23 automatically arranges the GND vias at an interval within a predetermined interval in a region excluding the peripheral edge portion and the inner edge portion of the GND overlapping conductive region (hereinafter, the central portion).
In step 106, the processing program ends.

Next, the operation of the printed circuit board design support apparatus according to the present embodiment will be described based on the detailed flowcharts shown in FIGS. 4 and 5 with reference to the schematic diagrams shown in FIGS. In the following description, a schematic diagram shown in FIG. 6 is used as a printed board in order to facilitate understanding of the invention. It goes without saying that the actual printed circuit board has a high density and complicated wiring, but the following schematic explanation does not exclude it.
Here, a schematic diagram of the printed circuit board shown in FIG. 6 will be described. The printed circuit board shown in FIG. 6 has a structure in which four conductive layers are laminated via insulating layers. Specifically, as shown in the cross-sectional view of FIG. 6 (e), the conductive layers 60, 61, 62, and 63 are laminated via the insulating layer 64. 6A, 6 </ b> B, 6 </ b> C, and 6 </ b> D are plan views when the insulating layer side is viewed from the conductive layer side of the conductive layers 60, 61, 62, and 63, respectively. In each plan view, a gray portion, a black circle, and a black line portion are conductive portions. Further, the white portion is a portion having no conductivity (a portion where the insulator is exposed when stacked on the insulating layer).

  Components 600 and 630 shown in FIGS. 6A and 6D are active components arranged on a printed circuit board. Further, black solid line portions 601, 621, and 631 shown in FIGS. 6A, 6C, and 6D are conductive regions of signal wirings having a potential different from that of GND. In addition, black circles 602, 622, and 632 shown in FIGS. 6A, 6C, and 6D are vias of signal wirings having different potentials from GND. In addition, gray portions 603, 613, 623, and 633 shown in FIGS. 6A to 6D are wirings having a GND potential, that is, GND conductive regions. In FIGS. 6A to 6D, only the conductive regions and vias of some signal wirings are denoted by reference numerals for easy understanding of the drawing.

Next, the flowcharts of FIGS. 4 and 5 will be described in detail.
First, in step S400, when a processing program execution instruction is input from the input unit 20, the external storage information extraction unit 21 transfers the processing program 141 to the main storage device 11, and the graphic calculation unit 22 and the via automatic arrangement unit 23 perform processing. The program 141 is executed.
Next, in step S401, the input unit 20 sets the input via automatic arrangement condition. Here, the via automatic arrangement conditions are the allowable maximum value L1, the allowable maximum value L2, the allowable maximum value L3, and the like. The permissible maximum value L1 (hereinafter referred to as the predetermined interval L1) is the permissible maximum value of the interval from the periphery of the region where the GND conductive regions of each layer overlap two-dimensionally (hereinafter referred to as the GND overlapping conductive region) to the GND via. . The allowable maximum value L2 (hereinafter, the predetermined interval L2) is an allowable maximum value of the GND via interval at the peripheral edge portion and the inner edge portion of the GND overlapping conductive region. The allowable maximum value L3 (hereinafter, the predetermined interval L3) is the allowable maximum value of the GND via interval at the center of the GND overlapping conductive region.

Here, it is preferable that the predetermined intervals L2 and L3 be smaller than one half (λ / 2) of the wavelength (λ) of the signal current having the largest frequency flowing through the conductive region of the printed circuit board. This is to prevent the return current flowing on the GND conductive region of the printed circuit board and the reflected current from resonating. In practice, it is preferable that the GND or the power supply via is disposed within a distance range of λ / 2 in all directions as viewed from one GND via. On the other hand, in reality, radiation noise can be sufficiently suppressed if they are arranged at intervals of λ / 10 or less. Therefore, L2 = L3 = λ / 10 is sufficient.
Further, in the case where the GND vias are arranged at a small interval between the peripheral edge portion and the inner edge portion of the GND overlapping conductive region as compared with the central portion, even if L2 = λ / 10 and L3 = λ / 4 are set. Good. For example, when the frequency of the fastest signal current on the printed circuit board is 1 GHz, the wavelength of the signal on the printed circuit board is about 15 cm. Therefore, it is preferable to set L2 = 1.5 cm and L3 = 3.75 cm. More precisely, the frequency is f, the dielectric constant is ε _r ,
When the permeability is μ _r and the speed of light is c, the wavelength λ _p of the signal on the printed circuit board is λ _p = c / (f ×
√ (ε _r μ _r )). Therefore, the wavelength calculated by this calculation formula may be used.

Next, an example of a method for setting via automatic arrangement conditions in step S401 will be described with reference to FIG. FIG. 7A is a diagram illustrating an example of an input screen on which via automatic arrangement conditions can be input. The user can input the predetermined intervals L1 to L3 described above into the input fields 71 to 73 of the input screen 70 via the input device 13. The input unit 20 reads the input via automatic arrangement condition and stores it in the main storage device 11. Note that the method for setting the via automatic arrangement condition is not limited to the one that is input on the input screen shown in FIG. For example, a file 74 describing via automatic arrangement conditions as shown in FIG. 7B is stored in the external storage device 14 in advance, and the CPU 10 reads the file and stores the via automatic arrangement conditions in the main storage device 11. It may be set automatically, for example. In this case, the configuration of the file describing the via automatic arrangement conditions is not limited to that shown in FIG. 7B, and any configuration may be used as long as the via automatic arrangement conditions can be read. Further, when the via automatic arrangement condition is made constant regardless of the printed circuit board, the via automatic arrangement condition may be described in the processing program 141.
As described above, the via automatic arrangement condition can be calculated by the wavelength λ of the signal current. Therefore, a method in which the user inputs the frequency of the signal current on the input screen, calculates the wavelength λ based on the frequency, and calculates L2 and L3, for example, L2 = λ / 10 and L3 = λ / 4. It is done.

Returning to the flowchart shown in FIG. 4, step S402 and subsequent steps will be described. The operation processing from step S402 to step S406 is processing performed by the graphic calculation unit 22 based on the layout information 142 stored in the main storage device 11.
In step S <b> 402, the graphic calculation unit 22 extracts the GND wiring name from the layout information 142.
Next, in step S403, the graphic computation unit 22 selects one GND wiring name to be verified from the plurality of extracted GND wiring names.
Next, in step S404, the graphic calculation unit 22 specifies the GND conductive region of each layer related to the selected GND wiring name. This process corresponds to an example of a ground conductive region specifying step.
Next, in step S <b> 405, the graphic calculation unit 22 extracts a region where the identified GND conductive regions of each layer overlap in a two-dimensional manner as a GND overlapping conductive region A. This process corresponds to an example of an overlapping conductive region extraction step.
Next, in step S406, the graphic calculation unit 22 determines whether or not there is a GND wiring name from which a GND overlapping conductive region has not yet been extracted. If there is a GND wiring name from which the GND overlapping conductive area is not extracted, the process returns to step S403. If not, the process proceeds to step S407.

The following operation processing from step S407 to step S419 is processing performed by the via automatic arrangement unit 23 based on the layout information 142 stored in the main storage device 11.
In step S <b> 407, when the GND overlapping conductive area A is extracted with all GND wiring names, the via automatic arrangement unit 23 acquires position information and shape information of the GND overlapping conductive area A from the layout information 142.
Next, in step S408, the via automatic arrangement unit 23 has one via (hereinafter referred to as GND) having the same potential as GND in the GND overlapping conductive region A within a predetermined interval L1 from each component point forming the GND overlapping conductive region A. (GND via) is arranged.
Next, in step S409, the via automatic arrangement unit 23 is a distance between the GND vias adjacent to each other along a line (hereinafter referred to as a configuration line) that forms the periphery of the GND overlapping conductive region A among the vias arranged in step S408. D1 is calculated. The via automatic arrangement unit 23 calculates a value N1 obtained by adding 1 to the integer part of the quotient obtained by dividing D1 by the predetermined interval L2. Further, the via automatic arrangement unit 23 calculates a value C1 (= D1 / N1) obtained by dividing the distance D1 between the GND vias by N1, and the adjacent GND vias along the GND overlapping conductive region A of the via arranged in step S408. The space is divided into a distance C1 within a predetermined interval.
Next, in step S410, the via automatic arrangement unit 23 arranges a GND via at each division position divided in step S409. As described above, in steps S408 to S410, the via automatic arrangement unit 23 arranges the GND vias at a plurality of predetermined positions. This process corresponds to an example of the predetermined interlayer connecting member arranging step.

Next, from step A shown in FIG. 4 to step A shown in FIG. 5, in step S411, the via automatic arrangement unit 23 determines from the GND vias already arranged in the GND overlapping conductive region A from the layout information 142. Select one. This process corresponds to an example of an interlayer connection member selection step.
In step S412, the via automatic arrangement unit 23 is half the allowable maximum value L3 (L3 / L) of the GND via interval at the central portion of the GND overlapping conductive region in the positive and negative directions in the x direction and the y direction from the selected GND via. 2) Calculate 4 points that have been moved (separated). This process corresponds to an example of a position coordinate calculation step. Hereinafter, the point moved (separated) as described above is referred to as a slide position.
In step S413, the via automatic arrangement unit 23 selects one point P1 from the slide position calculated in step S412.
In step S414, the via automatic arrangement unit 23 determines whether or not a GND via exists within a range of a distance (L3 / 2) half the predetermined interval L3 from the slide position P1 selected in step S413. If a GND via exists, the process proceeds to step S417. If there is no GND via, the process proceeds to step S415.

In step S415, the via automatic arrangement unit 23 determines whether or not the point P1 is in the GND overlapping conductive region A. If the point P1 is in the GND overlapping conductive area A, the process proceeds to step S416. If the point P1 is not in the GND overlapping conductive region A, the process proceeds to step S417.
In step S416, the via automatic arrangement unit 23 arranges the GND via at the point P1. This process corresponds to an example of the other interlayer connecting member arranging step.
Next, in step S417, the via automatic arrangement unit 23 determines whether or not there is a slide position (slide position other than the point P1) that has not been determined in step S414 among the four points calculated in step S412. . If there is a slide position for which the process of step S414 is not performed, the process returns to step S413. If there is no slide position for which the process of step S414 has not been performed, the process proceeds to step S418.
In step S418, the via automatic arrangement unit 23 determines whether there is another GND via in the GND overlapping conductive region A that has not been processed in step S412. Here, the GND via disposed in step S415 is also a target of the GND via for determining whether or not the process of step S412 is performed. If there is a GND via that has not been processed in step S412, the process returns to step S411. If there is no GND via for which the process of step S412 has not been performed, the process program 141 is terminated in step S419.

Here, in the present embodiment, in the processing from step S402 to step S406, the GND overlapping conductive region is extracted from the GND conductive region having each GND wiring name. On the other hand, by providing the GND conductive area having each GND wiring name shown here with the attribute information of each GND other than the GND wiring name, the processing for each GND wiring name is the same as the processing from step S402 to step S406. A GND overlapping conductive region can be extracted.
It is also possible to have GND attribute information in all the GND conductive regions and extract the GND overlapping conductive regions for all the GND conductive regions.

  Here, FIG. 8 is an example of a flowchart showing an operation process similar to that of the present embodiment when the GND attribute information is given to all the GND conductive regions. In the flowchart shown in FIG. 8, in step S5804, the graphic calculation unit 22 extracts the conductive regions of each layer having attribute information of each GND, and two-dimensionally overlaps the same region of attribute information in step S405. Extract regions. Here, even when there are a plurality of GND attribute information, it is possible to extract a two-dimensionally overlapping area of each layer regardless of the difference in the GND attribute information. Note that step A shown in FIG. 8 follows step A shown in FIG.

Next, with reference to the schematic diagram of the printed board shown in FIG. 6 described above, the processing operation of the flowchart shown in FIGS. 4 and 5 will be specifically described from step S404 onward.
In step S404, the graphic calculation unit 22 selects the conductive areas having the GND wiring names selected in step S403 from the conductive areas of the respective layers shown in FIGS. Identify. FIG. 9 is a schematic plan view showing the GND conductive region identified in step S404. The printed circuit boards shown in FIGS. 9A to 9D correspond to the printed circuit boards shown in FIGS. 6A to 6D, respectively.
In step S405, the graphic calculation unit 22 projects the GND conductive regions 603, 613, 623, and 633 of each layer shown in FIGS. 9A to 9D, and the GND conductive regions overlap two-dimensionally in all layers. A region (hereinafter referred to as a GND overlapping conductive region) is extracted. FIG. 10 is a diagram showing the GND overlapping conductive region extracted in step S405. That is, the gray portion regions 80, 81, 82, 83, and 84 shown in FIG. 10 are GND overlapping conductive regions.

Hereinafter, in order to facilitate the description of the process of automatically arranging the GND vias, the process of automatically arranging the GND vias by focusing on the GND overlapping conductive area 81 in the GND overlapping conductive areas shown in FIG. 10 will be described.
In step S407, the via automatic arrangement unit 23 acquires position information and shape information of the GND overlapping conductive region 81. Specifically, first, the via automatic arrangement unit 23 acquires the coordinates and order of the configuration points 900, 901, 902, 903, 904, and 905 shown in FIG. Next, the via automatic arrangement unit 23 calculates the coordinates of the start point and the end point of the configuration lines 910, 911, 912, 913, 914, and 915 shown in FIG. 11 constituting the GND overlapping conductive region 81 from the coordinates and order of the configuration points. To do. Hereinafter, a process of automatically arranging GND vias within a predetermined interval at the peripheral edge executed in steps S408 to S410 based on position information and shape information of the GND overlapping conductive region 81 will be described.

In step S <b> 408, the via automatic arrangement unit 23 determines the GND vias 930, 931, 932, and 933 as shown in FIG. , 934, 935 are arranged. Here, a calculation method of the arrangement position of the GND via arranged in step S408 will be described. Here, description will be given focusing on the GND via 930 among the GND vias.
First, the via automatic arrangement unit 23 includes the angle θ _{1 of the} angle 920 and the angle θ of the angle 921 as viewed from the component parallel to the positive direction of the x-axis of the configuration point 900 of the configuration lines 915 and 910 constituting the GND overlapping conductive region 81. ₂ is calculated. Next, the via automatic arrangement unit 23 calculates an angle θ ₃ (= (θ ₁ + θ ₂ ) / 2) of a corner 922 between the corner 920 and the corner 921. Further, the via automatic arrangement unit 23 calculates a position in the direction of the angle 922 when viewed from the component point 900, that is, on the dotted line 923 and at a predetermined distance L1 from the component point 900, and arranges the GND via 930. To do. By this method, the GND via does not become inside the GND overlapping conductive region, and the distance from the periphery of the GND overlapping conductive region to the GND via does not become larger than the predetermined interval L1.

As another method, the via automatic arrangement unit 23 calculates a plurality of positions that are separated by a predetermined interval L1 in the direction of a predetermined plurality of angles from the component point 900, and enters the GND overlapping conductive region 81 from among them. It may be a method of selecting a position that is included. Furthermore, after calculating the angle θ ₁ , the via automatic arrangement unit 23 rotates clockwise by a predetermined angle from the configuration line 915, and for the first time GND
A method of calculating a position on the line facing into the overlapping conductive region 81 and a predetermined distance L1 from the constituent point 900 may be used. Note that the method for calculating the position where the GND via is arranged as described here calculates the position separated by the distance L1 from the configuration point 900, but the via automatic arrangement unit 23 is shorter than L1, such as L1 / 2 and L1 / 3. A value may be adopted.

In step S <b> 408, the via automatic arrangement unit 23 performs the same process on the other configuration points 901, 902, 903, 904, and 905 to arrange the GND vias 931, 932, 933, 934, and 935.
In step S409, the via automatic arrangement unit 23 divides the GND vias 931, 932, 933, 934, and 935 arranged in step S408 by a distance equal to or smaller than a predetermined interval L2, and as shown in FIG. 1000 is arranged. In FIG. 12, only some of the arranged GND vias 1000 are marked for easy understanding of the drawing. Here, an arrangement method for arranging GND vias in steps S408 and S409 will be described. Here, a description will be given focusing on the gap between the GND via 930 and the GND via 931.
First, the via automatic arrangement unit 23 calculates a linear distance D1 between the GND via 930 and the GND via 931. Next, the via automatic arrangement unit 23 obtains a quotient (D1 / L2) obtained by dividing D1 by a predetermined interval L2, and sets N1 to a value obtained by adding 1 to the integer part. Finally, the via automatic arrangement unit 23 calculates a quotient C1 (= D1 / N1) obtained by dividing D1 by N1. Next, the via automatic arrangement unit 23 arranges the GND via 1000 at a position for each distance C1 from the GND via 930 toward the GND via 931. Thus, the interval between the GND vias 1000 is always smaller than L2. Further, since the GND vias 930 and 931 are present within the predetermined interval L1 from the peripheral edge of the GND overlapping conductive region 81, the GND via 1000 is also disposed within the predetermined interval L1 from the peripheral edge of the GND overlapping conductive region 81. .

Here, the description has focused on the GND overlapping conductive region 81 that does not have an inner edge portion. However, since position information and shape information can be obtained even when the inner edge portion is provided, a method of arranging GND vias at the peripheral edge portion. In the same manner as described above, a GND via can also be arranged at the inner edge.
In the above description, the position of the GND via that is initially arranged in the GND overlapping conductive region is described as the vicinity of the constituent point of the GND overlapping conductive region. However, for example, the midpoint of the configuration line of the GND overlapping conductive region may be arranged at a position moved vertically to the configuration line by a half value L1 (L1 / 2) of a predetermined interval to the inside of the GND overlapping conductive region. .
Furthermore, it is not always necessary to dispose the GND via in the vicinity of the configuration point. For example, each point on the configuration lines 915 and 911 and within the distance L1 from the configuration line 910 is calculated, and the two points are divided into intervals smaller than L2 as described above, and GND vias are arranged at the divided points. May be.

Next, the processing operation from step S411 to step S417 for automatically arranging the GND vias within the predetermined interval L3 in the central portion of the GND overlapping conductive region 81 will be specifically described.
In step S411, the via automatic arrangement unit 23 selects one of the plurality of GND vias already arranged in the GND overlapping conductive region 81. Here, for example, the via automatic arrangement unit 23 selects the GND via 1100 shown in FIG.
In step S412, the via automatic arrangement unit 23 calculates a plurality of slide positions moved from the GND via 1100 by a predetermined distance in a predetermined direction. Here, a method for calculating the slide position will be described. First, the via automatic arrangement unit 23 sets a position moved in the positive and negative directions in the x-axis direction and the y-axis direction by a half distance (L3 / 2) of a predetermined interval L3 as a slide position. Specifically, as shown in FIG. 13, the positions moved in the positive direction in the x-axis direction, the negative direction in the x-axis direction, the positive direction in the y-axis direction, and the negative direction in the y-axis direction are slide positions 1101 and 1102, respectively. 1103 and 1104. As another method, the via automatic arrangement unit 23 performs L3 in a direction rotated clockwise by, for example, an angle of 30 ° from a half line drawn from the GND via 1100 such as the positive direction of the x axis or the positive direction of the y axis. A position moved by a value smaller than L3, such as / 2 or L3 / 3, may be set as the slide position.

In step S413, the via automatic arrangement unit 23 selects one of the slide positions 1101, 1102, 1103, and 1104. For example, when the slide position 1101 is selected, in step S414, the via automatic arrangement unit 23 is within a range of a distance (L3 / 2) half the predetermined interval L3 from the slide position 1101, that is, within a circle 1111 shown in FIG. It is determined that there is no other GND via.
Next, in step S415, the via automatic arrangement unit 23 determines that the slide position 1101 is within the GND overlapping conductive region 81.
Therefore, in step S416, the via automatic arrangement unit 23 arranges the GND via 1101 at the slide position 1101.
Next, in step S417, the via automatic arrangement unit 23 does not determine whether or not there is another GND via within a predetermined range for the remaining slide positions 1102, 1103, and 1104. Return to.

  If the via automatic arrangement unit 23 selects the slide position 1102 in step S413, another GND via is located in the range of the distance L3 / 2 from the slide position 1102 in step S414, that is, in the circle 1112 shown in FIG. Judge that it does not exist. Next, in step S415, since the via automatic arrangement unit 23 determines that the slide position 1102 is outside the GND overlapping conductive region 81, the process proceeds to step S417. In step S417, the via automatic arrangement unit 23 does not determine whether or not there is another GND via in the predetermined range for the remaining slide positions 1103 and 1104, and thus the process returns to step S413.

If the via automatic arrangement unit 23 selects the slide position 1103 in step S413, the GND via 1123 exists in the range of the distance L3 / 2 from the slide position 1103, that is, in the circle 1113 shown in FIG. 13, in step S414. Judge that. Accordingly, the process proceeds to step S417.
In step S417, the via automatic arrangement unit 23 does not determine whether or not there is another GND via in the predetermined range for the remaining slide position 1104. Therefore, the process returns to step S413.

  In step S413, the via automatic arrangement unit 23 selects the slide position 1104. In step S414, the via automatic arrangement unit 23 determines that the GND via 1124 exists in the circle 1114, similarly to the case where the position 1103 is determined. Therefore, the process proceeds to step S417. In step S417, since there is no slide position for the via automatic arrangement unit 23 to determine, the process proceeds to step S418.

  In step S418, the via automatic arrangement unit 23 determines that there is a GND via not subjected to the process of step S412 and returns the process to step S411. In step S411, the via automatic arrangement unit 23 selects one from a plurality of GND vias that have not been processed in step S412. Thereafter, by repeating the processing from step S411 to step S418, the GND via is automatically arranged in the central portion of the GND overlapping conductive region 81.

  Next, a case where the via automatic arrangement unit 23 selects the GND via 1200 shown in FIG. 14 from a plurality of GND vias in step S411 will be described. In this case, in step S412, the via automatic arrangement unit 23 calculates slide positions 1201, 1202, 1203, and 1204 as shown in FIG. For the slide positions 1201, 1202, and 1203, in step S414, the via automatic arrangement unit 23 does not have GND vias within the distance range of L3 / 2 (inside the circles 1211, 1212, and 1213 shown in FIG. 14). Is determined. Further, in step S415, the via automatic arrangement unit 23 determines that it is in the GND overlapping conductive region 81. Therefore, in step S416, the via automatic arrangement unit 23 arranges the GND vias 1201, 1202, and 1203.

On the other hand, regarding the slide position 1204, since the GND via is already arranged at the same position as the slide position 1204, in step S414, the via automatic arrangement unit 23 is within the range of L3 / 2 (in the circle 1214 shown in FIG. 14). It is determined that there is a GND via. Therefore, the via automatic arrangement unit 23 does not arrange the GND via. Hereinafter, similarly, the processing from step S411 to step S418 is repeatedly executed until there is no GND via for which the processing of step S412 is not performed.
In step S418, if the via automatic arrangement unit 23 determines that there is no GND via not subjected to the process of step S412, the program ends in step S419.

FIG. 15 is a diagram showing the arrangement state of the GND vias in the GND overlapping conductive region 81 at the time when the program ends in step S419. As shown in FIG. 15, GND vias are arranged within a predetermined interval at the periphery and the center of the GND overlapping conductive region 81.
FIG. 16 is a diagram showing the arrangement state of the GND vias on the GND overlapping conductive regions 80, 81, 82, 83, 84 at the time when the program is finished in step S419. Here, in the description so far, in order to make the drawing easy to see, the sign of the slide position where the GND via is arranged and the arranged GND via are made the same.

In the above description, in the arrangement of the GND vias in the central portion of the GND overlapping conductive region, in order to reliably arrange the GND vias within the predetermined interval L3, the moving distance of step S412 is set to L3 / 2, and the slide position of step S414 The search range of GND vias around is set to L3 / 2. However, when considering the cost, there are cases where it is desired to arrange as few GND vias as possible. In such a case, for example, the moving distance in step S412 may be set to L3, and the search range of other GND vias in step S414 may be set to a predetermined ratio distance to L3 that can be set by the user. By doing so, although the GND vias are not necessarily arranged within the predetermined interval L3, the GND vias can be arranged in a relatively small amount, and therefore, the GND vias can be arranged in consideration of the cost.
In the above description, in order to automatically arrange all the GND vias in the GND overlapping conductive region, an example in which one via is disposed near each corner of the GND overlapping conductive region in step S408 has been described. However, it is possible for the user to perform the same processing as in step S408. That is, by using the display device 12 to display an instruction screen in which one or a plurality of vias are arranged near the GND overlapping conductive region and each corner, the GND via is displayed near the corner of the GND overlapping conductive region to the user. Can be arranged.

  In the above description, the position information and the shape information of the GND overlapping conductive region are mainly described by coordinates. However, in the case where the region is represented by an equation / inequality on the plane or space, such as an inequality on the xy plane, for example. Even if it exists, automatic arrangement | positioning of a GND via | veer can be performed. For example, in the case of an inequality on the xy plane, the position coordinates of each constituent point of the GND overlapping conductive region can be obtained by the coordinates of the intersection of the equality in which the inequality is represented by an equal sign. In addition, the determination of whether a specific point is inside or outside the GND overlapping conductive region can be made by simply applying coordinates to an inequality. Therefore, it is possible to perform the same processing as in the above-described embodiment.

As described above, in the present embodiment, as shown in FIG. 16, the GND vias are provided at a distance within the predetermined interval L2 at a distance within the predetermined interval L1 from the peripheral edge of the GND overlapping conductive region and the peripheral edge of the inner edge portion of the printed circuit board. Can be placed automatically. In addition, the GND vias can be automatically arranged at intervals within the predetermined interval (L3) in the center of the GND overlapping conductive region.
In addition, when the GND vias are actually arranged, the predetermined intervals L1, L2, and L3 described above may be varied within a single substrate by a value within L1, a value within L2, and a value within L3, depending on the situation. Can do. However, by setting the values of L1, L2, and L3 so as not to fluctuate, that is, to be arranged at equal intervals, the calculation of the fluctuations of the values of L1, L2, and L3 depending on the situation becomes unnecessary, and the program operation becomes faster. There is.

  Further, in the present embodiment, the description has been given of the case where GND vias are automatically arranged through all conductive layers of a printed circuit board. However, a part (for example, two layers) of conductive layers constituting the printed circuit board is interposed. It is also possible to automatically arrange GND vias. In that case, it is only necessary to extract the overlapping conductive region only for the conductive layer through the GND via and arrange the GND via in the overlapping conductive region as in the above-described embodiment. At that time, the GND via can be efficiently arranged by handling the GND via via a plurality of layers including a part of the corresponding conductive layer as the already arranged GND via.

(Second Embodiment)
In the first embodiment, as shown in step S408 of the flowchart shown in FIG. 4, the description has been given of the case where the GND via serving as a reference for automatically arranging the GND via is arranged in the vicinity of each constituent point of the GND overlapping conductive region. . On the other hand, in order to shorten the return current of the high-speed signal, it is preferable to arrange a GND via in the vicinity of the via of the high-speed signal wiring. In the present embodiment, a case will be described in which a GND via serving as a reference for automatically arranging a GND via is arranged in the vicinity of a via of a high-speed signal line.

  The processing operation performed by the printed circuit board design support apparatus according to the present embodiment based on the printed circuit board design support program (processing program) is the same as the flowchart shown in FIG. FIG. 17 is a flowchart showing in detail the operation of some steps of the flowchart shown in FIG. Here, step A shown in FIG. 17 follows step A shown in FIG. The processing operation of the printed circuit board design support apparatus according to this embodiment will be described below with reference to the flowcharts shown in FIGS. 17 and 5 and the schematic diagrams shown in FIGS.

In the flowchart shown in FIG. 17, the processing from step S400 to step S407 and the processing from step S408 to step S410 perform the same processing as the same step number shown in FIG. . In the present embodiment, processing from step S1600 to step S1602 is added between step S407 and step S408 in the flowchart shown in FIG.
In step S1600, the graphic computation unit 22 selects a high-speed wiring via. This process corresponds to an example of a high-speed signal interlayer connecting member selection step. Here, an example of a high-speed wiring via selection method will be described. For example, the input unit 20 displays an input screen on the display device 12 in which high-speed wiring attributes can be set for each wiring. The user inputs the high-speed wiring attribute in the input field of the input screen via the input device 13, whereby the input unit 20 reads the input information and stores it in the main storage device 11. The graphic computation unit 22 selects a via for a wiring having a high-speed wiring attribute based on the stored information. The method of inputting the high-speed wiring attribute may be a method of inputting information indicating high-speed wiring for each wiring. Further, by using the high-speed wiring list, the graphic operation unit 22 selects a via of the wiring input to the list by inputting a wiring name into the list or selecting a wiring to be added to the list. It may be.

  Further, the method for selecting a via for high-speed wiring may be as follows. That is, when a circuit designer inputs a high-speed wiring attribute for each wiring in advance on the circuit diagram design system, circuit diagram information having attribute information for each wiring is stored in the main storage device 11 or the external storage device 14. Is done. Therefore, the input unit 20 reads circuit diagram information from the main storage device 11 or the external storage device 14 to determine whether each wiring has a high-speed wiring attribute, and selects a via having a high-speed wiring attribute. can do. Here, as a method of inputting the high-speed wiring attribute to the wiring, the same method as described above may be performed on the printed circuit board design system. In addition, the circuit designer inputs the frequency of the current flowing in each wiring on the circuit diagram design system, compares the frequency with a predetermined threshold value, and a wiring larger than the predetermined threshold has a high-speed wiring attribute. The wiring may be determined.

In step S1601, the graphic calculation unit 22 calculates a point (shortest point) at the shortest interval from the via of the high-speed wiring selected in step S1600 on each GND overlapping conductive region extracted in step S405.
In step S1602, the via automatic arrangement unit 23 arranges a GND via in the vicinity of the shortest point. This process corresponds to an example of the high-speed signal vicinity interlayer connection member arranging step. Here, when the shortest point is on the configuration line of the GND overlapping conductive region, the via automatic placement unit 23 is on the extension of the line segment connecting the shortest point to the via of the high-speed wiring and has a distance of a predetermined interval L1 from the shortest point. A GND via is disposed within the range. When the shortest point is on the constituent point of the GND overlapping conductive region, the via automatic arrangement unit 23 arranges the GND via by the same processing as Step S408 of the first embodiment.

  In the above description, the case where the graphic calculation unit 22 calculates the shortest point from the via of each high-speed wiring to each GND overlapping conductive region in step S1601 has been described. However, when the interval from the via of the high-speed wiring to the shortest point is larger than the predetermined value L3, the process of step S1602 need not be performed. For example, a predetermined interval L2 is used as the predetermined value L3. Further, a process of notifying the user of a high-speed wiring via in which the shortest point at which the distance from the via of the high-speed wiring to the shortest point is equal to or less than the predetermined value L3 cannot be found or making it visible may be added.

  Next, the processing operation of the flowchart shown in FIG. 17 will be described with reference to the schematic diagram of the printed board shown in FIG. FIG. 18 is a schematic diagram of a printed circuit board before automatic placement of GND vias. Of the component placement positions and wiring conditions shown in FIG. 18, those similar to those in FIG. 6 are assigned the same reference numerals and explanations thereof are omitted. Here, the signal wirings 15210 and 15211 and the signal wiring vias 15220 and 15221 shown in FIG. 18C have a high-speed wiring attribute. Further, the signal wirings 15310, 15311, 15312, and 15313 and the signal wiring vias 15320, 15321, 15322, and 15323 shown in FIG. 18D have a high-speed wiring attribute.

  Before the process of step S406 in the flowchart shown in FIG. 17, the graphic calculation unit 22 projects the GND conductive regions of each layer shown in FIGS. 18A to 18D, and the GND conductive regions are two-dimensionally displayed in all layers. GND overlapping conductive regions overlapping each other are extracted. FIG. 19 is a diagram showing the extracted GND conductive region. That is, the gray portion regions 80, 82, 83, 1700, and 1701 shown in FIG. 19 are GND overlapping conductive regions.

Hereinafter, in order to facilitate the description of the process of automatically arranging the GND vias, the process of automatically arranging the GND vias by focusing on the GND overlapping conductive area 1700 in the GND overlapping conductive areas shown in FIG. 19 will be described. Needless to say, GND vias are also automatically arranged in the GND overlapping conductive regions 80, 82, 83, and 1701 in the same manner.
In step S407, the via automatic arrangement unit 23 acquires position information and shape information of the GND overlapping conductive region 1700.
Next, in step S1600, the graphic calculation unit 22 selects vias 1800, 1801, 1802, and 1803 having high-speed wiring attributes (hereinafter, high-speed wiring vias) as shown in FIG. Here, when the high-speed wiring vias correspond to the signal wiring vias shown in FIG. 18, the high-speed wiring via 1800 matches the signal wiring vias 15221 and 15322. The high-speed wiring via 1802 matches the signal wiring vias 15221 and 15323. Further, the high-speed wiring via 1801 coincides with the signal wiring vias 15220 and 15320. Further, the high-speed wiring via 1803 coincides with the signal wiring vias 15220 and 15321.

  Next, in step S1601, the graphic calculation unit 22 calculates shortest points 1810, 1811, and 1812 as shown in FIG. 20 for the GND overlapping conductive regions 1700 from the high-speed wiring vias 1800, 1801, 1802, and 1803, respectively. . Specifically, a perpendicular line from the outside of the GND overlapping conductive region is calculated for each constituent line of the GND overlapping conductive region from each high-speed wiring via. Next, the graphic calculation unit 22 compares the distance from the high-speed wiring via to the intersection of each perpendicular and the constituent line with the distance from the high-speed wiring via to each constituent point, and the intersection or constituent point that makes the smallest distance Is the shortest point. For example, in the case of the high-speed wiring via 1800, the shortest distance from the high-speed wiring via 1800 to the constituent line 1840 of the GND overlapping conductive region 1700 is calculated by the perpendicular line 1830 drawn from the high-speed wiring via 1800 to the constituent line 1840. The That is, the shortest distance is the distance from the high-speed wiring via 1800 to the intersection 1810 between the perpendicular 1830 and the constituent line 1840. A configuration point closest to the high-speed wiring via 1800 is a configuration point 1831. Here, when comparing the distance from the high-speed wiring via 1800 to the intersection 1810 and the distance from the high-speed wiring via 1800 to the composing point 1831, the figure calculation unit 22 has a smaller distance from the high-speed wiring via 1800 to the intersection 1810. Therefore, the intersection 1810 (shortest point 1810) is calculated as the shortest point. In the above description, only the distance from the high-speed wiring via 1800 to the intersection 1810 is compared with the distance from the high-speed wiring via 1800 to the constituent point 1831. In practice, however, perpendicular lines are drawn from the high-speed wiring via to all the constituent lines. Determine if you can. In addition, distances are calculated for all the configuration points from the high-speed wiring via.

  Similarly, the graphic calculation unit 22 calculates the shortest point 1811 as the shortest point for the high-speed wiring via 1801. In the case of the high-speed wiring vias 1802 and 1803, the shortest point is the same. Therefore, the graphic calculation unit 22 calculates the shortest point 1812 as the shortest point.

In step S1602, the via automatic arrangement unit 23 arranges a GND via in the vicinity of the shortest point. Here, the processing differs depending on whether the shortest point is on the configuration line of the GND overlapping conductive region 1700 or the configuration point. First, when the shortest point is on the configuration line like the shortest point 1810, the via automatic arrangement unit 23 is an extension of the perpendicular 1830 and has a value (L1 / 2) that is a half of the predetermined interval L1 from the shortest point 1810. A GND via 1820 is disposed at the position of the distance. Here, the GND via is disposed at a position of a distance of L1 / 2 from the shortest point, but it may actually be within a predetermined distance L1. Similarly, the via automatic arrangement unit 23 arranges the GND via 1821 with respect to the shortest point 1811.
Next, when the shortest point is a constituent point like the shortest point 1812, the via automatic arrangement unit 23 arranges the GND via 1822 by the same method as step S408 of the flowchart shown in FIG. 4 of the first embodiment.

  In the case where the GND via is already arranged within the distance of the predetermined distance L2 from the GND via 1820, 1821 or 1822 and within the distance of the predetermined distance L1 from the configuration line of the GND overlapping conductive region 1700. May add a process of eliminating the GND via. In addition, here, the search range of the GND via is limited to the range of the predetermined interval L2, but any value may be used as long as the value is within the range of L2 or less. Furthermore, the GND via search range may be a range in which a conductive region formed around a nearby GND via partially overlaps a conductive region formed around the GND via 1820.

Next, the processing after step S408 is the same as the processing after step S408 shown in the flowchart shown in FIG. 4 of the first embodiment and the processing shown in the flowchart shown in FIG.
In step S <b> 408, the via automatic arrangement unit 23 arranges GND vias in the vicinity of each corner of the GND overlapping conductive region 1700. Here, with reference to FIG. 21, the GND via disposed in the GND overlapping conductive region after the process of step S408 will be described. As shown in FIG. 21, GND vias 1900, 1901, 1902, 1903, 1904, and 1905 are arranged in the GND overlapping conductive region 1700. For the configuration point 1812, since the GND via 1822 has already been arranged in step S1602, it is not necessary to perform the GND via arrangement processing in step S408. Here, in step S408, if the GND via to be arranged is very close to the GND via in the vicinity of the high-speed wiring arranged in step S1601, the via automatic arrangement unit 23 does not arrange the GND via in step S408. May be. Note that the case of very close proximity is the same as the case where a GND via near the high-speed wiring already exists in the search range equivalent to the search range of the GND via to be excluded in step S1601.
Next, the processing after step S409 is performed in the same manner as the processing described in the first embodiment, thereby arranging the GND vias within the predetermined interval in the GND overlapping conductive region 1700 as shown in FIG.
In the above description, in order to automatically arrange all the GND vias, the example in which the GND vias are automatically arranged in the vicinity of the vias of the high-speed signal line in steps S1600 to S1602 has been described. However, it is also possible for the user to perform processing equivalent to these series of processing. That is, the display device 12 is used to display an instruction screen in which one or a plurality of vias are arranged in the vicinity of the GND overlapping conductive region, the high-speed signal line vias, or the entire high-speed signal line vias. A GND via can be disposed in the GND overlapping conductive region and in the vicinity of the via of each school rule signal line.

  In the above description, the position information and the shape information of the GND overlapping conductive region are mainly described by coordinates. However, in the case where the region is represented by an equation / inequality on the plane or space, such as an inequality on the xy plane, for example. Even if it exists, automatic arrangement | positioning of a GND via | veer can be performed. For example, in the case of an inequality on the xy plane, the position coordinates of each constituent point of the GND overlapping conductive region can be obtained by the coordinates of the intersection of the equality in which the inequality is represented by an equal sign. In addition, the determination of whether the inside or outside of the GND overlapping conductive region for a specific point can be made by simply applying the coordinates to the inequality. Therefore, it is possible to perform the same processing as in the above-described embodiment.

  As described above, in this embodiment, in addition to the effects of the first embodiment, the GND vias can be automatically arranged so that the return current path of the high-speed wiring becomes shorter. Moreover, this embodiment is a partial modification of the first embodiment, and has an application range equivalent to the application range described in the first embodiment.

(Third embodiment)
In the first embodiment, the case where the GND overlapping conductive region is divided into the peripheral portion, the inner edge portion, and the central portion and the GND vias are arranged step by step has been described. In the present embodiment, a case will be described in which GND vias are automatically arranged without dividing the entire GND overlapping conductive region.
The processing operation performed by the printed circuit board design support apparatus according to the embodiment based on the printed circuit board design support program (processing program) is the same as the flowchart in FIG. 3 in which step S103 is omitted. In the printed circuit board design support apparatus described in the first embodiment, since the GND vias are arranged at the peripheral edge and the inner edge of the GND overlapping conductive region, the effect of the radiation noise countermeasure is greater.

  The processing operation of the printed circuit board design support apparatus according to this embodiment will be described below with reference to the flowcharts shown in FIGS. 23 and 24 and the schematic diagrams shown in FIGS. For ease of explanation, FIGS. 25 to 27 show only the GND overlapping conductive region 81 shown in FIG. In practice, however, it goes without saying that GND vias are similarly arranged in the GND overlapping conductive regions 80, 82, 83, 84.

  In the flowcharts shown in FIGS. 23 and 24, the operation processing from step S400 to step S407, step S408, and step S411 to step S419 is the same as the same step number shown in FIGS. Description is omitted. However, the via automatic addition condition of the present embodiment is the allowable maximum value L5 of the GND via interval (hereinafter, a predetermined interval L5). In the present embodiment, unlike the first embodiment, Step S2200 is added between Step S407 and Step S408.

  Here, in step S2200, whether or not a GND via already exists in each GND overlapping conductive region A extracted in step S405 while the via automatic arrangement unit 23 refers to the layout information 142 in the main storage device 11. Determine. If a GND via exists in the GND overlapping conductive area A, the process proceeds to step S411. If there is no GND via, the process proceeds to step S408. If a GND via already exists in the GND overlapping conductive region A by this step S2200, the GND via is automatically arranged based on the existing GND via, and therefore the process of step S408 is not necessary. However, as in the first embodiment, step S2200 may be omitted, and a GND via serving as a reference may be disposed in step S408 regardless of whether or not a GND via already exists in the GND overlapping conductive region A. Good.

  Further, in this embodiment, unlike the first embodiment, steps S409 and S410 are omitted. Steps S409 and S410 of the first embodiment are steps in which the via automatic arrangement unit 23 automatically arranges the GND vias within a predetermined interval in the peripheral edge portion and the inner edge portion of the GND overlapping conductive region A. Therefore, this processing is unnecessary in this embodiment. As in the second embodiment, in order to preferentially arrange the GND via in the vicinity of the high-speed wiring via, the step of the flowchart shown in FIG. 17 is performed between step S407 and step B of the flowchart shown in FIG. What is necessary is just to add step S1602 from S1600.

Next, description will be made with reference to the flowcharts shown in FIGS. 23 and 24 and the schematic diagrams shown in FIGS. First, the case where there is no existing GND via in the GND overlapping conductive region, that is, the case where there is no existing via in the GND overlapping conductive region in step S2200, and the case where the process proceeds to step S408 will be described.
In step S408, the via automatic arrangement unit 23 is connected to the GND vias 930, 931, 932, near the component points 900, 901, 902, 904, 905, which are the corners of the GND overlapping conductive region 81, as shown in FIG. 933, 934, and 935 are arranged. Here, reference GND vias are arranged in the vicinity of each corner of the GND overlapping conductive region 81. However, for example, only the vicinity of the component point 900 or a plurality of corners that are not all of the component points 900, 901, etc. A GND via may be disposed in the gate. Further, the reference GND via is not necessarily near the corner. For example, a reference GND via is formed at a point where the midpoint of the configuration line 910 shown in FIG. 25 is moved by a value within a predetermined interval L5 in a direction perpendicular to the configuration line 910 and toward the inside of the GND overlapping conductive region 81. You may arrange. In addition, a reference GND via can be arranged at an arbitrary point within the GND overlapping conductive region 81.

Next, in step S411, the via automatic arrangement unit 23 selects one of the GND vias arranged in step S408. Here, the via automatic arrangement unit 23 selects, for example, the GND via 930 shown in FIG.
In step S412, the via automatic arrangement unit 23 calculates a slide position moved from the GND via 930 in the positive and negative directions in the x-axis direction and the y-axis direction by a distance (L5 / 2) that is a half of the predetermined interval L5. Specifically, the via automatic arrangement unit 23 has the slide positions 2301 and 2302 as positions moved in the positive direction in the x-axis direction, the negative direction in the x-axis direction, the positive direction in the y-axis direction, and the negative direction in the y-axis direction, respectively. 2303 and 2304 are calculated.

In step S413, the via automatic arrangement unit 23 selects one of the slide positions 2301, 2302, 2303, and 2304. For example, when the slide position 2301 is selected, in step S414, the via automatic arrangement unit 23 is within a range of a distance (L5 / 2) half the predetermined interval L5 from the slide position 2301, that is, within a circle 2311 shown in FIG. It is determined that there is no other GND via.
Next, in step S415, the via automatic arrangement unit 23 determines that the slide position 2301 is within the GND overlapping conductive region 81.
Therefore, in step S416, the via automatic arrangement unit 23 arranges the GND via 2301 at the slide position 2301.
Next, in step S417, the via automatic arrangement unit 23 does not determine whether there are other GND vias within the predetermined range for the remaining slide positions 2302, 2303, and 2304, so the process of step S413 is performed. Return.

  Next, in step S413, when the via automatic arrangement unit 23 selects the slide position 2302, in step S414, another GND via exists in the range of L5 / 2 from the slide position 2302, that is, in the circle 2312 shown in FIG. Judge that not. Next, in step S415, since the via automatic arrangement unit 23 determines that the slide position 2302 is outside the GND overlapping conductive region 81, the process proceeds to step S417. In step S417, the via automatic arrangement unit 23 does not determine whether or not another GND via exists within a predetermined range for the remaining slide positions 2303 and 2304, and thus the process returns to step S413.

Thereafter, similarly, the via automatic arrangement unit 23 repeatedly executes a series of processes from step S413 to step S417, does not arrange the GND via at the slide position 2303, and arranges the GND via 2304 at the slide position 2304. The process proceeds to step S417.
In step S417, since there is no slide position for the via automatic arrangement unit 23 to determine, the process proceeds to step S418.

  Next, the via automatic arrangement unit 23 does not perform the process of step S412 for the newly added GND vias 2301 and 2304 and the GND vias 931, 932, 933, 934, and 935. Therefore, in step S418, the via automatic arrangement unit 23 determines that there is a GND via not subjected to the process of step S412 and returns the process to step S411. Thereafter, the GND via is automatically arranged in the GND overlapping conductive region 81 by repeatedly executing the processing from step S411 to step S418.

Here, a case where the GND via 2400 is selected in step S411 will be described with reference to FIG.
In step S412, the via automatic arrangement unit 23 calculates slide positions 2401, 2402, 2403, and 2404.
In step S413, the via automatic arrangement unit 23 sequentially selects one of the slide positions. For the slide positions 2401 and 2404, the via automatic arrangement unit 23 determines in step S414 that there is no other GND via within the range of L5 / 2 (in the circles 2411 and 2414, respectively), and in step S415, the GND overlapping conductive region. 81. Therefore, in step S416, the via automatic arrangement unit 23 arranges the GND via 2401 and the GND via 2404.
On the other hand, at the slide positions 2402 and 2403, GND vias already exist at the same positions as the slide positions 2402 and 2403, that is, other GND vias exist within the range of L5 / 2 (inside the circles 2412 and 2413, respectively). . Therefore, in step S414, the via automatic arrangement unit 23 determines that another GND via exists at the slide positions 2402 and 2403. Therefore, the via automatic arrangement unit 23 does not arrange the GND via.

Thereafter, similarly, the via automatic arrangement unit 23 repeatedly executes the processing from step S411 to step S418 until there is no GND via that does not perform the processing of step S412 in step S418. In step S418, if there is no GND via that has not been processed in step S412, the via automatic arrangement unit 23 ends the program in step S419.
FIG. 27 is a diagram showing the arrangement state of the GND vias on the GND overlapping conductive region 81 at the time when the program ends in step S419. Here, in the description so far, in order to make the drawing easy to see, the sign of the slide position where the GND via is arranged and the arranged GND via are made the same.

  In the present embodiment, as in the first embodiment, the user can set the desired GND via arrangement by enabling the user to set the movement distance in step S412 and the search range around the slide position in step S414. The situation can be realized. By doing so, it is possible to arrange the GND vias in consideration of the cost by reducing the number of GND vias arranged rather than arranging the GND vias within a predetermined interval. Further, even if the position information and shape information of the GND overlapping conductive area are expressed by an inequality on the coordinate plane or space, the GND vias can be automatically arranged.

Thus, in this embodiment, as shown in FIG. 27, the GND vias can be automatically arranged within the predetermined interval L5 in the GND overlapping conductive region of the printed circuit board.
In the above description, in order to automatically arrange all the GND vias in the GND overlapping conductive region, an example in which one via is arranged in the GND overlapping conductive region in Step S2200 and Step S408 has been shown. However, it is possible for the user to perform the same processing as in steps S2200 and S408. That is, when it is determined in step S2200 that there is no GND via in the GND overlapping conductive region, the display device 12 is used to arrange the GND overlapping conductive region in which the GND via is not arranged and one or a plurality of vias. Display a simple instruction screen. As a result, the user can arrange the GND vias near each corner of the GND overlapping conductive region.
In addition, when the GND via is actually arranged, the predetermined interval L5 described above may be changed within a range of L5 in one substrate depending on the situation. However, by setting the L5 value not to be changed, that is, to be arranged at equal intervals, there is an advantage that the calculation of the change of the L5 value depending on the situation becomes unnecessary and the operation of the program becomes faster.

  Further, in the present embodiment, the case where the GND vias through all the conductive layers of the printed circuit board are automatically arranged has been described. However, the GND vias through some of the conductive layers constituting the printed circuit board are automatically arranged. It can also be arranged. In that case, it is only necessary to extract the overlapping conductive region only for the conductive layer through the GND via and arrange the GND via in the overlapping conductive region as in the above-described embodiment. At that time, the GND via can be efficiently arranged by handling the GND via via a plurality of layers including a part of the corresponding conductive layer as the already arranged GND via.

(Fourth embodiment)
In the first embodiment, as a calculation method of the arrangement position of the GND via, the position is moved by a predetermined distance in a predetermined direction with reference to the GND via already arranged or newly arranged in the GND overlapping conductive region. The method was explained. In the present embodiment, as a method for calculating the arrangement position of the GND via, an area in which the GND via can be arranged is divided into areas of a predetermined size (hereinafter referred to as blocks), and one point in the divided area is used as the arrangement position. Will be described.

  The processing operation performed by the printed circuit board design support apparatus according to the present embodiment based on the printed circuit board design support program (processing program) is the same as the flowchart shown in FIG. FIG. 28 is a flowchart showing in detail the operation of some steps of the flowchart shown in FIG. Here, Step B shown in FIG. 28 is continued from Step B shown in FIG. Note that the processing up to step B shown in FIG. 23 is the same as in the first and third embodiments, and thus the description thereof is omitted. Further, in the present embodiment, in order to preferentially arrange the GND vias in the vicinity of the high-speed wiring vias as in the second embodiment, it is shown in FIG. 17 between step S407 and step B shown in FIG. Steps S1600 to S1602 may be added.

  The processing operation of the printed circuit board design support apparatus according to the present embodiment will be described below with reference to the flowchart shown in FIG. 28 and the schematic diagrams shown in FIGS. The processing from step S2600 to step S419 shown in FIG. 28 is processing performed by the via automatic arrangement unit 23 based on the layout information 142 stored in the main storage device 11. For ease of explanation, FIGS. 29 to 33 show only the GND overlapping conductive region 81 shown in FIG. In practice, however, it goes without saying that GND vias are similarly arranged in the GND overlapping conductive regions 80, 82, 83, 84. In the present embodiment, as in the first embodiment, a method will be described in which the peripheral edge, the inner edge, and the central portion are divided, and GND vias are automatically arranged step by step. Accordingly, the via automatic arrangement condition in step S401 is the same as the predetermined interval L1, the predetermined interval L2, and the predetermined interval L3 in the first embodiment.

Hereinafter, the flowchart shown in FIG. 28 will be described in detail.
In step S2600, when the via automatic arrangement unit 23 acquires the position information and the shape information of the GND overlapping conductive area A in step S407 shown in FIG. 23, the via automatic arrangement unit 23 selects one constituent line of the GND overlapping conductive area A. The via automatic arrangement unit 23 calculates the length D2 of the selected configuration line, and calculates a value N2 obtained by adding 1 to the integer part of the quotient (D2 / L2) obtained by dividing the calculated length D2 by the predetermined interval L2. . Further, the via automatic arrangement unit 23 calculates a length C2 (= D2 / N2) obtained by dividing D2 by N2.

In step S2601, the via automatic arrangement unit 23 selects the block having the length of the side perpendicular to the configuration line as the predetermined interval L1 and the length of the side in the direction along the configuration line as C2 as the configuration line selected in step S2600. Create along. Here, when the rectangular block having the size cannot be created in the GND overlapping conductive area A, such as in the vicinity of the constituent point of the GND overlapping conductive area A, the via automatic arrangement unit 23 determines the GND overlapping conductive area from the rectangular size. The shape excluding the outer part of A is the shape of the block.
In step S2602, the via automatic arrangement unit 23 selects one (block B1) from the divided blocks after the block division.
In step S2603, the via automatic arrangement unit 23 determines whether or not a GND via is already arranged in the block B1. If the GND via is already arranged in the block B1, the process proceeds to step S2605. If the GND via is not yet arranged, the process proceeds to step S2604.

In step S2604, the via automatic arrangement unit 23 arranges a GND via in the block B1.
Next, in step S2605, the via automatic arrangement unit 23 does not execute the process of step S2603, that is, whether there is a block (a block other than the block B1) in which the presence or absence of the GND via in the block is not determined. Determine. If there is a block for which the process of step S2603 has not been executed, the process returns to step S2602. If there is no block for which the process of step S2603 has not been executed, the process proceeds to step S2606.

In step S2606, the via automatic arrangement unit 23 determines whether there is a configuration line that has not executed the process of step S2601. If there is a configuration line for which the process of step S2601 has not been performed, the process returns to step S2600. If there is no configuration line for which the process of step S2601 has not been performed, the process proceeds to step S2607.
In step S2607, the via automatic arrangement unit 23 acquires position information and shape information of the central part of the GND overlapping conductive region A. The central portion here is a region (hereinafter referred to as a central region B) in which all the blocks divided in step S2601 from the GND overlapping conductive region A are excluded.
In step S2608, the via automatic arrangement unit 23 acquires the position information and shape information of the central area B, and then divides the central area B into square blocks each having a half distance (L3 / 2) of the predetermined distance L3. To do. This process corresponds to an example of a block division step. Here, when a square block having one side of L3 / 2 in the vicinity of the configuration line of the central region B or the configuration point cannot be created in the central region B, the via automatic arrangement unit 23 moves from the square block to the outside of the central region B. The shape excluding this part is the block shape.

In step S2609, the via automatic arrangement unit 23 divides the central area B into blocks, and then arranges GND vias in blocks where GND vias are not yet arranged in each block. This process corresponds to an example of the intra-block interlayer connecting member placement step. The process in step S2609 is the same as the series of processes in steps S2602 to S2605.
In step S419, the via automatic arrangement unit 23 ends the processing program 141 after arranging the GND via in the central region B.
Next, a specific description will be given with reference to the flowchart shown in FIG. 28 and the schematic diagrams shown in FIGS. First, in step S2600, the via automatic arrangement unit 23 selects one of the configuration lines 910, 911, 912, 913, 914, and 915 of the position information and shape information acquired in step S407 shown in FIG. For example, it is assumed that the via automatic arrangement unit 23 selects the configuration line 910.

In step S2601, the via automatic arrangement unit 23 divides the peripheral portion of the GND overlapping conductive region 81 along the configuration line 910 into blocks as shown in FIG. As a block division method in step S2601, the via automatic arrangement unit 23 first calculates the length D2 of the configuration line 910. Next, the via automatic arrangement unit 23 calculates a value N2 obtained by adding 1 to the integer part of the quotient obtained by dividing the length D2 by the predetermined interval L2, and then a value C2 (= D2) obtained by dividing the length D2 by N2. / N2) is calculated. Next, the via automatic arrangement unit 23 sets the one side in the direction perpendicular to the configuration line 910 as the predetermined interval L1, and sets the one side in the direction along the configuration line 910 as the value C2, from block 2700 to block 2711 shown in FIG. Create along the configuration line 910 from the end of 910. In the case of the configuration line 910 shown in FIG. 29, since the corners of the configuration points 900 and 901 are right angles, all can be divided by rectangular blocks. However, in an actual printed circuit board, the corners of the GND overlapping conductive region are not always perpendicular. When the divided rectangular block protrudes from the GND overlapping conductive region, a figure obtained by excluding the external region of the GND overlapping conductive region from the divided rectangle may be applied as the block shape.
Further, when the peripheral edge portion of the GND overlapping conductive region is left with respect to the rectangle divided near the end point of the constituent line 910, a shape obtained by adding the surplus figure to the end block of the constituent line can be applied as the block.

In step S2602, the via automatic arrangement unit 23 selects one from the blocks created in step S2601. For example, it is assumed that the via automatic arrangement unit 23 selects the block 2700.
In step S2603, the via automatic arrangement unit 23 advances the process to step S2604 in order to determine that the GND via is not yet arranged in the block 2700.
In step S2604, the via automatic arrangement unit 23 arranges the GND via 2720. Here, the arrangement position of the GND via in step S2604 is preferably the center of the block 2700. As other positions, any position inside the block 2700 such as the center of gravity of the block 2700 and the position near the boundary with the adjacent block 2701 can be considered.
Next, in step S2605, the via automatic arrangement unit 23 returns to the process of step S2602 in order to determine that there is a block that has not been determined in step S2603 for the blocks 2701 to 2711.

  Thereafter, similarly, the via automatic arrangement unit 23 repeatedly executes the processing from step S2602 to step S2605, thereby sequentially arranging the GND vias 2720 at the peripheral edge along the configuration line 910 as shown in FIG. In step S2605, when the via automatic arrangement unit 23 determines that there is no block that has not been determined in step S2603, the process proceeds to step S2606. In step S2606, the via automatic arrangement unit 23 determines that there is a configuration line for which no block is created for the configuration line 911 to the configuration line 915, and advances the processing to step S2600.

In step S2600, the via automatic arrangement unit 23 selects a configuration line again. For example, if the via automatic arrangement unit 23 selects the configuration line 911, a block 2806 is created from the block 2800 in step S2601, as shown in FIG.
In step S2602, the via automatic arrangement unit 23 selects one block from the blocks 2800 to 2806. For example, when the via automatic arrangement unit 23 selects the block 2800, in step S2603, the via automatic arrangement unit 23 proceeds to the process of step S2605 in order to determine that the GND via 2840 exists in the block 2800.

  In step S2605, the via automatic arrangement unit 23 determines that there is a block (from block 2801 to block 2806) that has not been determined in step S2603, returns to the process in step S2602, and selects one block again. For example, if the via automatic arrangement unit 23 selects the block 2801, in step S2603, the process proceeds to step S2604 in order to determine that the GND via is not yet arranged in the block 2801. In step S2604, the via automatic arrangement unit 23 arranges the GND via 2820 in the block 2801, and proceeds to the process of step S2605.

  Thereafter, similarly, the via automatic arrangement unit 23 repeatedly executes the processing from step S2602 to step S2605, and sequentially arranges the GND vias 2820. Similarly, the via automatic arrangement unit 23 repeatedly executes the processing from step S2600 to step S2606 until there is no configuration line that is not divided into blocks in step S2606. As a result, the GND vias can be arranged within the predetermined interval L2 in the peripheral portion within the predetermined interval L1 from the configuration line of the GND overlapping conductive region 81. FIG. 31 is a view showing a state after the GND vias are arranged at the peripheral edge portion of the GND overlapping conductive region 81. Here, there is no inner edge portion in the GND overlapping conductive region 81. However, when the inner edge portion exists, the via automatic arrangement unit 23 acquires the position information and the shape information of the inner edge in step S407, so that the via automatic arrangement unit 23 Can be arranged at the inner edge. In other words, the via automatic arrangement unit 23 repeatedly executes the processing from step S2600 to step S2606 based on the position information and the shape information of the inner edge, thereby arranging the GND via to the area within the predetermined interval L1 from the inner edge. Place within.

Next, a processing operation for automatically arranging a GND via in the center of the GND overlapping conductive region 81 will be described in detail.
In step S2607, the via automatic arrangement unit 23 excludes all the blocks created in step S2601 from the GND overlapping conductive area 81, that is, the position information and shape information of the central part 3000 which is the gray part area shown in FIG. To get. In step S2608, the via automatic arrangement unit 23 divides the central part 3000 into blocks. Here, as a block division method, first, the via automatic arrangement unit 23 selects one of the constituent points of the central part 3000. Here, it is assumed that the via automatic arrangement unit 23 selects the configuration point 3001 shown in FIG. The via automatic arrangement unit 23 creates a square block 3010 shown in FIG. 32 inside the central part 3000 with the configuration point 3001 as one vertex, a predetermined interval L3 as one side length, and one side parallel to the x axis. . Here, the length of one side of the square block is not necessarily L3. For example, the value may be L3 / 2, L3 / 3, or the like L3 or less. Then, a square block 3011 sharing one side with the block 3010 and sharing a partial area with the central part 3000 is created. The via automatic arrangement unit 23 sequentially creates a square block 3012 that shares one side with the created square block and shares a partial area with the central part 3000. Here, when the created square block 3012 protrudes from the central part 3000, the via automatic arrangement unit 23 applies a shape excluding the area protruding from the central part 3000 from the square block 3012 as the shape of the block.

  Next, in step S2609, the via automatic arrangement unit 23 determines whether or not a GND via already exists in each of the created blocks 3010, 3011, and 3012. If the GND via does not exist, the via via 3020 is set. Execute the placement process. In step S2609, the processing from step S2602 to step S2606 described above may be applied to block 3012. In step S419, the via automatic arrangement unit 23 ends the program.

In the present embodiment, by adjusting the size of the block to be divided by a process such as adopting a value obtained by multiplying the predetermined interval L2 or L3 by the ratio set by the user, the GND via arrangement state desired by the user is realized. be able to. As a result, it is possible to place a GND via that places importance on reducing the number of GND vias arranged, that is, in consideration of cost, rather than arranging the GND vias within a predetermined interval. In FIG. 32, all of the GND vias 2720, 2820, 3020, and the block 3012 are not marked.
Further, it is not always necessary to arrange the GND vias in all the blocks. In other words, by adding processing such as not arranging GND vias to blocks of a predetermined area or less, GND vias unnecessary for the user are not arranged, that is, it is possible to arrange GND vias considering the cost as in the above case. It becomes.
Furthermore, as in the first embodiment, the present invention can be applied even when the position information and shape information of the GND overlapping conductive region are expressed by inequality on the coordinate plane and space.

According to the present embodiment, as shown in FIG. 33, GND vias are automatically arranged at a distance within a predetermined interval L2 at a distance within a predetermined interval L1 from the peripheral edge of the GND overlapping conductive region and the inner edge of the printed circuit board. can do. Furthermore, GND vias can be automatically arranged at intervals within a predetermined interval L3 in the central portion of the GND overlapping conductive region. In the present embodiment, the predetermined intervals L1, L2, and L3 for determining the size and shape of the block are values within L1 depending on the situation in one substrate when the GND vias are actually arranged. Or a value within L3. However, by setting the values of L1, L2, and L3 so as not to fluctuate, that is, to divide the block at equal intervals, calculation of fluctuations in the values of L1, L2, and L3 depending on the situation becomes unnecessary, and the program operation becomes faster. The effect which becomes can be acquired.
Further, in the present embodiment, an example in which the GND vias are automatically arranged by dividing the peripheral portion, the inner edge portion, and the central portion of the GND overlapping conductive region of the printed circuit board in stages is shown. On the other hand, it is also possible to automatically arrange GND vias on the entire printed circuit board. In this case, by applying the method in which the central portion is divided into blocks in step S2607 in FIG. 28 to the entire GND overlapping conductive region as it is, GND vias are automatically arranged in the entire GND overlapping conductive region within a predetermined interval. It is possible.

  Further, in the present embodiment, the description has been given of the case where the GND vias are automatically arranged through all the conductive layers of the printed board. However, the GND vias are partially arranged through some of the conductive layers constituting the printed board. You can also. In that case, an overlapping conductive region for only the conductive layer through the GND via may be extracted, and the GND via may be arranged in the overlapping conductive region as in the present embodiment. At that time, the GND via can be efficiently arranged by handling the GND via via a plurality of layers including a part of the corresponding conductive layer as the already arranged GND via.

(Fifth embodiment)
In the first to fourth embodiments, the case where the GND vias are automatically arranged in the GND overlapping conductive region of the printed circuit board has been described. In the present embodiment, a description will be given of a case where GND vias are rearranged within a predetermined interval when a GND overlapping conductive region is changed due to a change in wiring of a signal or the like.
In this embodiment, the printed circuit board shown in FIG. 6 is referred to as a schematic diagram of the printed circuit board before the wiring change. Moreover, the printed circuit board shown in FIG. 34 is referred as a schematic diagram of the printed circuit board after the wiring change. Here, the wiring change point of the printed circuit board in this embodiment will be described. In this embodiment, the inner layer signal wiring 6210 and the signal wiring via 6220 shown in FIG. 6C are changed to the inner layer signal wiring 3210 and the signal wiring via 3220 shown in FIG. Further, the signal wiring 6310 and the signal wiring via 6320 on the surface layer shown in FIG. 6D are changed to the signal wiring 3211 and the signal wiring via 3221 on the surface layer shown in FIG. Along with this wiring change, the shapes of the GND conductive regions 623 and 633 shown in FIGS. 6C and 6D are changed to GND conductive regions 3230 and 3231 shown in FIGS. 34C and 34D, respectively.

  The processing operation of the printed circuit board design support apparatus according to this embodiment will be described below with reference to the flowcharts shown in FIGS. 35 and 36 and the schematic diagrams shown in FIGS. 34 and 37 to 44. The operation processing from step S400 to step S407, step S409, and S410 shown in FIG. 35 is the same as the same step number shown in FIG. 4 of the first embodiment, and thus detailed description thereof is omitted. Also, the flowchart shown in FIG. 36 is the same as the flowchart shown in FIG.

Here, a part of the process shown in the flowchart of FIG. 35 will be described.
In step S404, the graphic calculation unit 22 specifies again the GND conductive region of each layer related to the GND wiring name selected in step S403. This process corresponds to an example of a ground conductive region respecifying step.
Next, in step S405, the graphic calculation unit 22 again extracts a region where the identified GND conductive regions of each layer overlap two-dimensionally in the height direction as a GND overlapping conductive region C. This process corresponds to an example of the overlapping conductive region re-extraction step.
Next, processing from step S3300 to step S3304 will be described. Here, the processes from step S3300 to step S3304 are performed by the via automatic arrangement unit 23 reading out the layout information 142 stored in the main storage device 11.

In step S3300, the via automatic arrangement unit 23 excludes the GND via in step S407 after acquiring the position information and the shape information of the GND overlapping conductive region C after the wiring change. This process corresponds to an example of an interlayer connection member removal step. Specifically, the via automatic arrangement unit 23 excludes GND vias arranged outside the GND overlapping conductive region C. This process corresponds to an example of the step of eliminating the overlapping conductive area.
In step S3301, the via automatic arrangement unit 23 calculates a via arrangement position near each corner of the GND overlapping conductive region C.
In step S3302, the via automatic arrangement unit 23 excludes GND vias within a predetermined interval L2 from the via arrangement position calculated in step S3301.
In step S3303, the via automatic arrangement unit 23 arranges the GND via at the via arrangement position calculated in step S3301.

In step S409, the via automatic arrangement unit 23 divides two GND vias adjacent to each other along the configuration line of the GND overlapping conductive region C among the GND vias arranged in step S3303 by a distance within a predetermined interval L2.
In step S3304, the via automatic arrangement unit 23 excludes GND vias that are already arranged within a predetermined interval L2 from the divided position.
In step S410, the via automatic arrangement unit 23 arranges a GND via at each position divided in step S409. This process corresponds to an example of an automatic rearrangement step. Here, in the case of changing the high-speed wiring, processing from step S1600 to step S1602 shown in FIG. 17 is added between step S3300 and step S3301. In this case, the high-speed wiring via selected in step S1600 may be only the changed high-speed wiring via.

Next, the processing operation of the printed circuit board design support apparatus according to the present embodiment will be specifically described with reference to the schematic diagrams of FIGS. 34 and 37 to 44.
First, in steps S401 to S406, the via automatic arrangement unit 23 extracts a GND overlapping conductive region. These processes are the same as those in the first embodiment. FIG. 37 is a diagram showing the extracted GND conductive region. That is, the gray portions 80, 82, 83, 3581, and 3584 shown in FIG. 37 are GND overlapping conductive regions. The GND overlapping conductive regions 80, 82, and 83 coincide with the GND overlapping conductive regions having the same reference numerals shown in FIG. That is, the GND overlapping conductive regions 3581 and 3584 are changed GND overlapping conductive regions.

  FIG. 38 is a diagram showing the GND overlapping conductive region and the arrangement state of the GND via at the time when step S406 is completed. In step S407, the via automatic arrangement unit 23 acquires the position information and shape information of the GND overlapping conductive region, and then excludes the GND via 3600 shown in FIG. 38 outside the GND overlapping conductive region in step S3300. FIG. 39 is a diagram showing the arrangement state of the GND vias after eliminating the GND vias outside the GND overlapping conductive region. As shown in FIG. 39, the GND via outside the GND overlapping conductive region is eliminated.

  Next, the processing operation for rearranging the GND vias in the GND overlapping conductive region will be specifically described. Here, for ease of explanation, a processing operation for rearranging GND vias in the changed GND overlapping conductive region 3584 shown in FIG. 38 will be described. In practice, it goes without saying that the rearrangement process is similarly performed on the other GND overlapping conductive regions 80, 82, 83, and 3581. Further, by adding a flow for discriminating the changed GND overlapping conductive region, it is possible to perform the rearrangement of the GND vias only for the changed GND overlapping conductive region.

  Here, as in the first embodiment, a case will be described in which the peripheral portion, the inner edge portion, and the central portion of the GND overlapping conductive region are divided stepwise and the GND vias are rearranged in each portion. Therefore, the via automatic arrangement conditions set in step S401 are predetermined intervals L1, L2, and L3. First, the operation of rearranging the GND vias at the peripheral edge and inner edge of the GND overlapping conductive region 3584 will be specifically described. Here, the gray area shown in FIG. 40 is an enlarged view of the GND overlapping conductive area 3584.

In step S3301, the via automatic arrangement unit 23 extracts each component point based on the position information and shape information of the GND overlapping conductive region 3584 acquired in step S407, and calculates a via arrangement position 3800 near each component point. The via arrangement position calculation method near each component point may be the same method (see FIG. 11) as step S408 in the flowchart shown in FIG. 4 of the first embodiment.
In step S3302, the via automatic arrangement unit 23 excludes the GND via 3801 within a predetermined distance L2 from the via arrangement position 3800, that is, inside the circle 3810 shown in FIG.
Next, in step S3303, the via automatic arrangement unit 23 arranges the GND via 3800 at each via arrangement position 3800.

Next, in step S409, the via automatic arrangement unit 23 divides the GND vias arranged in step S3303 between adjacent GND vias along the configuration line of the GND overlapping conductive region 3584 at an interval within a predetermined interval L2. . Here, as the division method, the method described in step S409 in the flowchart shown in FIG. 4 of the first embodiment may be used. Here, black circles 3900 shown in FIG. 41 indicate the positions divided in step S409.
In step S3304, the via automatic arrangement unit 23 excludes the GND via 3901 that is already arranged within the predetermined interval L2 from each position divided in step S409, that is, inside the circle 3910 shown in FIG. Here, in FIG. 41, there is a GND via 3901 that completely overlaps the position 3900 along the configuration line that does not change between the GND overlapping conductive region 84 and the GND overlapping conductive region 3584, and the via automatic arrangement unit 23 also excludes those GND vias 3901.

  In step S410, the via automatic arrangement unit 23 arranges the GND via 3900 at each position divided in step S409. Here, in order to make the drawing easier to see, the same reference numerals are given to the position 3900 divided in step S409 and the GND via 3900 arranged in step S410.

Next, the operation of arranging the GND via at the center of the GND overlapping conductive region 3584 will be specifically described. FIG. 42 is a diagram showing a state in which a GND via is arranged in the central portion of the GND overlapping conductive region 3584.
In step S411, the via automatic arrangement unit 23 selects one GND via existing in the GND overlapping conductive region 3584. Here, for example, it is assumed that the via automatic arrangement unit 23 selects the GND via 4000 shown in FIG.
In step S412, the via automatic arrangement unit 23 calculates the slide position from the GND via 4000 in the same manner as described in step S412 of the flowchart shown in FIG. 5 of the first embodiment. That is, the via automatic arrangement unit 23 calculates a position moved by a half distance (L3 / 2) of the predetermined interval L3 in the positive and negative directions in the x-axis direction and the y-axis direction. Specifically, the positions moved in the positive direction in the x-axis direction, the negative direction in the x-axis direction, the positive direction in the y-axis direction, and the negative direction in the y-axis direction are slide positions 4001, 4002, 4003, shown in FIG. 4004.

In step S413, the via automatic arrangement unit 23 selects one of the slide positions 4001, 4002, 4003, and 4004. Here, for example, the via automatic arrangement unit 23 selects the slide position 4001.
In step S414, the via automatic arrangement unit 23 does not arrange any other GND vias within the range of the distance (L3 / 2) half of the predetermined interval L3 from the slide position 4001, that is, inside the circle 4011 shown in FIG. And the process proceeds to step S415.
In step S415, the via automatic arrangement unit 23 determines that the slide position 4001 is within the GND overlapping conductive region 3584, and the process proceeds to step S416.
Therefore, in step S416, the via automatic arrangement unit 23 arranges the GND via 4001 at the slide position 4001. This process corresponds to an example of an automatic rearrangement step.

In step S417, the via automatic arrangement unit 23 determines that there are slide positions 4002, 4003, and 4004 that have not been determined in step S414 yet, and thus the process returns to step S413.
In step S413, the via automatic arrangement unit 23 selects one of the slide positions 4002, 4003, and 4004. Here, for example, the via automatic arrangement unit 23 selects the slide position 4002. In this case, in step S414, the via automatic arrangement unit 23 determines that the GND via 4022 has already been arranged within the distance L3 / 2 from the slide position 4002, that is, inside the circle 4012 shown in FIG. The process proceeds to S417. In step S417, since the via automatic arrangement unit 23 determines that there are slide positions 4003 and 4004 that have not been determined in step S414, the process returns to step S413.

Thereafter, the via automatic arrangement unit 23 repeatedly executes the processing from step S413 to step S417 until no remaining slide position exists in step S417. The via automatic arrangement unit 23 does not arrange the GND via at the slide position 4003 but arranges the GND via 4004 at the slide position 4004. When there is no remaining slide position in step S417, the process proceeds to step S418.
In step S418, the via automatic arrangement unit 23 determines that there is a GND via that has not been subjected to the process of step S412. Therefore, the process returns to the process of step S411.

  Thereafter, the via automatic arrangement unit 23 similarly repeatedly performs the processing from step S411 to step S418 until there is no GND via that does not perform the processing of step S412 in step S418. If there are no GND vias that have not undergone the process of step S412 in step S418, the program ends in step S419.

  FIG. 43 shows the arrangement state of the GND vias in the GND overlapping conductive region 3584. FIG. 44 shows an arrangement state of GND overlapping conductive regions and GND vias on the entire printed circuit board after the program is finished. In order to make the drawing easy to see, the GND via 3800, circle 3810 in FIG. 40, the GND via 3900, circle 3910, and GND via 3901 in FIG.

As described above, in the present embodiment, the case where the GND vias are newly rearranged when the GND vias are rearranged at the peripheral edge and the inner edge of the GND overlapping conductive region has been described. However, as a result of the wiring change, a search is made for a place where the GND via is not arranged at the peripheral edge and the inner edge of the GND overlapping conductive area, or the changed configuration line is determined and arranged only at the peripheral edge and the inner edge. May be.
Further, the GND vias outside the GND overlapping conductive region may be moved one by one or a plurality by being corrected to a position where they are not arranged despite the necessity of arrangement. This process corresponds to an example of an automatic correction placement step. At this time, as a method for calculating the position that needs to be arranged, the method described in step S3301 of the flowchart shown in FIG. 35 of the present embodiment or step S412 of the flowchart shown in FIG. 36 may be applied.
In the present embodiment, the GND overlapping conductive region is divided into the peripheral portion, the inner edge portion, and the central portion, and the GND vias are rearranged stepwise. However, the GND via arranging method according to the third embodiment By applying, it is possible to arrange the GND vias without dividing them step by step.

  As in the first embodiment, this embodiment realizes a user's desired GND via arrangement state by enabling the user to set the movement distance in step S412 and the search range around the slide position in step S414. be able to. By doing so, it is possible to arrange the GND vias in consideration of the cost by reducing the number of GND vias arranged rather than arranging the GND vias within a predetermined interval. Further, even if the position information and shape information of the GND overlapping conductive area are expressed by an inequality on the coordinate plane or space, the GND vias can be automatically arranged.

  As described above, in the present embodiment, even when the GND overlapping conductive region is changed as shown in FIG. 44, a predetermined distance L1 from the edge of the peripheral edge and the inner edge of the GND overlapping conductive region. The GND vias can be automatically rearranged at intervals within the interval L2. Further, the GND vias can be automatically rearranged at intervals within the predetermined interval L3 in the central portion of the GND overlapping conductive region. Note that the predetermined intervals L1, L2, and L3 in the present embodiment are values within L1, values within L2, and values within L3, respectively, depending on the situation in one substrate when GND vias are actually arranged. It may be varied. However, by setting the values of L1, L2, and L3 so as not to fluctuate, that is, to be arranged at equal intervals, the calculation of the fluctuations of the values of L1, L2, and L3 depending on the situation becomes unnecessary, and the program operation becomes faster. There is.

  In the present embodiment, the explanation has been given of the case where the GND vias are automatically arranged through all the conductive layers of the printed circuit board. However, the GND vias are partially arranged through some of the conductive layers constituting the printed circuit board. You can also In that case, it is only necessary to extract the overlapping conductive region only in the conductive layer through the GND via and arrange the GND via in the overlapping conductive region as in the above-described embodiment. At that time, the GND via can be efficiently arranged by handling the GND via via a plurality of layers including a part of the corresponding conductive layer as the already arranged GND via.

(Sixth embodiment)
In the fifth embodiment, the case has been described in which the GND vias are automatically rearranged in response to the change in the GND overlapping conductive region accompanying the wiring change. At this time, the method of rearranging the GND vias is a method of eliminating the GND vias only from the position information and shape information of the GND overlapping conductive regions after the wiring change and additionally arranging them. In the present embodiment, a case will be described in which GND vias are eliminated from changes in the shape of signal wirings accompanying wiring changes, and then GND vias are additionally arranged in the GND overlapping conductive regions.
FIG. 45 is a flowchart illustrating an example of a processing procedure performed by the printed circuit board design support apparatus according to the present embodiment based on the printed circuit board design support program. Step C shown in FIG. 45 follows the flowchart of step C shown in FIG. 36 of the fifth embodiment. Hereinafter, the processing operation of the printed circuit board design support apparatus according to the present embodiment will be described with reference to the flowchart shown in FIG. 45 and the schematic diagrams shown in FIGS. The diagrams before and after the wiring change refer to the schematic diagrams of FIGS. 6 and 34, respectively, as in the fifth embodiment.

First, the flowchart shown in FIG. 45 will be described in detail. Here, the flowchart shown in FIG. 45 is obtained by adding Step S4300, Step S4301, and Step S4302 after the start of the flowchart shown in FIG. 35 of the fifth embodiment. Therefore, only step S4300, step S4301, and step S4302 will be described in detail.
In step S4300, the external storage information extraction unit 21 acquires via placement prohibited area information for each component and wiring placed on the printed circuit board. This process corresponds to an example of a prohibited area information acquisition step. As a method for acquiring the via placement prohibited area information, a method in which the via placement prohibited area information is included in the layout information 142 and the external storage information extracting unit 21 acquires from the layout information 142 in the main storage device 11 is preferable. The following method is also conceivable. The signal wiring and component type attribute information is included in the layout information 142, and the external storage information extraction unit 21 extracts the signal wiring and component type attribute information from the layout information 142 in the main storage device 11. Next, correspondence data D between the attribute information of each signal wiring or component type and the via placement prohibited area information is stored in advance in the external storage device 14, and the external storage information extraction unit 21 then stores the external storage device 14. The correspondence data D is stored in the main storage device 11. Then, the external storage information extraction unit 21 collates the attribute information of the signal wiring or component type with the correspondence data D, and the via placement prohibited area information given from the correspondence D to the attribute information of the corresponding signal wiring or component type To get.

Next, in step S4301, the graphic computation unit 22 calculates a via placement prohibited area for each changed wiring or component while referring to the layout information 142 and via placement prohibited area information in the main storage device 11. . This process corresponds to an example of a prohibited area calculation step. For example, when the signal wiring E is changed and the via placement prohibition area information for the signal wiring E is within the distance L6A from the conductive area of the signal wiring E, the distance within the distance L6A from the conductive area of the signal wiring E after the change. The range is calculated as a via placement prohibited area. For example, assume that the arrangement position of the component F is changed. If the via placement prohibited area information of the component F is within the range of the distance L6B from the outer shape of the component F, the range within the distance L6B from the outer shape of the component F at the changed position is calculated as the via placement prohibited region.
On the other hand, it is assumed that the via placement prohibited area information of the component F is within a distance L6C from a conductive region (hereinafter referred to as a pin pad) for electrically connecting each pin of the component F to the conductive region of the printed circuit board. In this case, a range within a distance L6C from the pin pad of each pin of the component F after the change is calculated as a via placement prohibited area.

Further, when the via placement prohibited area information of the part F is the graphic information F5 including the configuration points that can be calculated with reference to the part placement position of the part F, the via placement prohibited area is determined from the placement position of the part F and the graphic information F5. Is calculated.
Further, for example, the position of the signal wiring via G is changed, and the distance L6D from the conductive region (hereinafter referred to as via pad) provided for improving the electrical connection of the signal wiring via G in the via placement prohibited area of the signal wiring via G. It is assumed that it is in the range. In that case, the range within the distance L6D from the via pad of the signal wiring via G after the change is calculated as the via placement prohibited area.
In step S4302, when the via placement prohibited area for each changed wiring or component is calculated in step S4301, the via automatic placement unit 23 refers to the layout information 142 in the main storage device 11 and is included in the via placement prohibited area. Eliminate GND vias. This process corresponds to an example of an interlayer connection member removal step.
The above is an example of a part of the processing procedure of the printed circuit board design support apparatus according to the present embodiment.

In the flowchart shown in FIG. 45, the processing from step S4300 to step S4302 is executed immediately after the start of the flowchart, that is, immediately after step S400. However, the same result can be obtained even if the processing from step S4300 to step S4302 is executed immediately after step S406.
Further, as a response to the change of the high-speed wiring, the processing from step S1600 to step S1602 shown in FIG. 17 may be added between step S3300 and step S3301. In this case, only the changed high-speed wiring via may be selected as the high-speed wiring via selected in step S1600.

Next, the processing operation of the printed circuit board design support apparatus according to the present embodiment will be specifically described with reference to schematic diagrams of FIGS. 46 to 48. Here, in order to facilitate understanding of the explanation, the processing from step S401 to step S406 is executed after the start, then the processing from step S4300 to step S4302 is executed, and then the processing from step S407 to the end of the program is executed. .
When the series of steps from step S400 to step S406 are repeatedly executed, the graphic calculation unit 22 performs the GND overlapping conductive regions 80, 82, 83, and 3581 shown in FIG. 38 described in the fifth embodiment. , 3584 are extracted. 46, in addition to FIG. 38, changed signal wirings 3210 and 3211 and changed signal wiring vias 3220 are shown.

In step S4300, the external storage information extraction unit 21 acquires via placement prohibited area information of the signal wirings 3210 and 3211 and the signal wiring via 3220. Here, for example, the via placement prohibited area information of the signal wiring 3210 and the signal wiring 3211 is in the range of the distance L6A from the conductive area of the signal wiring, and the via placement prohibited area information of the signal wiring via 3220 is in the range of the distance L6D from the via pad. Suppose there is.
In step S4301, the graphic calculation unit 22 calculates a range of distance L6A from the conductive regions of the lines of the signal wiring 3210 and the signal wiring 3211, that is, a rectangle 4400 and a rectangle 4401 respectively indicated by dotted lines shown in FIG. Further, a range of a distance L6D from the via pad of the signal wiring via 3220, that is, a circle 4402 indicated by a dotted line shown in FIG. 46 is calculated.

  In step S4302, the via automatic arrangement unit 23 excludes the GND vias included in the rectangles 4400 and 4401 and the circle 4402, that is, the GND via 4420 included in the rectangle 4400 and the GND via 4421 included in the rectangle 4401. Note that all the GND vias 4420 and 4421 are not marked for the sake of clarity. FIG. 47 is a diagram showing the GND overlapping conductive region and the arrangement state of the GND via after the GND via 4420 and the GND via 4421 in the via arrangement prohibition region are excluded. Note that the processing from step S407 to step S419 is the same as that described in the fifth embodiment, and a description thereof will be omitted. FIG. 48 is a diagram showing the GND overlapping conductive region and the arrangement state of the GND via after the program is finished.

  According to the present embodiment, as in the fifth embodiment, the GND vias can be automatically rearranged even when the shape of the GND overlapping conductive region changes due to the wiring change of the printed circuit board. In the present embodiment, a case has been described in which the GND vias that have entered the via placement prohibited area after the wiring change is completed are eliminated. However, every time a wiring or a component is arranged, calculation of the via placement prohibited area, elimination of the GND via in the via placement prohibited area, and rearrangement of the GND via in the GND overlapping conductive area may be performed. Thereby, the user can confirm the relocation status of the GND vias while changing the wiring. However, when the GND via rearrangement is executed every time the wiring is changed, a graphic calculation process is required every time the position and direction of the wiring are changed, which may hinder the user's smooth work. Therefore, here, an example is shown in which the GND vias that have entered the via placement prohibited area after the completion of the wiring change are eliminated.

In the present embodiment, the case where the via placement prohibited area for the line is rectangular has been described. Good. In addition, although the via placement prohibition area for the via pad is a circle, an ellipse or a rectangle may be used instead. As described above, the shape of the via placement prohibited area information for each wiring or component can be various.
Further, in the present embodiment, the case has been described in which the GND vias that pass through all the conductive layers of the printed board are automatically corrected and additionally arranged. However, it is also possible to automatically arrange the GND vias through a part of the conductive layers constituting the printed circuit board. In that case, an overlapping conductive region for only the conductive layer through the GND via may be extracted, and the GND via may be arranged in the overlapping conductive region as in the present embodiment. At that time, the GND via can be efficiently arranged by handling the GND via via a plurality of layers including a part of the corresponding conductive layer as the already arranged GND via.

(Seventh embodiment)
In the first to third embodiments, the case where the GND vias are automatically arranged in the GND overlapping conductive region has been described. In the fifth embodiment and the sixth embodiment, the case where the GND vias are automatically rearranged when the shape of the GND overlapping conductive region is changed due to the wiring change or the like has been described.
In the present embodiment, a printed circuit board design apparatus will be described in which GND vias are automatically placed before component placement and wiring are performed, and GND vias that should be removed along with component placement and wiring are eliminated.

  FIG. 49 is a flowchart illustrating an example of a processing procedure performed by the printed circuit board design support apparatus according to this embodiment based on the printed circuit board design support program. The processing operation of the printed circuit board design support apparatus according to this embodiment will be described below with reference to the flowchart shown in FIG. 49 and the schematic diagrams shown in FIGS. FIG. 50 is a diagram showing a state of the printed circuit board after designing the printed circuit board according to the present embodiment. Here, the component arrangement and the wiring state shown in FIG. 50 will be described. The component arrangement and the wiring situation in the schematic diagram of the printed board shown in FIG. 50 coincide with the arrangement and the wiring situation excluding the thick solid wiring in the layer 62 shown in FIG. Here, in order to make the diagram shown in FIG. 50 easier to see, the thick solid line is excluded. Further, the gray area shown in FIG. 50 indicates a GND overlapping conductive area.

Next, the flowchart shown in FIG. 49 will be described in detail.
First, the processing of step S4700 and step S4701 is the same as step S400 and step S401 of the flowchart shown in FIG. 4 described in the first embodiment, and description thereof is omitted. However, the via automatic arrangement conditions in this embodiment are the same as the predetermined intervals L1, L2, and L3 described in the first embodiment, and these conditions are applied by replacing the GND overlapping conductive region with the board outline. Shall. In addition to the predetermined intervals L1, L2, and L3, the via automatic addition condition includes a via arrangement prohibition distance L7 (hereinafter referred to as a prohibition distance L7) from the periphery of the GND overlapping conductive region. Hereinafter, the processing performed from step S4702 to step S4708 is processing performed by the via automatic arrangement unit 23 reading out the layout information 142 stored in the main storage device 11.

In step S4702, the via automatic arrangement unit 23 acquires position information and shape information of the outer shape of the printed board.
In step S4703, the via automatic arrangement unit 23 arranges the GND vias within a predetermined interval in the board outer shape. As a method of arranging GND vias within a predetermined interval in step S4703, the GND overlapping conductive region in the first embodiment or the fourth embodiment described in the first embodiment or the fourth embodiment is used in this embodiment. What is necessary is just to replace and apply to the inside of the external shape of the board | substrate in a form.

  In step S4704, the via automatic arrangement unit 23 creates a via arrangement prohibited area every time a user adds or changes a component or wiring, that is, changes the layout information 142, after arranging the GND via in step S4703. Determine whether it is necessary. If it is necessary to create a via placement prohibited area, the processing of step S4705, step S4706, and step S4707 is executed, and the processing returns to step S4704 again. If it is not necessary to create a via placement prohibited area, the process proceeds to step S4708. Here, in step S4705, step S4706, and step S4707, processing similar to that in step S4300, step S4301, and step S4302 shown in FIG. 45 described in the sixth embodiment is executed. Therefore, the detailed description about the process of step S4705, step S4706, and step S4707 is abbreviate | omitted.

In step S4708, the graphic calculation unit 22 determines whether or not a surface graphic of the GND conductive region has been inserted (whether or not a surface has been inserted). If the GND conductive area is filled, the process proceeds to step S4709. If the component placement or wiring is changed without placing the face, the process returns to step S4704.
In step S4709, the graphic calculation unit 22 reads the layout information 142 in the main storage device 11 and extracts the GND overlapping conductive region. As a method for extracting the GND overlapping conductive region in step S4709, the method from step S402 to step S406 in the flowchart shown in FIG. 4 of the first embodiment may be applied.

Hereinafter, the processing from step S4710 to step S4712 is processing performed by the via automatic arrangement unit 23 reading out the layout information 142 stored in the main storage device 11.
In step S4710, the via automatic arrangement unit 23 acquires position information and shape information of the extracted GND overlapping double conductive region.
Next, in step S4711, the via automatic arrangement unit 23 excludes GND vias arranged outside the GND overlapping conductive region or within a predetermined distance L7 from the periphery and inner edge of the GND overlapping conductive region. In step S4712, the processing program 141 ends.
The above is the detailed description of the flowchart shown in FIG. 49 according to the present embodiment. In the present embodiment, a case has been described in which GND vias are arranged within an equal interval in the entire GND overlapping conductive region of the printed circuit board. However, the peripheral and inner edge portions and the central portion of the GND overlapping conductive region may be arranged separately. In this case, steps S3301 to S410 in the flowchart shown in FIG. 35 described in the fifth embodiment are added after step S4711 in the flowchart shown in FIG. 49, and the GND vias may be rearranged in the GND overlapping conductive region. .

When the GND via is disposed in the vicinity of the high-speed wiring via as in the second embodiment, the processing from step S1600 to step S1602 in the flowchart shown in FIG. 17 may be added between step S4710 and step S4711. .
Further, the wiring or the like may be changed even after the GND surface placement in step S4708. In this case, as in the sixth embodiment, whenever a wiring or the like is changed, a via placement prohibited area corresponding to the change is created, and a process of eliminating the GND via may be performed.

Hereinafter, the processing operation according to the present embodiment will be described in detail with reference to the schematic diagrams of FIGS. 50 to 59. When the processing from step S4700 to step S4703 is executed, GND vias are arranged within a predetermined interval at the peripheral edge, the inner edge, and the center of the board outer shape. This specific operation can be realized by replacing the GND overlapping conductive region with the substrate outline in the processing from step S407 to step S418 in the flowcharts shown in FIGS. 4 and 5 described in the first embodiment. In addition, the processing from step S2600 to step S2609 of the flowchart shown in FIG. 28 described in the fourth embodiment can be realized by replacing the GND overlapping conductive region with the substrate outline.
Note that when the GND vias are arranged within the predetermined interval without dividing the peripheral edge, the inner edge, and the central portion from step S407 to step S418 shown in FIGS. 23 and 24 of the third embodiment. This processing can be realized by replacing the GND overlapping conductive region with the substrate outer shape. Here, FIG. 51 is a diagram showing the arrangement state of the GND vias of the printed circuit board after the GND vias are arranged in the board outer shape. As shown in FIG. 51, a GND via 4801 is arranged within a predetermined interval (L2) at the peripheral edge in the substrate outer shape 4800, and a GND via 4802 is arranged within a predetermined interval (L3) at the center. .

The processing after step S4704 is executed by placing components, wirings, etc. on the printed circuit board by the user. For example, as shown in FIG. 52A, when a component 4900 (a component having a via placement prohibited area) is placed, in step S4704, the via automatic placement unit 23 performs an additional placement that must create a via placement prohibited area. Judge that there was. Then, by executing step S4705 and step S4706, a via placement prohibited area 4910 surrounded by a dotted line shown in FIG. 52A is calculated. Here, a case has been described in which the via placement prohibited area information of the component 4900 is represented by a graphic shape including constituent points that can be calculated on the basis of the coordinates of the placement position of the component 4900.
In step S4707, the via automatic arrangement unit 23 excludes the GND via 4920 included in the via arrangement prohibited area 4910. Similarly, the processing from step S4705 to step S4707 is executed each time the components 4901, 4902, and 4903 are arranged, and the GND vias 4921, 4922, and 4923 included in the calculated via arrangement prohibition areas 4911, 4912, and 4913 are displayed. Exclude.

  FIG. 53A is a diagram showing a state of the printed circuit board after the components 4900, 4901, 4902, and 4304 are arranged. Here, the parts 4900 and 4901 are arranged on the layer 60 shown in FIG. 53B, and the parts 4902 and 4903 are arranged on the layer 63. Next, as shown in FIG. 54A, when the signal wiring 5100 is arranged in the layer 60, it is necessary to set a via arrangement prohibition region around the signal wiring. Therefore, by executing the processing of step S4705 and step S4706, the via automatic arrangement unit 23 calculates the dotted via arrangement prohibited area 5110 shown in FIG. 54A, and is included in the via arrangement prohibited area 5110 in step S4707. The GND via 5120 is eliminated. FIG. 55A is a diagram showing a state of the printed circuit board after the signal wiring 5100 is arranged.

Next, the case where the signal wiring and the signal wiring via are arranged as shown in FIG. 56A will be described. In FIG. 56A, signal wirings 5300, 5301, and 5302 are disposed in the layers 60, 62, and 63, respectively, and signal wiring vias 5303 that connect the signal wirings 5300 and 5301 and signals that connect the signal wirings 5301 and 5302 are shown. A wiring via 5304 is disposed. Here, it is necessary to set a via placement prohibited area around the signal wiring and the signal wiring via. Therefore, by executing the processing of step S4705 and step S4706, the via automatic arrangement unit 23 calculates the via arrangement prohibited areas 5310, 5311, and 5312 for the signal wirings 5300, 5301, and 5302. Further, the via automatic arrangement unit 23 calculates via arrangement prohibition areas 5313 and 5314 for the signal wiring vias 5303 and 5304. Next, in step S4707, the via automatic arrangement unit 23 excludes the GND via 5320 included in the via arrangement prohibited areas 5310, 5311, 5312, 5313, and 5314.
FIG. 57A is a diagram showing a state of the printed circuit board after the signal wirings 5300, 5301, and 5302 are arranged.

Hereinafter, similarly, every time a user places a component, wiring, or the like on the printed circuit board, the via automatic placement unit 23 executes the processing from step S4705 to step S4707 until the grounding of the GND conductive region is performed.
FIG. 58 (a) is a diagram showing the printed circuit board in a state where all wiring has been completed. In FIG. 58A, signal wirings 5500, 5501, and 5502 are arranged in the layers 60, 62, and 63, respectively, and signal wiring vias 5520 that connect them are arranged. Further, as shown in FIG. 58A, the GND vias around the signal wiring and the signal wiring via are excluded.

Next, when GND placement is performed by the user, in step S4709, the graphic calculation unit 22 extracts a GND overlapping conductive region. Here, the gray region shown in FIG. 59A is the GND overlapping conductive region 5600.
In step S4710, the via automatic arrangement unit 23 acquires position information and shape information of the GND overlapping conductive region 5600.
In step S4711, the via automatic arrangement unit 23 excludes the GND via 5601 included in the range of the prohibited distance L7 from the peripheral edge and the inner edge of the GND overlapping conductive region 5600. In step S4712, the program ends.

FIG. 50A shows a state of the printed circuit board after the GND via is removed. However, in FIG. 50 (a), in order to make the drawing easier to see, the GND via 4801 shown in FIG. 51, the GND vias 4920, 4922, 4922, 4923 shown in FIG. 52 (a), and the GND via 5120 shown in FIG. 54 (a). The reference numerals of the GND vias 5320 shown in FIG. Further, the reference numerals of the signal wiring via 5420 shown in FIG. 58A and the GND via 5601 shown in FIG. 59A are not attached.
The above is the processing operation by the printed circuit board design support apparatus according to the present embodiment. According to this embodiment, as shown in FIG. 50A, GND vias can be automatically arranged within a predetermined interval at the peripheral edge and the inner edge of the printed circuit board. In addition, the GND via can be automatically arranged within a predetermined interval in the central portion of the printed circuit board and in the entire GND overlapping conductive region.

  In this embodiment, the case where the position information and the shape information of the GND overlapping conductive region are mainly indicated by coordinates has been described. However, for example, the region is represented by an equation / inequality on the plane or space, such as an inequality on the xy plane. Even in this case, GND vias can be automatically arranged. For example, in the case of an inequality on the xy plane, the position coordinates of each constituent point of the GND overlapping conductive region can be obtained by the coordinates of the intersection of the equality in which the inequality is represented by an equal sign. In addition, the determination of whether the inside or outside of the GND overlapping conductive region for a specific point can be made by simply applying the coordinates to the inequality. Therefore, processing equivalent to that of the above-described embodiment can be performed.

  Further, in the present embodiment, the case where the GND vias are arranged within the predetermined interval in the entire GND overlapping conductive region has been described. However, it is also possible to arrange GND vias within a predetermined interval at the peripheral edge and inner edge of the GND overlapping conductive region. In this case, steps S3300 to S3304 in the flowchart shown in FIG. 35 may be added between step S4710 and step S4711. Similarly to the second embodiment, when the GND via is arranged in the vicinity of the high-speed wiring via, the processing from step S1600 to step S1602 shown in FIG. 17 is added between step S4710 and step S4711. Good.

  As described above, each unit of the printed circuit board design support apparatus and each step of the printed circuit board design support method in the embodiment of the present invention is realized by executing the printed circuit board design support program stored in the external storage device 14. it can. A computer-readable recording medium recording this program is included in the present invention.

  10: Central processing unit (CPU) 11: Main storage device 12: Display device 13: Input device 14: External storage device 15: Output device 16: Bus 141: Processing program 142: Layout information 20: Input unit 21: External storage information Extraction unit 22: Graphic operation unit 23: Via automatic arrangement unit

Claims (10)

A ground conductive region specifying step for specifying a conductive region that can be used as a ground of a printed circuit board having a plurality of conductive layers;
An extraction step of extracting an overlapping conductive region in which the conductive region specified by the ground conductive region specifying step overlaps two-dimensionally;
A first disposing step of disposing an interlayer connection member that electrically connects at least two of the plurality of conductive layers in the overlapping conductive region extracted by the extracting step at an interval within a predetermined distance; A printed circuit board design support program to be executed by
The first arranging step includes
A block dividing step of dividing the overlapping conductive region extracted by the extracting step;
And a second arrangement step of arranging the interlayer connection member in the block divided by the block division step. The first arranging step includes
2. The printed circuit board design according to claim 1, wherein the interlayer connection members are arranged within a predetermined distance within a predetermined distance from a peripheral edge or an inner edge of the overlapping conductive region extracted by the extracting step. Support program. When wiring changes are made,
A ground conductive region respecifying step for respecifying a conductive region that can be used as the ground;
A re-extraction step for re-extracting an overlapping conductive region in which the conductive region specified by the ground conductive region re-specification step overlaps two-dimensionally;
An interlayer connection member exclusion step of eliminating one or more of the interlayer connection members;
The printed circuit board design support program according to claim 1, further causing the computer to execute an automatic rearrangement step of rearranging the interlayer connection members in the overlapping conductive regions extracted again by the reextraction step. The interlayer connection member exclusion step includes
4. The printed circuit board design support program according to claim 3, further comprising a step of excluding an overlapping conductive region that excludes an interlayer connection member outside the overlapping conductive region extracted again by the re-extraction step. The interlayer connection member exclusion step includes
5. The printed circuit board design support program according to claim 4, wherein an interlayer connection member within a predetermined distance range is excluded from a wiring having a potential different from that of the ground. When wiring changes are made,
A ground conductive region respecifying step for respecifying a conductive region that can be used as the ground;
A re-extraction step for re-extracting an overlapping conductive region in which the conductive region specified by the ground conductive region re-specification step overlaps two-dimensionally;
The printed circuit board design support program according to claim 1, further causing the computer to execute an automatic correction arrangement step of correcting and arranging an interlayer connection member in the overlapping conductive region extracted again by the re-extraction step. The automatic correction placement step includes:
The interlayer connection member arranged outside the overlapping conductive region extracted again by the re-extraction step is moved to the inside of the overlapping conductive region extracted again by the re-extraction step. Printed circuit board design support program. When a part or wiring change is made,
A prohibited area information acquisition step for acquiring via placement prohibited area information of a part or wiring that has been changed;
A prohibited area calculating step of calculating a via placement prohibited area based on the via placement prohibited area information acquired by the prohibited area information acquisition step;
The printed circuit board design support program according to claim 1, further causing the computer to execute an interlayer connection member removing step of removing an interlayer connection member arranged in the via arrangement prohibited area calculated in the prohibited area calculation step. A ground conductive region specifying step for specifying a conductive region that can be used as a ground of a printed circuit board having a plurality of conductive layers based on the layout information of the printed circuit board stored in the storage device;
An extracting step for extracting an overlapping conductive region in which the conductive regions specified in the ground conductive region specifying step overlap two-dimensionally; and
First arrangement means arranges interlayer connection members that electrically connect at least two of the plurality of conductive layers in the overlapped conductive region extracted in the extraction step at intervals within a predetermined distance. A printed circuit board design support method comprising: 1 placement step,
The first arranging step includes
A block dividing step for dividing the overlapping conductive region extracted by the extracting step into blocks;
A printed circuit board design support method comprising: a second arrangement step in which a second arrangement means arranges the interlayer connection member in the block divided by the block division step. A ground conductive region specifying means for specifying a conductive region that can be used as a ground of a printed circuit board having a plurality of conductive layers;
Extracting means for extracting an overlapping conductive area in which the conductive areas specified by the ground conductive area specifying means overlap two-dimensionally;
First arrangement means for arranging an interlayer connection member for electrically connecting at least two of the plurality of conductive layers in the overlapping conductive region extracted by the extraction means at an interval within a predetermined distance; A printed circuit board design support device,
The first arrangement means includes
Block dividing means for dividing the overlapping conductive region extracted by the extracting means;
A printed circuit board design support apparatus, comprising: a second arrangement unit that arranges the interlayer connection member in a block divided by the block division unit.

Images