JP2013098614A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable the setting of an arbitrary tolerance of oscillation frequency variation.SOLUTION: A semiconductor device (21) includes: an oscillator (12) whose oscillation frequency is changed by a trimming value held in a trimming register (11); and a correction circuit (20) capable of correcting the oscillation frequency. The correction circuit includes: an upper limit value register (6) capable of setting an upper limit value; a lower limit value register (7) capable of setting a lower limit value; a frequency division circuit (13) for dividing the oscillation frequency; and a counter (3) for counting an output of the frequency division circuit. The correction circuit further includes: a buffer register (4) capable of holding an output of the counter; a comparator (5) for determining whether or not the value held in the buffer register is between the upper limit value and the lower limit value; and a trimming value correction control circuit (8) for correcting the trimming value on the basis of the result of determination. A user can set an arbitrary tolerance of oscillation frequency variation with the use of the upper limit value and the lower limit value.

Description

  The present invention relates to a technique for allowing a user (customer) of a semiconductor device to arbitrarily set an allowable range of oscillation frequency fluctuations in a semiconductor device, and further, an internal oscillator (OCO; On-Chip Oscillator) included in the semiconductor device.

  Patent Document 1 describes a timer device for realizing a highly accurate count operation even if a variation occurs in the system clock of a microcomputer.

  Patent Document 2 describes an oscillation control device that can maintain and switch the system clock oscillator frequency of a microcomputer with high accuracy.

Japanese Patent Laid-Open No. 2004-334577 Japanese Patent Laid-Open No. 7-15237

  The inventor of the present application has studied a built-in oscillator of a microcomputer, which is an example of a semiconductor device, and has found the following problems.

  The frequency of the built-in oscillator is temperature dependent, and in order to maintain a highly accurate frequency over a wide range of temperatures, it is necessary to always correct the frequency by performing frequency trimming. In addition, the oscillation frequency of the built-in oscillator and the allowable range of its variation vary depending on the system in which the microcomputer is mounted. According to Patent Documents 1 and 2, the oscillation frequency can be corrected, but the allowable range of oscillation frequency fluctuation cannot be arbitrarily set. For example, although the user wants to guarantee the oscillation frequency of an oscillator built in the microcomputer to 40 [MHz] ± 1.0%, the user cannot make such a setting for the microcomputer. .

  An object of the present invention is to provide a semiconductor device capable of arbitrarily setting an allowable range of oscillation frequency fluctuations in a built-in oscillator.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, the semiconductor device includes a trimming register capable of storing a trimming value, an oscillator whose oscillation frequency is changed according to the trimming value in the trimming register, and a correction circuit capable of correcting the oscillation frequency of the oscillator. At this time, the correction circuit includes an upper limit value register that can set an upper limit value for frequency trimming, a lower limit value register that can set a lower limit value for frequency trimming, and a frequency divider for dividing the oscillation frequency of the oscillator. A circuit and a counter for counting the output of the frequency dividing circuit. Further, the correction circuit includes a buffer register capable of holding the output of the counter, and whether or not the holding value of the buffer register is between the holding value of the upper limit register and the holding value of the lower limit register. And a trimming value correction control circuit for correcting the trimming value of the trimming register based on the discrimination result of the comparator.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, it is possible to provide a semiconductor device capable of arbitrarily setting an allowable range of oscillation frequency fluctuations in the built-in oscillator.

1 is a block diagram illustrating a configuration example of a microcomputer as an example of a semiconductor device according to the present invention. It is a flowchart which shows the flow of operation | movement of the principal part in the microcomputer shown by FIG. FIG. 2 is an operation timing chart of a main part in the microcomputer shown in FIG. 1. FIG. 2 is an operation timing chart of a main part in the microcomputer shown in FIG. 1. FIG. 11 is a block diagram showing another configuration example of a microcomputer as an example of a semiconductor device according to the present invention.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  [1] In a semiconductor device (21) according to a typical embodiment of the present invention, a trimming register (11) capable of storing a trimming value and an oscillation frequency are changed according to the trimming value in the trimming register. An oscillator (12) and a correction circuit (20) capable of correcting the oscillation frequency of the oscillator are included. The correction circuit divides the oscillation frequency of the oscillator, and an upper limit value register (6) capable of setting an upper limit value for frequency trimming, a lower limit value register (7) capable of setting a lower limit value for frequency trimming. And a counter (3) that counts the output of the frequency divider circuit. Further, the correction circuit includes a buffer register (4) capable of holding the output of the counter, and a holding value of the buffer register between the holding value of the upper limit register and the holding value of the lower limit register. A comparator (5) for determining whether or not there is a trimming value, and a trimming value correction control circuit (8) for correcting the trimming value of the trimming register based on the determination result of the comparator.

  According to the above configuration, since the trimming value is corrected by the trimming value correction control circuit 8 after the upper limit value and the lower limit value are set, the transmission frequency can be stabilized. A user of the semiconductor device can arbitrarily set an allowable range of oscillation frequency fluctuation in the oscillator according to the application. This setting is easy because it is only necessary to set the upper limit value and the lower limit value in the upper limit register and the lower limit register, respectively.

  [2] The semiconductor device according to [1] includes a non-volatile memory (18, 19) that holds a trimming value of the oscillation frequency of the oscillator, and in the power-on reset process, the holding value of the non-volatile memory is the trimming value. It can be configured to be written to a register.

  [3] In the above [2], when the trimming value of the trimming register is corrected by the trimming value correction circuit, the trimming value in the nonvolatile memory (19) is updated with the corrected trimming value. It can be constituted as follows. As a result, the initial value of the trimming register after the power-on reset process is the trimming value immediately before the previous power-off, so the time until the oscillation frequency stabilizes after the power is turned on to the semiconductor device is reduced. Can do.

2. Details of Embodiments Embodiments will be further described in detail.

Embodiment 1
FIG. 1 shows a configuration example of a microcomputer as an example of a semiconductor device according to the present invention.

  The microcomputer 21 shown in FIG. 1 is not particularly limited, but is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

  1 includes an OCO frequency trimming register 11, an OCO (On-Chip Oscillator) 12, a SUB clock oscillator 14, a CPU (Central Processing Unit) 16, a RAM (Random Access Memory) 17, and a ROM. (Read Only Memory) 18 and an OCO frequency automatic correction circuit 20 are included. The OCO frequency trimming register 11, the CPU 16, the RAM 17, the ROM 18, and the OCO frequency automatic correction circuit 20 are coupled to each other via the internal data bus 15 so that signals can be exchanged.

  The OCO frequency trimming register 11 holds a trimming value of the OCO frequency. The OCO 12 is an oscillator whose oscillation frequency is changed according to the trimming value in the OCO frequency trimming register 11. The SUB clock oscillator 14 generates a SUB clock (reference clock) of 32 [kHz]. Since this 32 [kHz] SUB clock is formed by a crystal resonator externally attached to the microcomputer 21, the frequency is stable. The SUB clock signal generated by the SUB clock oscillator 14 is supplied to the OCO frequency automatic correction circuit 20. The CPU 16 executes a predetermined calculation process by executing a preset program. The RAM 17 is used as a work area for arithmetic processing in the CPU 16. The ROM 18 is a non-volatile memory, and the ROM 18 stores a program executed by the CPU 16 and an OCO trimming register value. The OCO trimming register value in the ROM 18 is written before the microcomputer 21 is shipped from the factory. The OCO trimming register value in the ROM 18 is set as the initial value in the OCO frequency trimming register 11 by the power-on reset process executed by the CPU 16.

  The OCO frequency automatic correction circuit 20 is not particularly limited, but includes a SUB clock dividing circuit 1, an edge selection circuit 2, a counter 3, a buffer register 4, a comparator 5, an upper limit register 6, a lower limit register 7, and trimming value correction control. A circuit 8, a flag status register 9, a trimming value correction control register 10, and an OCO frequency dividing circuit 13 are included. The SUB clock dividing circuit 1 divides the SUB clock signal output from the SUB clock oscillator 14. When the period of the SUB clock signal is φ, the divided outputs of the SUB clock frequency dividing circuit 1 are, for example, φ, φ / 32, φ / 128, φ / 1024, φ / 8192. The edge selection circuit 2 forms a measurement clock signal SCK for controlling the counting operation of the counter 3 based on the output of the SUB clock frequency dividing circuit 1. The measurement clock signal SCK is formed based on one of the rising edge, the waveform falling edge, and both the waveform rising and falling edges of the output waveform of the SUB clock divider circuit 1. The OCO divider circuit 13 divides the OCO clock signal output from the OCO 12. When the cycle of the OCO clock signal is φ, the frequency-divided outputs of the OCO frequency dividing circuit 13 are, for example, φ, φ / 2, φ / 4, φ / 8, and φ / 40. The frequency-divided output of the OCO frequency dividing circuit 13 is supplied to an internal circuit in the microcomputer 21. The counter 3 counts the output of the OCO frequency dividing circuit 13 based on the measurement clock signal SCK formed by the edge selection circuit 2 when the clock monitoring enable signal CKN is enabled. The clock monitoring enable signal CKN can be formed by the CPU 16. The buffer register 4 holds the count value of the counter 3. When the count value is held in the buffer register 4, the counter 3 is cleared and the next measurement is started. The upper limit register 6 holds an upper limit value for frequency trimming. The lower limit register 7 holds a lower limit value for frequency trimming. The upper limit value and the lower limit value for frequency trimming can be set by the CPU 16. The comparator 5 determines whether or not the holding value of the buffer register 4 is between the holding value of the upper limit register 6 and the holding value of the lower limit register 7. The trimming value correction control circuit 8 controls the correction of the trimming value in the OCO frequency trimming register 11 based on the determination result in the comparator 5. The trimming value correction control circuit 8 does not correct the trimming value when the holding value of the buffer register 4 is between the holding value of the upper limit register 6 and the holding value of the lower limit register 7. The trimming value correction control circuit 8 corrects the trimming value in the OCO frequency trimming register 11 so as to lower the OCO frequency when the holding value of the buffer register 4 is larger than the holding value of the upper limit value register 6. The trimming value correction control circuit 8 corrects the trimming value in the OCO frequency trimming register 11 so as to increase the OCO frequency when the holding value of the buffer register 4 is smaller than the holding value of the lower limit value register. The flag status register 9 holds the state of the frequency normal flag, the upper limit over flag, and the lower limit unachieved flag. When the holding value of the buffer register 4 is larger than the holding value of the upper limit value register 6, the trimming value correction control circuit 8 sets the upper limit over flag in the flag status register 9. When the holding value of the buffer register 4 is smaller than the holding value of the lower limit value register 7, the trimming value correction control circuit 8 sets the lower limit unachieved flag in the flag status register 9. The CPU 16 can monitor the state of the upper limit over flag and the state of the lower limit unachieved flag via the internal data bus 15. A trimming value correction control signal (command) is set in the trimming value correction control register 10. This trimming value correction control signal is set by the CPU 16 via the internal data bus 15. The operation of the trimming value correction control circuit 8 is controlled by a trimming value correction control signal set in the trimming value correction control register 10.

  Next, the operation of the above configuration will be described.

  FIG. 2 shows a flow of main operations in the microcomputer 21 shown in FIG. 3 and 4 show the operation timing of the main part of the microcomputer 21 shown in FIG.

  In this example, a case where ± 1.0 [%] is guaranteed for 40 [MHz] will be described.

  The CPU 16 sets the upper limit register 6 and the lower limit register 7 (201). Values corresponding to 40 [MHz] ± 0.75 [%] are stored as the upper limit value and the lower limit value. The reason of ± 0.75 [%] is that a margin is provided for ± 1.0 [%]. When the CPU 16 sets the clock monitor enable signal CKN to the high level, the count operation in the counter 3 is started (202). Each time the measurement clock signal SCK is formed by the edge selection circuit 2, the count value of the counter 3 is held in the buffer register 4 and compared with the upper limit value and the lower limit value in the comparator 5 (203 to 205). ). In the case of this example, 40 [MHz] clock is measured based on the 32 [kHz] reference clock, so the count number in the counter 3 is ideally 1 / 32k ÷ (1 / 40M) ≈1250. It is said. In this example, the upper limit value is 1260 (≈40.3 [MHz]), and the lower limit value is 1240 (≈39.7 [MHz]).

  When the held value of the buffer register 4 is larger than the upper limit value and smaller than the lower limit value (206), it is set in an illegal state (207), and reset or predetermined interrupt processing by the CPU 16 is performed (208).

  As shown in FIG. 4, when the oscillation frequency of the OCO 12 is equal to or lower than the lower limit value (39.7 [MHz]), that is, when the holding value of the buffer register 4 is smaller than the upper limit value and smaller than the lower limit value. (209), the trimming value correction control circuit 8 sets a lower limit unachieved flag (210). As a result, the trimming value of the OCO frequency trimming register 11 is corrected so as to increase the oscillation frequency in the OCO 12, and the oscillation frequency is raised by switching the trimming tap of the OCO frequency trimming register 11 (211).

  As shown in FIG. 3, when the oscillation frequency of the OCO 12 is equal to or higher than the upper limit value (40.3 [MHz]), that is, when the holding value of the buffer register 4 is larger than the upper limit value and larger than the lower limit value. (212), the trimming value correction control circuit 8 sets the upper limit over flag in the flag status register 9 (213). As a result, the trimming value of the OCO frequency trimming register 11 is corrected so as to lower the oscillation frequency in the OCO 12, and the oscillation frequency is lowered by switching the trimming tap in the OCO 12 (214).

  When the holding value of the buffer register 4 is smaller than the upper limit value and larger than the lower limit value (215), the frequency normality flag is set by the trimming value correction control circuit 8 (216). In this case, trimming value correction is not performed.

  The microcomputer 21 can be applied to a control device for automobiles, a control device for home appliances, etc., and the user can arbitrarily set the allowable range of oscillation frequency fluctuations in the built-in oscillator 12 according to the application. it can. This setting is easy because it is only necessary to set the upper limit value and the lower limit value in the upper limit register 6 and the lower limit register 7 through the CPU 16, respectively. After the upper limit value and the lower limit value are set, the trimming value correction control circuit 8 corrects the trimming value of the OCO frequency, so that the OCO frequency can be stabilized.

<< Embodiment 2 >>
FIG. 5 shows another configuration example of a microcomputer as an example of a semiconductor device according to the present invention. The microcomputer 21 shown in FIG. 5 is greatly different from that shown in FIG. 1 in that a flash memory is provided in place of the ROM 18. The flash memory is a kind of EEPROM (Electrically Erasable Programmable Read-Only Memory) and is a nonvolatile memory capable of rewriting stored information. The flash memory 19 stores a program executed by the CPU 16 and an OCO trimming register value. Further, in this example, when the trimming value in the OCO frequency trimming register 11 is corrected by the trimming value correction control circuit 8, the trimming value in the flash memory 19 is updated by the corrected trimming value in the OCO frequency trimming register 11. Is done. This update is performed under the control of the CPU 16. Even when the power of the microcomputer 21 is shut off, the flash memory 19 holds the trimming value in the OCO frequency trimming register 11 immediately before the power is shut off. When the microcomputer 21 is turned on next time, the trimming value in the flash memory 19 is written to the OCO frequency trimming register 11 in the power-on reset process executed by the CPU 16. As a result, the initial value of the OCO frequency trimming register 11 after the power-on reset process is the trimming value immediately before the previous power shutdown. Therefore, as in the microcomputer 21 shown in FIG. 1, the time until the oscillation frequency is stabilized after the power is turned on can be shortened compared to the case where the trimming value set before factory shipment is used as the initial value. Can be planned.

  As mentioned above, although the invention made by this inventor was concretely demonstrated based on embodiment, it cannot be overemphasized that this invention is not limited to it and can be variously changed in the range which does not deviate from the summary.

DESCRIPTION OF SYMBOLS 1 SUB clock dividing circuit 2 Edge selection circuit 3 Counter 4 Buffer register 5 Comparator 6 Upper limit register 7 Lower limit register 8 Trimming value correction control circuit 9 Flag status register 10 Trimming value correction control register 11 OCO frequency trimming register 12 OCO
13 OCO Divider Circuit 14 SUB Clock Oscillator 15 Built-in Data Bus 16 CPU
17 RAM
18 ROM
19 Flash memory

Claims (3)

A trimming register capable of storing trimming values;
An oscillator whose oscillation frequency is changed according to the trimming value in the trimming register;
A correction circuit capable of correcting the oscillation frequency of the oscillator,
The correction circuit is
An upper limit register that can set an upper limit for frequency trimming;
A lower limit register that can set a lower limit for frequency trimming;
A frequency dividing circuit for dividing the oscillation frequency of the oscillator;
A counter that counts the output of the divider circuit;
A buffer register capable of holding the output of the counter;
A comparator for determining whether the holding value of the buffer register is between the holding value of the upper limit register and the holding value of the lower limit register;
A semiconductor device comprising: a trimming value correction control circuit that corrects a trimming value of the trimming register based on a result of determination by the comparator.   The semiconductor device according to claim 1, wherein the semiconductor device includes a non-volatile memory that holds a trimming value of an oscillation frequency of the oscillator, and the holding value of the non-volatile memory is written to the trimming register by a power-on reset process.   3. The semiconductor device according to claim 2, wherein when the trimming value in the trimming register is corrected by the trimming value correction circuit, the trimming value in the nonvolatile memory is updated with the corrected trimming value.

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