JP2000268019A - Semiconductor integrated circuit with built-in non- volatile memory circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable the write and erasure of a memory by forming a write pulse or erase pulse having an exact pulse width even when an oscillation frequency is dispersed by a process dispersion in the semiconductor integrated circuit of a microcomputer or the like with built-in non-volatile memory circuit and oscillator. SOLUTION: The semiconductor integrated circuit of the microcomputer or the like with built-in non-volatile memory circuit and oscillator is provided with trimming circuits capable of regulating the oscillation frequency of an internal oscillator(OSC), a first counter 31 for counting the oscillation frequency of the oscillator, a second counter 32 for counting a clock supplied from the outside or clock derived from that clock and a frequency measuring means (CPU 34) for comparing the count value of the first counter with the count value of the second counter and discriminating one frequency from the other frequency.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique which is effective when applied to setting of a writing time and an erasing time (pulse width) of an electrically writable and erasable nonvolatile memory circuit. The present invention relates to a technology that is effective when used in a microcomputer having a built-in flash memory capable of erasing data.

[0002]

2. Description of the Related Art A flash memory uses a nonvolatile memory element having a control gate and a floating gate as a memory cell, and the memory cell can be constituted by one transistor. In such a flash memory, in a write operation, a voltage of, for example, 6.7 V (volt) is applied to the drain region of the nonvolatile memory element, and a write of, for example, -10.0 V is applied to the word line to which the control gate is connected. By applying a pulse, charges are extracted from the floating gate to the drain region, and the threshold voltage is set to a low state (logic "0"). In the erasing operation, the source region and the base (well region) are set to, for example, -10.0 V, a high voltage pulse such as 10.5 V is applied to the control gate, and negative charges are injected into the floating gate. The threshold is set to a high state (logic "1"). Thus, one bit of data is stored in one storage element.

[0003]

In a flash memory, it is necessary to control a pulse applied to a storage element during a write operation or an erase operation so as to have a predetermined pulse width depending on the characteristics of the element. Such a pulse is configured such that a write pulse or an erase pulse having an optimum pulse width is formed and applied by a maker in a flash memory having a sequencer for internally executing a write process or an erase process. In an LSI such as a microcomputer with a built-in flash memory that does not have such a sequencer, a writing process, an erasing process, and the like are executed by software.

[0004] However, when the writing and erasing processes are executed by software, the pulse width is set by a soft timer, so that if the operating frequency of the LSI is different, the pulse width will be different in the same program.
Therefore, it is necessary to create a write program and an erase program for each operating frequency.

In some cases, a microcomputer having a built-in flash memory has a built-in oscillator for generating an internal clock. However, the oscillation frequency of the internal oscillator varies due to process variations. As a result, it has been clarified that there is a problem that an accurate write pulse or erase pulse cannot be formed.

An object of the present invention is to form a write pulse or an erase pulse having a desired pulse width by the same program even if the operating frequency is different in a semiconductor integrated circuit such as a microcomputer having a built-in nonvolatile memory circuit. An object of the present invention is to enable writing and erasing of a memory.

Another object of the present invention is to provide a semiconductor integrated circuit such as a microcomputer having a built-in non-volatile memory circuit and an oscillator, in which a write pulse or an erase pulse having an accurate pulse width is obtained even if the oscillation frequency varies due to process variations. Formed so that writing and erasing of the memory can be performed.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

The following is a brief description of an outline of typical inventions disclosed in the present application.

That is, in a semiconductor integrated circuit such as a microcomputer incorporating a nonvolatile memory circuit and an oscillator, a trimming circuit capable of adjusting the oscillation frequency of an internal oscillator, a first counter for counting the oscillation frequency of the oscillator, and an external A second counter for counting a clock supplied from the second counter or a clock derived therefrom, and a frequency measurement for comparing the count value of the first counter and the count value of the second counter to determine one frequency from the other frequency Means is provided.

According to the above means, an accurate clock whose frequency is known is input from the outside while counting by the first counter while operating the oscillator and counting is performed by the second counter to compare the frequency. In addition, it is possible to detect a shift in the frequency of the internal oscillator and adjust the trimming circuit according to the shift amount. After the oscillation frequency of the internal oscillator is adjusted by the trimming circuit, even if an operation clock whose frequency is unknown from the outside is input, the operation clock is counted by the second counter, and the first operation of counting the oscillation frequency of the oscillator is performed. A semiconductor integrated circuit that operates on clocks having different frequencies by comparing the count value of the counter with the frequency of the operation clock and determining the number of executions of the memory write routine and erase routine by calculating or referring to a table. Even with a circuit, accurate writing and erasing can be executed by the same program.

The frequency deviation of the internal oscillator detected by the frequency measuring means is stored in an external memory, set in an internal register or the like at the time of initial setting, and reflected in a trimming circuit. May be corrected.However, an area for storing the detected deviation amount of the frequency of the internal oscillator or a correction value determined according to the deviation amount is provided, and the internal sequence is automatically performed when the power is turned on. It is desirable to read the shift amount or the correction value and correct the frequency.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to a microcomputer having a built-in flash memory (hereinafter referred to as a flash microcomputer) will be described below with reference to the drawings. FIG. 1 shows a schematic configuration of a flash microcomputer to which the present invention is applied. Although not particularly limited, each circuit block shown in FIG. 1 is formed on one semiconductor chip such as single crystal silicon.

In FIG. 1, FLASH is a memory circuit comprising a memory array in which memory cells as nonvolatile storage elements each comprising a MOSFET having a floating gate are arranged in a matrix and a memory peripheral circuit such as an address decoder for selecting a memory cell. FLC is a flash controller for writing, erasing, and trimming the flash memory circuit, CPU is a central processing unit that controls the entire chip, and RAM is a random access memory that temporarily stores data and provides a work area for the central processing unit CPU. , PRP is CPU such as A / D conversion circuit
Peripheral circuits, I / Os are input / output circuits for inputting and outputting signals to and from the outside, BUS is a bus connecting the central processing unit CPU and the flash memory circuits FLASH, RAM, I / O, and DVD is supplied from the outside. A frequency dividing and multiplying circuit that divides the reference clock φc to form an operation clock signal CLK necessary for the operation of the system inside the chip. In addition,
The CPU is integrally provided with a bus controller for controlling the occupation right of the bus BUS and the like.

In this embodiment, in addition to the above-mentioned circuit block, a trimming circuit is provided so as to be capable of adjusting the oscillation frequency, and a clock RCLK for defining the pulse width of a write pulse and an erase pulse required in the flash memory circuit FLASH. Oscillator OSC that generates
A frequency measurement circuit FDC is provided which compares the clock RCLK generated by the SC with the operation clock CLK supplied from the frequency division / multiplication circuit DVD to determine one frequency from the other.

Although not shown in FIG. 1, in the case of a microcomputer such as a single-chip microcomputer, the CPU peripheral circuit PRP has an internal memory and an external memory in addition to an A / D conversion circuit. DMA transfer control circuit for controlling DMA (Direct Memory Access) transfer to / from the CPU, an interrupt control circuit for determining the generation of an interrupt request to the CPU and determining the priority, and performing an interrupt, and performing serial communication with an external device A serial communication interface circuit, various timer circuits, a watchdog timer for system monitoring, and the like are provided as necessary.

In this embodiment, a frequency divider / multiplier circuit DVD for dividing an externally supplied clock to form an operation clock signal CLK necessary for the operation of a system inside the chip.
However, it is also possible to use the clock supplied from the outside as the operation clock as it is.

FIG. 2 shows the flash memory circuit FL
The schematic configuration of the ASH is shown. In FIG. 2, 11
Is a memory array in which memory cells as nonvolatile storage elements each composed of a MOSFET having a floating gate are arranged in a matrix, 12 is a data register for holding externally input write data, and 13 is held in the data register 12. A writing circuit for writing data to the memory array 11 based on the data.

An address register 14 holds an address signal, and an X decoder 15 selects one word line corresponding to the X address taken into the address register 14 from the word lines in the memory array 11. ,
Reference numeral 16 denotes a Y decoder for decoding the Y address taken into the address register 14 and selecting one byte (or one word) of data in one sector, and 17 an erasure for selecting a block (mat) at the time of erasure. Control circuit, 1
Reference numeral 8 denotes a sense amplifier that amplifies and outputs data read from the memory cell array 11.

Further, the flash memory circuit of this embodiment includes, in addition to the above-described circuit blocks, a control circuit 27 for forming an operation timing control signal for each circuit in the flash memory in accordance with a control signal from the CPU; An I / O buffer circuit 23 for inputting / outputting a signal, a write voltage based on a power supply voltage Vcc externally supplied,
A power supply circuit 25 that generates voltages required inside the chip such as an erase voltage, a read voltage, and a verify voltage. A desired voltage is selected from these voltages according to the operation state of the memory and supplied to the memory array 11. A power supply switching circuit 26 and the like are provided.

In a general flash memory chip and some flash microcomputers, when a write command or an erase command is input from an external or internal CPU, it is decoded and a power supply switching circuit, a decoder circuit, and the like are operated according to a predetermined sequence. A control circuit (sequencer) is provided to control and form an optimum write pulse or erase pulse to execute writing, erasing, etc. In the flash microcomputer chip of this embodiment, the flash memory FLASH
Is provided with a control circuit 27 that generates a simple timing signal, and is configured so that the CPU executes functions such as control of the number of application of the write pulse and write verification according to a program stored in the RAM. As a result, the circuit scale is small, and the chip size can be reduced.

FIG. 3 shows a configuration example of the frequency measurement circuit FDC. Frequency measuring circuit FD of this embodiment
C is a first counter 31 for counting the oscillation clock RCLK from the oscillator OSC, and a frequency dividing / multiplying circuit DVD
Counting the operation clock signal CLK supplied from the
Counter 32, a measurement result storage register 33 that holds the count value when the second counter 32 is stopped, and controls the start of oscillation of the oscillator OSC and the end of counting of the first and second counters 31 and 32. And a frequency measurement controller 34 for performing the operation.

The frequency measurement controller 34 has a module control register MCR having a bit MFST for instructing the oscillator OSC to start oscillating and a bit CSTP for notifying that the first and second counters 31 and 32 have completed counting. And a trimming register TRMR for holding a trimming value for adjusting the oscillation frequency of the oscillator OSC.

The measurement result storage register 33, the module control register MCR, and the trimming register T
The RMR is connected to the internal bus BUS, and is configured so that the CPU can freely read and set the value of each register. When the bit MFST is set to "1", the module control register MCR outputs an oscillation start signal MFST to the oscillator OSC. The counting start signal is delayed by the delay circuit DLY and is supplied to the first and second counters 31 and 32 as the counting start signal MFSS. The reason why the operation start timings of the oscillator OSC and the first and second counters 31 and 32 are shifted is that the oscillation frequency of the oscillator immediately after the start of operation is not stable.

FIG. 4 shows a specific example of an oscillator OSC capable of trimming the oscillation frequency. The oscillator according to this embodiment includes a ring oscillator in which a plurality of inverters G0, G1,... Gn are connected in cascade, and the output of the last-stage inverter Gn is connected back to the input terminal of the first-stage inverter G1. It is configured. A switch MO is connected to the output terminals of the inverters G0 to Gn-1.
Capacitor C via SFETs S1, S2,..., Sn
1, C2... Cn are connectable.

These switch MOSFETs S1, S
2,... The trimming register T is connected to the gate terminal of Sn.
The set values FR1 to FRn of RMR are applied, the corresponding switch MOSFET is turned on, and the capacitive element is selectively connected. As a result, the larger the connected capacitance, the longer the delay time of the entire ring oscillator and the lower the oscillation frequency.

Table 1 shows the setting values FR1, FR2, FR3 of the trimming register TRMR when there are four capacitive elements.
An example of the relationship between FR4 and the oscillation frequency of the ring oscillator is shown. Table 1 shows the case where the capacitance values of the capacitance elements C1 to C4 are set equal. If it is desired to increase the adjustment range and the number of steps, the capacitance values of the capacitance elements C1 to C4 may be weighted by 2 n.

[0028]

[Table 1] In the oscillator of the embodiment shown in FIG. 4, the power supply voltage and the ground potential can be supplied and cut off via the power switch MOSFETs Q1 and Q2. Is provided with an OR gate G10 which receives an oscillation start signal MFST from the module control register MCR and a system start signal STR as input signals, and supplies a power supply voltage when one of the signals is set to a high level. Then oscillation starts.

Further, the oscillator of this embodiment is configured to be driven by the voltage Vcc1 from the voltage generation circuit 40 which has no dependency on the power supply voltage. Thus, a stable oscillation frequency can be obtained even if the power supply voltage fluctuates. The voltage generation circuit 40 includes a reference voltage generation circuit 41, an operational amplifier 42 to which a reference voltage Vref such as 2.5 V generated by the reference voltage generation circuit 41 is input to a non-inverting input terminal (+), MOSFET Q10 having an output voltage of 42 applied to its gate;
Q10 and resistors R1 and R2 connected in series,
The voltage divided by the resistors R1 and R2 is input to the inverting input terminal (-) of the operational amplifier 42.

As a result, the voltage generation circuit 40
When the power supply voltage Vcc decreases, the current flowing through the resistors R1 and R2 decreases, the voltage fed back to the inverting input terminal (-) of the operational amplifier 42 decreases, the output voltage of the operational amplifier 42 increases, and the gate voltage of the MOSFET Q10 increases. As a result, the drain current increases to act to increase the current flowing through the resistors R1 and R2. That is, a stable voltage can be generated regardless of the fluctuation of the power supply voltage Vcc. As a result, the oscillation frequency of the oscillator OSC can be made constant irrespective of the fluctuation of the power supply voltage.

FIG. 5 shows a configuration example of the first counter 31. 5 includes a counter unit CNT in which a plurality of flip-flops FF1, FF2,... FFm are connected in cascade, and a flip-flop FF1.
A stop signal output portion STG including a NOR gate G21 having an input of the output of FFn and an inverter G22 for inverting the output thereof, and an oscillation clock R of the oscillator OSC.
And a pulse forming section PSG for detecting a rise and a fall of CLK to form a pulse signal having a predetermined pulse width. The reset terminal of each flip-flop constituting the counter unit CNT has the oscillation start signal MF
A signal MFSS obtained by delaying ST by a delay circuit DLY is input. When the signal MFSS is set to a low level, the reset is released, and each flip-flop can take in an output signal of a previous stage, and a counter unit. Starts the counting operation.

The counter 31 of this embodiment is provided with a stop signal CSTP after the signal MFSS becomes low level depending on the number of flip-flops constituting the counter unit CNT.
Is changed to the low level. Therefore, the counter 31 is set so that a desired measurement time Tcnt is obtained from the relationship with the oscillation frequency of the oscillator OSC.
May be determined by determining the number of stages of the flip-flops constituting.

In the counter 31 of this embodiment, the pulse synchronized with the rising edge of the oscillation clock RCLK and the pulse synchronized with the falling edge of the oscillation clock RCLK formed by the pulse forming unit PSG are respectively the odd-numbered flip-flop and the even-numbered number of the counter unit CNT. The flip-flop is configured to be inputted to the set terminal of the flip-flop so that the racing can be avoided without using the flip-flop in a master-slave configuration.

FIG. 6 shows a configuration example of the second counter 32. The counter 32 shown in FIG. 6 includes 16 cascade-connected JK flip-flops, a NAND gate G30 which receives the count stop signal CSTP output from the first counter 31 and the internal operation clock CLK as inputs.
The output signal of the NAND gate G30 is input to the trigger terminal T of the first-stage flip-flop. Further, the J terminal and the K terminal are fixed to the power supply voltage Vcc, and the reset state is released by turning the count start signal MFSS, which is commonly input to the reset terminal of each flip-flop, to the low level, and the NA is reset.
Operation clock CL supplied via ND gate G30
An operation of counting the number of K pulses is performed. NAND gate G3
0 is a count stop signal C output from the first counter 31
When the STP is set to the low level, the operation clock CLK is cut off, so that the count value of the counter 32 is not further increased, and the count value at the time of the stop is held in the measurement result storage register 33.

Next, a method of adjusting the oscillation frequency using the oscillator OSC and the frequency measurement circuit FDC will be described with reference to FIG.

In order to adjust (trim) the oscillation frequency of the oscillator OSC, first, a reference clock φc having a known frequency is supplied to the frequency dividing / multiplying circuit DVD from outside the chip. Then, the dividing / multiplying circuit DV
D frequency-divides the reference clock φc to form an internal operation clock signal CLK having a predetermined frequency,
To supply. In addition, the frequency measurement circuit FDC is provided by the CPU.
M of the module control register MCR in the
Set "1" to FST. Then, the oscillation start signal MFST is supplied from the module control register MCR to the oscillator OSC, and the oscillator starts oscillating.

Then, the start signal MFSS delayed by the delay circuit DLY is supplied to the counters 31 and 32 to start counting operations (at timing t in FIG. 7).
1). In this embodiment, the second counter 32 is configured not to overflow before the first counter 31 counts up.
When the oscillation clock RCLK from C reaches a predetermined number, a count-up signal is output. This signal is supplied to the second counter 32 as the count stop signal CSTP, the counting operation is stopped, and the count value at the time of the stop is held in the measurement result storage register 33 (at timing t in FIG. 7).
2).

Here, the count end value of the first counter 31 is uniquely determined by the number of bits (the number of flip-flop stages) (however, it can be arbitrarily set by using a load type counter). Therefore, the frequency of the internal operation clock signal CLK formed based on the reference clock φc supplied from the outside is f2, the count-up value of the first counter 31 is CN1, and the second counter 32 is stopped after starting counting. If the count value up to is CN2,
Since f2 and CN1 are known in advance, the frequency f1 of the oscillator OSC is calculated from the count value of the second counter 32 by f
1 = (CN1 / CN2) · f2. The count stop signal CSTP is also configured to be supplied to a CPU or the like. The CPU immediately reads the value of the second counter 32 as soon as the count stop signal CSTP comes in, and reads the oscillation frequency from the above arithmetic expression. f1 can be calculated.

Thus, the oscillator OS inside the chip is
When the oscillation frequency of C is known, the trimming register TRMR is referred to a table showing the relationship between the oscillation frequency RCLK and the trimming values FR1 to FR4 as shown in Table 1 prepared in advance. The trimming values FR1 to FRn to be set are determined. Then, when the determined trimming values FR1 to FRn are set in the trimming register TRMR, the switch MO in the oscillator OSC is set.
The switches corresponding to the set values FR1 to FRn among the SFETs S1 to Sn are turned on, and the frequency is adjusted by connecting the capacitance element to the ring oscillator as a load capacitance. As a result, in the control circuit of the flash memory FLASH receiving the supply of the oscillation clock RCLK,
A highly accurate write pulse or erase pulse can be formed, and variation in the threshold value of the memory element after writing or erasing can be reduced to improve the reliability of the memory.

The operation according to the above procedure is performed by using the R in the chip.
It can be easily realized by storing the frequency adjustment program in the AM and causing the CPU to execute the program. It is desirable that such oscillation frequency measurement be performed at the final stage of manufacturing on the manufacturer side, and that the trimming value determined be stored at a predetermined address of the flash memory FLASH and provided to the user, for example.

Further, a program for adjusting the frequency using the trimming value is provided to the user as an initialization program or is incorporated in the user program.
Then, the initialization program is executed when the user system starts up, and the internal flash memory FLA is started.
The trimming value stored in the SH is read out and set in the trimming register TRMR in the frequency measuring circuit FDC to adjust the frequency of the built-in oscillator OSC, so that the oscillator can automatically oscillate at a desired frequency. .

Next, a description will be given of a method of measuring the frequency of the internal operation clock using the oscillator OSC and the frequency measurement circuit FDC, and an operation procedure of writing and erasing data in the flash memory using the measurement result.

When the flash microcomputer incorporating the oscillator whose frequency is adjusted by the above-described method is used in a user system, an operation clock of an arbitrary frequency is used by the user within an operation guarantee range. The flash microcomputer of the present embodiment can detect the frequency of the operation clock by executing the frequency measurement program of the operation clock that operates according to the procedure described below.
By performing the writing operation and the erasing operation according to the flowchart shown in FIG. 8 or FIG. 9, writing and erasing can be performed with optimal writing and erasing pulses.

The method of measuring the frequency of the internal operation clock CLK in the flash microcomputer of this embodiment is almost the same as the method of adjusting the oscillation frequency. That is, in a state where the reference clock φc is externally input to the frequency dividing / multiplying circuit DVD, the CPU measures the frequency measuring circuit FD.
"1" is set to the bit MFST of the module control register MCR in C. Then, the oscillation start signal MFST is supplied from the module control register MCR to the oscillator OSC, and the oscillator starts oscillating.

Then, the start signal MFSS delayed by the delay circuit DLY is supplied to the counters 31 and 32 to start counting operations (at timing t in FIG. 7).
1). When the first counter 31 counts the oscillation clock RCLK from the oscillator OSC and reaches a predetermined number, a count-up signal is output. This signal is the count stop signal CS
The count value is supplied to the second counter 32 as TP, and the counting operation is stopped.
3 (timing t2 in FIG. 7).

Here, an internal operation clock signal CLK formed based on a reference clock φc supplied from the outside.
Is f2, the count-up value of the first counter 31 is CN1, and the count value from when the second counter 32 starts counting until it stops is CN2, since f1 and CN1 are known in advance, the internal operation The frequency f2 of the clock signal CLK is calculated from the count value of the second counter 32 by f2
= (CN2 / CN1) · f1.

The count stop signal CSTP is also configured to be supplied to a CPU or the like.
By reading the value of the counter 32, the frequency f2 of the internal operation clock signal CLK can be calculated by the above equation. Also, the frequency f2 of the internal operation clock signal CLK
, The number of wait loops in the write processing routine and the erase routine required to form the write pulse and the erase pulse having the optimum pulse width can be determined based on this.

It is desirable that the calculated frequency f2 of the internal operation clock signal CLK or the determined number of times of the wait loop be stored in a RAM or a flash memory FLASH in the chip. This eliminates the need to measure the operating frequency and determine the number of wait loops every time a write operation or an erase operation is performed. This corresponds to steps S11, S12 and S2 in the flowcharts of FIGS.
1, the operation frequency measurement and wait loop number determination processing in S22 are performed at the time of system startup, reset, or when a predetermined interrupt occurs, and at the time of individual writing processing or erasing processing, the operating frequency stored in the memory or This can be realized by configuring a program to read the number of wait loop times.

The determined or read number of times of the wait loop is used in the pulse application routines of steps S14 and S24 in the flowcharts of FIGS. 8 and 9, and is performed by repeating the designated wait loop. Even in systems with different operating clock frequencies, write pulses and erase pulses having the same pulse width can be formed and applied to the selected memory element.

In the write operation, write verify is performed after the application of the write pulse to determine whether the write is completed (step S15 in FIG. 8). In the erase operation, erase verify is performed after the application of the write pulse to determine whether the erase is completed. (Step S25 in FIG. 9), if not completed, the application of the pulse is repeated until the number of times of writing or erasing is exceeded, respectively (steps S16 and S2).
6).

Step S in the flowchart of the write operation
The reason why the rewriting data operation is performed in step 17 is to prevent the threshold value from excessively lowering due to excessive writing by applying a writing pulse again only to the memory element not reaching the predetermined threshold value. is there. In the case of erasing, there is no problem that the threshold value is excessively raised due to excessive erasing as in the case of writing. Has been avoided.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, even in the flash memory of the above embodiment, the threshold value of the storage element is increased by the erase operation and the threshold value of the storage element is decreased by the write operation. A type in which the threshold value is increased may be used.

In the embodiment, the trimming value of the oscillator is also determined by the internal CPU based on the count value of the second counter provided in the flash microcomputer in the frequency measurement mode. The trimming value of the internal oscillator may be determined externally by reading the count value of the counter to the outside.

In the above description, the case where the invention made by the present inventor is mainly applied to a microcomputer having a built-in flash memory, which is the field of application, has been described. However, the present invention is not limited to this. Therefore, it can be widely used for a semiconductor integrated circuit having a built-in nonvolatile memory and an oscillator.

[0055]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, according to the present invention, even if the operating frequency is different, a write pulse or an erase pulse having a desired pulse width can be formed by the same program to perform writing and erasing of the memory, and oscillation due to process variation. A semiconductor integrated circuit such as a microcomputer having a built-in nonvolatile memory circuit capable of writing and erasing a memory by forming a writing pulse or an erasing pulse having an accurate pulse width even when the frequency varies can be obtained.

[Brief description of the drawings]

FIG. 1 is an overall block diagram schematically showing an embodiment of a microcomputer with a built-in flash memory to which the present invention is applied.

FIG. 2 is a block diagram illustrating a configuration example of a flash memory circuit unit.

FIG. 3 is a block diagram illustrating a configuration example of a clock frequency measurement circuit.

FIG. 4 is a circuit configuration diagram illustrating a configuration example of an oscillator including a frequency trimming circuit.

FIG. 5 is a circuit configuration diagram showing a configuration example of a first counter.

FIG. 6 is a circuit configuration diagram showing a configuration example of a second counter.

FIG. 7 is a timing chart showing an example of signal timing when measuring a clock frequency in the frequency measurement circuit of the embodiment.

FIG. 8 is a flowchart showing an example of a procedure for writing data to a flash memory in a flash microcomputer to which the present invention is applied.

FIG. 9 is a flowchart showing an example of a data erase procedure of a flash memory in a flash microcomputer to which the present invention is applied.

[Explanation of symbols]

 Reference Signs List 11 memory array 12 data register 13 writing circuit 14 address register 15 X decoder 17 Y decoder 25 power supply circuit 26 power supply switching circuit 31 first counter 32 second counter 33 count value holding register 34 frequency measurement control circuit OSC oscillator FDC frequency measurement Circuit TRMR Trimming value setting register

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 29/788 H01L 29/78 371 29/792 F term (Reference) 5B025 AA00 AB00 AC00 AD04 AD08 AD09 AD15 AE00 AE08 5B062 AA08 CC01 DD06 DD10 HH01 HH04 5F001 AE02 AE08 AE50 AG40 5F083 ER22 GA17 GA30 LA10 ZA13

Claims (7)

[Claims] 1. A semiconductor integrated circuit having a built-in nonvolatile memory circuit and an oscillator, a trimming circuit capable of adjusting an oscillation frequency of an internal oscillator, a first counter for counting the oscillation frequency of the oscillator, and an externally supplied counter. A second counter that counts a clock derived therefrom or a clock derived therefrom; and a frequency measurement unit that compares the count value of the first counter and the count value of the second counter to determine one frequency from the other. A semiconductor integrated circuit, comprising: 2. The semiconductor integrated circuit according to claim 1, further comprising a register for holding a trimming value for adjusting the frequency of said oscillator determined based on the frequency measured by said frequency measuring means. . 3. The semiconductor integrated circuit according to claim 2, further comprising control means for determining an oscillator adjustment trimming value based on the frequency measured by said frequency measuring means and setting the trimming value in said register. . 4. The control means has a function of setting an effective pulse width of a write pulse or an erase pulse applied to the nonvolatile memory circuit based on the frequency of the clock measured by the frequency measurement means. 4. The semiconductor integrated circuit according to claim 3, wherein: 5. A voltage generating circuit for generating a voltage independent of the power supply voltage from a power supply voltage supplied from the outside,
5. The semiconductor integrated circuit according to claim 1, wherein said oscillator is configured to oscillate by a voltage generated by said voltage generation circuit. 6. The first counter is a counter that counts a predetermined number, and is configured to stop the counting operation of the second counter when the counter has counted a predetermined number. Claims 1 and 2,
6. The semiconductor integrated circuit according to 3, 4, or 5. 7. The semiconductor device according to claim 1, further comprising a register for holding a count value of said second counter.
6. The semiconductor integrated circuit according to 2, 3, 4, or 5.