JP2013097296A - Liquid crystal display device and driving method of liquid crystal display element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve a driving method of a cholesteric liquid crystal display element and a cholesteric liquid crystal device suitable for a TFT type.SOLUTION: The liquid crystal display device has: an active matrix type liquid crystal display element 10 containing cholesteric liquid crystal material; a drive control circuit 21-23 for performing writing of applying voltage depending on display data, to pixels of the liquid crystal display element; and a temperature sensor 35 for detecting temperature of the liquid crystal display element. The drive control circuit performs the writing corresponding to the display data at least once, and the frequency of the writing of the same display data is varied according to the detected temperature of the liquid crystal display element.

Description

  The present invention relates to a liquid crystal display device and a method for driving a liquid crystal display element.

  Cholesteric liquid crystal has attracted attention as an effective method for electronic paper (especially color) because it has excellent characteristics such as semi-permanent display retention (memory property), vivid color display, high contrast, and high resolution.

  Until now, display elements using cholesteric liquid crystals have a simple matrix (passive matrix) type configuration and are generally driven by a simple matrix driving method. As described above, since the cholesteric liquid crystal display element has a memory property, the display can be maintained without supplying power except during screen rewriting, and color display can be performed with zero power consumption. It has a great feature not found in liquid crystal display elements. However, since the response speed of cholesteric liquid crystal is low, a selection of several ms to several tens of ms is required to apply a voltage sufficient for the liquid crystal on the selected line to respond when driven by a simple matrix driving method. Needed a period. For this reason, when the number of lines is 1000, it takes several seconds to several tens of seconds to rewrite the screen.

  On the other hand, a general liquid crystal display element for displaying moving images is generally an active matrix type in which a switching element such as a TFT (Thin Film Transistor) is provided in each pixel. In an active matrix display element, a voltage is applied to the liquid crystal by turning on a switching element such as a TFT provided in each pixel for several tens of μs, and then the switching element is turned off (OFF). Hold the voltage. For this reason, it is possible to maintain the data voltage that has already been applied to the pixel while writing to apply the data voltage to the pixel connected to the other gate line, greatly increasing the data voltage application time. It can be lengthened. As a result, the time required for screen rewriting can be greatly reduced.

  An active matrix type display element using a cholesteric liquid crystal has been studied in order to shorten the screen rewriting time. However, a voltage application method suitable for a cholesteric liquid crystal has not been sufficiently studied.

JP 2007-65555 A JP-A-7-199149 International Publication WO2007 / 116438 JP 2004-191837 A

  According to the embodiment, an active matrix type cholesteric liquid crystal device and a driving method of a cholesteric liquid crystal display element suitable for the active matrix type are realized.

  According to a first aspect of the invention, an active matrix liquid crystal display element including a cholesteric liquid crystal material, a drive control circuit for performing writing to apply a voltage corresponding to display data to a pixel of the liquid crystal display element, and a liquid crystal display element A temperature sensor that detects the temperature, and the drive control circuit performs writing corresponding to the display data at least once, and changes the number of times the same display data is written according to the detected temperature of the liquid crystal display element A display device is provided.

  According to a second aspect of the invention, there is provided a driving method for an active matrix liquid crystal display element containing a cholesteric liquid crystal material, wherein the temperature of the liquid crystal display element is detected and the pixel of the liquid crystal display element is responsive to display data. Provided is a method for driving a liquid crystal display element in which the number of times of writing to which a voltage is applied is determined according to the detected temperature of the liquid crystal display element, and the same data is written to the liquid crystal display element. .

  According to the embodiment, a cholesteric liquid crystal display device and a driving method of a cholesteric liquid crystal display element that perform high-quality display are realized.

FIG. 1 is a diagram schematically showing a general cross-sectional configuration of a liquid crystal display element capable of full color display using a cholesteric liquid crystal. FIG. 2 is a diagram for explaining the state of the cholesteric liquid crystal. FIG. 3 is a diagram illustrating an example of a state change of the liquid crystal in the conventional driving method. FIG. 4 is a diagram illustrating an example of a voltage waveform applied to a liquid crystal cell (pixel) and an example of a response characteristic of reflectivity when the illustrated voltage waveform is applied in the conventional driving method. FIG. 5 is a diagram illustrating a schematic configuration of the color display device according to the first embodiment. FIG. 6 is a diagram schematically showing a cross-sectional configuration of a color display element using a cholesteric liquid crystal used in the color display device of the first embodiment. FIG. 7 is a diagram illustrating a signal applied by the gate driver to the gate line, a signal applied by the data driver to one data line, and a voltage applied to the pixel corresponding to the gate line in the first embodiment. . FIG. 8 is a diagram showing a change in contrast ratio with respect to a temperature change in the blue (B) panel used in the first embodiment, with the number of writings as a parameter. FIG. 9 is a diagram illustrating a change in contrast ratio with respect to a temperature change in the green (G) panel used in the first embodiment, using the number of writings as a parameter. FIG. 10 is a diagram illustrating a change in contrast ratio with respect to a temperature change in the red (R) panel used in the first embodiment, using the number of writings as a parameter. FIG. 11 is a flowchart showing the write count determination process in the first embodiment. FIG. 12 is a diagram illustrating a schematic configuration of a color display device according to the second embodiment. FIG. 13 is a diagram showing a table used to determine the number of writes in the second embodiment. FIG. 14 is a flowchart showing the write count determination process in the second embodiment.

  Before describing embodiments of the present invention, a basic configuration of a display element using cholesteric liquid crystal will be described.

  FIG. 1 schematically shows a general cross-sectional configuration of a liquid crystal display element 10 capable of full color display using a cholesteric liquid crystal. The liquid crystal display element has a structure in which a blue (B) display unit 10B, a green (G) display unit 10G, and a red (R) display unit 10R are stacked in order from the display surface. Each display unit has the same configuration, and only the reflection center wavelength is different. In FIG. 1, the upper substrate side is a display surface, and external light (solid arrow) enters the display surface from above the substrate. Note that the observer's eyes and the observation direction (broken arrows) are schematically shown above the substrate.

  The B display unit 10B is configured to apply a predetermined pulse voltage to the upper substrate 11B, the lower substrate 13B, the blue (B) liquid crystal layer 12B sealed between the pair of upper and lower substrates, and the B liquid crystal layer 12B. Voltage source 18B. Similarly, the G display unit 10G includes an upper substrate 11G, a lower substrate 13G, a green (G) liquid crystal layer 12G, and a pulse voltage source 18G, and the R display unit 10R includes the upper substrate 11R. , A lower substrate 13R, a red (R) liquid crystal layer 12R, and a pulse voltage source 18R. A light absorption layer 17 is disposed on the back surface (lower surface) of the lower substrate 13R of the R display portion 10R.

  The cholesteric liquid crystal used in each of the B liquid crystal layer 12B, the G liquid crystal layer 12G, or the R liquid crystal layer 12R has a content of several tens wt% of a chiral additive (also called a chiral material) in the nematic liquid crystal. A liquid crystal mixture added in a relatively large amount. When a relatively large amount of chiral material is contained in the nematic liquid crystal, a cholesteric phase in which nematic liquid crystal molecules are strongly twisted in a spiral shape can be formed. For this reason, cholesteric liquid crystals are also called chiral nematic liquid crystals.

  Cholesteric liquid crystal has bistability (memory property) and can take either a planar state, a focal conic state, or an intermediate state by mixing them by adjusting the electric field strength applied to the liquid crystal. . Once the planar state, the focal conic state, or an intermediate state therebetween, the state is stably maintained even in the absence of an electric field. The planar state can be obtained, for example, by applying a predetermined high voltage between the upper and lower substrates to apply a strong electric field to the liquid crystal layer, bringing the liquid crystal into a homeotropic state, and then suddenly reducing the electric field to zero.

  The focal conic state can be obtained, for example, by applying a predetermined voltage lower than the above high voltage between the upper and lower substrates to apply an electric field to the liquid crystal layer and then suddenly reducing the electric field to zero. Alternatively, it can be obtained by gradually applying a voltage from the planar state.

  In the intermediate state between the planar state and the focal conic state, for example, a voltage lower than the voltage at which the focal conic state is obtained is applied between the upper and lower substrates to apply an electric field to the liquid crystal layer, and then the electric field is suddenly reduced to zero. Can be obtained.

  The display principle of the liquid crystal display element using the cholesteric liquid crystal will be described by taking the B display unit 10B as an example. FIG. 2A shows the alignment state of the liquid crystal molecules LC of the cholesteric liquid crystal when the B liquid crystal layer 12B of the B display unit 10B is in the planar state. As shown in FIG. 2A, the liquid crystal molecules in the planar state are sequentially rotated in the thickness direction of the upper and lower substrates 11B and 13B to form a spiral structure, and the spiral axis of the spiral structure is substantially perpendicular to the substrate surface. become.

  In the planar state, light having a predetermined wavelength corresponding to the helical pitch of the liquid crystal molecules is selectively reflected by the liquid crystal layer 12B. When the average refractive index of the liquid crystal layer is n and the helical pitch is p, the wavelength λ at which the reflection is maximum is expressed by λ = n · p.

  Accordingly, in order to selectively reflect blue light in the planar state in the B liquid crystal layer 12B of the B display unit 10B, the average refractive index n and the helical pitch p are determined so that, for example, λ = 480 nm. The average refractive index n can be adjusted by selecting a liquid crystal material and a chiral material, and the helical pitch p can be adjusted by adjusting the content of the chiral material.

  FIG. 2B shows the alignment state of the liquid crystal molecules LC of the cholesteric liquid crystal when the B liquid crystal layer 12B of the B display unit 10B is in the focal conic state. As shown in FIG. 2B, the liquid crystal molecules LC in the focal conic state are sequentially rotated in the in-plane directions of the upper and lower substrates 11B and 13B to form a spiral structure, and the spiral axis of the spiral structure is on the substrate surface. It becomes almost parallel. In the focal conic state, the selectivity of the reflection wavelength is lost in the B liquid crystal layer, and most of the incident light is transmitted. Since the transmitted light is absorbed by the light absorption layer disposed on the back surface of the lower substrate of the R display portion, dark (black) display can be realized.

  In the intermediate state between the planar state and the focal conic state, the ratio of the reflected light and the transmitted light can be adjusted according to the state, so that the intensity of the reflected light can be varied and halftone display can be realized.

  Thus, in the cholesteric liquid crystal, the amount of reflected light can be controlled by the alignment state of the liquid crystal molecules twisted in a spiral.

  Similar to the B liquid crystal layer 12B, a cholesteric liquid crystal that selectively reflects green or red light in the planar state is encapsulated in the G liquid crystal layer 12G and the R liquid crystal layer 12R, respectively. An element is fabricated.

  As described above, using cholesteric liquid crystal and laminating liquid crystal display elements that selectively reflect red, green, and blue light, a full-color display device with memory characteristics becomes possible. Color display is possible with zero power. When all of the B liquid crystal layer 12B, the G liquid crystal layer 12G, and the R liquid crystal layer 12R are brought into a focal conic state, a black display is obtained. When only one of the B liquid crystal layer 12B, the G liquid crystal layer 12G, and the R liquid crystal layer 12R is brought into a planar state, a corresponding color is displayed. For example, when the G liquid crystal layer 12G is in a planar state and the B liquid crystal layer 12B and the R liquid crystal layer 12R are in a focal conic state, a green display is obtained. Further, when only one of the B liquid crystal layer 12B, the G liquid crystal layer 12G, and the R liquid crystal layer 12R is brought into a focal conic state, a corresponding color is displayed. For example, when the G liquid crystal layer 12G is in the focal conic state and the B liquid crystal layer 12B and the R liquid crystal layer 12R are in the planar state, a magenta color display is obtained. When all of the B liquid crystal layer 12B, the G liquid crystal layer 12G, and the R liquid crystal layer 12R are in the planar state, white display is performed. In the white display, since the reflection of the three layers of the B liquid crystal layer 12B, the G liquid crystal layer 12G, and the R liquid crystal layer 12R is combined, a very bright white display can be obtained.

  Next, the principle of driving a display element using cholesteric liquid crystal will be described.

  Many driving methods have been proposed for displaying images on a cholesteric liquid crystal display element, but they can be broadly classified into two methods, “conventional driving method” and “dynamic driving method”. The dynamic driving method uses a transient planar state in addition to the above-mentioned “homeotropic state”, “planar state”, and “focal conic state”. The dynamic drive method can rewrite the display at a relatively high speed even in the case of a simple matrix type display element, but has a problem that it is difficult to perform precise gradation display. On the other hand, the conventional driving method can display a precise gradation, but a simple matrix display element has a problem that it takes a long time to rewrite the display.

  FIG. 3 is a diagram illustrating an example of a state change of the liquid crystal in the conventional driving method. In the conventional driving method, after applying a high voltage to all the pixels to bring them into a homeotropic state, the electric field is released, and a reset operation is performed to bring all the pixels into a planar state or a focal conic state. Thereafter, a write operation for changing the state of each pixel from the planar state or the focal conic state is performed by applying a write pulse having a relatively low voltage and a short pulse width by a simple matrix driving method. FIG. 3 shows an operation in which the planar state is maintained or changed to a focal conic state or a state in which the planar state and the focal conic state are mixed after all the pixels are brought into the planar state by the reset operation.

  FIG. 4 is a diagram illustrating an example of a voltage waveform applied to a liquid crystal cell (pixel) and an example of a response characteristic of reflectivity when the illustrated voltage waveform is applied in the conventional driving method. 4A shows a reset voltage waveform (pulse) applied in the reset operation, and FIG. 4B shows a response to the application of the reset pulse. 4C shows an example of a write voltage waveform (pulse) applied in the write operation. FIG. 4D shows the write of FIG. 4C when the initial state is the planar state. The response to the application of a pulse is shown. 4E shows a write pulse having a narrower pulse width than that of FIG. 4C. FIG. 4F shows the case of FIG. 4E when the initial state is the planar state. The response to the application of the write pulse is shown. In other words, FIGS. 4D and 4F show changes in the left inclined portion indicated by P in FIG. 4B.

  The driving waveform of the cholesteric liquid crystal needs to be an alternating current in order to suppress deterioration (polarization) of the liquid crystal material. First, the state change when the pulse voltage is gradually increased from 0 V in the case of applying a pulse having a wide pulse width of 60 ms including the positive and negative pulses as shown in FIG. 4A will be described. When the initial state is the planar state, the state changes along a line indicated by P in FIG. When the pulse voltage exceeds a certain voltage, the state gradually changes to the focal conic state, and the reflectivity rapidly decreases. When the reflectance reaches a minimum value, the reflectance hardly changes unless the pulse voltage exceeds a certain voltage. When the pulse voltage exceeds a certain voltage, the state gradually changes to the planar state, and the reflectance increases rapidly. When the reflectance reaches the maximum value, the reflectance does not change even if the pulse voltage is increased. Such voltage-reflectance characteristics are generally called “VR characteristics”. When the initial state is the focal conic state, the state changes along the line indicated by FC in FIG. The reflectivity does not change unless the pulse voltage exceeds a certain voltage. When the pulse voltage exceeds a certain voltage, the state gradually changes to the planar state, and the reflectance increases rapidly. When the reflectance reaches the maximum value, the reflectance does not change even if the pulse voltage is increased. Whether the initial state is the planar state or the focal conic state, when a voltage higher than a certain voltage is applied, the planar state with the maximum reflectance is always obtained. In FIG. 4B, in the case of a pulse having a pulse width of 60 ms and a voltage of ± 36 V, a planar state is always obtained, so that this pulse can be used as a reset pulse.

  When applying a pulse having a narrower pulse width than this, the response is shifted. For example, when a pulse with a pulse width of 2 ms and a pulse voltage of ± 24 V and ± 12 V shown in FIG. 4C is applied and the initial state is the planar state, the state is L in FIG. It changes along the line indicated by. In FIG. 4D, the reflectivity does not change with a pulse of ± 12 V, and the planar state is maintained. With a pulse of ± 24 V, the halftone with a slightly reduced reflectivity is obtained. When the reflectivity in which the initial state is a mixture of the planar state and the focal conic state is an intermediate value, the state changes along a line indicated by M in FIG. Also in this case, the reflectivity does not change with a pulse of ± 12 V, and the reflectivity slightly decreases with a pulse of ± 24 V.

  Further, when a pulse with a pulse width of 1 ms and a pulse voltage of ± 24 V and ± 12 V shown in FIG. 4E is applied and the initial state is the planar state, the state is N in FIG. It changes along the line indicated by. In FIG. 4F, the reflectivity does not change with a pulse of ± 12 V, and the planar state is maintained. In the case of a pulse of ± 24 V, the halftone with a slight decrease in reflectivity is obtained, but the decrease in reflectivity is smaller than that in the case of a pulse width of 2 ms. That is, 2 ms is darker than 1 ms. When the reflectance is an intermediate value in which the initial state is the planar state and the focal conic state, the state changes along the line indicated by O in FIG. Also in this case, the reflectivity does not change with a pulse of ± 12 V, and the reflectivity slightly decreases with a pulse of ± 24 V.

  As described above, when the initial state is the planar state, it is understood that when a short pulse with a relatively small voltage is applied, the reflectivity is decreased, and the amount of decrease in reflectivity changes according to the pulse voltage and the pulse width. . Specifically, the lower the pulse voltage, the larger the pulse width, the greater the amount of decrease in reflectance. In addition, the same change occurs even when pulses are applied separately from the changes indicated by M and O in FIGS. 4D and 4F, and the amount of decrease in reflectivity is the sum of pulse widths, that is, cumulative pulse application. Related to time.

  The above description is an example in which the initial state is the planar state and the left inclined portion indicated by P in FIG. 4B is used. However, the initial state is the focal conic state, and FIG. The same applies to the case where the right inclined portion indicated by FC is used in (B).

  Several conventional driving methods have been proposed, but differ depending on whether the initial state is the planar state or the focal conic state. In other words, in FIG. 4B, it differs depending on whether the left inclined portion indicated by P or the right inclined portion indicated by FC is used. Hereinafter, the case where the initial state is the planar state and the left inclined portion indicated by P in FIG. 4B is used will be described as an example. However, the present invention is not limited to this.

  As described above, until now, display elements using cholesteric liquid crystals have a simple matrix (passive matrix) type configuration and are generally driven by a simple matrix driving method. Since the response speed of cholesteric liquid crystal is low, a selection period of several ms to several tens of ms is required to apply a voltage sufficient for the liquid crystal on the selected line to respond when driven by a simple matrix driving method. It was. For this reason, when the number of lines is 1000, it takes several seconds to several tens of seconds to rewrite the screen, and an improvement in display rewriting speed has been desired.

[First Embodiment]
FIG. 5 is a diagram illustrating a schematic configuration of the color display device according to the first embodiment. FIG. 6 is a diagram schematically showing a cross-sectional configuration of a color display element using a cholesteric liquid crystal used in the color display device of the first embodiment.

  As shown in FIG. 5, the color display device according to the first embodiment includes a color display element 10, a gate driver 21, a data driver 22, a drive control unit 23, and a temperature sensor 35. Here, a portion including the gate driver 21, the data driver 22, and the drive control unit 23 is referred to as a drive control circuit.

  As shown in FIGS. 5 and 6, the color display element 10 includes a B display unit 10B, a G display unit 10G, an R display unit 10R, a light absorption layer 17, a blue cut filter 19B, and a green cut filter 19G. And having. The B display unit 10B has a B liquid crystal layer 12B that reflects blue light in a planar state, and the G display unit 10G has a G liquid crystal layer 12G that reflects green light in a planar state, and displays an R display. The unit 10R includes an R liquid crystal layer 12R that reflects red light in a planar state. The B display unit 10B, the G display unit 10G, and the R display unit 10R are stacked in this order from the light incident surface (display surface) side. The light absorption layer 17 is provided on the back side of the R display unit 10R and absorbs incident visible light so as not to be reflected. The blue cut filter 19B is provided between the B display unit 10B and the G display unit 10G, and cuts a wavelength component corresponding to blue light. The green cut filter 19G is provided between the G display unit 10G and the R display unit 10R, and cuts a wavelength component corresponding to green light. The light absorption layer 17, the blue cut filter 19B, and the green cut filter 19G may be provided as necessary.

  The B display unit 10B includes a pair of upper and lower substrates 11B and 13B arranged opposite to each other, a B liquid crystal layer 12B sealed between both substrates, a common electrode layer 14B formed on the upper substrate 11B, and a lower substrate. And a pixel electrode layer 15B formed on 13B. The B liquid crystal layer 12B has B cholesteric liquid crystal adjusted so as to selectively reflect blue in a planar state. For example, the reflection center wavelength of the B liquid crystal layer 12B is 480 nm corresponding to blue.

  The G display section 10G includes a pair of upper and lower substrates 11G and 13G arranged opposite to each other, a G liquid crystal layer 12G sealed between both substrates, a common electrode layer 14G formed on the upper substrate 11G, and a lower substrate. And a pixel electrode layer 15G formed on 13G. The G liquid crystal layer 12G has G cholesteric liquid crystal adjusted to selectively reflect green in a planar state. For example, the reflection center wavelength of the G liquid crystal layer 12G is 550 nm corresponding to green.

  Similarly, the R display unit 10R includes a pair of upper and lower substrates 11R and 13R arranged opposite to each other, an R liquid crystal layer 12R sealed on both substrates, a common electrode layer 14R formed on the upper substrate 11R, And a pixel electrode layer 15R formed on the lower substrate 13R. The R liquid crystal layer 12R has R cholesteric liquid crystal adjusted to selectively reflect red in a planar state. For example, the reflection center wavelength of the R liquid crystal layer 12R is 630 nm corresponding to red.

  Here, the liquid crystal composition filled in each liquid crystal layer will be described in detail. The liquid crystal composition constituting the liquid crystal layer is a cholesteric liquid crystal obtained by adding 10 to 40 wt% of a chiral material to a nematic liquid crystal mixture. The addition amount of the chiral material is a value when the total amount of the nematic liquid crystal component and the chiral material is 100 wt%. As the nematic liquid crystal, various conventionally known liquid crystals can be used. The refractive index anisotropy (Δn) is preferably 0.18 to 0.24. If it is smaller than this range, the reflectivity in the planar state is lowered, and if it is larger than this range, the scattering reflection in the focal conic state is increased, the viscosity is also increased, and the response speed is lowered. The thickness of the liquid crystal layer is preferably 3 to 6 μm. If the thickness is smaller than this, the planar reflectivity is lowered, and if it is larger, the driving voltage becomes too high.

  Next, the optical rotation of each liquid crystal layer will be described. In the laminated structure of the B, G, and R display portions, the optical rotation in the G liquid crystal layer 12G in the planar state is different from the optical rotation in the B liquid crystal layer 12B and the R liquid crystal layer 12R.

  The upper substrate and the lower substrate are required to have translucency. Here, two polyethylene naphthalate (PEN) film substrates cut into a size of 12 cm × 12 cm in length and width are used. Moreover, it can replace with a PEN board | substrate and can also use film substrates, such as a glass substrate, a polyethylene terephthalate (PET), and a polycarbonate (PC). Here, the upper substrate and the lower substrate of each display unit are both translucent, but the lower substrate 13R of the R display unit 10R disposed in the lowermost layer is opaque. Also good.

  The common electrode layer 14B is provided on the B liquid crystal layer 12B side of the upper substrate 11B of the B display unit 10B, and a common electrode is formed on the entire surface. The pixel electrode layer 15B is provided on the B liquid crystal layer side 12B of the lower substrate 13B of the B display unit 10B, and a pixel electrode 31, a TFT 32, a gate line 33, and a data line 34 are formed. The plurality of gate lines 33 extend in parallel to each other in the first direction (here, the lateral direction). The plurality of data lines 34 extend in parallel to each other in a second direction (here, the vertical direction) orthogonal to the first direction, and are formed with respect to the plurality of gate lines 33 via an insulating layer. A plurality of pixel electrodes 31 are provided in a region delimited by the plurality of gate lines 33 and the plurality of data lines 34. Accordingly, the plurality of pixel electrodes 31 are arranged in a matrix, and the pixel electrode 31 corresponds to a pixel. A plurality of switching elements 32 such as TFTs are provided corresponding to the intersections of the plurality of gate lines 33 and the plurality of data lines 34. Each pixel electrode 31 is connected to a corresponding data line 34 via a corresponding switching element 32. The control terminal of each switching element 32 is connected to the corresponding gate line 33. When a selection signal is applied to the gate line 33, the switching element 32 connected to the gate line 33 is turned on (same communication), and the pixel electrodes 31 corresponding to the gate line 33 are connected to the data line 34, respectively. The

  Here, the pixel electrodes 31, the switching elements 32, the gate lines 33, and the data lines 34 are formed at a pitch of 0.24 mm so that a 320 × 240 dot QVGA display can be performed. There are 320 data lines 34.

  As a material for forming the common electrode and the pixel electrode, for example, indium tin oxide (ITO) is representative, but other transparent conductive films such as indium zinc oxide (IZO), aluminum, or aluminum A metal electrode such as silicon or a photoconductive film such as amorphous silicon or bismuth silicate (BSO) can be used.

  Here, the switching element 32 is formed of a TFT element. TFT semiconductors include polycyclic aromatic hydrocarbons such as pentacene, anthracene, and rubrene, which are known as Si and organic semiconductors, and low molecular weight compounds such as tetracyanoquinodimethane (TCNQ), polyacetylene, and poly (ethylene). Polymers such as -3-hexylthiophene (P3HT) and polyparaphenylene vinylene (PPV) can be used. Further, an oxide semiconductor typified by a-InGaZnO can be used.

  It is preferable that an alignment film (both not shown) for controlling the alignment of liquid crystal molecules is coated on the electrode as a functional film. For the alignment film, organic films such as polyimide resin, polyamideimide resin, polyetherimide resin, polyvinyl butyral resin, and acrylic resin, and inorganic materials such as silicon oxide and aluminum oxide can be used. Here, for example, an alignment film is applied (coated) on the entire surface of the substrate on the electrode.

  The B liquid crystal layer 12B is sealed between both substrates by a sealing material 16B applied to the outer periphery of the upper substrate 11B and the lower substrate 13B. Further, it is necessary to keep the thickness (cell gap) of the B liquid crystal layer 12B uniform. In order to maintain a predetermined cell gap, spherical spacers made of resin or inorganic oxide are dispersed in the B liquid crystal layer 12B, or a plurality of columnar spacers made of a structure are formed in the B liquid crystal layer 12B. Here, columnar spacers are provided in the B liquid crystal layer 12B to maintain the cell gap uniformity. The cell gap of the B liquid crystal layer 12B is preferably in the range of 3 μm ≦ d ≦ 6 μm.

  Since the G display unit 10G and the R display unit 10R have the same structure as the B display unit 10B, description thereof is omitted.

  The plurality of gate lines 33 and the plurality of data lines 34 of the B display unit 10B, the G display unit 10G, and the R display unit 10R are drawn to the end of the lower substrate and connected to the terminals of the gate driver 21 and the data driver 22, respectively. Is done. The gate driver 21 applies a selection signal to one of the plurality of gate lines 33, applies a non-selection signal to the other gate lines, and sequentially shifts the position of the gate line 33 to which the selection signal is applied. The data driver 22 applies a data voltage corresponding to the display data of the pixel to the pixel electrode connected via the TFT 32 to the gate line to which the selection signal is applied in synchronization with the selection signal. Note that the gate driver 21 used here can be fully selected to output the same voltage as the selection signal to all output terminals.

  Here, in order to simplify the configuration of the drive circuit of the color display device, the gate driver 21 that drives the gate lines 33 of the B display unit 10B, the G display unit 10G, and the R display unit 10R is shared. It is also possible to provide 21 separately. The gate driver may be shared as necessary. On the other hand, the data driver 22 can individually apply voltages to all the data lines 34 of the three layers of the B display unit 10B, the G display unit 10G, and the R display unit 10R.

  Further, the common electrode provided in the common electrode layers 14B, 14G, and 14R is connected to a ground level terminal.

  The drive control unit 23 controls the gate driver 21 and the data driver 22 so as to perform the above operation.

  Next, the B display unit 10B, the G display unit 10G, and the R display unit 10R are manufactured in the same manufacturing process. Hereinafter, an example of a manufacturing process will be described.

  TFT element so that QVGA display of 320 × 240 dots can be made at 0.24 mm pitch on one substrate of two polyethylene naphthalate (PEN) film substrates cut to a size of 12 cm × 12 cm in length and width. And a pixel electrode made of IZO. On the other substrate, a common electrode made of IZO having a size corresponding to the one substrate is formed.

  Next, the substrate on which the TFTs and electrodes are formed is washed, polyimide is applied as an alignment film at a thickness of 50 nm, and baked at 150 ° C. for 1 hour. Thereafter, rubbing is performed with a rayon cloth. The rubbing direction is a direction that is orthogonal (cross-rubbing) when two substrates are overlapped. Rubbing may be performed as necessary.

  Next, a photoresist is applied on one PEN film substrate, the resist is patterned through a photolithography process, and baked at 150 ° C. for 120 minutes, thereby producing a structure with a height of 4 μm. This structure is for maintaining a gap when two substrates are stacked.

Next, an epoxy sealant is applied to the peripheral edge of the other PEN film substrate using a dispenser. Next, the two PEN film substrates are bonded together and heated at 160 ° C. for 1 hour while being pressed with a force of 1 kg / cm ² . As a result, the sealant is cured and bonded to both substrates. At the same time, the structure is bonded to both substrates.

  Next, after injecting cholesteric liquid crystal by a vacuum injection method, the injection port is sealed with an epoxy-based sealing material, and the display portion is completed. The spiral direction of the liquid crystals of the R liquid crystal layer 12R and the B liquid crystal layer 12B is opposite to the spiral direction of the liquid crystals of the G liquid crystal layer 12G.

  Next, a driving method for driving the display element 10, that is, driving signals output from the gate driver 21 and the data driver 22 will be described. Here, drive signals applied to the gate lines and data lines of one display portion will be described, but the same applies to the other display portions.

  FIG. 7 is a diagram showing main waveforms in the liquid crystal display device of the first embodiment having the color liquid crystal display element shown in FIG. Specifically, in FIG. 7, GL1, GL2 and GL240 are signals applied from the gate driver 21 to the gate lines GL1, GL2 and GL240. D is a signal applied by the data driver 22 to one data line D. LC1, LC2, and LC240 are diagrams showing voltages applied to pixels corresponding to GL1, GL2, and GL240.

  As shown in FIG. 7, the drive sequence includes a reset period, a stable period, an address period, and a display process period. The reset period includes a positive polarity reset period and a negative polarity reset period. The write period includes a plurality of write process periods, and each write process period includes a positive write process period and a negative write process period. The number of write processing periods can be arbitrarily set, and FIG. 7 shows a case where there are three write processing periods. As will be described later, in the first embodiment, the drive control unit 23 determines the number of write processing periods according to the temperature of the color display element 10 detected by the temperature sensor 35.

  The selection signal applied to the gate lines GL1, GL2,..., GL240 is a + 30V 70 μs / line pulse, and the non-selection signal is a −30V 70 μs / line pulse. By applying a selection signal to the gate of the switching element (TFT) 32, the TFT 32 is turned on and becomes conductive regardless of the potential of the data line and the pixel electrode. Further, by applying a non-selection signal to the gate of the TFT 32, the TFT 32 is turned off and becomes non-conductive regardless of the potential of the data line and the pixel electrode.

  During the reset period and the stable period, a selection signal (+ 30V) is applied to all the gate lines GL1, GL2,. In the positive reset period in the first half of the reset period, a positive reset voltage is applied to all data lines D. The positive reset voltage is a voltage for bringing the liquid crystal into a homeotropic state, and is assumed to be +40 V here. As a result, all the TFTs 32 are turned on, and +40 V is applied to all the pixel electrodes 31. Since the common electrode is connected to the ground, +40 V is applied to the liquid crystals LC1, LC2,. The positive reset period is 16.8 ms, and during that time, a state in which +40 V is applied to the liquid crystals LC1, LC2,.

  In the negative reset period in the latter half of the reset period, a negative reset voltage is applied to all data lines D. The negative reset voltage is a voltage for bringing the liquid crystal into a homeotropic state, and is assumed to be −40 V here. As a result, all the TFTs 32 are turned on, and −40 V is applied to all the pixel electrodes 31. Since the common electrode is connected to the ground, −40 V is applied to the liquid crystals LC1, LC2,. The negative polarity reset period is 16.8 ms, and during that time, a state in which −40 V is applied to the liquid crystals LC1, LC2,.

  As described above, in the reset period, a reset voltage of ± 40 V (+40 V is 16.8 ms, −40 V is 16.8 ms) having a pulse width of 33.6 ms is simultaneously applied to all pixels simultaneously. . Thereby, in the reset period, the liquid crystals LC1, LC2,..., LC240 of all the pixels are in a homeotropic state.

  In the stable period, by applying a stabilization voltage of 0V to all the data lines D, 0V is applied to all the pixel electrodes 31, and 0V is applied to the liquid crystals LC1, LC2,. . The stable period has a length of 16.8 ms, for example. Here, the processes of the reset period and the stable period are collectively referred to as pre-writing process.

  As described above, when a high voltage is applied to the cholesteric liquid crystal to bring it into a homeotropic state and then the applied voltage is rapidly reduced, a planar state is obtained. Therefore, when the stabilization voltage (0 V) is applied during the stabilization period, the liquid crystals LC1, LC2,..., LC240 of all the pixels are in a planar state. Here, the stabilization voltage is set to 0 V, but any voltage may be used as long as it is a planar state.

  In the positive write processing period in the first half of one write processing period, a scan operation is performed in which a selection signal (+30 V) having a pulse width of 70 μs is sequentially applied to the gate lines GL1, GL2,. Then, in synchronization with the application of the selection signal to each gate line, a positive data voltage corresponding to the display data of the pixels connected to the gate line via the TFT is applied to all the data lines. The positive data voltage is determined depending on whether the liquid crystal in the planar state is maintained in the planar state as it is, in a state in which the planar state and the focal conic state are mixed, or almost in the focal conic state. Here, it is 0 to + 25V. The positive data voltage is 0 V when the planar state is maintained, and +25 V when almost the focal conic state is established. When the planar state and the focal conic state are mixed, the positive data voltage is a voltage between 0 and +25 V and is determined according to the mixing ratio.

  As shown in FIG. 7, in synchronization with the selection signal being applied to the gate line GL1, a positive data voltage corresponding to the display data of the pixels on the first line is applied to all the data lines D. As a result, the first line TTFT 32 connected to the gate line GL1 is turned on, and the positive data voltage of the corresponding data line is applied to the pixel electrode 31 of the first line. Therefore, a positive data voltage is applied to the liquid crystal LC1 of the pixels on the first line.

  The pulse width of the selection signal is 70 μs. When the selection signal is applied to the gate line GL1, the first line TTFT 32 connected to the gate line GL1 is turned off and applied to the pixel electrode 31 of the first line. The positive data voltage is maintained as it is. Therefore, the state where the positive data voltage is applied to the liquid crystal LC1 of the pixels on the first line is maintained, and this state continues until the selection signal is applied to the gate line GL1 again. However, as will be described later, the voltage applied to the liquid crystal LC1 of the pixels on the first line gradually decreases.

  When the application of the selection signal to the gate line GL1 is completed, the selection signal is applied to the gate line GL2, and in synchronization therewith, the positive polarity corresponding to the display data of the pixels of the second line is applied to all the data lines D. Apply the data voltage. As a result, the TTFT 32 of the second line connected to the gate line GL2 is turned on, and the positive data voltage of the corresponding data line is applied to the pixel electrode 31 of the second line, so that the liquid crystal LC2 of the pixel of the second line A positive data voltage is applied to. The state in which the positive data voltage is applied to the liquid crystal LC2 of the pixel on the second line continues until the selection signal is applied again to the gate line GL2, but the applied voltage gradually decreases.

  Thereafter, the selection signal is sequentially applied to the 240th gate line, and the same operation is repeated. Since the pulse width of the selection signal is 70 μs, the application of the selection signal for performing the positive polarity writing is completed in 70 μs × 240 = 16.8 ms. When application of the selection signal to the last gate line GL240 is completed, negative-polarity writing to the first gate line GL1 is started.

  In the negative polarity write process period in the latter half of the write process period, a scan operation is performed in which a selection signal (+30 V) having a pulse width of 70 μs is sequentially applied to the gate lines GL1, GL2,. Then, in synchronization with the application of the selection signal to each gate line, a negative data voltage corresponding to the display data of the pixel connected to the gate line via the TFT is applied to all the data lines. The negative data voltage has the same polarity as the reverse polarity of the positive data voltage.

  In the negative write processing period, the display data of the pixels on the first line corresponds to all data lines D in synchronization with the selection signal being applied to the gate line GL1, as in the positive write processing period. A negative data voltage is applied. As a result, the first line TTFT 32 connected to the gate line GL1 is turned on, the negative data voltage of the corresponding data line is applied to the pixel electrode 31 of the first line, and the liquid crystal LC1 of the pixel of the first line is applied. A negative data voltage is applied to.

  Thereafter, the selection signal is sequentially applied to the 240th gate line, and the same operation is repeated. As a result, a negative data voltage is applied to the liquid crystal of the pixels in each line.

  As shown in FIG. 7, when writing of the negative voltage to the liquid crystal of the pixel on the 240th line in the first writing process period is completed, the liquid crystal of the pixel on the first line in the second writing process period is displayed. Is started, and the same operation as described above is repeated. When the operation of the determined number of write processing periods ends, the display process period starts. Here, the processing in the display processing period is referred to as post-writing processing.

  The positive writing process period of each line continues until a negative data voltage is applied, so the period during which the positive data voltage is applied to the liquid crystal of the pixels of each line is 16.8 ms, Each shift is 70 μs. Further, since the negative polarity writing period of each line continues until the second positive polarity data voltage is applied, the period during which the negative polarity data voltage is applied to the liquid crystal of the pixels of each line is 16.8 ms. That is, every line is shifted by 70 μs.

In a general liquid crystal display device that displays a moving image, writing for displaying one display screen (one frame) is normally performed only once. There are also cases where two consecutive frames are displayed by positive writing and negative writing.
In contrast, in the first embodiment, as described above, one or more write processing periods including a positive write process period and a negative write process period are provided, and writing of the same data voltage is performed at least once. Do. The number of write processing periods is determined according to the temperature of the color display element 10 detected by the temperature sensor 35.

  In the display processing period, the application of the selection signal (+ 30V) with a predetermined width is started in order from the gate line of the line where the negative polarity writing period has ended, and the application of the selection signal (+ 30V) to the last gate line GL240 is completed. At this point, the display processing period ends. During the display processing period, a sustain voltage is applied to all data lines. Specifically, a scanning operation is performed in which a very long selection signal (+30 V) having a predetermined width is sequentially applied to the gate lines GL1, GL2,. The sustain voltage is a voltage that does not change the state of the liquid crystal, and is 0 V here. As a result, 0V is sequentially applied to the liquid crystals LC1, LC2,.

  As shown in FIG. 7, when a selection signal is applied to the gate line GL1 during the display processing period, the first line TTFT 32 connected to the gate line GL1 is turned on, and the pixel electrode 31 of the first line is set to 0V. Is applied, and 0 V is applied to the liquid crystal LC1 of the pixels in the first line. Hereinafter, the selection signal is sequentially applied to the last gate line GL240, and 0V is applied to the liquid crystals LC1, LC2,. A non-selection voltage (−30 V) is applied to each of the gate lines GL1, GL2,... Except the last gate line GL240 when the selection signal (+30 V) is applied. As a result, the TFTs 32 are sequentially turned off for each line. The time for applying the selection signal to each gate line in order to apply the sustain voltage is a time corresponding to a predetermined width, and is the same for all gate lines.

  The display processing period ends after a time corresponding to 16.8 ms + predetermined width after the application of the sustain voltage of the first line is started. As will be described later, when the sustain voltage (0 V) is applied to the data line, the time corresponding to the predetermined width does not change the liquid crystal state of the pixel even if the voltage actually applied to the pixel is applied for a long time. Sufficient time to reach the voltage.

  When 0V is applied to the liquid crystal of each pixel, the state at that time is maintained. Thereby, in the writing period, the state of each pixel set by the data voltage, that is, the display image is maintained.

  After the display image is rewritten by performing the above-described series of processing, the state after the end of the display processing period is maintained until the display image is rewritten next time. The time for which the display image is maintained is determined according to the application, and when it is long, it may be several days to several weeks or more. Therefore, after the display processing period ends, the power supply to the color display device of the embodiment may be stopped until the display image is rewritten. Thereby, a display image can be maintained in a state of zero power consumption.

  The gate driver 21 and the data driver 22 were connected to the B display unit 10B, the G display unit 10G, and the R display unit 10R manufactured by the above manufacturing method, and the contrast ratio was measured when driven by the driving sequence shown in FIG. The measurement was performed with the data display voltages of 0 V and 30 V with the B, G, and R display units independent, and the number of write processing periods of 1, 2, and 4.

  FIG. 8 is a diagram showing the change of the contrast ratio in the B display unit 10B with respect to the temperature change, using the number of write processing periods as a parameter. In FIG. 8, A shows a case where the write processing period is one time, B shows a case where the write processing period is two times, and C shows a case where the write processing period is four times.

  FIG. 9 is a diagram showing the change of the contrast ratio in the G display unit 10G with respect to the temperature change, using the number of write processing periods as a parameter. In FIG. 9, A shows a case where the write processing period is one time, B shows a case where the write processing period is two times, and C shows a case where the write processing period is four times.

  FIG. 10 is a diagram showing the change of the contrast ratio in the R display unit 10R with respect to the temperature change, using the number of write processing periods as a parameter. In FIG. 10, A indicates a case where the write processing period is one time, B indicates a case where the write processing period is two times, and C indicates a case where the write processing period is four times.

  As shown in FIGS. 8 to 10, it can be seen that the contrast ratio shows a maximum value around 25 ° C., and decreases when the temperature becomes lower or higher than that. In particular, the contrast ratio greatly decreases on the high temperature side. It can also be seen that the contrast ratio can be increased particularly on the high temperature side by increasing the number of times of writing, which is the application of the data voltage.

  The decrease in the contrast ratio on the low temperature side is considered to be due to a decrease in the responsiveness of the liquid crystal molecules as the temperature decreases. On the other hand, the decrease in the contrast ratio on the high temperature side is considered to be because the resistance of the liquid crystal decreases as the temperature increases due to the influence of impurity ions in the panel. When the resistance of the liquid crystal decreases, it becomes difficult to maintain the data voltage applied to the liquid crystal even when the gate is turned off by turning on the gate of the TFT during the writing process period. The applied voltage is effectively reduced. This effective decrease in the voltage applied to the liquid crystal is referred to as a decrease in voltage holding ratio. FIG. 7 shows how the absolute value of the data voltage applied to the liquid crystal of each pixel gradually decreases.

  The decrease in the voltage holding ratio can be compensated for by increasing the number of write processes. This is because the voltage application to the liquid crystal can be increased by increasing the number of writing processes. For example, since the voltage applied to the liquid crystal effectively decreases with time, the effect of compensating for the decrease in the voltage holding ratio even if the application time is extended, that is, the cycle time of the writing process period is increased. Is relatively small compared to increasing the number of write operations.

  Next, looking at the influence of the temperature for each of the B, G, and R display units in FIGS. 8 to 10, the B display unit has an upper limit temperature that maintains a contrast ratio of 50%. It is 53 degreeC by 2 times, and is 60 degreeC or more by 4 times. On the other hand, in the B display section, the upper limit temperature for maintaining the contrast ratio of 50% is 38 ° C. for the number of writing processes once, 48 ° C. for the second time, and 57 ° C. for the fourth time. Further, in the R display section, the upper limit temperature for maintaining the contrast ratio of 50% is 34 ° C. at the number of writing processes once, 42 ° C. at 2 times, and 53 ° C. at 4 times. Thus, it can be seen that the influence of the panel temperature differs for each of the R, G, and B display units.

  FIG. 11 is a flowchart illustrating a process in which the drive control unit 23 determines the number of write processes based on the temperature of the color display element 10 detected by the temperature sensor 35 in the first embodiment. Here, for all of the B, G, and R display portions, the number of write processes is one in the temperature range of 0 ° C. to less than 30 ° C., and the number of write processes is twice in the temperature range of 30 ° C. to less than 35 ° C. In the above temperature range, display is performed with the number of writings set to four.

  In step S <b> 11, the drive control unit 23 detects the temperature T of the color display element 10 with the temperature sensor 35.

  In step S12, the drive control unit 23 determines whether or not the detected temperature T is less than 30 ° C. If it is less than 30 ° C, the process proceeds to step S13, and if it is 30 ° C or more, the process proceeds to step S14.

  In step S13, the drive control unit 23 sets the number of write processes N to 1 and proceeds to step S17.

  In step S14, the drive control unit 23 determines whether or not the detected temperature T is less than 35 ° C., and if it is less than 35 ° C., the process proceeds to step S15, and if it is 35 ° C. or more, the process proceeds to step S16.

  In step S15, the drive control unit 23 sets the write processing count N to 2 and proceeds to step S17.

  In step S16, the drive control unit 23 sets the number N of write processes to 4 and proceeds to step S17.

  In step S17, the drive control unit 23 executes the display process according to the drive sequence of FIG.

  In the first embodiment, by executing the process of FIG. 11, the contrast ratio decrease is less than 50% up to 53 ° C. and the contrast is high up to 53 ° C. in the R display unit having a large contrast ratio decrease rate on the high temperature side. It is possible to obtain an indication of the ratio.

Regardless of the temperature, it is possible to obtain a display with a high contrast ratio if the number of write processes N = 4. However, increasing the number of write processes is not preferable because power consumption increases accordingly. Therefore, in the first embodiment, the number of write processes N is increased at a high temperature where the contrast ratio is greatly reduced.
Note that when used at an extremely low temperature of 0 ° C. or lower, a large reduction in the contrast ratio occurs. Therefore, the number of write processes may be increased similarly at an extremely low temperature.

  As shown in FIGS. 8 to 10, when the influence of the temperature of the B, G, and R display portions is observed, it can be seen that the temperature characteristics are greatly different for each display portion. In the first embodiment, the number of write processes is determined by paying attention to the decrease in the contrast ratio of the R display unit that is most affected by the temperature change. However, if the number of write processes is set for each display unit, more precise control is possible. Is possible. In the second embodiment to be described next, the number of write processes is set for each display unit.

[Second Embodiment]
FIG. 12 is a diagram illustrating a schematic configuration of a color display device according to the second embodiment.
In the color display device of the second embodiment, the gate driver 21 can independently apply a selection signal and a non-selection signal to the gate lines 33 of the B display unit 10B, the G display unit 10G, and the R display unit 10R. However, unlike the first embodiment, the other parts have the same configuration.

FIG. 13 is a table showing the number of write processes BN, GN, and RN in the B display unit 10B, the G display unit 10G, and the R display unit 10R according to the temperature range.
As shown in FIG. 13, GN and RN are set to once in the temperature range of 0 ° C. to less than 30 ° C., twice in the temperature range of 30 ° C. to less than 35 ° C., and set to 4 times in the temperature range of 35 ° C. or higher. . On the other hand, BN is set once in the temperature range of 0 ° C. to less than 35 ° C. and twice in the temperature range of 35 ° C. or higher.

  FIG. 14 is a flowchart illustrating a process in which the drive control unit 23 determines the number of write processes based on the temperature of the color display element 10 detected by the temperature sensor 35 in the second embodiment.

  In step S <b> 21, the drive control unit 23 detects the temperature T of the color display element 10 with the temperature sensor 35.

  In step S22, the drive control unit 23 writes data in the B, G, and R display units (panels) 10B, 10G, and 10R at the detected temperature T from the table of FIG. 13 stored in the memory in the drive control unit 23. The processing times BN, GN and RN are read out.

  In step S23, BN, GN, and RN are set in the control parameters Bn, Gn, and Rn of the number of write processes in the B, G, and R display units 10B, 10G, and 10R in the drive sequence.

  In step S24, a pre-writing process including a sequence in the reset period and the stable period in FIG. 7 is performed.

  In step S25, the writing process is performed on the display unit corresponding to the control parameters Bn, Gn and Rn which are not zero. In the first writing process, since Bn, Gn, and Rn are all 1 or more, the writing process is performed at least once.

In step S26, 1 is subtracted from the control parameters Bn, Gn and Rn.
In step S27, the control parameters Bn, Gn and Rn are classified according to whether they are zero. The display unit corresponding to the non-zero control parameter returns to step S25, and the display unit corresponding to the zero control parameter is displayed. Proceed to step S28.

In step S28, post-writing processing including a sequence in the display processing period shown in FIG. 7 is performed, and then the processing ends.
Accordingly, the writing process is further performed on the display unit corresponding to the control parameter that is not zero, while the post-writing process is performed on the display unit corresponding to the control parameter that is zero. Further, since the step S26 is not performed for the display unit in which the control parameter has already become zero, the control parameter is maintained at zero.

In step S27, steps S25 to S27 are repeated until all of the control parameters Bn, Gn and Rn become zero, and step S28 is performed as needed in parallel.
As described above, a series of rewriting operations involving the number of write processes corresponding to the temperature set in the table of FIG. 13 are performed on the three display units.

  In the second embodiment, display is performed by setting the number of writing processes according to the temperature for each display unit (panel), so that a display with a high contrast ratio up to 53 ° C. can be obtained as in the first embodiment. is there. In the second embodiment, the number of write processes can be substantially reduced as compared with the first embodiment, so that power consumption can be further reduced.

Here, with the liquid crystal display element 10 similar to that of the first embodiment, regardless of the temperature, when the display was performed with the number of writing processes being one, a high contrast ratio could be obtained only up to 34 ° C.
As described above, in the first and second embodiments, in the active matrix type cholesteric liquid crystal display device in which switching elements such as TFTs are provided in each pixel, data writing failure can be prevented, and the brightness and contrast ratio are excellent. A display device can be provided.

  In the above embodiment, the effect of the present invention has been described using the driving method in which the cholesteric liquid crystal enters the planar state after the reset (planar reset) and the cholesteric liquid crystal enters the focal conic state by data writing. However, it goes without saying that the same effect can be obtained in a driving method in which the cholesteric liquid crystal is in a focal conic state (focal conic reset) after reset and the cholesteric liquid crystal is in a planar state by data writing.

  Furthermore, the drive sequence of FIG. 7 can be variously modified. For example, the selection voltage is continuously applied to the gate line during the reset period and the stable period, but the pulse-shaped selection voltage is applied at the beginning of the positive and negative periods and the stable period of the reset period. Also good. Furthermore, it is possible to change the order of the positive polarity write processing period and the negative polarity write processing period.

  Although the embodiment has been described above, all examples and conditions described herein are described for the purpose of helping understanding of the concept of the invention applied to the invention and the technology. It is not intended to limit the scope of the invention, and the construction of such examples in the specification does not indicate the advantages and disadvantages of the invention. Although embodiments of the invention have been described in detail, it should be understood that various changes, substitutions and modifications can be made without departing from the spirit and scope of the invention.

DESCRIPTION OF SYMBOLS 10 Display element 21 Gate driver 22 Data driver 23 Drive control circuit 31 Pixel electrode 32 Switching element (TFT)
33 Gate line 34 Data line 35 Temperature sensor

Claims (5)

An active matrix liquid crystal display element containing a cholesteric liquid crystal material;
A drive control circuit for performing writing to apply a voltage according to display data to the pixels of the liquid crystal display element;
A temperature sensor for detecting the temperature of the liquid crystal display element,
The drive control circuit performs writing corresponding to display data at least once, and changes the number of writing of the same display data according to the detected temperature of the liquid crystal display element.   2. The liquid crystal display device according to claim 1, wherein the drive control circuit increases the number of times of writing the same display data as the detected temperature of the liquid crystal display element is within a predetermined temperature or higher and the temperature is higher. The liquid crystal display element includes a plurality of stacked cholesteric liquid crystal panels,
3. The liquid crystal display device according to claim 1, wherein the number of times of writing the same display data is individually changed for each of the plurality of cholesteric liquid crystal panels. The liquid crystal display element includes a common electrode, pixel electrodes arranged in a matrix, a liquid crystal layer in which a cholesteric liquid crystal material is disposed between the common electrode and the pixel electrode, and switching that controls application of a voltage to the pixel electrode. With elements,
The drive control circuit includes a driver that outputs a voltage applied between the common electrode and the pixel electrode, and sequentially applies a reset voltage, a stabilization voltage, a data voltage, and a sustain voltage to the cholesteric liquid crystal material. 4. The switching element corresponding to the pixel electrodes of a plurality of lines is maintained in an ON state while applying and maintaining the sustain voltage. 5. The liquid crystal display device described. A driving method of an active matrix type liquid crystal display element containing a cholesteric liquid crystal material,
Detecting the temperature of the liquid crystal display element;
The number of times of writing to apply a voltage according to display data to the pixels of the liquid crystal display element is determined according to the detected temperature of the liquid crystal display element,
A method of driving a liquid crystal display element, wherein the same data is written to the liquid crystal display element for the determined number of times of writing.

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