JP5115217B2 - Dot matrix type liquid crystal display device - Google Patents

Description

  The present invention relates to a dot matrix type liquid crystal display device, and more particularly to a dot matrix type liquid crystal display device using a cholesteric liquid crystal and performing a reset operation to reset to a planar state or a focal conic state in a first step before writing display data.

  A dot matrix type display element such as a liquid crystal display element is widely used as a monitor of a television receiver or a computer system. The dot matrix display device has a plurality of scan lines arranged in parallel and a plurality of data lines (segment lines) arranged so as to intersect the scan lines perpendicularly. Pixels are formed at the intersections of the segment lines. Writing of an image to be displayed is performed by sequentially applying scan pulses to the scan lines and outputting data for one line to a plurality of segment lines in synchronization with the application of the scan pulses. There are various types of dot matrix type display elements such as CRT, PDP, EL, and liquid crystal display elements, and liquid crystal display elements are particularly widely used.

  In recent years, electronic paper has been actively developed at companies and universities as rewritable display devices that can retain display contents even when the power is turned off. As application fields in which electronic paper is expected to be used, various application forms such as electronic books, sub-displays for mobile terminal devices, and display units for IC cards have been proposed. One of the leading methods for electronic paper is cholesteric liquid crystal. Cholesteric liquid crystal has excellent characteristics such as semi-permanent display retention (memory property), vivid color display, high contrast, and high resolution.

  Cholesteric liquid crystals are sometimes referred to as chiral nematic liquid crystals, and by adding a relatively large amount (several tens of percent) of chiral additives (chiral materials) to nematic liquid crystals, the molecules of nematic liquid crystals are helical. It is a liquid crystal that forms a cholesteric phase.

  FIG. 1 is a diagram for explaining a state of a cholesteric liquid crystal. As shown in FIGS. 1A and 1B, the display element 10 using cholesteric liquid crystal has an upper substrate 11, a cholesteric liquid crystal layer 12, and a lower substrate 13. A cholesteric liquid crystal has a planar state that reflects incident light as shown in FIG. 1A and a focal conic state that transmits incident light as shown in FIG. The state is stably maintained even in the absence of an electric field.

  In the planar state, light having a wavelength corresponding to the helical pitch of the liquid crystal molecules is reflected. The wavelength λ at which the reflection is maximum is expressed by the following formula from the average refractive index n of the liquid crystal and the helical pitch p.

λ = n · p
On the other hand, the reflection band Δλ varies greatly depending on the refractive index anisotropy Δn of the liquid crystal.

  In the planar state, incident light is reflected, so that a “bright” state, that is, white can be displayed. On the other hand, in the focal conic state, by providing a light absorption layer under the lower substrate 13, light transmitted through the liquid crystal layer is absorbed, so that a "dark" state, that is, black can be displayed.

  As described above, in the planar state, light of a wavelength corresponding to the helical pitch of the liquid crystal molecules is reflected. Therefore, the liquid crystal material and the chiral material are selected, the content of the chiral material is determined, and blue (blue), green Three panels that selectively reflect each wavelength of (green) and red (red) are obtained, and they are laminated to obtain a color display element.

  Next, a method for driving a display element using cholesteric liquid crystal will be described.

  FIG. 2 shows an example of voltage-reflection characteristics of a general cholesteric liquid crystal. The horizontal axis represents the voltage value (V) of the pulse voltage applied with a predetermined pulse width between the electrodes sandwiching the cholesteric liquid crystal, and the vertical axis represents the reflectance (%) of the cholesteric liquid crystal. The solid curve P shown in FIG. 2 shows the voltage-reflectance characteristics of the cholesteric liquid crystal whose initial state is the planar state, and the broken curve FC shows the voltage-reflectance characteristics of the cholesteric liquid crystal whose initial state is the focal conic state. .

  In FIG. 2, when a predetermined high voltage VP100 (for example, ± 36 V) is applied between the electrodes to generate a relatively strong electric field in the cholesteric liquid crystal, the helical structure of the liquid crystal molecules is completely unwound and all molecules are Becomes homeotropic according to the direction of the electric field. Next, when the liquid crystal molecules are in a homeotropic state, the applied voltage is rapidly decreased from VP100 to a predetermined low voltage (for example, VF0 = ± 4 V), and the electric field in the liquid crystal is suddenly reduced to almost zero. The spiral axis is perpendicular to the electrode, and a planar state in which light according to the spiral pitch is selectively reflected is obtained.

  On the other hand, when a predetermined low voltage VF100b (for example, ± 24V) is applied between the electrodes to generate a relatively weak electric field in the cholesteric liquid crystal, the spiral structure of the liquid crystal molecules cannot be completely solved. In this state, when the applied voltage is suddenly lowered from VF100b to the low voltage VF0 and the electric field in the liquid crystal is suddenly made substantially zero, or a strong electric field is applied and the electric field is gently removed, The helical axis is parallel to the electrode, and a focal conic state in which incident light is transmitted is obtained.

  In addition, when an electric field having an intermediate strength is applied and the electric field is rapidly removed, a planar state and a focal conic state are mixed, and halftone display is possible.

  Here, in the curve P shown in FIG. 2, within the broken line frame A, the reflectance of the cholesteric liquid crystal can be lowered by increasing the ratio of the focal conic state as the voltage value of the applied voltage pulse is increased. Further, in the curves P and FC shown in FIG. 2, within the broken line frame B, the reflectance of the cholesteric liquid crystal can be lowered by increasing the ratio of the focal conic state as the applied voltage value is lowered.

  In order to display a halftone, area A or area B is used. When the area A is used, after a pixel is initialized and brought into a planar state, a voltage pulse between VF0 and VF100a is applied to partially bring the focal conic state. Further, when the region B is used, a pixel is initialized to a focal conic state, and then a voltage pulse between VF100b and VP0 is applied to partially make a planar state.

  The principle of the driving method based on the voltage response characteristics described above will be described with reference to FIGS. 3A, 4A, and 4C show waveforms of voltage pulses. 3B, 4B, and 4D show the pulse response characteristics when the voltage pulses of FIGS. 3A, 4A, and 4C are applied, respectively. . FIG. 3A shows a voltage pulse having a voltage value of ± 36 V and a pulse width of several tens of ms. FIG. 4A shows a voltage pulse having a voltage value of ± 20 V when turned on (ON), a voltage value of ± 10 V when turned off (OFF), and a pulse width of 2 ms. FIG. 4C shows a voltage pulse having a voltage value of ± 20 V when turned on (ON), a voltage value of ± 10 V when turned off (OFF), and a pulse width of 1 ms. 3B, 4B, and 4D, the horizontal axis represents voltage (V), and the vertical axis represents reflectance (%). 3B schematically shows the curves P and FC of FIG. 2, and the voltage-reflectivity characteristics of FIGS. 4B and 4D are the curves P and FC of FIG. Only is shown schematically. The voltage pulse used here combines positive and negative pulses in order to prevent display deterioration due to polarization, as is well known as a driving pulse for liquid crystal.

  As shown in FIGS. 3A and 3B, when the pulse width is large, when the initial state is the planar state, when the voltage is raised to a certain range, the focal conic state is reached, and when the voltage is further raised, It becomes a planar state again. When the initial state is the focal conic state, the planar state is gradually increased as the pulse voltage is increased.

  When the pulse width is large, the pulse voltage that always becomes the planar state regardless of whether the initial state is the planar state or the focal conic state is ± 36 V in FIG. Also, with this intermediate pulse voltage, the planar state and the focal conic state are mixed, and a halftone is obtained.

  On the other hand, as shown in FIGS. 4A and 4B, when the pulse width is 2 ms, the reflectivity does not change when the pulse voltage is ± 10 V when the initial state is the planar state. The planar state and the focal conic state are mixed, and the reflectance decreases. The amount of decrease in reflectivity increases as the voltage increases, but the amount of decrease in reflectivity becomes constant when the voltage becomes higher than ± 36V. This is the same even when the initial state is a mixture of the planar state and the focal conic state. Therefore, when the initial state is the planar state, the reflectance decreases to some extent when a voltage pulse having a pulse width of 2 ms and a pulse voltage of ± 20 V is applied once. In this way, when the planar state and the focal conic state are mixed and the reflectance is slightly lowered, when a voltage pulse having a pulse width of 2 ms and a pulse voltage of ± 20 V is further applied, the reflectance is further lowered. When this is repeated, the reflectance decreases to a predetermined value.

  As shown in FIGS. 4C and 4D, when the pulse width is 1 ms, the reflectance is lowered by applying a voltage pulse, as in the case where the pulse width is 2 ms. The degree of decrease is smaller than that when the pulse width is 2 ms.

  From the above, if a pulse of 36V is applied with a pulse width of several tens of ms, a planar state is obtained, and if a pulse of about 10 to 20V is applied with a pulse width of about 2 ms, the planar state is changed to the planar state. It is considered that the reflectivity decreases due to the mixed state, and the decrease in reflectivity is related to the accumulated pulse time.

  Therefore, in the cholesteric liquid crystal display element, an initialization (reset) pulse with a pulse width of several tens of ms is applied to the pixel to be rewritten in the first step to make it a planar state, and in the next second step, the pixel to be halftone A gradation pulse having a narrow pulse width of about ± 20.0 V is applied, and the cumulative application time is set to a value corresponding to the halftone level. In other words, this display method displays the halftone level using the area A in FIG.

  In the above description, the case where the initialization state is the planar state has been described. However, the initialization state is the focal conic state, and after resetting to the focal conic state in the first step, the pixels to be halftone in the second step are narrow. It is also possible to display a halftone by applying a grayscale pulse having a pulse width of about ± 20.0 V and mixing the planar state and the focal conic state. In the following description, the case where the initialization (reset) state is the planar state will be described as an example.

  In the display element, a plurality of scan electrodes parallel to each other are provided on one surface of the display material layer, and a plurality of data electrodes parallel to each other are provided on the other surface of the display material layer. Pixels are formed at the intersections of the data electrodes. Here, the scan electrode is referred to as a scan line, and the data electrode is referred to as a data line. In the display element, the common driver applies a scan pulse to the scan line, and the segment driver applies a data pulse to the data line. It is preferable from the viewpoint of cost that the driver uses a general-purpose STN driver having a binary output.

  As will be described later, in the first step, a reset operation is performed by simultaneously applying pulses to all the scan lines and all the data lines in order to shorten the time. In the second step, since the gradation level is set for each pixel, when the scan pulse is applied to one scan line, the data pulse is applied to all the data lines, so that the pixels in one scan line are applied. The voltage pulse is applied. Thereafter, the application of the voltage pulse to the pixels of all the scan lines is completed while sequentially shifting the scan lines to which the scan pulses are applied.

  In the second step, while the selected scan voltage corresponding to the scan pulse is applied to one scan line, the non-selected scan voltage is applied to the other scan lines. In addition, a selection data voltage corresponding to the data pulse is applied to the data line of the pixel that performs gradation writing, and a non-selection data voltage is applied to the data line of the pixel that does not perform gradation writing. Therefore, a pixel to which a selected scan voltage and a selected data voltage are applied, a pixel to which a non-selected scan voltage and a selected data voltage are applied, a pixel to which a selected scan voltage and a non-selected data voltage are applied, and a non-selected scan voltage and a non-selected voltage. There are pixels to which the selected data voltage is applied. Selective scan voltage and non-selected scan so that the reflectance (gradation) is reduced only in the pixels to which the selected scan voltage and the selected data voltage are applied, and the reflectance (gradation) is not lowered in the other three types of pixels. It is necessary to set the voltage, the selected data voltage, and the non-selected data voltage.

  In a display device using a cholesteric liquid crystal, the segment driver and the common driver output, for example, pulses as shown in FIG. 5A as gradation pulses to be applied to change from the planar state to the halftone level. By applying such a pulse, a voltage as shown in FIG. 5B is applied to the pixel. The reason for having the positive electrode phase and the negative electrode phase is to prevent the polarization described above.

  The segment driver is supplied with 20V as V0, 10V as V21S and V34S, the base voltage is 10V, V0 pulse in the positive phase (FR = 1), 0V pulse in the negative phase (FR = 0) Is output.

  The common driver is supplied with 20V as V0, 15V as V21C, and 5V as V341C. In the positive phase (FR = 1), the base voltage is 15V and the pulse of 0V is supplied in the negative phase (FR = 0). The base voltage is 5V and a pulse of 20V is output.

  When a pulse as shown in FIG. 5A is applied, the scan line is in a selected state (common is on) and the data line is also in a selected state (segment is on). 20V is applied in the negative phase (FR = 0). When the scan line is selected (common is on) and the data line is not selected (segment is off), 10V is applied in the positive phase (FR = 1) and -10V is applied in the negative phase (FR = 0). The When the scan line is not selected (common is off) and the data line is selected (segment is on), 5 V is applied in the positive phase (FR = 1) and −5 V is applied in the negative phase (FR = 0). The When the scan line is in the non-selected state (common is off) and the data line is in the non-selected state (segment is off), -5V is applied in the positive phase (FR = 1) and 5V is applied in the negative phase (FR = 0). Is done.

  Therefore, the waveform of the voltage pulse applied to each pixel of the scan line in the selected state is as shown in FIG. 6A, and the waveform of the voltage pulse applied to each pixel of the scan line in the non-selected state is shown in FIG. 6B, in both cases, the waveform of the selected data line is indicated by a solid line, and the waveform of the non-selected data line is indicated by a dotted line. As shown in FIG. 4B, in the case of a voltage pulse with a pulse width of 2 ms, the state of the liquid crystal, that is, the reflectance changes when the voltage is ± 20 V, but the reflectance does not change when the voltage is ± 10 V. In the case of the waveform as described above, when both the scan line and the data line are ON, writing by the gradation pulse is performed, and in other cases, writing is not performed. Actually, there is a problem of crosstalk, but since it is not directly related to the present invention, description thereof is omitted.

  As described above, the voltage pulse actually applied in the display device has a waveform as shown in FIG. 6, but in the following description, in order to simplify the explanation, it is a positive / negative pulse symmetrical about 0V. May represent. Further, the OFF pulse voltage is set to a level at which writing is not performed, and the pulse voltage indicates the ON pulse voltage.

  Various driving methods have been proposed for multi-tone display methods using cholesteric liquid crystals. The driving method of multi-tone display of cholesteric liquid crystal can be divided into two methods of dynamic driving and conventional driving.

  Patent Document 1 describes a dynamic driving method. However, the dynamic driving method has a problem that the manufacturing waveform is high because the driving waveform is complicated, so that a complicated control circuit and a driver IC are required, and the transparent electrode of the panel is also required to have a low resistance. In addition, the dynamic driving method has a problem that power consumption is large.

  Non-Patent Document 1 describes a conventional driving method. Non-Patent Document 1 uses a cumulative time peculiar to liquid crystal and adjusts the number of times a short pulse is applied to gradually change the quasi-video rate from the planar state to the focal conic state or from the focal conic to the planar state. A method of driving at high speed is described.

  When the gradation is set using the cumulative time in the conventional driving method, there are a method of adjusting the number of times of applying a short pulse and a method of making the pulse width W different. The method of varying the pulse width is more advantageous in suppressing power consumption than adjusting the number of times of applying a short pulse. Furthermore, there is a method of changing the accumulated time of pulse application by both the pulse width and the number of pulse applications. FIG. 7 is a diagram showing an example of a voltage pulse in such a method, and shows a voltage pulse and a gradation state that changes by applying the voltage pulse.

  FIG. 7A shows a reset pulse used in the first step. The pulse voltage is ± 36 V and has a relatively large pulse width. By applying this reset pulse, the liquid crystal of the pixel is in a planar state and is in a maximum gradation state. 7B to 7D are first to third gradation pulses used in the second step, each having a pulse voltage of ± 20 V, but pulsed in the order of the first to third gradation pulses. The width becomes narrower. When the pulses (B) to (D) in FIG. 7 are applied, a part of the liquid crystal in the pixel changes from the planar state to the focal conic state, and the gradation is lowered. Decreases from (D) to (D). In other words, when the pulses (B) to (D) are applied, the gradation becomes relatively low, medium, and high. Here, (B) is referred to as a low gradation pulse, (C) as a medium gradation pulse, and (D) as a high gradation pulse. In this case, only one of the pulses (B) to (D) is applied or only none is applied, so that four gradations can be expressed, but the three types of pulses shown in FIG. 7 can be combined. is there. For example, it is possible to express a large number of gradations by combining n periods T into one line period nT and selecting a pulse width in each period T. Further, by applying gradation pulses in a plurality of frames and selecting whether or not to apply any of the pulses (B) to (D) in each frame, a large number of gradations can be obtained. It is possible to express.

  As described above, the display method of the cholesteric liquid crystal display element is greatly different from a normal liquid crystal display element using a twisted nematic liquid crystal or the like, and the driving method is also greatly different accordingly.

  8A and 8B are diagrams for explaining a driving sequence of the cholesteric liquid crystal display element. FIG. 8A shows a state before the reset operation, FIG. 8B shows a state after the reset operation, and FIG. It shows the state in the middle of going. As shown in the figure, a common driver 28 that drives a scan line of the panel 10 and a segment driver 29 that drives a data line of the panel 10 are connected to the display element (panel) 10. The image displayed on the panel 10 as shown in FIG. 8A is erased as shown in FIG. 8B by performing the reset operation, and the entire screen becomes uniform. Thereafter, display data is written as shown in FIG.

  Since the cholesteric liquid crystal has display holding characteristics (memory property), when writing to the display device, a reset operation for erasing previous display contents is required before writing. In the reset operation, the cholesteric liquid crystal is brought into a planar state by applying a voltage pulse having a width greater than VP100 in FIG.

  FIG. 9 is a time chart of drive signals for the common driver 28 in the reset operation when the common driver 28 and the segment driver 29 are configured by general-purpose binary STN drivers. With the forced OFF signal / DSPOF set to “L (0)” and the driver output turned off, the input data DIO is set to “H (1)” and the data fetch clock LP-COM is input to select all lines. To. When the polarity control signal FR is set to “1” and / DSPOF is changed to “1”, a reset voltage is output to all the scan lines. At the same time, the segment driver 29 also outputs a reset voltage to all data lines, and a positive phase reset voltage is applied to all pixels. When FR is changed to “0” after a predetermined time (several tens of ms), a reset voltage is output to all scan lines and all data lines, and a reset voltage in the negative phase is applied to all pixels.

  FIG. 10 is a diagram illustrating voltages output from the common driver 28 and the segment driver 29 and voltages applied to the pixels during the reset operation. Here, a reset voltage pulse of ± 36V is applied.

  Since the power consumption of the reset operation is proportional to the panel size, the reset operation requires a large power consumption in a large display device with a large number of lines. In particular, when the inrush current is large, not only does the power supply circuit become a heavy burden, but it is necessary to use a driver having a high driving capability, which increases the cost. As described above, when a reset voltage pulse is simultaneously applied to all the pixels in the reset operation, there is a problem that the inrush current becomes very large.

  Patent Document 2 describes that inrush current is reduced by shifting the phase of a reset voltage pulse applied to each scan line.

  Patent Document 3 describes that the inrush current is reduced by reducing the number of scan lines to which the reset voltage pulse is simultaneously applied and by shifting the phase of the reset voltage pulse.

JP 2001-228459 A Japanese Patent Laid-Open No. 2001-100196 JP 2005-266163 A Y.-M.Zhu, D-K.Yang, Cumulative Drive Schemes for Bistable Reflective Cohlesteric LCDs, SID 98 DIGEST, pp798-801, 1998

  Although the inrush current is reduced by the techniques described in Patent Documents 2 and 3, the dot matrix liquid crystal display device, particularly electronic paper, is required to further reduce the inrush current.

  Patent Documents 2 and 3 describe reducing the number of scan lines to which a reset voltage pulse is simultaneously applied and shifting the phase of the reset voltage pulse, but each pixel has a positive phase and a negative phase. The reset pulse is continuously applied, and the polarity inversion discharges the charge charged to one polarity (for example, +) and then charges to the other polarity (for example,-). Therefore, there is a problem that the power load increases.

  An object of the present invention is to realize a dot matrix liquid crystal display device with a low inrush current and a small power load.

  In the dot matrix type liquid crystal display device disclosed herein, the number of scan lines to which the first polarity reset voltage is applied is gradually increased to a predetermined number before the display data is written, and then the first polarity reset voltage is applied. Resetting the display element to an initial state by stopping the application of the second polarity reset voltage after gradually increasing the number of scan lines to which the second polarity reset voltage is applied to a predetermined number I do.

  In the disclosed dot matrix liquid crystal display device, the number of scan lines to which the first and second polarity reset voltages are applied is gradually increased to a predetermined number, so that the charge amount is dispersed and the inrush current can be reduced. Further, since the application of the reset voltage of the first polarity and the application of the reset voltage of the second polarity are performed separately, the power load is 1 as compared with the case where the application of the reset voltage of the first and second polarity is continuously performed. / 2.

  FIG. 11 is a diagram illustrating a configuration of the display element 10 used in the embodiment. As shown in FIG. 11, the display element 10 includes three panels, a blue panel 10 </ b> B, a green panel 10 </ b> G, and a red panel 10 </ b> R, in order from the viewing side. The light absorption layer 17 is provided below the red panel 10R. The panels 10B, 10G, and 10R have the same configuration, but the panel 10B has a blue central wavelength of reflection (about 480 nm), the panel 10G has a green central wavelength of reflection (about 550 nm), and the panel 10R has a central wavelength of reflection. The liquid crystal material and the chiral material are selected so as to be red (about 630 nm), and the content of the chiral material is determined. Panels 10B, 10G, and 10R are driven by blue layer control circuit 18B, green layer control circuit 18G, and red layer control circuit 18R, respectively.

  FIG. 12 is a diagram showing a basic configuration of one panel 10A among the three panels 10B, 10G, and 10R constituting the display element 10 of FIG. The three panels 10B, 10G, and 10R have a substantially common configuration except for the reflection wavelength. The panel used in the embodiment will be described with reference to FIG.

  As shown in FIG. 12, the display element 10A includes an upper substrate 11, an upper electrode layer 14 provided on the surface of the upper substrate 11, a lower electrode layer 15 provided on the surface of the lower substrate 13, and a seal. Material 16. The upper substrate 11 and the lower substrate 13 are arranged so that the electrodes face each other, and after sealing a liquid crystal material therebetween, they are sealed with a sealing material 16. A spacer is disposed in the liquid crystal layer 12 but is not shown. A voltage pulse signal is applied from the drive circuit 18 to the electrodes of the upper electrode layer 14 and the lower electrode layer 15, whereby a voltage is applied to the liquid crystal layer 12. A voltage is applied to the liquid crystal layer 12 to display the liquid crystal molecules in the liquid crystal layer 12 in a planar state or a focal conic state. As described above, the display element 10A has a memory property, and the planar state and the focal conic state are maintained even after the application of the pulse voltage is stopped.

  The upper substrate 11 and the lower substrate 13 are both translucent, but the lower substrate 13 of the panel 10R may be opaque. Although there exists a glass substrate as a board | substrate which has translucency, you may use film substrates, such as PET (polyethylene terephthalate) and PC (polycarbonate), besides a glass substrate.

  As a material for the electrodes of the upper electrode layer 14 and the lower electrode layer 15, for example, indium tin oxide (ITO) is representative, but other indium zinc oxide (IZO: Indium Zic Oxide), etc. It is possible to use a transparent conductive film.

  The transparent electrode of the upper electrode layer 14 is formed as a plurality of strip-shaped upper transparent electrodes parallel to each other on the upper substrate 11, and the transparent electrode of the lower electrode layer 15 is a plurality of strip-shaped parallel to each other on the lower substrate 13. Is formed as a lower transparent electrode. The upper substrate 11 and the lower substrate 13 are arranged so that the upper electrode and the lower electrode intersect when viewed from a direction perpendicular to the substrate, and pixels are formed at the intersection. An insulating functional film is formed on the electrode. The functional film is a thin film having a function of preventing a short circuit between the electrodes of the liquid crystal display element and improving the reliability of the liquid crystal display element as a gas barrier layer. If this thin film is thick, it is necessary to increase the drive voltage, and it becomes difficult to configure a drive circuit with a general-purpose STN driver. Conversely, if there is no thin film, a leakage current flows, which causes a problem that power consumption increases. Here, since the thin film has a relative dielectric constant of about 5 and is considerably lower than that of the liquid crystal, the thickness of the thin film is suitably about 0.3 μm or less.

This insulating thin film can be realized by a thin film of SiO ₂ or an organic film such as polyimide resin or acrylic resin known as an orientation stabilizing film.

  As described above, the spacers are arranged in the liquid crystal layer 12 so that the distance between the upper substrate 11 and the lower substrate 13, that is, the thickness of the liquid crystal layer 12 is constant. The spacer is generally a sphere made of a resin or an inorganic oxide, but it is also possible to use a fixed spacer having a substrate surface coated with a thermoplastic resin. The cell gap formed by this spacer is suitably in the range of 3.5 μm to 6 μm. If the cell gap is smaller than this value, the reflectance is lowered and the display is dark. On the other hand, if the cell gap is larger than this value, the driving voltage rises and driving by the general-purpose driver IC becomes difficult.

  The liquid crystal composition forming the liquid crystal layer 12 is a cholesteric liquid crystal obtained by adding 10 to 40% by weight (wt%) of a chiral material to a nematic liquid crystal mixture. Here, the addition amount of the chiral material is a value when the total amount of the nematic liquid crystal component and the chiral material is 100 wt%.

  As the nematic liquid crystal, various types of conventionally known liquid crystals can be used, but a liquid crystal material having a dielectric anisotropy (Δε) in the range of 15 to 50 is desirable. If the dielectric anisotropy is too lower than this range, the drive voltage will increase. Conversely, if the dielectric anisotropy is too higher than this range, the drive voltage itself will decrease, but the specific resistance will be reduced, particularly increasing the power consumption at high temperatures. However, the stability and reliability of the device are reduced, and image defects and image noise are likely to occur. If the dielectric anisotropy is 15 or more, the drive voltage is relatively low, and if it is 20 or more, the selection range of usable chiral materials is widened.

  The refractive index anisotropy (Δn) is preferably 0.18 to 0.24. If the refractive index anisotropy is smaller than this range, the reflectivity in the planar state is low, resulting in a dark display with insufficient brightness. If the refractive index anisotropy is larger than this range, the scattering reflection in the focal conic state is increased. In addition to a blurred display with insufficient purity and contrast, the viscosity increases and the response speed decreases. A lower viscosity can suppress voltage increase and contrast decrease at low temperatures.

  FIG. 13 is a diagram illustrating an overall configuration of the display device according to the embodiment. The display element 10 is A4 size XGA specification and has 1024 × 768 pixels. The power source 21 outputs a voltage of 3V to 5V, for example. The boosting unit 22 boosts the input voltage from the power source 21 to 36V to 40V by a regulator such as a DC-DC converter. As this boost regulator, a dedicated IC is widely used, and the IC has a function of adjusting the boost voltage by setting a feedback voltage. Therefore, it is possible to change the boosted voltage by selecting a plurality of voltages generated by voltage division by a resistor and supplying the selected voltages to the feedback terminal.

  The voltage switching unit 23 generates various voltages by resistance division or the like. For switching between the reset voltage and the gradation write voltage in the voltage switching unit 23, an analog switch having a high withstand voltage may be used, but a simple switching circuit using a transistor can also be used. The voltage stabilizing unit 24 desirably uses an operational amplifier voltage follower circuit in order to stabilize various voltages supplied from the voltage switching unit 23. It is desirable to use an operational amplifier having a strong characteristic against a capacitive load. In addition, the structure which switches an amplification factor by switching the resistance connected to an operational amplifier is widely known, and if this structure is used, the voltage output from the voltage stabilization part 24 can be switched easily.

  The original oscillation clock unit 25 generates a basic clock that is a basic operation. The frequency divider 26 divides the basic clock to generate various clocks necessary for the operation described later.

  The control circuit 27 generates a control signal based on the basic clock, various clocks, and the image data D, and supplies the control signal to the common driver 28 and the segment driver 29. The control circuit 27 is realized by a microcomputer or FPGA. The common driver 28 and the segment driver 29 drive the three panels 10B, 10G, and 10R independently.

  The common driver 28 drives 1024 scan lines of each panel, and the segment driver 29 drives 768 data lines. Since the image data given to each pixel of RGB is different, the segment driver 29 drives each data line independently. In this embodiment, a general-purpose binary output STN driver is used as the driver IC. Various general-purpose STN drivers can be used.

  The image data input to the segment driver 29 is 4-bit data D0-D3 obtained by converting a full-color original image into 4096 colors of RGB with 16 gradations using an error diffusion method. The gradation conversion is preferably performed by a method capable of obtaining high display quality, and a blue noise mask method or the like can be used in addition to the error diffusion method.

  FIG. 14 is a circuit diagram when the common driver 28 and the segment driver 29 for driving the three panels 10B, 10G, and 10R are configured using general-purpose STN drivers. As shown, the common driver 28B that drives the scan line of the blue panel 10B is composed of two driver ICs 28B-1 and 28B-2, and the segment driver 29B that drives the data line is a single driver IC 29B. Composed. The same applies to the other panels. A drive circuit using a general-purpose STN driver IC is widely known and has been described with reference to FIGS. Also, display data writing processing is widely known, and the disclosed technique is not limited to the writing processing method, and therefore description of the writing processing is also omitted.

  FIG. 15 is a diagram illustrating a reset operation in the display device according to the first embodiment. A black portion in the panel 10 indicates a selected line to which a scan pulse is applied from the common driver 28, and a white portion indicates a non-selected line to which no scan pulse is applied. FIG. 16 is a diagram illustrating a control signal applied to the common driver during the reset operation of FIG. 15 and a scan pulse applied to the scan line of the panel 10.

  The common driver 28 and the segment driver 29 are supplied with the voltage shown in FIG. As shown in the figure, in the positive polarity sequence of FR = 1, after FR is set to “1”, DIO and / DSPOF are set to a value “1” indicating a selected state, and a clock signal is input to LP-COM. Since data is captured in synchronization with the fall of the clock signal, a positive reset voltage (0 V) is output to the first output line of the common driver 28 at the first fall of the clock. At this time, since the segment driver 29 outputs the positive reset voltage (36V), the positive reset pulse voltage 36V is applied to the first scan line SP1. Since the non-selection voltage (36V) is output to the other output lines of the common driver 28, 0V is applied to the pixels on the second and subsequent scan lines SP2-SPn.

  In synchronization with the fall of the next clock signal, a reset voltage is also output to the second output line of the common driver 28, and positive polarity reset is performed on the pixels of the first and second scan lines SP1 and SP2. A pulse voltage of 36V is applied. Thereafter, as shown in FIG. 15, the number of selected scan lines gradually increases, and all the scan lines are selected. As a result, a positive reset pulse voltage 36V is applied to all pixels.

  Next, when DIO is set to a value “0” indicating a non-selected state, the first output line of the common driver 28 is in a non-selected state and outputs 36 V, so that 0 V is output to the first scan line SP1. Is done. Thereafter, as shown in FIG. 15, the number of scan lines in the non-selected state gradually increases, and all the scan lines are in the non-selected state. At this time, 0 V is applied to all pixels.

  Next, as shown in FIG. 16, the negative polarity sequence is started by setting FR to “0” and DIO to “1”. Since DIO is “1”, in synchronization with the fall of the clock signal, the first output line of the common driver 28 is selected and outputs a negative reset voltage (36 V). At this time, since the segment driver 29 outputs a negative reset voltage (0V), the negative reset pulse voltage −36V is applied to the first scan line SP1. Note that 0 V is applied to pixels on the second and subsequent scan lines SP2-SPn. Thereafter, as shown in FIG. 15, the number of selected scan lines gradually increases, and all the scan lines are selected. As a result, a negative reset pulse voltage of −36 V is applied to all pixels.

  Next, when DIO is set to a value “0” indicating a non-selected state, the first output line of the common driver 28 is in a non-selected state and outputs 0 V, so that 0 V is applied to the pixels of the first scan line SP1. Is output. Thereafter, as shown in FIG. 15, the number of scan lines in the non-selected state gradually increases, and all the scan lines are in the non-selected state. At this time, 0 V is applied to all pixels.

  As described above, the entire surface of the panel 10 is reset.

  17 and 18 are diagrams for explaining the principle of the reset operation in the embodiment. In the cholesteric liquid crystal electronic paper, since the pixel has a capacitive load, the pixel is shown as a capacitor C in FIG. Pixels are formed corresponding to the intersections of the scan lines driven by the common driver 28 and the data lines driven by the segment driver 29, and the pixels are shown as capacitors C connected between the scan lines and the data lines. .

  As shown in FIG. 18A, when the first scan line is selected, 0V is applied, and a capacitor C connected between the data line to which 36V is applied and the scan line. Is charged. Since 36 V is applied to the other scan lines in a non-selected state, both the data line and the scan line are 36 V, and the capacitor C is not charged. In this way, since charging is performed on pixels for one scan line, the charging current is small.

  When the charging of the pixels of the first scan line is completed, the charging current decreases. When the second scan line is also selected in this state, the pixels of the second scan line are charged as shown in FIG. Also in this case, since charging is performed for pixels corresponding to one scan line, the charging current is small. Hereinafter, the pixels of all the scan lines are charged while increasing the number of scan lines in the selected state. However, since the pixels that are charged simultaneously are pixels for one scan line, the charging current is small.

  (C) of FIG. 18 is a figure which shows the change of the charging current Imax. As shown in the figure, Imax indicates a pulse shape that once rises to a predetermined value and attenuates using the product of the total capacitance and resistance of pixels for one scan line as a time constant. Here, the pulse interval Δt is a time interval for increasing the selected scan line by one line. In order to reduce the charging current, it is desirable that the pulse interval Δt is longer than the time until the charging current pulse decays to approximately zero.

  When increasing the number of scan lines in the non-selected state, a discharge current flows from the capacitor C. However, since the discharge is performed for pixels for one scan line, the discharge current is small.

  In the case of the negative polarity, only the voltages output from the common driver 28 and the segment driver 29 are reversed, and the charging current and discharging current are small.

  In the first embodiment, since the negative charge and discharge are performed after the positive charge and discharge are performed on the entire surface of the panel, the power load is smaller than in the case of performing one line at a time as in Patent Document 3. small.

  In the above description, the number of scan lines to be changed to the selected state or the non-selected state is one by one. However, if there is a margin in the drive performance and power supply load of the driver, the number of scan lines to be changed is plural. For example, two scan lines may be changed to a selected state or a non-selected state. As a result, the charge amount and the discharge current increase as compared with the case where the charge amount and the discharge current are changed one by one (although n times the number), the reset operation time can be shortened.

  FIG. 19 is a diagram illustrating a reset operation in the display device according to the second embodiment. FIG. 20 is a diagram showing control signals applied to the common driver during the reset operation of FIG.

  In the display device of the first embodiment, when all the scan lines are selected and then set to the non-selected state, that is, when discharging, the number of non-selected scan lines is gradually increased to discharge. went. As a result, the discharge current can be reduced. However, at the present time, the discharge current is merely wasted, and even if all the pixels are discharged simultaneously, there is no power load. Therefore, in the display device of the second embodiment, the positive and negative charges are performed in the same manner as in the first embodiment, but the discharge is performed simultaneously for all the pixels as described in FIGS.

  As shown in FIG. 20, in the first half of the positive polarity sequence, as in the first embodiment, FR, DIO and DSPOF are set to “1” and LP-COM is supplied. Accordingly, as shown in FIG. 19, as in the first embodiment, the number of scan lines in the positive polarity selected state gradually increases, and all the scan lines are selected. The supply of LP-COM is stopped, and this state is maintained for a predetermined period (several tens of ms). Then, DSPOF and DIO are set to “0”, a clock with a high frequency is supplied as LP-COM, and the internal output of the scan driver is set to the non-selected state, and then DSPOF is set to “1”. Deselect all scan lines. The same applies to the negative polarity sequence. Similarly to the first embodiment, the number of scan lines in the negative polarity selection state is gradually increased, and after all the scan lines are in the selection state, DSPOF is set to “0”. After the internal output of the scan driver is set to the non-selected state, DSPOF is set to “1” to set all the scan lines to the non-selected state.

  FIG. 21 is a diagram illustrating a reset operation in the display device according to the third embodiment.

  In the first and second embodiments, the number of scan lines in the selected state is gradually increased until all the scan lines are in the selected state. However, as shown in FIG. 4 groups), and the reset operation of the first or second embodiment can be performed for each group. In the third embodiment, the time interval for applying positive and negative pulses is shortened, which is advantageous when using a liquid crystal material that is easily polarized.

  Although the embodiment has been described above, it goes without saying that various modifications are possible.

  For example, the example of the color cholesteric liquid crystal display element having the three-layer structure shown in FIG. 13 has been described. However, the disclosed technique can be similarly applied to a single-layer cholesteric liquid crystal display element and a two-layer cholesteric liquid crystal display element. . It is also possible to apply the configuration described in Patent Documents 2 and 3 that shifts the phase to the drive signals of each layer.

  Further, any method may be used for writing the image data after the reset operation.

FIG. 1 is a diagram illustrating a bistable state (planar state and focal conic state) of a cholesteric liquid crystal. FIG. 2 is a diagram for explaining a change in the state of the cholesteric liquid crystal due to the pulse voltage. FIG. 3 is a diagram for explaining a change in reflectance due to a large voltage applied to the cholesteric liquid crystal and a pulse having a wide pulse width. FIG. 4 is a diagram for explaining a change in reflectance due to an intermediate voltage applied to the cholesteric liquid crystal and pulses of two narrow pulse widths. FIG. 5 is a diagram illustrating a driver output voltage and a liquid crystal application voltage when a grayscale pulse is applied. FIG. 6 is a diagram illustrating an example of a symmetrical pulse that is actually applied. FIG. 7 is a diagram illustrating an example of an initialization pulse applied to the liquid crystal and a plurality of gradation pulses having different pulse widths. FIG. 8 is a diagram for explaining a conventional full-scale planar reset process. FIG. 9 is a time chart showing common driver signals in the conventional full-scale planar reset process. FIG. 10 is a diagram showing the driver output voltage and the applied voltage in the full-plane planar reset process. FIG. 11 is a diagram illustrating a stacked structure of cholesteric liquid crystal elements of the color display device according to the embodiment. FIG. 12 is a diagram illustrating a structure of one cholesteric liquid crystal element of the color display device according to the embodiment. FIG. 13 is a diagram illustrating a schematic configuration of the color display device according to the embodiment. FIG. 14 is a diagram illustrating a configuration of a drive circuit configured with a general-purpose STN driver in the embodiment. FIG. 15 is a diagram for explaining a reset operation in the first embodiment. FIG. 16 is a time chart showing signals of the common driver in the reset operation of the first embodiment. FIG. 17 is a diagram showing an equivalent circuit of the panel for explaining the reset operation in the first embodiment. FIG. 18 is a diagram illustrating the reset operation according to the first embodiment using an equivalent circuit. FIG. 19 is a diagram illustrating a reset operation according to the second embodiment. FIG. 20 is a time chart showing common driver signals in the reset operation of the second embodiment. FIG. 21 is a diagram for explaining a reset operation in the third embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Display element 11 Upper substrate 12 Liquid crystal layer 13 Lower substrate 14 Upper electrode layer 15 Lower electrode layer 17 Light absorption layer 18 Control circuit 21 Power supply 22 Booster part 23 Voltage switching part 24 Voltage stabilization part 27 Control circuit 28 Common driver 29 Segment driver

Claims (6)

A dot matrix type liquid crystal display element having a memory liquid crystal layer, a plurality of scan lines and a plurality of data lines;
A common driver for driving the plurality of scan lines;
A segment driver for driving the plurality of data lines;
A control circuit for controlling the common driver and the segment driver,
The control circuit sequentially increases the number of the scan lines to which the reset voltage of the first polarity is applied to a predetermined number before the display driver writes the display data to the common driver and the segment driver, and then the first polarity. When applying the reset voltage of the second polarity to the predetermined number of scan lines to which the reset voltage of the first polarity is applied, the application of the reset voltage is stopped, after sequentially increasing the number to the predetermined number, and controls so as to stop the application of the second polarity reset voltage,
The application of the first and second polarity reset voltages is stopped by sequentially decreasing the number of the scan lines to which the first and second polarity reset voltages are applied to 0, thereby the dot matrix type. 2. A dot matrix type liquid crystal display device characterized in that a liquid crystal display element is in an initial state. A dot matrix type liquid crystal display element having a memory liquid crystal layer, a plurality of scan lines and a plurality of data lines;
A common driver for driving the plurality of scan lines;
A segment driver for driving the plurality of data lines;
A control circuit for controlling the common driver and the segment driver,
The control circuit sequentially increases the number of the scan lines to which the reset voltage of the first polarity is applied to a predetermined number before the display driver writes the display data to the common driver and the segment driver, and then the first polarity. When applying the reset voltage of the second polarity to the predetermined number of scan lines to which the reset voltage of the first polarity is applied, the application of the reset voltage is stopped, after sequentially increasing the number to the predetermined number, and controls so as to stop the application of the second polarity reset voltage,
The application of the first and second polarity reset voltages is stopped by simultaneously stopping the application of the first and second polarity reset voltages to the predetermined number of the scan lines. 2. A dot matrix type liquid crystal display device characterized in that a liquid crystal display element is in an initial state. The memory-type liquid crystal layer, a dot-matrix type liquid crystal display device according to claim 1 or 2, characterized in that a liquid crystal layer forming a cholesteric phase. The time interval for sequentially increasing the number of the scan lines for applying a second polarity of the reset voltage, claim 1, wherein the go than a length the charging time of the pixel of the scan line number to be increased at a time 4. A dot matrix type liquid crystal display device according to any one of items 1 to 3 . Before writing display data to a dot matrix type liquid crystal display element having a memory liquid crystal layer, a plurality of scan lines, and a plurality of data lines, a first polarity reset voltage and a second polarity reset are applied to the dot matrix type liquid crystal display element. A dot matrix type liquid crystal display element resetting method for applying a voltage to bring the dot matrix type liquid crystal display element into an initial state,
Sequentially increasing the number of scan lines to which the reset voltage of the first polarity is applied to a predetermined number;
Stop applying the reset voltage of the first polarity;
When applying a second polarity of the reset voltage to the scan lines of the predetermined number of applying the first polarity reset voltage, sequentially the number of the scan lines for applying the second polarity reset voltage to the predetermined number Increase,
Stop applying the reset voltage of the second polarity ;
Stopping application of the first and second polarity reset voltages is performed by sequentially decreasing the number of scan lines to which the first and second polarity reset voltages are applied to zero. A reset method for a matrix type liquid crystal display element. Before writing display data to a dot matrix type liquid crystal display element having a memory liquid crystal layer, a plurality of scan lines, and a plurality of data lines, a first polarity reset voltage and a second polarity reset are applied to the dot matrix type liquid crystal display element. A dot matrix type liquid crystal display element resetting method for applying a voltage to bring the dot matrix type liquid crystal display element into an initial state,
Sequentially increasing the number of scan lines to which the reset voltage of the first polarity is applied to a predetermined number;
Stop applying the reset voltage of the first polarity;
When applying a second polarity of the reset voltage to the scan lines of the predetermined number of applying the first polarity reset voltage, sequentially the number of the scan lines for applying the second polarity reset voltage to the predetermined number Increase,
Stop applying the reset voltage of the second polarity ;
Stopping application of the first and second polarity reset voltages simultaneously stops application of the first and second polarity reset voltages to the predetermined number of the scan lines. How to reset the display element.

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