JP2013093649A - Semiconductor relay device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor relay device capable of entirely reducing the size, the cost and the mounting area of chips.SOLUTION: A p-channel type MOSFET208 (see fig. (a)) (in a charge-discharge circuit) formed on a conventional p-type single crystal silicon island 213 is replaced with an n-channel type MOSFET8 (see fig. (b)) formed on an n-type single crystal silicon island 13. With this, even when the cross sectional area of passage of carriers in the n-type single crystal silicon island 13 is reduced to a half of the cross sectional area of passage of carriers in the p-type single crystal silicon island 213, the identical resistance value is ensured in the passage of carriers. Therefore, by forming the MOSFET8 with a n-channel type in the n-type single crystal silicon island 13, the gate width W3 of the MOSFET8 can be reduced to be smaller than the gate width W1 of the conventional MOSFET208 without increasing the ON-resistance to be larger than that of the conventional MOSFET208.

Description

  The present invention relates to an optically coupled semiconductor relay device.

  In recent years, optically coupled semiconductor relay devices have been increasingly used in place of conventional electromagnetic relay devices. This optically coupled semiconductor relay device has advantages such as small size, high sensitivity, high speed, and high reliability as compared with an electromagnetic relay device. In an optically coupled semiconductor relay device, an input (electrical) signal is converted into an optical signal by a light emitting element (for example, an LED (Light Emitting Diode)), and a light receiving element (for example, a photodiode array) optically coupled to the light emitting element. The received optical signal is converted into an electrical signal. The optically coupled semiconductor relay device outputs a signal from an output terminal by driving a semiconductor switching element such as a MOSFET or a bipolar transistor with the electrical signal converted by the light receiving element. .

  In the conventional optically coupled semiconductor relay device, the semiconductor switching element and the light receiving element are generally formed on a p-type single crystal silicon island on a dielectric isolation substrate (see, for example, Patent Document 1). ).

Japanese Patent Laid-Open No. 2005-252909

  However, with the recent revision of safety standards such as JIS (Japan Industrial Standard), there is an increasing need for improving the breakdown voltage of the semiconductor relay device. In order to improve the breakdown voltage of the semiconductor relay device, the distance between the electrodes of the semiconductor elements such as the semiconductor switching element and the light receiving element (for example, the distance between the drain and the source) is set to the semiconductor element in the conventional semiconductor relay device. It is necessary to make it larger than the distance between the electrodes. For this reason, the chip size of each semiconductor element in the semiconductor relay device becomes large, which causes problems such as an increase in chip cost and an increase in mounting area in the semiconductor relay device.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor relay device capable of reducing the chip size and the mounting area by reducing the chip size of the entire device. .

  In order to solve the above problems, a semiconductor relay device of the present invention includes a light emitting element that emits light based on an input signal and a plurality of photodiode cells connected in series, and receives light from the light emitting element. A photodiode array for generating photovoltaic power, one or more output MOSFETs connected to the photodiode array, and connected to the photodiode array in parallel, to the photovoltaic power generated in the photodiode array. In response, the charge / discharge circuit comprising: a charge / discharge circuit that opens and closes the one or more output MOSFETs by switching between charging and discharging of the gates of the one or more output MOSFETs. Includes a semiconductor element, and the semiconductor element is formed on an n-type single crystal silicon island on a dielectric isolation substrate. To.

  In this semiconductor relay device, it is preferable that the semiconductor element is a semiconductor switching element that is switched on / off based on a photovoltaic power generated in the photodiode array.

  In this semiconductor relay device, it is preferable that the photodiode array outputs a photovoltaic power having a magnitude of 10 times or more a gate threshold voltage of each of the one or more output MOSFETs.

  In this semiconductor relay device, the photodiode array preferably includes 14 or more photodiode cells connected in series.

  In this semiconductor relay device, the semiconductor element may be a vertical semiconductor element.

  In this semiconductor relay device, the photodiode array and the charge / discharge circuit are formed on the same dielectric isolation substrate, and the depth of the n-type single crystal silicon island on which the photodiode array is formed is It is desirable that the depth is such that the near infrared light absorption rate by the photodiode array is 90% or more.

  In this semiconductor relay device, the depth of the n-type single crystal silicon island in which the photodiode array is formed is desirably 40 μm or more and 70 μm or less.

  According to the semiconductor relay device of the present invention, the semiconductor element in the charge / discharge circuit is formed on the n-type single crystal silicon island on the dielectric isolation substrate. Here, in general, in the case of a semiconductor element having the same breakdown voltage and the same resistance value, the element region can be made smaller when the impurity semiconductor forming the element is an n-type semiconductor than when it is a p-type semiconductor. This is because, for example, when n-type single crystal silicon and p-type single crystal silicon having the same impurity concentration are considered, the carrier mobility of n-type single crystal silicon is twice or more larger than that of p-type single crystal silicon. That's it. For this reason, the resistance value of n-type single crystal silicon is less than or equal to half the resistance value of p-type single crystal silicon having the same length and cross-sectional area. Therefore, when the length of the carrier passage (for example, the channel in the case of MOSFET) is the same, the cross-sectional area of the carrier passage of n-type single crystal silicon is set to be half the cross-sectional area of the carrier passage of p-type single crystal silicon Even if it is 1 or less, the resistance values in the paths of these carriers can be made the same. For this reason, the resistance value (ON in the case of MOSFET) is changed by changing the semiconductor element (in the charge / discharge circuit) that has been conventionally formed on the p-type single crystal silicon island to be formed on the n-type single crystal silicon island. The cross-sectional area of the carrier passage can be reduced without increasing the resistance. The breakdown voltage is determined by the impurity concentration of the single crystal silicon (impurity semiconductor) and the distance between the electrodes of the semiconductor element regardless of whether the single crystal silicon (impurity semiconductor) is n-type or p-type. For this reason, in the case of a semiconductor element having the same breakdown voltage and the same resistance value, the cross-sectional area of the carrier passage can be reduced by forming the semiconductor element on the n-type single crystal silicon island. Therefore, by forming the semiconductor element in the charge / discharge circuit on the n-type single crystal silicon island on the dielectric isolation substrate, the resistance value is increased compared to the case where the semiconductor element is formed on the p-type single crystal silicon island. Accordingly, the chip size of the semiconductor element in the charge / discharge circuit can be reduced while securing the distance between the electrodes of the semiconductor element necessary for the withstand voltage. Thereby, the chip size of the entire semiconductor relay device can be reduced, and the chip cost and the mounting area can be reduced.

The circuit block diagram of the semiconductor relay apparatus which concerns on the 1st Embodiment of this invention. Sectional drawing of n channel type MOSFET and photodiode cell which were formed on the dielectric isolation board | substrate of the said semiconductor relay apparatus. (A) is a top view of MOSFET of the semiconductor relay apparatus of a prior art example, (b) is a top view of MOSFET of the semiconductor relay apparatus of 1st Embodiment. Sectional drawing of n channel type MOSFET and photodiode cell which were formed on the dielectric isolation board | substrate of the semiconductor relay apparatus of a prior art example. Sectional drawing of n channel type MOSFET and photodiode cell which were formed on the dielectric isolation board | substrate of the semiconductor relay apparatus by the 2nd Embodiment of this invention. Sectional drawing of the n-type single crystal silicon island in which the photodiode cell of 1st and 2nd embodiment was formed. The graph which shows the relationship between the depth of the n-type single crystal silicon island in which the said photodiode cell was formed, and a light absorption rate.

  Hereinafter, a semiconductor relay device according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a circuit configuration of a semiconductor relay device according to a first embodiment of the present invention. The semiconductor relay device 1 according to the first embodiment uses an n-channel depletion type lateral MOSFET 8 (hereinafter simply referred to as a MOSFET 8) as a semiconductor element and a semiconductor switching element in the claims. The semiconductor relay device 1 includes a light emitting element 2 (for example, an LED) that emits light based on input signals input from input terminals IT1 and IT2, and a photodiode that receives light from the light emitting element 2 and generates photovoltaic power. And an array 3. The photodiode array 3 has a plurality of photodiode cells 3a connected in series.

  The semiconductor relay device 1 also includes a charge / discharge circuit 7 connected in parallel with the photodiode array 3, and output MOSFETs 5 and 6 connected to the charge / discharge circuit 7 and the photodiode array 3. As shown in the figure, these output MOSFETs 5 and 6 are connected in reverse series by connecting their sources (electrodes) to each other. In the semiconductor relay device 1, by connecting the output MOSFETs 5 and 6 as described above, bidirectional current can be extracted from the output terminals OT1 and OT2 connected to the drains (electrodes) of the output MOSFETs 5 and 6. ing. That is, the output MOSFETs 5 and 6 are so-called bidirectional switches. In the figure, D1 and D2 indicate parasitic diodes of the output MOSFETs 5 and 6, respectively.

  The charge / discharge circuit 7 includes the MOSFET 8 and the resistor 9 described above. The drain and gate of the MOSFET 8 are connected to the anode side and the cathode side of the photodiode array 3, respectively. As will be described in detail later, the MOSFET 8 is switched on / off based on the photovoltaic power generated in the photodiode array 3. The resistor 9 has one end connected to the source of the MOSFET 8 and the sources of the output MOSFETs 5 and 6, and the other end connected to the gate of the MOSFET 8 and the cathode side of the photodiode array 3.

  The charging / discharging circuit 7 switches between charging and discharging the gates of the two output MOSFETs 5 and 6 according to the presence or absence of the photovoltaic power generated in the photodiode array 3, so that these output MOSFETs 5 and 6 are switched. Open and close. In this semiconductor relay device 1, the two output MOSFETs 5 and 6 are simultaneously opened and closed in response to input signals input from the input terminals IT1 and IT2. Thereby, the conduction between the external output terminals OT1 and OT2 and the interruption are switched.

  The photodiode array 3 outputs a photovoltaic power having a magnitude of 10 times or more the gate threshold voltage (Vth) of each of the two output MOSFETs 5 and 6. Here, the gate threshold voltage is a voltage between the gate and the source where the output MOSFETs 5 and 6 belonging to the so-called power MOSFET start to turn on. In general, it is sufficient to apply a voltage of 3 V to 5 V to the gate in order to operate the output MOSFET in the semiconductor relay device. However, in recent years, there is a growing market need for reducing power loss due to low on-resistance of semiconductor relay devices. In order to satisfy this need, the semiconductor relay device 1 increases the voltage between the gate and source of the output MOSFETs 5 and 6 to increase the cross-sectional area of the channels of the output MOSFETs 5 and 6, thereby increasing the output MOSFET 5. , 6 is reduced in on-resistance.

  More specifically, in the semiconductor relay device 1, the photodiode array 3 outputs a photovoltaic power having a magnitude of 10 times or more the gate threshold voltage of each of the output MOSFETs 5 and 6. Specifically, assuming that the gate threshold voltage of each of the output MOSFETs 5 and 6 is 0.8 V, the photodiode array 3 is 10 times (8 V) of 0.8 V that is the gate threshold voltage of each of the output MOSFETs 5 and 6. ) Output photovoltaic power of the above magnitude. As a result, the on-resistances of the two output MOSFETs 5 and 6 can be greatly reduced, so that the overall on-resistance of the semiconductor relay device 1 can be reduced. As shown in FIG. 1, since the output MOSFET 5 and the output MOSFET 6 are connected in parallel, the gates of these output MOSFETs 5 and 6 are both output from the photodiode array 3. A voltage (photoelectromotive force) of 8V is applied.

  Moreover, the gate threshold voltage of the output MOSFET used in this type of semiconductor relay device 1 is often 0.8 V or more. Here, assuming that the photoelectromotive force from one photodiode cell 3a corresponding to the intensity of light transmitted from the light emitting element 2 is set to 0.6 V, 10 times the gate threshold voltage of each of the output MOSFETs 5 and 6 ( In order to obtain a photovoltaic power of 8 V or higher, 14 or more cells are required. This is because 13 <(8V / 0.6V) <14. The photodiode array 3 used in the semiconductor relay device 1 includes 14 or more series-connected photodiodes in order to obtain a photovoltaic power having a magnitude of 10 times or more (8 V or more) of the gate threshold voltage of each of the output MOSFETs 5 and 6. It has a connected photodiode cell 3a.

  As described above, when the voltage applied to the gates of the two output MOSFETs 5 and 6 (potential difference between the gate and the source) is made larger than the conventional one, the MOSFET 8 of the charge / discharge circuit 7 is connected to the conventional charge / discharge circuit. The withstand voltage must be higher than that of the MOSFET. However, in general, when the breakdown voltage of a semiconductor element is increased, the distance between the electrodes of the semiconductor element increases, so that the chip size of the semiconductor element increases. As will be described in detail later, the semiconductor relay device 1 is configured to form a semiconductor element such as a MOSFET 8 on an n-type single crystal silicon island on a dielectric isolation substrate, so that the chip size of a high breakdown voltage semiconductor element such as the MOSFET 8 is increased. The increase is prevented.

  Next, switching processing between conduction and interruption between the external output terminals OT1 and OT2 performed in the semiconductor relay device 1 will be described in detail. When signals are input from the input terminals IT1 and IT2, the light emitting element 2 emits light based on the input signals. When the photodiode array 3 receives light from the light emitting element 2, it generates a photovoltaic force. As a result, current flows in the direction of arrow A in the figure. At this time, since the depletion type and normally-on type MOSFET 8 remains conductive, the current flowing from the photodiode array 3 in the direction of arrow A flows in the path of arrow B. As a result, a potential difference as shown in FIG.

  When the potential difference between the + side and the − side in the resistor 9 reaches a predetermined level or more, the gate of the depletion type MOSFET 8 becomes a predetermined negative potential, and the MOSFET 8 is switched from on to off. Therefore, the current flowing from the photodiode array 3 in the direction of arrow A does not flow in the path of arrow B but flows in the path of arrow C. Due to this current, charges are accumulated in the gates of the two MOSFETs 5 and 6, so that a potential difference is generated between the gate and source of the MOSFETs 5 and 6, and the MOSFETs 5 and 6 are turned on (conducting state) (closed state). Thus, the external output terminals OT1 and OT2 are conducted and the relay is closed.

  On the other hand, when the signal is cut off from the input terminals IT1 and IT2 and the light emitting element 2 stops emitting light, no photoelectromotive force is generated in the photodiode array 3. As a result, the potential difference between the + side and the − side in the resistor 9 that existed in a state where the external output terminals OT1 and OT2 are in a conductive state disappears, so that a negative voltage is not applied to the gate of the depletion type MOSFET 8, MOSFET 8 switches from off to on. As a result, the electric charge accumulated in the gates of the two MOSFETs 5 and 6 flows through the path indicated by the arrow B to the source side of the MOSFETs 5 and 6 and is discharged, so that the MOSFETs 5 and 6 are turned off (non-conducting state). ) (Opened). For this reason, the external output terminals OT1 and OT2 are disconnected and the relay is opened.

Next, with reference to FIG. 2, the structure of the MOSFET 8 and the photodiode cells 3a constituting the photodiode array 3 will be described. The photodiode array 3 and the charging / discharging circuit 7 are formed on the same dielectric isolation substrate 11, and the MOSFET 8 in the charging / discharging circuit 7 and each photodiode cell 3a in the photodiode array 3 are different from each other. The n-type single crystal silicon islands 13 and 14 are formed. The dielectric isolation substrate 11 is a structure in which single crystal silicon is separated into islands by a silicon oxide film 12 as a dielectric layer. The n-type single crystal silicon island 14 constituting the photodiode cell 3a and the MOSFET 8 are arranged. The n-type single crystal silicon island 13 is formed. The n-type single crystal silicon island 13 includes a p-type high concentration region 16 for fixing the p ^- well potential, a source region 15 of the MOSFET 8, a gate region 17, a drain region 18, a gate electrode 19, and a p-type. The p ^- well 20 is a low concentration region.

The MOSFET 8 has an offset region 13a which is an n-type (n ⁻ ) offset impurity layer having a lower concentration than the source region 15 and the drain region 18, and is a so-called offset gate type MOSFET. The n-type single crystal silicon island 14 includes an anode region 21 and a cathode region 22 of the photodiode cell 3a. In FIG. 2 and FIGS. 4 and 5 described later, the illustration of the oxide film of the MOSFET is all saved.

  According to the semiconductor relay device 1, the MOSFET 8 in the charge / discharge circuit 7 is formed on the n-type single crystal silicon island 13 on the dielectric isolation substrate 11. Here, in general, in the case of a semiconductor element having the same breakdown voltage and the same resistance value, the element region can be made smaller when the impurity semiconductor forming the element is an n-type semiconductor than when it is a p-type semiconductor. This is because, for example, when n-type single crystal silicon and p-type single crystal silicon having the same impurity concentration are considered, the carrier mobility of n-type single crystal silicon is twice or more larger than that of p-type single crystal silicon. That's it. For this reason, the resistance value of n-type single crystal silicon is less than or equal to half the resistance value of p-type single crystal silicon having the same length and cross-sectional area. Therefore, when the length of the carrier passage (for example, the channel in the case of MOSFET) is the same, the cross-sectional area of the carrier passage of n-type single crystal silicon is set to be half the cross-sectional area of the carrier passage of p-type single crystal silicon Even if it is 1 or less, the resistance values in the paths of these carriers can be made the same. Therefore, by changing the p-channel type MOSFET (in the charge / discharge circuit) that has been conventionally formed on the p-type single crystal silicon island to the n-channel type MOSFET 8 formed on the n-type single crystal silicon island 13, The cross-sectional area of the carrier passage can be reduced without increasing the on-resistance of the MOSFET 8. Therefore, by forming the MOSFET 8 on the n-type single crystal silicon island 13 in the n-channel type, the gate width of the MOSFET 8 can be made smaller than that of the conventional MOSFET without increasing the on-resistance of the MOSFET 8 as compared with the conventional MOSFET.

  As described above, when considering n-type single crystal silicon and p-type single crystal silicon having the same impurity concentration, the carrier mobility of n-type single crystal silicon is twice or more that of p-type single crystal silicon. Is the size of Therefore, the impurity concentration, length, and cross-sectional area of the n-type single crystal silicon island 14 in which the photodiode cell 3a of the present embodiment is formed and the p-type single crystal silicon island in which the conventional photodiode cell is formed. However, if all are the same, That is, the resistance value rn (see FIG. 2) of the n-type single crystal silicon island 14 is less than or equal to half the resistance value rp (see FIG. 4) of the p-type single crystal silicon island. Accordingly, the internal resistance of the photodiode 3 can be made smaller when the photodiode cell 3a is formed on the n-type single crystal silicon island 14 than when it is formed on the p-type single crystal silicon island. In the semiconductor relay device 1 of the present embodiment, since the photodiode cell 3a is formed on the n-type single crystal silicon island 14, the internal resistance of the photodiode 3 can be reduced and the operation speed of the photodiode 3 can be improved. it can. This also applies to the semiconductor relay devices according to the following second and third embodiments.

  Next, referring to FIGS. 3A and 3B, the reduction of the gate width in the MOSFET 8 will be specifically described. 3A and 3B show a top view of the conventional MOSFET 208 shown in FIG. 4 to be described later and a top view of the MOSFET 8 of the present embodiment shown in FIG. 2 is a cross-sectional view taken along the line EE of the MOSFET 8 of the present embodiment shown in FIG. 3B, and FIG. 4 is a cross-sectional view taken along the line D-D of the conventional MOSFET 208 shown in FIG. FIG. As described above, in the present semiconductor relay device 1, the n-channel MOSFET 208 that has been conventionally formed on the p-type single crystal silicon island 213 is changed to the n-channel MOSFET 8 that is formed on the n-type single crystal silicon island 13. did. As a result, the gate width W3 of the MOSFET 8 can be made smaller than the gate width W1 of the conventional MOSFET 208, as shown in FIGS. 3A and 3B, without increasing the on-resistance of the MOSFET 8 compared to the conventional MOSFET 208. . Accordingly, the chip width of the MOSFET 8 (width of the n-type single crystal silicon island 13) W4 is made smaller than the chip width of the conventional MOSFET 208 (width of the p-type single crystal silicon island 213) W2, and the chip size of the MOSFET 8 is reduced. Miniaturization can be achieved. Thereby, the chip size of the whole semiconductor relay device 1 can be reduced, and the chip cost and the mounting area can be reduced.

  Next, with reference to FIG. 4, the superiority of the MOSFET 8 in the semiconductor relay device 1 over the conventional n-channel type depletion type MOSFET formed on the p-type single crystal silicon island will be described. FIG. 4 shows a dielectric isolation substrate 211 formed on a conventional p-type single crystal silicon island and formed with an n-channel depletion type lateral MOSFET 208 (hereinafter simply referred to as MOSFET 208) and each photodiode cell 203a. Indicates.

The dielectric isolation substrate 211 is a structure in which single crystal silicon is isolated in an island shape by a silicon oxide film 212 which is a dielectric layer, and a p-type single crystal silicon island 214 constituting the photodiode cell 203a; And a p-type single crystal silicon island 213 constituting the MOSFET 208. The p-type single crystal silicon island 213 includes a p-type high concentration region 216 for fixing the p ⁻ substrate potential, a source region 215 of the MOSFET 208, a gate region 217, a drain region 218, and a gate electrode 219. ing. The p-type single crystal silicon island 214 includes an anode region 221 and a cathode region 222 of the photodiode cell 203a.

When the n-channel MOSFET 8 is formed on the n-type single crystal silicon island 13 as shown in FIG. 2 and when the n-channel MOSFET 208 is formed on the p-type single crystal silicon island 213 as shown in FIG. As a result, the chip size of the MOSFET can be easily reduced. This is because, unlike the case where the n-channel type MOSFET 208 is formed on the p-type single crystal silicon island 213, when the n-channel type MOSFET 8 is formed on the n-type single crystal silicon island 13, as shown in FIG. It becomes a gate type MOSFET. The offset gate MOSFET 8 has a low-concentration n-type (n ⁻ ) offset region 13 a between the gate region 17 and the drain region 18, and a part of the gate region has a low concentration. It can be regarded as an n-type region. Therefore, as shown in FIG. 5, since the resistance value of the entire channel increases as compared with the case where the entire gate region 217 is formed of high-concentration n-type, it is possible to increase the breakdown voltage when the MOSFET 8 is turned off. it can.

To supplement the above point, in general, the on-resistance (R _on ) of a semiconductor is proportional to the distance (L) and inversely proportional to the impurity concentration (Nd). That is,
R _on ∝ L / Nd (1)
It is. From this equation, by providing a low-concentration n-type (n ⁻ ) offset region 13a to make a part of the gate region a low-concentration n-type, the entire gate region 217 is formed as shown in FIG. It can be seen that the on-resistance of the entire channel is increased as compared with the case of forming n-type with a high concentration. In general, the on-resistance per unit area of the MOSFET is proportional to the 2.5th power of the breakdown voltage. Accordingly, by providing the offset region 13a and making a part of the gate region a low-concentration n-type, as shown in FIG. 4, the entire gate region 217 is formed in a high-concentration n-type. Thus, the breakdown voltage can be improved.

  In the case of MOSFET, the distance (L) in the above equation (1) mainly means the distance between the source and the drain. Therefore, by providing the offset region 13a and lowering the impurity concentration (Nd) of a part of the gate region, the distance between the source and the drain (in comparison with the case where the entire gate region is formed of high-concentration n-type ( The same on-resistance value can be maintained even if (corresponding to L) is reduced. This is because by providing the offset region 13a as in the MOSFET 8, as shown in FIG. 4, the distance between the source and the drain can be reduced as compared with the case where the entire gate region 217 is formed of high-concentration n-type. This means that the same withstand voltage can be obtained even if it is reduced. Therefore, when the n-channel MOSFET 8 is formed on the n-type single crystal silicon island 13 as shown in FIG. 2, the n-channel MOSFET 208 is formed on the p-type single crystal silicon island 213 as shown in FIG. As compared with the case, the chip size of the MOSFET can be easily reduced. Thereby, the chip size of the whole semiconductor relay device 1 can be reduced, and the chip cost and the mounting area can be reduced.

  Next, a semiconductor relay device 1 according to a second embodiment of the present invention will be described with reference to FIG. The semiconductor relay device 1 according to the second embodiment is characterized in that each semiconductor element (mainly MOSFET and each photodiode cell in the photodiode array) on the dielectric isolation substrate 31 has a vertical structure. This is different from the first embodiment. Specifically, high-concentration n-type impurities are implanted into the outer periphery of each n-type single crystal silicon island on the dielectric isolation substrate 31 of the present embodiment. Thereby, for example, the cathode region 32 of each photodiode cell 33 a extends to the outer peripheral portion of the n-type single crystal silicon island 14, and the drain region 38 of the MOSFET 28 extends to the outer peripheral portion of the n-type single crystal silicon island 13. It is extended to. Other configurations in the present embodiment are the same as those in the first embodiment.

  According to the semiconductor relay device 1 of the present embodiment, a semiconductor element such as the MOSFET 28 on the dielectric isolation substrate 31 has a vertical structure, so that a distance for holding a withstand voltage (in the case of the MOSFET 28, in FIG. The distance indicated by the double arrow can be taken in the vertical direction. Here, in general, when the horizontal semiconductor element is replaced with a vertical semiconductor element, the breakdown voltage can be increased. Therefore, when the horizontal semiconductor element is replaced with a vertical semiconductor element with the same breakdown voltage, The distance between the electrodes of the semiconductor element can be reduced. Therefore, by making the MOSFET 28 and the photodiode cell 33a have a vertical structure, the chip size of these semiconductor elements can be made smaller than when these semiconductor elements have a horizontal structure.

  Next, referring to FIGS. 6 and 7, the chip size of each photodiode cell 3a in the photodiode array 3 that is commonly used in the semiconductor relay device 1 of the first and second embodiments is described. A device for reducing the size will be described. Hereinafter, in order to avoid redundant description, the semiconductor relay device 1 according to the first embodiment will be described as an example, and a device for reducing the chip size will be described. In this semiconductor relay device 1, the photodiode array 3 and the charge / discharge circuit 7 are formed on the same dielectric isolation substrate (dielectric isolation substrate 11 shown in FIG. 2). Further, the n-type single crystal silicon island 14 on which the photodiode array 3 is formed has a depth SD (see FIG. 6) at which the near infrared light absorption rate by the photodiode array 3 is 90% or more. It is formed as follows. Here, the light absorptance is the ratio of the light incident energy to the light incident energy at the position where the depth in the n-type single crystal silicon island 14 is 0 μm (the surface of the n-type single crystal silicon island 14). The percentage of energy that is absorbed by the n-type single crystal silicon island 14 is expressed as a percentage. The depth SD of the n-type single crystal silicon island 14 is also the thickness of the light absorption layer.

  The depth SD of the n-type single crystal silicon island 14 is actually set to 40 μm or more and 70 μm or less (range indicated by a double arrow in FIG. 7). Here, the reason why the depth SD of the n-type single crystal silicon island 14 is set to 40 μm or more is that when the near-infrared wavelength is 850 μm, the depth of the n-type single crystal silicon island 14 becomes 90%. Is 40 μm. The reason why the depth SD of the n-type single crystal silicon island 14 is set to 70 μm or less is as follows. That is, since the straight line 162 of the light absorption amount y = 100 [%] in FIG. 7 corresponds to an asymptotic line with respect to the curve 161 indicating the relationship between the depth SD of the n-type single crystal silicon island 14 and the light absorption rate. Even if the depth SD is set to 70 μm or more, the light absorptance is hardly improved. Therefore, considering the manufacturing cost (chip cost), it is practical to set the depth SD of the n-type single crystal silicon island 14 to 70 μm or less. For near infrared rays having wavelengths other than 850 μm, the relationship between the depth SD of the n-type single crystal silicon island 14 and the light absorption rate is substantially the same as the curve 161 shown in FIG.

  As described above, the photodiode array 3 is formed so that the depth SD thereof has a near-infrared light absorption rate of 90% or more by the photodiode array 3, so that each photodiode cell 3 a has a unit surface area. The power generation efficiency (by near-infrared light) can be maximized. As a result, the surface area of each photodiode cell 3a can be brought close to the minimum, so that the chip size of each photodiode cell 3a can be reduced and the chip size of the entire semiconductor relay device 1 can be further reduced. Therefore, the chip cost of the entire semiconductor relay device 1 can be further reduced and the mounting area can be reduced.

  In addition, this invention is not restricted to the structure of the said embodiment, A various deformation | transformation is possible in the range which does not change the meaning of invention. For example, in the above-described embodiment, an example in which the semiconductor element (in the charge / discharge circuit) in the claims is a depletion type offset gate type MOSFET has been described, but the semiconductor element is not limited thereto. For example, an enhancement type MOSFET or a MOSFET other than an offset gate type may be used. In the above-described embodiment, the number of output MOSFETs is two. However, the number of output MOSFETs is not limited to this, and may be one, for example.

DESCRIPTION OF SYMBOLS 1 Semiconductor relay apparatus 2 Light emitting element 3 Photodiode array 3a Photodiode cell 5, 6 Output MOSFET
7 Charging / discharging circuit 8 MOSFET (semiconductor element, semiconductor switching element)
11, 31 Dielectric isolation substrate 13 n-type single crystal silicon island 28 MOSFET (semiconductor element, semiconductor switching element, vertical semiconductor element)

Claims (7)

A light emitting element that emits light based on an input signal;
A photodiode array having a plurality of photodiode cells connected in series, receiving light from the light emitting element and generating photovoltaic power;
One or more output MOSFETs connected to the photodiode array;
The one or more outputs are connected in parallel with the photodiode array and switched between charging and discharging the gates of the one or more output MOSFETs based on the photovoltaic power generated in the photodiode array. In a semiconductor relay device comprising a charge / discharge circuit that opens and closes a power MOSFET,
The charge / discharge circuit includes a semiconductor element, and the semiconductor element is formed on an n-type single crystal silicon island on a dielectric isolation substrate.   The semiconductor relay device according to claim 1, wherein the semiconductor element is a semiconductor switching element that is switched on / off based on a photovoltaic power generated in the photodiode array.   3. The semiconductor according to claim 1, wherein the photodiode array outputs a photovoltaic power having a magnitude of 10 times or more a gate threshold voltage of each of the one or more output MOSFETs. Relay device.   4. The semiconductor relay device according to claim 3, wherein the photodiode array includes 14 or more photodiode cells connected in series.   The semiconductor relay device according to claim 1, wherein the semiconductor element is a vertical semiconductor element.   The photodiode array and the charging / discharging circuit are formed on the same dielectric isolation substrate, and the depth of the n-type single crystal silicon island on which the photodiode array is formed is determined by the near infrared ray by the photodiode array. The semiconductor relay device according to any one of claims 1 to 5, wherein the depth is such that the light absorptance of the semiconductor is 90% or more.   The semiconductor relay device according to claim 6, wherein a depth of the n-type single crystal silicon island in which the photodiode array is formed is 40 μm or more and 70 μm or less.

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