JP2013093470A - Circuit board, active matrix substrate, display device, and manufacturing method of circuit board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit board capable of accurately predicting a quality of an active element such as a TFT element equipped with an oxide semiconductor layer.SOLUTION: An insulating substrate 2 is provided with a pattern for measuring a trap level 3, comprising: a first electrode 4; a second electrode 6 electrically separated from the first electrode 4; and an oxide semiconductor layer 5 formed so as to have contact with the first electrode 4 and the second electrode 6.

Description

  The present invention relates to a circuit board, a method for manufacturing the circuit board, and an active matrix substrate and a display device including the circuit board.

  In the fields of liquid crystal display devices (LCD) and organic EL display devices (OLED), for example, a thin film transistor element (hereinafter referred to as a TFT element) is provided as an active element for each pixel in order to achieve higher image quality. In general, an active matrix type substrate is used.

  As a material of the semiconductor layer provided in the TFT element, a low temperature polysilicon layer (Low Temperature) obtained by crystallization in a relatively low temperature process using a hydrogenated amorphous silicon layer (a-Si: H), a laser, or the like. Poly Si; LTPS) has been commonly used.

  However, the hydrogenated amorphous silicon layer has a problem of low mobility, and the low temperature polysilicon layer has a problem of local non-uniformity that occurs during crystallization, so in recent years, high mobility can be obtained even at room temperature. An oxide semiconductor typified by an oxide containing indium (In), gallium (Ga), and zinc (Zn) (IGZO) has attracted attention.

  When such an oxide semiconductor is used as an active layer of a TFT element, the carrier concentration in the oxide semiconductor is an important parameter. If the carrier concentration is too high, the oxide semiconductor becomes a conductor and functions as a TFT element. There is a problem of losing.

  FIG. 18A shows the IV characteristics of a normal TFT element provided with an oxide semiconductor film with an appropriate carrier concentration. FIG. 18B shows that the carrier concentration is too high to be a conductor. The IV characteristic of the defective TFT element provided with the oxide semiconductor film is shown.

  The carrier concentration in an oxide semiconductor is greatly affected by trap levels generated by oxygen vacancies. Therefore, by evaluating the trap level of an oxide semiconductor, the oxide semiconductor has a carrier concentration before it is completely formed. It is considered that the carrier concentration can be grasped and the quality of a TFT element manufactured using such an oxide semiconductor can be predicted.

  However, a method for evaluating the trap level of an oxide semiconductor has not been established yet, and it is only possible to determine the quality of the TFT element by measuring electrical characteristics after completing the TFT element including the oxide semiconductor. However, there is a large time lag between the occurrence of a defect and the discovery of the defect.

  That is, even if a large number of oxygen defects are generated in the oxide semiconductor film formation step and a conductor oxide semiconductor film is formed, the conductor oxide is formed immediately after the oxide semiconductor film formation step. It is not possible to notice that a semiconductor film has been formed, and after that, a post-process for forming a TFT element is performed, and after completing the TFT element, the electrical characteristics of the TFT element are measured, and the oxide that is made into a conductor for the first time You will notice that the semiconductor film has been formed.

  Such an evaluation method of an oxide semiconductor film is a method that is not preferable in consideration of the unit production cost and the production efficiency because the material and time are wasted when it is determined that the TFT element is defective later. It is.

  Therefore, Patent Document 1 discloses an inspection method capable of quickly and non-destructively examining the film quality of an amorphous or polycrystalline oxide semiconductor layer.

  FIG. 19A is a diagram for explaining the method for inspecting the film quality of an oxide semiconductor layer described in Patent Document 1, and FIG. 19B is a photo obtained by the above-described inspection method. It is a figure which shows the spectrum of luminescence light.

  In Patent Document 1, as illustrated in FIG. 19A, a substrate 110 on which an amorphous or polycrystalline inspected oxide semiconductor layer to be inspected is formed on a surface is described. Photoluminescence light in a wavelength region longer than the wavelength corresponding to the band gap energy among the reflected light 103 irradiated with the excitation light 102 emitted from the excitation light source 101 such as a laser light source and reflected from the oxide semiconductor layer to be inspected. A configuration is disclosed in which the intensity of 104 is measured by the photodetector 105, data as shown in FIG. 19B is obtained, and the data is sent to a measuring device not shown.

  In the above configuration, the oxide semiconductor layer to be inspected is manufactured in the same process as the oxide semiconductor layer to be inspected before measurement, and has the same elemental composition and film thickness as the oxide semiconductor layer to be inspected. With respect to the amorphous or polycrystalline reference oxide semiconductor layer having, the same photoluminescence light intensity measurement and film quality measurement, to obtain the relationship between the photoluminescence light intensity and the film quality, Based on this relationship, the film quality of the oxide semiconductor layer to be inspected can be estimated.

JP 2010-123872 (released on June 3, 2010)

  However, although the method for inspecting the quality of an oxide semiconductor layer described in Patent Document 1 is effective for evaluating an oxide semiconductor layer formed as a single layer, it is used as an active layer of an actual TFT element. There is a problem that the state of the formed oxide semiconductor layer cannot be sufficiently reflected.

  That is, a source electrode, a drain electrode, and an insulating film made of a metal film are formed on the oxide semiconductor layer used as an active layer of an actual TFT element, and an interface between these films and the oxide semiconductor layer. It is known that oxygen vacancies also occur and the effect of the oxygen vacancies generated at the interface on the characteristics of the oxide semiconductor layer is large, but the above-mentioned patent document shown in FIG. In the method for inspecting the film quality of the oxide semiconductor layer described in No. 1, it is not possible to reflect the oxygen deficiency generated at the interface in this way. Cannot be used.

  The present invention has been made in view of the above problems, a circuit board capable of accurately predicting the quality of an active element such as a TFT element including an oxide semiconductor layer, an active matrix substrate, An object of the present invention is to provide a display device and a method for manufacturing the circuit board.

  In order to solve the above problems, a circuit board of the present invention is a circuit board provided with an oxide semiconductor layer on one surface of an insulating substrate, and the oxide semiconductor layer is provided on the insulating substrate. The surface on which the first electrode is formed is in contact with the first electrode, the second electrode that is electrically separated from the first electrode, and the first electrode and the second electrode. The above-described oxide semiconductor layer is provided with a trap level measurement pattern.

  According to the above configuration, the first electrode, the second electrode, the first electrode, and the second electrode are formed on the surface of the insulating substrate on which the oxide semiconductor layer is formed. A trap level measurement pattern including an oxide semiconductor layer formed to be in contact with the oxide semiconductor layer is provided.

  Since the oxide semiconductor layer is formed so as to be in contact with the first electrode and the second electrode, if the thermally stimulated current measurement is performed using the trap level measurement pattern, for example, Not only the oxygen deficiency state in the oxide semiconductor layer but also the oxygen deficiency state at the interface between the oxide semiconductor layer and the first electrode and the second electrode can be reflected.

  Therefore, it is possible to realize a circuit board capable of predicting the quality of an active element such as a TFT element including the oxide semiconductor layer with high accuracy.

  In the circuit board of the present invention, a surface of the insulating substrate on the side where the oxide semiconductor layer is formed includes a first region which is a region including a central portion of the insulating substrate, and the first region. And a second region which is a region including an end portion of the insulating substrate, and the trap level measurement pattern is provided in the second region. preferable.

  According to the above configuration, the trap level measurement pattern including the first electrode, the second electrode, and the oxide semiconductor layer is a peripheral region of the first region, and the insulating substrate. The light shielding member is provided so as to cover only the second region when it is necessary to make the trap level measurement pattern invisible. Therefore, a circuit board that can be easily used for a display device or the like can be realized.

  Further, it is easy to remove the trap level measurement pattern as necessary.

  In the trap level measurement pattern of the circuit board of the present invention, it is preferable that the oxide semiconductor layer is interposed between the first electrode and the second electrode.

  According to the above configuration, for example, the thermal stimulation current measurement is performed using the trap level measurement pattern in which the oxide semiconductor layer is interposed between the first electrode and the second electrode. For example, not only the oxygen deficiency state in the oxide semiconductor layer but also the oxygen deficiency state at the interface between the oxide semiconductor layer and the first electrode and the second electrode can be reflected.

  Therefore, it is possible to realize a circuit board capable of predicting the quality of an active element such as a TFT element including the oxide semiconductor layer with high accuracy.

  In the trap level measurement pattern of the circuit board of the present invention, the first electrode and the second electrode are both formed on either the upper or lower portion of the oxide semiconductor layer. Is preferred.

  According to the above configuration, each of the first electrode and the second electrode uses the trap level measurement pattern formed on either the upper or lower portion of the oxide semiconductor layer. For example, if thermally stimulated current measurement is performed, not only the oxygen deficiency state in the oxide semiconductor layer but also the oxygen deficiency state at the interface between the oxide semiconductor layer and the first electrode and the second electrode Can be reflected.

  Therefore, it is possible to realize a circuit board capable of predicting the quality of an active element such as a TFT element including the oxide semiconductor layer with high accuracy.

  Further, according to the above configuration, since the first electrode and the second electrode are both formed on either the upper side or the lower side of the oxide semiconductor layer, the first electrode And the second electrode can be formed in one step.

  Therefore, the step of forming the trap level measurement pattern can be shortened.

  In the trap level measurement pattern of the circuit board of the present invention, both the first electrode and the second electrode are formed on either the upper part or the lower part of the oxide semiconductor layer, The third electrode is preferably formed on the other side of the oxide semiconductor layer opposite to the one side with an insulating layer interposed therebetween.

  According to the above configuration, not only the thermal stimulation current measurement that can be performed using the first electrode and the second electrode, but also one of the first electrode and the second electrode as a source. The characteristics of the transistor element including the oxide semiconductor layer can be evaluated by acting as an electrode, the other as a drain electrode, and the third electrode as a gate electrode.

  Therefore, it is possible to realize a circuit board that can predict the quality of an active element such as a TFT element including the oxide semiconductor layer with higher accuracy.

  Each of the first electrode and the second electrode in the circuit board of the present invention forms an electrode layer and a wiring of an active element formed on the insulating substrate provided with the oxide semiconductor layer as a semiconductor layer. It is preferable that the conductive layer is formed of the same material.

  According to the above configuration, the first electrode and the second electrode in the trap level measurement pattern do not need to be formed of a separate new conductive material, and the active layer having the oxide semiconductor layer is provided. It is made of the same material as the electrode layer of the element and the conductive layer forming the wiring.

  Therefore, if necessary, the first electrode and the second electrode in the trap level measurement pattern, and one conductive layer forming an electrode layer and a wiring of an active element including the oxide semiconductor layer. Since the layers can be formed in the same process, the number of manufacturing steps of the circuit board can be reduced.

  In the circuit board of the present invention, each of the first electrode, the second electrode, and the third electrode is an active element formed on the insulating substrate including the oxide semiconductor layer as a semiconductor layer. It is preferable that the electrode layer and the conductive layer forming the wiring are formed of the same material.

  According to the above configuration, the first electrode, the second electrode, and the third electrode in the trap level measurement pattern do not need to be formed of a separate new conductive material. The electrode layer of the active element including the semiconductor layer and the conductive layer forming the wiring are formed of the same material.

  Therefore, if necessary, each of the first electrode, the second electrode, and the third electrode in the trap level measurement pattern may be replaced with an electrode layer of an active element including the oxide semiconductor layer, and Since it can be formed in the same process as the conductive layer forming process for forming the wiring, the number of manufacturing steps of the circuit board can be reduced.

  In the circuit board of the present invention, the oxide semiconductor layer preferably contains at least one element selected from In, Ga, and Zn.

  According to the above structure, a circuit board including an oxide semiconductor layer having high mobility even at room temperature can be realized.

  In order to solve the above problems, an active matrix substrate of the present invention includes the circuit substrate, and a plurality of active matrices including a semiconductor layer formed of the same layer as the oxide semiconductor layer on the circuit substrate. An element is provided. A pixel electrode is electrically connected to each of the active elements, and a plurality of the pixel electrodes are formed in a matrix.

  According to the above configuration, the active element including the oxide semiconductor layer having high mobility even at room temperature, and the active matrix substrate in which the pixel electrodes electrically connected to each of the active elements are formed in a matrix form. Can be realized.

  In the trap level measurement pattern of the active matrix substrate of the present invention, each of the first electrode and the second electrode includes an electrode layer of the active element including the pixel electrode and a conductive layer forming a wiring. It is preferable that they are made of the same material.

  According to the above configuration, the first electrode and the second electrode in the trap level measurement pattern do not need to be formed of a separate new conductive material, and the oxide semiconductor layer including the pixel electrode Are formed of the same material as the electrode layer of the active element and the conductive layer forming the wiring.

  Therefore, as necessary, the electrode layer and the wiring of the active element including the oxide semiconductor layer including the first electrode and the second electrode and the pixel electrode in the trap level measurement pattern are formed. Since one certain conductive layer can be formed in the same process, the number of manufacturing steps of the circuit board can be reduced.

  In the trap level measurement pattern of the active matrix substrate of the present invention, both the first electrode and the second electrode are formed on either the upper or lower portion of the oxide semiconductor layer. The third electrode is formed on the other side of the oxide semiconductor layer opposite to the one side with an insulating layer interposed therebetween, and the first electrode, the second electrode, and the third electrode Each of the electrodes is preferably formed of the same material as the electrode layer of the active element including the pixel electrode and the conductive layer forming the wiring.

  According to the above configuration, the first electrode, the second electrode, and the third electrode in the trap level measurement pattern do not need to be formed of a separate new conductive material, and the pixel electrode The electrode layer of the active element including the oxide semiconductor layer including the conductive layer is formed of the same material as the conductive layer forming the wiring.

  Therefore, if necessary, each of the first electrode, the second electrode, and the third electrode in the trap level measurement pattern may be active with the oxide semiconductor layer including the pixel electrode. Since it can be formed in the same step as the step of forming the electrode layer of the element and the conductive layer for forming the wiring, the number of manufacturing steps of the circuit board can be reduced.

  In order to solve the above problems, a display device of the present invention includes the active matrix substrate, a counter substrate, and a liquid crystal layer interposed between the active matrix substrate and the counter substrate. It is characterized by.

  According to the above configuration, it is possible to realize a liquid crystal display device capable of accurately predicting the quality of an active element such as a TFT element including an oxide semiconductor layer in the manufacturing process.

  In order to solve the above problems, a display device according to the present invention includes the active matrix substrate and an organic EL layer formed on the surface side of the active matrix substrate on which the pixel electrodes are formed. It is characterized by that.

  According to the said structure, the organic EL display apparatus which can perform the prediction of the quality of active elements, such as a TFT element provided with the oxide semiconductor layer, with high precision in the manufacturing process is realizable.

  In order to solve the above problems, a method for manufacturing a circuit board according to the present invention is a method for manufacturing a circuit board having an oxide semiconductor layer on one surface of an insulating substrate, wherein the insulating substrate includes the above-described method. On the surface on which the oxide semiconductor layer is formed, the first electrode, the second electrode electrically separated from the first electrode, the first electrode, and the second electrode A step of forming a trap level measurement pattern comprising the oxide semiconductor layer formed so as to be in contact with the substrate, a step of measuring the trap level of the oxide semiconductor layer by thermally stimulated current measurement, Is included.

  According to the manufacturing method, the trap level measurement includes the first electrode, the second electrode, and the oxide semiconductor layer formed so as to be in contact with the first electrode and the second electrode. And a step of measuring the trap level of the oxide semiconductor layer by thermally stimulated current measurement using the pattern for use.

  Since the oxide semiconductor layer is formed so as to be in contact with the first electrode and the second electrode, oxygen in the oxide semiconductor layer is measured in the measurement of the trap level of the oxide semiconductor layer. Not only the defect state but also the oxygen defect state at the interface between the oxide semiconductor layer and the first electrode and the second electrode can be reflected.

  Accordingly, it is possible to realize a circuit board manufacturing method capable of accurately predicting the quality of an active element such as a TFT element including an oxide semiconductor layer.

  In the method for manufacturing a circuit board according to the present invention, both the first electrode and the second electrode are formed on either the upper part or the lower part of the oxide semiconductor layer, and the third electrode is The other side of the oxide semiconductor layer opposite to the one side is formed with an insulating layer interposed therebetween, and either the first electrode or the second electrode is allowed to act as a source electrode. It is preferable that a process of evaluating the transistor element characteristics of the oxide semiconductor layer by including the other electrode as a drain electrode and the third electrode as a gate electrode is preferably included.

  According to the manufacturing method, not only the step of measuring the thermally stimulated current using the first electrode and the second electrode, but also any one of the first electrode and the second electrode. There is also included a step of evaluating characteristics of the oxide semiconductor layer as a transistor element by acting as a source electrode, the other as a drain electrode, and the third electrode as a gate electrode.

  Therefore, it is possible to realize a circuit board manufacturing method capable of predicting the quality of an active element such as a TFT element including an oxide semiconductor layer with higher accuracy.

  As described above, in the circuit board of the present invention, the first electrode and the first electrode are electrically separated on the surface of the insulating substrate on which the oxide semiconductor layer is formed. And a trap level measurement pattern including the second electrode and the oxide semiconductor layer formed so as to be in contact with the first electrode and the second electrode. .

  Further, as described above, the active matrix substrate of the present invention includes the circuit board, and a plurality of active elements including a semiconductor layer formed of the same layer as the oxide semiconductor layer is provided on the circuit board. A pixel electrode is electrically connected to each of the active elements, and a plurality of the pixel electrodes are formed in a matrix.

  In addition, as described above, the display device of the present invention is configured to include the active matrix substrate, the counter substrate, and the liquid crystal layer interposed between the active matrix substrate and the counter substrate. .

  In addition, as described above, the display device according to the present invention includes the active matrix substrate and the organic EL layer formed on the surface side of the active matrix substrate on which the pixel electrodes are formed. is there.

  In addition, as described above, in the method for manufacturing a circuit board according to the present invention, the first electrode and the first electrode are electrically connected to the surface of the insulating substrate on which the oxide semiconductor layer is formed. Forming a trap level measurement pattern comprising: the second electrode separated in a separated manner; and the oxide semiconductor layer formed in contact with the first electrode and the second electrode; And a step of measuring the trap level of the oxide semiconductor layer by thermally stimulated current measurement.

  Therefore, a circuit substrate, an active matrix substrate, a display device, and a method for manufacturing the circuit substrate that can accurately predict the quality of an active element such as a TFT element including an oxide semiconductor layer are realized. can do.

It is a figure which shows the case where a thermally stimulated current measuring system is produced using the trap level measurement pattern while showing the cross-sectional structure of the trap level measurement pattern provided on the circuit board of one embodiment of the present invention. . It is a figure which shows schematic structure of the circuit board of one embodiment of this invention. It is a figure which shows an example of the large sized active matrix board | substrate which is a circuit board of one embodiment of this invention. It is a figure which shows another example of the large sized active matrix board | substrate which is a circuit board of one embodiment of this invention. It is a figure for demonstrating the method of performing a thermally stimulated current measurement using the pattern for trap level measurement, (a) is the electron and the hole which were generated by the application of a trap voltage in the oxide semiconductor layer 5. A state where the trap level is trapped and frozen is shown. (B) shows a state where electrons and holes are released in order from the shallow trap level due to the thermal effect due to the temperature rise. It is a figure which shows the thermally stimulated current measurement result of the normal film of the oxide semiconductor layer with which the pattern for trap level measurement was provided, and a defective film. It is a figure which shows the manufacturing process of the active-matrix board | substrate with which the TFT element provided with the oxide semiconductor layer used conventionally is formed. Manufacturing process for forming a trap level measurement pattern including an oxide semiconductor layer and a TFT element including an oxide semiconductor layer on a large active matrix substrate which is a circuit substrate according to an embodiment of the present invention It is a figure which shows an example. A trap level measurement pattern including an oxide semiconductor layer is formed on an insulating substrate, which is a circuit board according to an embodiment of the present invention, and the formation conditions of the oxide semiconductor layer are determined first, and then the determined It is a figure which shows an example of the manufacturing process which forms the TFT element provided with the oxide semiconductor layer with the conventional method on the large sized substrate different from the said insulating substrate using the formation conditions of an oxide semiconductor layer. It is a figure which shows an example of the large sized active matrix board | substrate which is a circuit board of other one Embodiment of this invention. A cross-sectional structure of a trap level measurement pattern provided on a large-sized active matrix substrate, which is a circuit board according to another embodiment of the present invention, and a thermally stimulated current measurement system using the trap level measurement pattern It is a figure which shows the case where it produces. A trap level measurement pattern including an oxide semiconductor layer is formed on an insulating substrate, which is a circuit board according to another embodiment of the present invention, and the formation conditions of the oxide semiconductor layer are determined first, and then the determination is performed. It is a figure which shows an example of the manufacturing process which forms the TFT element provided with the oxide semiconductor layer on the large sized substrate different from the said insulating substrate by the conventional method using the formed formation conditions of the oxide semiconductor layer . A trap level measurement pattern including an oxide semiconductor layer and a TFT element including an oxide semiconductor layer are formed on a large active matrix substrate which is a circuit substrate according to another embodiment of the present invention. It is a figure which shows an example of a manufacturing process. It is a figure which shows an example of the large sized active matrix board | substrate which is a circuit board of further another embodiment of this invention. The cross-sectional structure of a trap level measurement pattern provided on a large active matrix substrate which is a circuit board of still another embodiment of the present invention is shown, and a thermally stimulated current measurement system using the trap level measurement pattern It is a figure which shows the case where is produced. It is a figure which shows an example in the case of measuring the electrical property as a TFT element using the pattern for trap level measurement provided in the large sized active matrix substrate which is the circuit board of further another embodiment of this invention. . A trap level measurement pattern including an oxide semiconductor layer and a TFT element including an oxide semiconductor layer are formed on a large-sized active matrix substrate which is a circuit substrate according to still another embodiment of the present invention. It is a figure which shows an example of the manufacturing process to do. It is a figure which shows the result of the electrical property measurement of a TFT element, (a) shows the IV characteristic of a normal TFT element provided with the oxide semiconductor film with an appropriate carrier concentration, and (b) shows the carrier concentration. 4 shows IV characteristics of a defective TFT element including an oxide semiconductor film that is too large to be a conductor. It is a figure which shows the spectrum of the photoluminescence light obtained by the inspection method of the film quality of the oxide semiconductor layer described in patent document 1, and the said inspection method.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the dimensions, materials, shapes, relative arrangements, and the like of the component parts described in this embodiment are merely one embodiment, and the scope of the present invention should not be construed as being limited thereto.

[Embodiment 1]
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.

  FIG. 2 is a diagram showing a schematic configuration of the circuit board 1 in which the trap level measurement pattern 3 is provided at an arbitrary position on the insulating substrate 2.

  The circuit board 1 includes a semiconductor substrate or display including a trap level measurement pattern 3 and an oxide semiconductor layer formed of the same layer as the oxide semiconductor layer 5 provided in the trap level measurement pattern 3. It can be an active matrix substrate used in the apparatus.

  As shown in the figure, the insulating substrate 2 includes a first region R1 that is a region including the central portion of the insulating substrate 2, a peripheral region of the first region R1, and an end of the insulating substrate 2. And a second region R2 that is a region including a portion, and the trap level measurement pattern 3 is preferably provided in the second region R2.

  The oxide semiconductor layer formed by the same layer as the oxide semiconductor layer 5 provided in the trap level measurement pattern 3 is formed in the first region R1 that is a region including the central portion of the insulating substrate 2. Will be.

  According to such a configuration, since the trap level measurement pattern 3 is provided in the second region R2, which is a region including the end of the insulating substrate 2, the trap level measurement pattern 3 cannot be seen. In the case where it is necessary to do so, a light shielding member may be provided so as to cover only the second region R2, so that the circuit board 1 that can be easily used for a display device or the like can be realized.

  FIG. 1 shows a cross-sectional structure taken along the line AA ′ of the trap level measurement pattern 3 shown in FIG. 2, and a thermal stimulation current measurement system, which will be described in detail later, is produced using the trap level measurement pattern 3. It is a figure which shows a case.

  As shown in the figure, the trap level measurement pattern 3 forms a first conductive film that forms the first electrode 4, the oxide semiconductor layer 5, and the second electrode 6 on the insulating substrate 2. The second conductive film is sequentially stacked, and the oxide semiconductor layer 5 is interposed between the first electrode 4 and the second electrode 6.

  The structure of the trap level measurement pattern is not limited to this. If the oxide semiconductor layer 5 is formed so as to be in contact with the first electrode 4 and the second electrode 6, for example, it will be described later. The structure as described in the second embodiment and the third embodiment may be used.

  According to such a configuration, the first electrode 4, the second electrode 6, the first electrode 4, and the second electrode are formed on the surface of the insulating substrate 2 on which the oxide semiconductor layer 5 is formed. A trap level measurement pattern 3 including an oxide semiconductor layer 5 formed so as to be in contact with the electrode 6 is provided.

  Since the oxide semiconductor layer 5 is formed so as to be in contact with the first electrode 4 and the second electrode 6, if the thermally stimulated current measurement described later is performed using the trap level measurement pattern 3, the oxide semiconductor layer 5 is oxidized. Reflects not only the oxygen deficiency state in the oxide semiconductor layer 5 (in the depth direction of the oxide semiconductor layer 5) but also the oxygen deficiency state at the interface between the oxide semiconductor layer 5 and the first electrode 4 and the second electrode 6. can do.

  Therefore, it is possible to realize the circuit board 1 that can accurately predict the quality of an active element such as a TFT element including the oxide semiconductor layer 5.

  Note that as the oxide semiconductor layer 5, an oxide containing at least one element selected from In, Ga, and Zn can be used. In this embodiment, an IGZO-based material that contains all of In, Ga, and Zn Although an oxide semiconductor layer is used, the present invention is not limited to this. For example, a Zn-O-based oxide, an In-Si-Zn-O-based oxide, an In-Al-Zn-O-based oxide, An In—Mg—Zn—O-based oxide or the like can also be used as the semiconductor layer.

  The crystal state of the oxide semiconductor layer 5 is not particularly limited, and can be, for example, an amorphous semiconductor layer, a polycrystalline semiconductor layer, or a continuous grain boundary crystal semiconductor layer.

  The material of the first conductive film that forms the first electrode 4 and the second conductive film that forms the second electrode 6 may be any material that has conductivity, but one example is tantalum (Ta). Molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), and the like. Since these materials have low resistance, it is possible to accurately measure even a minute current when measuring a thermally stimulated current.

  In addition, as a material of the first conductive film that forms the first electrode 4 and the second conductive film that forms the second electrode 6, a laminated film of the above-described conductive material can also be used.

  As shown in FIG. 2, the first region R <b> 1, which is a region including the central portion of the insulating substrate 2, is the same layer as the oxide semiconductor layer 5 provided in the trap level measurement pattern 3. A transistor element (hereinafter referred to as a TFT element), which is an active element including an oxide semiconductor layer formed by the above method, is formed. For example, when the TFT element is formed in a top gate type, the second element is used. The electrode 6 is formed of a gate wiring material, the first electrode 4 is formed of a source / drain wiring material, and the second electrode 6 and the first electrode are formed simultaneously with pattern formation of the gate wiring material and the source / drain wiring material. 4 may be patterned.

  On the other hand, when the TFT element is formed of a bottom gate type, the first electrode 4 is formed of a gate wiring material, the second electrode 6 is formed of a source / drain wiring material, and the gate wiring material or source The first electrode 4 and the second electrode 6 may be patterned at the same time when the drain wiring material pattern is formed.

  In this way, the trap level measurement pattern 3 can be formed without using a new material or increasing the number of steps.

  The second electrode 6 can also be formed of a pixel electrode formation layer connected to the TFT element. In the case where the pixel electrode is a reflective pixel electrode, it can be suitably used because it is formed of aluminum (Al) or the like.

  Further, the trap level measurement pattern 3 causes a malfunction when leaking with the wiring pattern electrically connected to the TFT element formed in the first region R1 illustrated in FIG. As shown in the figure, it is necessary to form the second region R2 with a floating island structure.

  As will be described in detail later, the trap level measurement pattern 3 can be formed prior to the step of forming the TFT element in the first region R1 shown in FIG.

  Note that the thickness of the oxide semiconductor layer 5 in the trap level measurement pattern 3 is not particularly limited, but the oxide semiconductor layer provided in the TFT element formed in the first region R1 illustrated in FIG. The film thickness may be the same, for example, about 50 nm.

  In addition, in order to perform thermally stimulated current measurement using the trap level measurement pattern 3, a voltage source is applied to either the first electrode 4 or the second electrode 6 in the trap level measurement pattern 3. In the present embodiment, a voltage source is connected to the first electrode 4 and the second electrode 6 is connected to the other electrode, as shown in FIG. Is connected to a thermal stimulation ammeter.

  And since it is necessary to connect a conductive wire to the 1st electrode 4 and the 2nd electrode 6 in order to apply a voltage in the case of thermal stimulation current measurement, the 1st electrode 4 and the 2nd electrode The electrode 6 is preferably formed with a size of about 5 mm × 1 mm or more.

  As shown in FIG. 1, the oxide semiconductor layer 5 and the second electrode 6 are formed so that the surface of the first electrode 4 is exposed to a size of about 5 mm × 1 mm or more. It is preferred that

  The film thicknesses of the first electrode 4 and the second electrode 6 are not particularly limited, but the gate electrode, source / drain electrode, and wiring of the TFT element formed in the first region R1 shown in FIG. The film thickness may be the same as the film thickness, and for example, the film thickness may be approximately 400 nm.

  Thermally stimulated current measurement can be performed using the trap level measurement pattern 3 formed as described above. However, since this measurement takes about 2 to 3 hours, it is preferably performed by sampling. .

  Further, after maintenance of the film deposition apparatus used to form the oxide semiconductor layer 5 provided in the TFT element formed in the trap region measurement pattern 3 and the first region R1 illustrated in FIG. When the thermally stimulated current measurement is performed using the trap level measurement pattern 3 and the film quality of the oxide semiconductor layer 5 is evaluated, a change in film quality due to maintenance can be detected at an early stage.

  In addition, when a thermally stimulated current generated by the trap level is observed to be large in the thermally stimulated current measurement, a TFT element including such an oxide semiconductor layer becomes defective. Measures such as increasing the pressure to suppress the occurrence of oxygen deficiency can be implemented quickly.

  By using the trap level measurement pattern 3, the thermally stimulated current measurement can be performed even before the TFT element is completed, so that the defect of the oxide semiconductor layer can be dealt with quickly without causing defective products to flow out. it can.

  The case where the circuit board is a large-sized active matrix substrate provided with the trap level measurement pattern 3 will be described below with reference to FIGS.

  FIG. 3 is a diagram showing an example of a large-size active matrix substrate 1 a provided with the trap level measurement pattern 3 on the insulating substrate 2.

  As illustrated, when the large-sized active matrix substrate 1a is divided, nine TFT substrates 11 (indicated by dotted lines in the figure) can be obtained.

  The TFT substrate 11 is provided with a display region R1 and a non-display region R2. The end region R3 existing at the end of the insulating substrate 2 that is located away from the TFT substrate 11 has a trap level. A position measuring pattern 3 is provided.

  By disposing the trap level measurement pattern 3 at such a position, the unnecessary trap level measurement pattern 3 can be removed when the large active matrix substrate 1a is divided.

  A pixel TFT element 7 having a pixel electrode 10 for each pixel is provided in the display region R1 of the TFT substrate 11.

  The pixel TFT element 7 includes a gate electrode 4G formed of the same layer as the first electrode 4 of the trap level measurement pattern 3, a gate insulating film 8, and an oxide semiconductor layer 5 of the trap level measurement pattern 3. And the source / drain electrodes 6S and 6D formed of the same layer as the second electrode 6 of the trap level measurement pattern 3 and the oxide semiconductor layer 5 formed of the same layer. Yes.

  The drain electrode 6D is electrically connected to the pixel electrode 10 through a contact hole formed in the interlayer insulating film 9.

  FIG. 4 is a diagram showing an example in which the position and number of the trap level measurement patterns 3 are changed on the large active matrix substrate.

  As shown in FIG. 3, the position and number of the trap level measurement patterns 3 on the large-sized active matrix substrate are limited to the end region R3 existing at the end of the insulating substrate 2 or one. However, for example, as shown in FIG. 4, the trap level measurement pattern 3 can be provided for each non-display region R <b> 2 of the TFT substrate 11.

  As shown in FIG. 4, even when the oxide semiconductor layer 5 is formed on the large-sized active matrix substrate 1 b by arranging the trap level measurement pattern 3, even if variation occurs at each formation position. Since the thermally stimulated current measurement can be performed using the trap level measurement pattern 3 provided on each TFT substrate 11, the quality of the TFT element including the oxide semiconductor layer 5 can be predicted with high accuracy. Can do.

  Further, since the trap level measurement pattern 3 remains on each TFT substrate 11 even after the large active matrix substrate 1b is divided into the TFT substrates 11, if necessary, after the dividing process of the large active matrix substrate 1b, Measurement can be performed using the trap level measurement pattern 3.

  Hereinafter, a method for performing the thermal stimulation current measurement will be described in detail with reference to FIGS.

  First, the circuit board 1 and the active matrix substrates 1a and 1b shown in FIGS. 2, 3 and 4 are used as samples, and at least the trap level measurement pattern 3 in the sample is cooled using liquid nitrogen.

  In the cooling using liquid nitrogen, only the trap level measurement pattern 3 may be cooled. If this is difficult, the entire circuit board 1 and active matrix substrates 1a and 1b are cooled. May be.

  FIG. 5A is a diagram showing a state in which generated electrons and holes are trapped and frozen in the trap level in the oxide semiconductor layer 5 by applying a trap voltage, and FIG. It is a figure which shows the state by which an electron and a hole are open | released in an order from a shallow trap level by the thermal effect by temperature rising.

  After the trap level measurement pattern 3 is cooled to the liquid nitrogen region, a trap voltage is applied to the first electrode 4 to generate electrons and holes. As shown in FIG. Electrons and holes are captured and frozen at the trap level in the semiconductor layer 5 (see FIG. 1).

  Electrons and holes can also be generated by light irradiation.

  Next, when the trap level measurement pattern 3 is heated at a constant speed, electrons and holes are released in order from the shallow trap level as shown in FIG. 5B due to the thermal effect. .

  These releases are observed through the second electrode 6 as thermally stimulated currents. By analyzing the thermally stimulated current value thus observed, information on the trap level in the band gap in the oxide semiconductor layer 5 can be obtained.

  In the oxide semiconductor layer 5, trap levels are generated largely depending on oxygen vacancies. Therefore, information on the trap levels and oxygen vacancies can be obtained by analyzing the thermally stimulated current value.

  In addition, the measurement conditions of the thermally stimulated current measurement used in this Embodiment are as follows.

The measurement atmosphere is performed under He which is an inert gas (sealing), the temperature rising rate is 10 ° C./min, the measurement temperature range is −180 ° C. to 350 ° C., the trap voltage is 30 V, and the light is The intensity was set to 100 μW / cm ² with reference to light having a wavelength of 520 nm, and the respective conditions were set so that irradiation was performed for 2 minutes.

  In the present embodiment, both the application of the trap voltage and the light irradiation are used as a method for generating electrons and holes.

  The above measurement conditions are an example, and the measurement conditions can be appropriately changed as necessary.

  FIG. 6 is a diagram showing the results of thermal stimulation current measurement of the normal film and the defective film of the oxide semiconductor layer 5.

  FIG. 6A shows the result of measuring the thermally stimulated current of the normal oxide semiconductor layer 5, and FIG. 6B shows the result of measuring the thermally stimulated current of the defective oxide semiconductor layer 5 in which the trap level exists. Results are shown.

  As shown in FIG. 6 (a), in the normal oxide semiconductor layer 5, no peak of current value is observed in the range of −200 ° C. to 100 ° C., but it is shown in FIG. 6 (b). As shown, in the defective oxide semiconductor layer 5 in which the trap level exists, a peak of the current value indicating the presence of the trap level is confirmed near 0 ° C.

  The temperature T at which the thermally stimulated current value exhibits a peak and the trap level depth E have a relationship represented by the following formula 1.

E = kT · ln (T ⁴ / β) (Formula 1)
In the above formula 1, k is a Boltzmann constant, β is a rate of temperature increase, and T is an absolute temperature.

  From the above formula 1, the thermally stimulated current value having a peak near 0 ° C. means that a trap level exists at a depth of 0.57 eV.

  As described above, the trap level that greatly affects the film quality of the oxide semiconductor layer 5 can be evaluated by measuring the thermally stimulated current.

  Hereinafter, based on FIG. 7 to FIG. 9, the trap level measurement pattern 3 including the oxide semiconductor layer 5 and the TFT element 7 including the oxide semiconductor layer 5 on the large-sized active matrix substrates 1a and 1b, A manufacturing process for forming the above will be described.

  FIG. 7 shows a manufacturing process of an active matrix substrate on which a TFT element having an oxide semiconductor layer that has been conventionally used is formed.

  As shown in the drawing, in this conventional manufacturing process, after completing the TFT element having the pixel electrode through steps S101 to S106, the electrical characteristics of the completed TFT element are measured (S107). Therefore, it is difficult to determine whether a defect is caused by the oxide semiconductor layer or another layer provided in the TFT element. there were.

  In addition, after completing the TFT element, the result of measuring the electrical characteristics (S107) is poor, and after analyzing the cause, there is a problem in the film forming process of each layer provided in the TFT element. This means that the material and time are wasted, which is an undesirable manufacturing process considering the unit production cost and production efficiency.

  In the manufacturing process shown in FIG. 8 described below, the trap level measurement pattern 3 including the oxide semiconductor layer 5 and the TFT element 7 including the oxide semiconductor layer 5 are formed in the same substrate. FIG. 9 shows an example of a manufacturing process to be formed. The manufacturing process shown in FIG. 9 includes a trap level measurement pattern 3 including an oxide semiconductor layer 5 and a TFT element including the oxide semiconductor layer 5 on two different substrates. 7 shows an example of a manufacturing process for forming each of 7.

  FIG. 8 shows a manufacturing process for forming a trap level measurement pattern 3 including an oxide semiconductor layer 5 and a TFT element 7 including an oxide semiconductor layer 5 on a large-sized active matrix substrate 1a or 1b. It is a figure which shows an example.

  First, the first electrode 4 provided in the trap level measurement pattern 3 and the gate electrode 4G provided in the TFT element 7 are formed in one forming process using the same layer (S11).

  Then, the gate insulating film 8 is formed in a region other than the region where the trap level measurement pattern 3 is formed (S12).

  Then, the oxide semiconductor layer 5 provided in the trap level measurement pattern 3 and the TFT element 7 is formed in one forming process using the same layer (S13).

  Then, the second electrode 6 provided in the trap level measurement pattern 3 and the source / drain electrodes 6S and 6D provided in the TFT element 7 are formed in one forming process using the same layer ( S14).

  Thermally stimulated current measurement (S15) can be performed using the trap level measurement pattern 3 including the oxide semiconductor layer 5 formed so as to be in contact with the first electrode 4 and the second electrode 6.

  If the result of thermal stimulation current measurement is good, the next step, the interlayer insulating film 9 forming step (S16) and the pixel electrode 10 pattern forming step (S17), are performed to complete the TFT element 7.

  On the other hand, if the result of the thermally stimulated current measurement is a defect determination, there is a problem in the step of forming the oxide semiconductor layer 5 (S13), so the conditions for forming the oxide semiconductor layer 5 are reviewed and a new substrate is formed. Steps S11 to S14 are performed, and the thermal stimulation current measurement (S15) is performed again.

  By using such a manufacturing process, it is possible to accurately grasp whether the oxide semiconductor layer 5 provided in the TFT element 7 is normally formed before the TFT element 7 is completed.

  In addition, since it is possible to grasp whether the oxide semiconductor layer 5 is normally formed at an intermediate stage before the TFT element 7 is completed, the TFT element 7 is defective after the TFT element 7 is completed. When it is determined that there is a problem, it can be estimated that there is a high possibility that a problem has occurred in a portion other than the oxide semiconductor layer 5.

  Therefore, it becomes easy to specify whether the cause of the defect of the TFT element 7 is caused by the oxide semiconductor layer 5 or is not caused by another layer provided in the TFT element 7.

  Moreover, by using such a manufacturing process, even if a sudden trouble occurs in the vapor deposition process of the oxide semiconductor layer 5 and a defect occurs in the film quality, the trap level in the oxide semiconductor layer 5 is evaluated. By doing so, it is possible to respond quickly and provide quick feedback to the manufacturing process.

  Therefore, it is possible to quickly solve troubles, and as a result, it can be expected to improve production efficiency and yield.

  In such a manufacturing process, each of the first electrode 4 and the second electrode 6 includes an electrode layer of a TFT element 7 including the oxide semiconductor layer 5 as a semiconductor layer, and a conductive layer forming a wiring. Since they are formed of the same material, it is not necessary to add a new material or process, and the manufacturing cost can be suppressed.

  FIG. 9 shows the formation of the trap level measurement pattern 3 having the oxide semiconductor layer 5 on the insulating substrate, the conditions for forming the oxide semiconductor layer 5 are determined first, and then the determined oxide semiconductor layer 5 It is a figure which shows an example of the manufacturing process which forms the TFT element 7 provided with the oxide semiconductor layer 5 on the large sized substrate different from the said insulating substrate using the formation conditions of the conventional method.

  As shown in the figure, first, the first electrode 4 is formed on the insulating substrate (S21), then the oxide semiconductor layer 5 is formed (S22), and finally the second electrode 6 is formed. (S23) The trap level measurement pattern 3 is completed, and the trap level measurement pattern 3 including the oxide semiconductor layer 5 formed so as to be in contact with the first electrode 4 and the second electrode 6 is used. Then, the thermal stimulation current measurement (S24) is performed.

  If the result of this thermally stimulated current measurement (S24) is good, the conditions used in the step (S22) of forming the oxide semiconductor layer 5 are used as they are on a large substrate different from the insulating substrate. The TFT element 7 provided with the physical semiconductor layer 5 is formed by a conventional method constituted by steps S101 to S106.

  On the other hand, if the result of the thermal stimulation current measurement (S24) is a failure determination, the conditions used in the step (S22) of forming the oxide semiconductor layer 5 are reviewed, and the steps S21 to S23 are performed again on a new insulating substrate. The trap level measurement pattern 3 is completed, and the thermal stimulation current measurement (S24) is performed using the trap level measurement pattern 3.

  By using such a manufacturing process, the conditions for forming the oxide semiconductor layer 5 can be relatively easily formed, and the trap level capable of accurately grasping the trap level of the oxide semiconductor layer 5 can be obtained. The level measurement pattern 3 can be used for confirmation.

  The TFT substrate 11 can be suitably used for various display devices such as a liquid crystal display device and an organic EL display device.

[Embodiment 2]
Next, a second embodiment of the present invention will be described based on FIGS. In this embodiment, the trap level measurement pattern is formed on the insulating substrate 2 in the same manner as in the first embodiment, but the structure of the trap level measurement pattern 12 is the same as that in the first embodiment. This is different from the trap level measurement pattern 3. Other configurations are as described in the first embodiment. For convenience of explanation, members having the same functions as those shown in the drawings of the first embodiment are given the same reference numerals, and descriptions thereof are omitted.

  FIG. 10 is a view showing an example of a large-size active matrix substrate 1 c provided with the trap level measurement pattern 12 on the insulating substrate 2.

  As shown in the drawing, when the large active matrix substrate 1c is divided, nine TFT substrates 11 (indicated by dotted lines in the figure) can be obtained.

  The TFT substrate 11 is provided with a display region R1 and a non-display region R2. The end region R3 existing at the end of the insulating substrate 2 that is located away from the TFT substrate 11 has a trap level. A position measurement pattern 12 is provided.

  The trap level measurement pattern 12 has a structure in which both the first electrode 6 </ b> A and the second electrode 6 </ b> B, which are two independent electrodes, are formed on the oxide semiconductor layer 5.

  The first electrode 6A and the second electrode 6B are formed in the same layer, and in the present embodiment, the same layer as the source / drain electrodes 6S and 6D provided in the TFT element 7 is used. Was formed in one forming step.

  FIG. 11 is a diagram showing a cross-sectional structure of the trap level measurement pattern 12 shown in FIG. 10 taken along the line BB ′ and a case where a thermally stimulated current measurement system is manufactured using the trap level measurement pattern 12. It is.

  As shown in the figure, in the present embodiment, a voltage source is connected to the first electrode 6A, and a thermal stimulation ammeter is connected to the second electrode 6B.

  And since it is necessary to connect a conductive wire to the first electrode 6A and the second electrode 6B in order to apply a voltage at the time of thermal stimulation current measurement, the first electrode 6A and the second electrode 6B The electrode 6B is preferably formed with a size of about 5 mm × 1 mm or more.

  In addition, the distance between the first electrode 6A and the second electrode 6B is not particularly limited, but can be formed to be about 1 mm as an example.

  Further, the first electrode 6A and the second electrode 6B can be formed by a formation layer of the pixel electrode 10 connected to the TFT element 7. In the case where the pixel electrode 10 is a reflective pixel electrode, it can be preferably used because it is formed of aluminum (Al) or the like.

  In the manufacturing process shown in FIG. 12 described below, the trap level measurement pattern 12 including the oxide semiconductor layer 5 and the TFT element 7 including the oxide semiconductor layer 5 on two different substrates, An example of a manufacturing process for forming each of the above is shown. The manufacturing process shown in FIG. 13 includes the trap level measurement pattern 12 including the oxide semiconductor layer 5 and the oxide semiconductor layer 5 in the same substrate. An example of a manufacturing process for forming the TFT element 7 is shown.

  In FIG. 12, the trap level measurement pattern 12 including the oxide semiconductor layer 5 is formed on the insulating substrate, the formation conditions of the oxide semiconductor layer 5 are determined first, and then the determined oxide semiconductor layer 5 is determined. It is a figure which shows an example of the manufacturing process which forms the TFT element 7 provided with the oxide semiconductor layer 5 on the large sized substrate different from the said insulating substrate using the formation conditions of the conventional method.

  As shown in the figure, first, the oxide semiconductor layer 5 is formed (S31), and then the first electrode 6A and the second electrode 6B are formed on the oxide semiconductor layer 5 using the same layer. The trap level measurement including the oxide semiconductor layer 5 formed so as to be in contact with the first electrode 6A and the second electrode 6B is completed in one step (S32), and the trap level measurement pattern 12 is completed. The thermal stimulation current measurement (S33) is performed using the pattern 12 for use.

  In the trap level measurement pattern 12, the oxide semiconductor layer 5 is formed so as to be in contact with the first electrode 6A and the second electrode 6B. When current measurement is performed, not only the oxygen deficiency state in the oxide semiconductor layer 5 (in the depth direction of the oxide semiconductor layer 5) but also the oxide semiconductor layer 5 and the first electrode 6A and the second electrode 6B. The state of oxygen deficiency at the interface can also be reflected.

  As described above, the manufacturing process of the trap level measurement pattern 12 is shorter than the manufacturing process of the trap level measurement pattern 3 used in Embodiment 1, and the formation conditions of the oxide semiconductor layer 5 are the same. In addition, the trap level measurement pattern 12 that can be formed more easily and can accurately grasp the trap level of the oxide semiconductor layer 5 can be determined.

  Since the other steps have already been described in Embodiment 1, the description thereof is omitted.

  FIG. 13 shows an example of a manufacturing process in which a trap level measurement pattern 12 including the oxide semiconductor layer 5 and a TFT element 7 including the oxide semiconductor layer 5 are simultaneously formed on the large-sized active matrix substrate 1c. FIG.

  First, the gate electrode 4G provided in the TFT element 7 is formed (S41), and then the gate insulating film 8 is formed on the entire surface of the substrate (S42).

  Then, the oxide semiconductor layer 5 provided in the trap level measurement pattern 12 and the TFT element 7 is formed in one forming process using the same layer (S43).

  Then, the source / drain electrodes 6S and 6D provided in the TFT element 7 and the first electrode 6A and the second electrode 6B provided in the trap level measurement pattern 12 are combined into a single layer using the same layer. It is formed in a process (S44), and the trap level measurement pattern 12 is completed.

  Thermally stimulated current measurement (S45) can be performed using the trap level measurement pattern 12 including the oxide semiconductor layer 5 formed so as to be in contact with the first electrode 6A and the second electrode 6B.

  In the trap level measurement pattern 12, the oxide semiconductor layer 5 is formed so as to be in contact with the first electrode 6A and the second electrode 6B. When current measurement is performed, not only the oxygen deficiency state in the oxide semiconductor layer 5 (in the depth direction of the oxide semiconductor layer 5) but also the oxide semiconductor layer 5 and the first electrode 6A and the second electrode 6B. The state of oxygen deficiency at the interface can also be reflected.

  If the result of thermal stimulation current measurement is good, the next step, the formation process of the interlayer insulating film 9 (S46) and the pixel electrode 10 pattern formation process (S47), are performed to complete the TFT element 7.

  On the other hand, if the result of the thermally stimulated current measurement is a failure determination, there is a problem in the step of forming the oxide semiconductor layer 5 (S43), so the conditions for forming the oxide semiconductor layer 5 are reviewed and a new substrate is formed. Steps S41 to S44 are performed, and the thermal stimulation current measurement (S45) is performed again.

  By using such a manufacturing process, it is possible to grasp whether the oxide semiconductor layer 5 provided in the TFT element 7 is normally formed before the TFT element 7 is completed.

  In addition, since it is possible to grasp whether the oxide semiconductor layer 5 is normally formed at an intermediate stage before the TFT element 7 is completed, the TFT element 7 is defective after the TFT element 7 is completed. When it is determined that there is a problem, it can be estimated that there is a high possibility that a problem has occurred in a portion other than the oxide semiconductor layer 5.

  Therefore, it becomes easy to specify whether the cause of the defect of the TFT element 7 is caused by the oxide semiconductor layer 5 or is not caused by another layer provided in the TFT element 7.

  Moreover, by using such a manufacturing process, even if a sudden trouble occurs in the vapor deposition process of the oxide semiconductor layer 5 and a defect occurs in the film quality, the trap level in the oxide semiconductor layer 5 is evaluated. By doing so, it is possible to respond quickly and provide quick feedback to the manufacturing process.

  Therefore, it is possible to quickly solve troubles, and as a result, it can be expected to improve production efficiency and yield.

  Further, in such a manufacturing process, each of the first electrode 6A and the second electrode 6B includes an electrode layer of the TFT element 7 including the oxide semiconductor layer 5 as a semiconductor layer, and a conductive layer forming a wiring. Since they are formed of the same material, it is not necessary to add a new material or process, and the manufacturing cost can be suppressed.

[Embodiment 3]
Next, a third embodiment of the present invention will be described with reference to FIGS. In the present embodiment, the trap level measurement pattern is formed on the insulating substrate 2 in the same manner as in the first and second embodiments, but the structure of the trap level measurement pattern 13 is This is different from the trap level measurement pattern 3 used in the first embodiment and the trap level measurement pattern 12 used in the second embodiment. Other configurations are as described in the first embodiment and the second embodiment. For convenience of explanation, members having the same functions as those shown in the drawings of Embodiment 1 and Embodiment 2 described above are given the same reference numerals, and descriptions thereof are omitted.

  FIG. 14 is a diagram showing an example of a large-size active matrix substrate 1 d provided with the trap level measurement pattern 13 on the insulating substrate 2.

  As shown in the drawing, when the large-sized active matrix substrate 1d is divided, nine TFT substrates 11 (indicated by dotted lines in the figure) can be obtained.

  The TFT substrate 11 is provided with a display region R1 and a non-display region R2. The end region R3 existing at the end of the insulating substrate 2 that is located away from the TFT substrate 11 has a trap level. A position measuring pattern 13 is provided.

  FIG. 15 is a diagram showing a cross-sectional structure taken along the line CC ′ of the trap level measurement pattern 13 shown in FIG. 14 and a case where a thermally stimulated current measurement system is manufactured using the trap level measurement pattern 13. It is.

  As shown in FIG. 15, the trap level measurement pattern 13 includes both the first electrode 6 </ b> A and the second electrode 6 </ b> B that are two independent electrodes on the oxide semiconductor layer 5. In the lower layer of the oxide semiconductor layer 5, the third electrode 4A is provided with an insulating layer 8A interposed therebetween.

  The first electrode 6A and the second electrode 6B are formed in the same layer, and in the present embodiment, the same layer as the source / drain electrodes 6S and 6D provided in the TFT element 7 is used. Was formed in one forming step.

  In the present embodiment, the third electrode 4A is formed in one forming process using the same layer as the gate electrode 4G provided in the TFT element 7.

  As shown in the figure, in the present embodiment, a voltage source is connected to the first electrode 6A, and a thermal stimulation ammeter is connected to the second electrode 6B.

  FIG. 16 is a diagram illustrating an example of measuring electrical characteristics as a TFT element using the trap level measurement pattern 13.

  As shown in the figure, when the third electrode 4A acts as a gate electrode, one of the first electrode 6A and the second electrode 6B acts as a source electrode, and the other acts as a drain electrode. The trap level measurement pattern 13 can be operated as a TFT element.

  Therefore, it is possible to evaluate the electrical characteristics of the TFT element by using the trap level measurement pattern 13 used for evaluating the trap level of the oxide semiconductor layer 5 as it is.

  FIG. 17 shows an example of a manufacturing process for simultaneously forming the trap level measurement pattern 13 including the oxide semiconductor layer 5 and the TFT element 7 including the oxide semiconductor layer 5 on the large-sized active matrix substrate 1d. FIG.

  First, the gate electrode 4G provided in the TFT element 7 and the third electrode 4A provided in the trap level measurement pattern 12 are formed in one forming process using the same layer (S51). Thereafter, the gate insulating film 8 is formed on the entire surface of the substrate (S52).

  Then, the oxide semiconductor layer 5 provided in the trap level measurement pattern 13 and the TFT element 7 is formed in one forming process using the same layer (S53).

  Then, the source / drain electrodes 6S and 6D provided in the TFT element 7 and the first electrode 6A and the second electrode 6B provided in the trap level measurement pattern 13 are combined into a single layer using the same layer. The trap level measurement pattern 13 is completed by forming in the process (S54).

  Then, as shown in FIG. 15, thermal stimulation is performed using the trap level measurement pattern 13 including the oxide semiconductor layer 5 formed so as to be in contact with the first electrode 6A and the second electrode 6B. A current measurement system can be produced and thermally stimulated current measurement (S55) can be performed.

  In the trap level measurement pattern 13, the oxide semiconductor layer 5 is formed so as to be in contact with the first electrode 6 </ b> A and the second electrode 6 </ b> B. When current measurement is performed, not only the oxygen deficiency state in the oxide semiconductor layer 5 (in the depth direction of the oxide semiconductor layer 5) but also the oxide semiconductor layer 5 and the first electrode 6A and the second electrode 6B. The state of oxygen deficiency at the interface can also be reflected.

  Further, as shown in FIG. 16, the electrical characteristics measurement (S55) as the TFT element can be performed using the trap level measurement pattern 13.

  If the results of the thermal stimulation current measurement and the electrical characteristic measurement (S55) are good, the next step, the formation process of the interlayer insulating film 9 (S56) and the pixel electrode 10 pattern formation process (S57), are performed. Complete 7

  On the other hand, if the result of the thermally stimulated current measurement (S55) is a failure determination, there is a problem in the step of forming the oxide semiconductor layer 5 (S53), so the conditions for forming the oxide semiconductor layer 5 are reviewed, Steps S51 to S54 are performed on the new substrate, and the thermal stimulation current measurement and the electrical property measurement (S55) are performed again.

  Further, if the result of the thermal stimulation current measurement (S55) is a good judgment and the result of the electrical characteristic measurement (S55) is a bad judgment, the steps other than the step (S53) for forming the oxide semiconductor layer 5 (S51 and S52). Since there was a problem in S54), the formation conditions of such steps (S51, S52, S54) were reviewed, and the steps S51 to S54 were performed on a new substrate. Measurement (S55) is performed.

  By using such a manufacturing process, it is possible to grasp whether the oxide semiconductor layer 5 and other layers provided in the TFT element 7 are normally formed before the TFT element 7 is completed.

  Further, in the intermediate stage before the TFT element 7 is completed, the thermal stimulation current measurement and the electrical characteristic measurement (S55) can be performed. If the result of the thermal stimulation current measurement is a failure determination, the oxide semiconductor layer 5 If it can be estimated that there was a problem in the forming step (S53), the result of the thermal stimulation current measurement (S55) is a good judgment, and the result of the electrical characteristic measurement (S55) is a bad judgment, the oxide semiconductor Since it can be estimated that there was a problem in the steps (S51, S52, S54) other than the step of forming the layer 5 (S53), the cause of the defect of the TFT element 7 can be easily identified.

  Moreover, by using such a manufacturing process, even if a sudden trouble occurs in the vapor deposition process of the oxide semiconductor layer 5 and a defect occurs in the film quality, the trap level in the oxide semiconductor layer 5 is evaluated. By doing so, it is possible to respond quickly and provide quick feedback to the manufacturing process.

  Therefore, it is possible to quickly solve troubles, and as a result, it can be expected to improve production efficiency and yield.

  In such a manufacturing process, each of the first electrode 6A, the second electrode 6B, and the third electrode 4A includes an electrode layer and a wiring of the TFT element 7 including the oxide semiconductor layer 5 as a semiconductor layer. Since the conductive layer is formed of the same material as the conductive layer, it is not necessary to add a new material or process, and the manufacturing cost can be reduced.

  Although not shown in the drawings, as described in Embodiments 1 and 2, only the trap level measurement pattern 13 including the oxide semiconductor layer 5 is formed on the insulating substrate, and the trap level is formed. The thermal stimulation current measurement and the electrical property measurement are performed using the position measurement pattern 13, and the formation conditions of the oxide semiconductor layer 5 and other layers are determined in advance, and then the insulation is performed using the determined formation conditions. The TFT element 7 including the oxide semiconductor layer 5 can be formed on a large substrate different from the substrate by a conventional method.

  The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and the present invention can be obtained by appropriately combining technical means disclosed in different embodiments. Embodiments are also included in the technical scope of the present invention.

  The present invention can be suitably used in the fields of circuit boards, active matrix substrates, display devices, and the like.

DESCRIPTION OF SYMBOLS 1 Circuit board 1a, 1b, 1c, 1d Active matrix board | substrate 2 Insulating board | substrate 3 Pattern for trap level measurement 4 1st electrode 4A 3rd electrode 4G Gate electrode 5 Oxide semiconductor layer 6 2nd electrode 6A 1st Electrode 6B Second electrode 6S Source electrode 6D Drain electrode 7 TFT element 8 Gate insulating film 9 Interlayer insulating film 10 Pixel electrode 11 TFT substrate 12 Trap level measurement pattern 13 Trap level measurement pattern R1 Display area R2 Non-display area R3 end region

Claims (15)

A circuit board provided with an oxide semiconductor layer on one surface of an insulating substrate,
On the surface of the insulating substrate on which the oxide semiconductor layer is formed, a first electrode, a second electrode that is electrically separated from the first electrode, and the first electrode A circuit board comprising: a trap level measurement pattern comprising: an electrode; and the oxide semiconductor layer formed so as to be in contact with the second electrode. The surface on the side where the oxide semiconductor layer is formed in the insulating substrate includes a first region which is a region including a central portion of the insulating substrate, a peripheral region of the first region, and And a second region that is a region including an end portion of the insulating substrate,
The circuit board according to claim 1, wherein the trap level measurement pattern is provided in the second region.   3. The circuit according to claim 1, wherein, in the trap level measurement pattern, the oxide semiconductor layer is interposed between the first electrode and the second electrode. substrate.   The said trap level measurement pattern WHEREIN: Both the said 1st electrode and the said 2nd electrode are formed in either one of the upper part of the said oxide semiconductor layer, and the lower part, It is characterized by the above-mentioned. The circuit board according to 1 or 2. In the trap level measurement pattern, both the first electrode and the second electrode are formed on either the upper part or the lower part of the oxide semiconductor layer,
The circuit board according to claim 4, wherein the third electrode is formed on the other side of the oxide semiconductor layer, which is the surface opposite to the one side, through an insulating layer.   Each of the first electrode and the second electrode is made of the same material as an electrode layer of an active element formed on the insulating substrate including the oxide semiconductor layer as a semiconductor layer and a conductive layer forming a wiring. The circuit board according to claim 1, wherein the circuit board is formed.   Each of the first electrode, the second electrode, and the third electrode forms an electrode layer and a wiring of an active element formed on the insulating substrate including the oxide semiconductor layer as a semiconductor layer. The circuit board according to claim 5, wherein the circuit board is made of the same material as the conductive layer.   The circuit board according to claim 1, wherein the oxide semiconductor layer contains at least one element selected from In, Ga, and Zn. The circuit board according to any one of claims 1 to 8, comprising:
A plurality of active elements including a semiconductor layer formed of the same layer as the oxide semiconductor layer is provided on the circuit board.
A pixel electrode is electrically connected to each of the active elements,
An active matrix substrate, wherein the plurality of pixel electrodes are formed in a matrix.   In the trap level measurement pattern, each of the first electrode and the second electrode is formed of the same material as an electrode layer of the active element including the pixel electrode and a conductive layer forming a wiring. The active matrix substrate according to claim 9. In the trap level measurement pattern, both the first electrode and the second electrode are formed on either the upper part or the lower part of the oxide semiconductor layer,
The third electrode is formed on the other side of the oxide semiconductor layer opposite to the one side through an insulating layer,
Each of the first electrode, the second electrode, and the third electrode is formed of the same material as the electrode layer of the active element including the pixel electrode and the conductive layer forming the wiring. An active matrix substrate according to claim 9.   The active matrix substrate according to any one of claims 9 to 11, a counter substrate, and a liquid crystal layer interposed between the active matrix substrate and the counter substrate, Display device.   The active matrix substrate according to any one of claims 9 to 11, and an organic EL layer formed on a surface side of the active matrix substrate on which the pixel electrodes are formed. Display device. A method of manufacturing a circuit board provided with an oxide semiconductor layer on one surface of an insulating substrate,
On the surface of the insulating substrate on which the oxide semiconductor layer is formed, a first electrode, a second electrode electrically separated from the first electrode, the first electrode, Forming a trap level measurement pattern comprising: the oxide semiconductor layer formed to be in contact with the second electrode;
And a step of measuring the trap level of the oxide semiconductor layer by thermally stimulated current measurement. The first electrode and the second electrode are both formed on either the upper or lower portion of the oxide semiconductor layer,
The third electrode is formed on the other side of the oxide semiconductor layer opposite to the one side through an insulating layer,
One of the first electrode and the second electrode acts as a source electrode, the other acts as a drain electrode, the third electrode acts as a gate electrode, and the transistor element of the oxide semiconductor layer The method for manufacturing a circuit board according to claim 14, further comprising a step of evaluating characteristics.

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