JP6257799B2 - Metal oxide semiconductor film, thin film transistor, and electronic device - Google Patents
Metal oxide semiconductor film, thin film transistor, and electronic device Download PDFInfo
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- JP6257799B2 JP6257799B2 JP2016556442A JP2016556442A JP6257799B2 JP 6257799 B2 JP6257799 B2 JP 6257799B2 JP 2016556442 A JP2016556442 A JP 2016556442A JP 2016556442 A JP2016556442 A JP 2016556442A JP 6257799 B2 JP6257799 B2 JP 6257799B2
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- Prior art keywords
- oxide semiconductor
- metal oxide
- film
- semiconductor film
- zinc
- Prior art date
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- 239000010408 film Substances 0.000 title claims description 210
- 239000004065 semiconductor Substances 0.000 title claims description 167
- 229910044991 metal oxide Inorganic materials 0.000 title claims description 153
- 150000004706 metal oxides Chemical class 0.000 title claims description 153
- 239000010409 thin film Substances 0.000 title claims description 37
- 239000011135 tin Substances 0.000 claims description 85
- 239000011701 zinc Substances 0.000 claims description 69
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 50
- 229910052725 zinc Inorganic materials 0.000 claims description 50
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 49
- 229910052718 tin Inorganic materials 0.000 claims description 49
- 229910052751 metal Inorganic materials 0.000 claims description 41
- 239000002184 metal Substances 0.000 claims description 41
- 239000000203 mixture Substances 0.000 claims description 25
- 238000001004 secondary ion mass spectrometry Methods 0.000 claims description 13
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 9
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 8
- 229910052799 carbon Inorganic materials 0.000 claims description 8
- 229910052739 hydrogen Inorganic materials 0.000 claims description 8
- 239000001257 hydrogen Substances 0.000 claims description 8
- 239000012528 membrane Substances 0.000 claims 1
- 238000000034 method Methods 0.000 description 59
- 239000000758 substrate Substances 0.000 description 57
- 239000002243 precursor Substances 0.000 description 55
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- 238000006243 chemical reaction Methods 0.000 description 30
- 230000000052 comparative effect Effects 0.000 description 19
- 239000000463 material Substances 0.000 description 19
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- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 18
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- 150000002500 ions Chemical class 0.000 description 6
- 238000002161 passivation Methods 0.000 description 6
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- HPGGPRDJHPYFRM-UHFFFAOYSA-J tin(iv) chloride Chemical compound Cl[Sn](Cl)(Cl)Cl HPGGPRDJHPYFRM-UHFFFAOYSA-J 0.000 description 6
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- ZOIORXHNWRGPMV-UHFFFAOYSA-N acetic acid;zinc Chemical compound [Zn].CC(O)=O.CC(O)=O ZOIORXHNWRGPMV-UHFFFAOYSA-N 0.000 description 5
- 238000004458 analytical method Methods 0.000 description 5
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- 239000004020 conductor Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 5
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- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 3
- ZMXDDKWLCZADIW-UHFFFAOYSA-N N,N-Dimethylformamide Chemical compound CN(C)C=O ZMXDDKWLCZADIW-UHFFFAOYSA-N 0.000 description 3
- 229910007604 Zn—Sn—O Inorganic materials 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
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- 229910052779 Neodymium Inorganic materials 0.000 description 2
- XURCIPRUUASYLR-UHFFFAOYSA-N Omeprazole sulfide Chemical compound N=1C2=CC(OC)=CC=C2NC=1SCC1=NC=C(C)C(OC)=C1C XURCIPRUUASYLR-UHFFFAOYSA-N 0.000 description 2
- JUJWROOIHBZHMG-UHFFFAOYSA-N Pyridine Chemical compound C1=CC=NC=C1 JUJWROOIHBZHMG-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- WYURNTSHIVDZCO-UHFFFAOYSA-N Tetrahydrofuran Chemical compound C1CCOC1 WYURNTSHIVDZCO-UHFFFAOYSA-N 0.000 description 2
- 238000004833 X-ray photoelectron spectroscopy Methods 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 239000003153 chemical reaction reagent Substances 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
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- 238000011156 evaluation Methods 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000005286 illumination Methods 0.000 description 2
- 229910003437 indium oxide Inorganic materials 0.000 description 2
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 2
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 2
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- 239000007791 liquid phase Substances 0.000 description 2
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- 239000010935 stainless steel Substances 0.000 description 2
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- 229910052715 tantalum Inorganic materials 0.000 description 2
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 2
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- 229910001233 yttria-stabilized zirconia Inorganic materials 0.000 description 2
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- 239000011787 zinc oxide Substances 0.000 description 2
- NNWNNQTUZYVQRK-UHFFFAOYSA-N 5-bromo-1h-pyrrolo[2,3-c]pyridine-2-carboxylic acid Chemical compound BrC1=NC=C2NC(C(=O)O)=CC2=C1 NNWNNQTUZYVQRK-UHFFFAOYSA-N 0.000 description 1
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- 229910002651 NO3 Inorganic materials 0.000 description 1
- NHNBFGGVMKEFGY-UHFFFAOYSA-N Nitrate Chemical compound [O-][N+]([O-])=O NHNBFGGVMKEFGY-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
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Description
本発明は、金属酸化物半導体膜の製造方法、ならびに、金属酸化物半導体膜、薄膜トランジスタおよび電子デバイスに関する。 The present invention relates to a method for manufacturing a metal oxide semiconductor film, and a metal oxide semiconductor film, a thin film transistor, and an electronic device.
酸化物半導体膜または酸化物導体膜としての金属酸化物膜は真空成膜法による製造において実用化がなされ、現在注目を集めている。
また、耐熱性の低い樹脂基板へ金属酸化物半導体を形成するため、低温で金属酸化物半導体膜を形成することが求められている。
そこで、低温で、かつ、簡便に、大気圧下で高い半導体特性を有する酸化物半導体膜を形成することを目的とした、液相プロセスによる酸化物半導体膜の作製に関して研究開発が盛んに行われている。最近では、溶液を基板上に塗布し、紫外線を用いることで150℃以下の低温で高い輸送特性を有する薄膜トランジスタ(TFT:Thin Film Transistor)を製造する手法が報告されている(非特許文献1参照)。A metal oxide film as an oxide semiconductor film or an oxide conductor film has been put into practical use in production by a vacuum film forming method, and is currently attracting attention.
In addition, in order to form a metal oxide semiconductor on a resin substrate having low heat resistance, it is required to form a metal oxide semiconductor film at a low temperature.
Therefore, research and development have been actively conducted on the production of an oxide semiconductor film by a liquid phase process for the purpose of forming an oxide semiconductor film having high semiconductor characteristics at low temperature and easily under atmospheric pressure. ing. Recently, a method for manufacturing a thin film transistor (TFT) having high transport properties at a low temperature of 150 ° C. or lower by applying a solution on a substrate and using ultraviolet rays has been reported (see Non-Patent Document 1). ).
また、硝酸塩等を含む溶液を基材上に塗布した後、150℃程度で加熱して溶媒を揮発させることにより金属酸化物半導体の前駆体を含む薄膜を形成し、その後、酸素の存在下で紫外光(UV:Ultraviolet)を照射することにより、金属酸化物半導体を製造する方法が開示されている(特許文献1参照)。 In addition, after applying a solution containing nitrate or the like on the substrate, the thin film containing the precursor of the metal oxide semiconductor is formed by heating at about 150 ° C. to volatilize the solvent, and then in the presence of oxygen. A method of manufacturing a metal oxide semiconductor by irradiating with ultraviolet light (UV: Ultraviolet) has been disclosed (see Patent Document 1).
ここで、非特許文献1では、高い輸送特性を示したのは、金属酸化物半導体膜中にインジウムを含むもののみであり、インジウムを含まないZn−Sn−Oの系ではトランジスタ動作を確認することが出来なかったと報告している。
また、特許文献1には、インジウムを含む金属酸化物半導体が記載されるのみである。Here, in Non-Patent Document 1, only a metal oxide semiconductor film containing indium shows high transport characteristics, and transistor operation is confirmed in a Zn—Sn—O system that does not contain indium. I reported that I couldn't.
Patent Document 1 only describes a metal oxide semiconductor containing indium.
インジウムは生産量に限りのあるレアメタルであり、今後、供給量の逼迫、原料価格の高騰が予想されることから、金属酸化物半導体の材料としてインジウムを用いない材料が求められている。
そのため、インジウムを含まない金属酸化物半導体を、液相プロセスにより作製することが研究されている。
例えば、非特許文献2には、インジウムを含まない金属酸化物半導体である、Zn−Sn−O系薄膜の作製において、紫外線照射を併用したアニール処理を適用する試みが報告されている。Indium is a rare metal with a limited production volume, and in the future, the supply amount is expected to be tight and the raw material price is expected to rise. Therefore, a material that does not use indium is required as a metal oxide semiconductor material.
Therefore, it has been studied to produce a metal oxide semiconductor containing no indium by a liquid phase process.
For example, Non-Patent Document 2 reports an attempt to apply an annealing treatment combined with ultraviolet irradiation in the production of a Zn—Sn—O-based thin film that is a metal oxide semiconductor that does not contain indium.
しかしながら、非特許文献2に記載されるZn−Sn−O系薄膜の製造方法では、良好なトランジスタ動作を実現させるために、紫外線照射を併用したアニール処理を行った後に、真空中でのアニール処理を施す必要がある。そのため、生産コストが増加するという問題がある。 However, in the method for producing a Zn—Sn—O-based thin film described in Non-Patent Document 2, in order to realize a good transistor operation, an annealing process in combination with ultraviolet irradiation is performed, and then an annealing process in a vacuum is performed. It is necessary to apply. Therefore, there is a problem that the production cost increases.
本発明の目的は、このような従来技術の問題点を解決することにあり、レアメタルであるインジウムを含まない安価な材料を用いて、簡便に、低温で、かつ、大気圧下で形成可能で、高い半導体特性を有する酸化物半導体膜を形成することができる金属酸化物半導体膜の製造方法、ならびに、金属酸化物半導体膜、薄膜トランジスタおよび電子デバイスを提供することを目的とする。 An object of the present invention is to solve such problems of the prior art, and can be formed easily, at a low temperature, and under atmospheric pressure using an inexpensive material that does not contain indium, which is a rare metal. An object of the present invention is to provide a metal oxide semiconductor film manufacturing method capable of forming an oxide semiconductor film having high semiconductor characteristics, and a metal oxide semiconductor film, a thin film transistor, and an electronic device.
本発明者は、上記目的を達成すべく鋭意検討した結果、溶媒及び金属成分として亜鉛とスズとを含む溶液を基板上に塗布して金属酸化物半導体前駆体膜を形成する金属酸化物半導体前駆体膜形成工程と、金属酸化物半導体前駆体膜を加熱した状態で紫外線照射を行うことにより、金属酸化物半導体前駆体膜を金属酸化物半導体膜に転化させる転化工程とを有し、金属酸化物半導体前駆体膜中の全金属成分の80%以上が亜鉛およびスズであり、亜鉛とスズとの組成比が、0.7≦Sn/(Sn+Zn)≦0.9であることにより、インジウムを含まない安価な材料を用いて、簡便に、低温で、かつ、大気圧下で形成可能で、高い半導体特性を有する酸化物半導体膜を形成することができることを見出し、本発明を完成させた。
すなわち、以下の構成により上記目的を達成することができることを見出した。As a result of intensive studies to achieve the above object, the present inventor applied a solution containing zinc and tin as a solvent and metal components on a substrate to form a metal oxide semiconductor precursor film. A body film forming step and a conversion step of converting the metal oxide semiconductor precursor film into a metal oxide semiconductor film by irradiating with ultraviolet rays while the metal oxide semiconductor precursor film is heated. 80% or more of the total metal component in the semiconductor precursor film is zinc and tin, and the composition ratio of zinc and tin is 0.7 ≦ Sn / (Sn + Zn) ≦ 0.9, whereby indium It has been found that an oxide semiconductor film that can be easily formed at low temperature and under atmospheric pressure and has high semiconductor characteristics can be formed using an inexpensive material that does not include the present invention, and the present invention has been completed.
That is, it has been found that the above object can be achieved by the following configuration.
[1] 溶媒及び金属成分として亜鉛とスズとを含む溶液を基板上に塗布して金属酸化物半導体前駆体膜を形成する金属酸化物半導体前駆体膜形成工程と、
金属酸化物半導体前駆体膜を加熱した状態で紫外線照射を行うことにより、金属酸化物半導体前駆体膜を金属酸化物半導体膜に転化させる転化工程とを有し、
金属酸化物半導体前駆体膜中の全金属成分の80%以上が亜鉛およびスズであり、亜鉛とスズとの組成比が、0.7≦Sn/(Sn+Zn)≦0.9である金属酸化物半導体膜の製造方法。
[2] 金属酸化物半導体前駆体膜中におけるインジウムの成分比が5%未満である[1]に記載の金属酸化物半導体膜の製造方法。
[3] 転化工程において、紫外線照射中の基板の温度を250℃以下に保持する[1]または[2]に記載の金属酸化物半導体膜の製造方法。
[4] 転化工程において、金属酸化物半導体前駆体膜に照射される紫外線は、波長300nm以下の照度が30mW/cm2以上である[1]〜[3]のいずれかに記載の金属酸化物半導体膜の製造方法。
[5] 転化工程は、酸素を1体積%以上含む雰囲気中で行われる[1]〜[4]のいずれかに記載の金属酸化物半導体膜の製造方法。
[6] 金属酸化物半導体前駆体膜中の全金属成分の95%以上が亜鉛およびスズである[1]〜[5]のいずれかに記載の金属酸化物半導体膜の製造方法。
[7] 溶液が、亜鉛及びスズの金属塩または金属ハロゲン化物を溶媒に溶解してなるものである[1]〜[6]のいずれかに記載の金属酸化物半導体膜の製造方法。
[8] 溶媒が、メタノール、メトキシエタノール、または、水である[1]〜[7]のいずれかに記載の金属酸化物半導体膜の製造方法。
[9] 溶液中の金属成分の濃度が、0.01mol/L〜1.0mol/Lである[1]〜[8]のいずれかに記載の金属酸化物半導体膜の製造方法。
[10] [1]〜[9]のいずれかに記載の金属酸化物半導体膜の製造方法を用いて作製された金属酸化物半導体膜。
[11] 二次イオン質量分析法による膜中の炭素濃度が1×1019atoms/cm3以上1×1020atoms/cm3以下である[10]に記載の金属酸化物半導体膜。
[12] 二次イオン質量分析法による膜中の水素濃度が2×1022atoms/cm3以上4×1022atoms/cm3以下である[10]または[11]に記載の金属酸化物半導体膜。
[13] [10]〜[12]のいずれかに記載の金属酸化物半導体膜を含む活性層と、ソース電極と、ドレイン電極と、ゲート絶縁膜と、ゲート電極とを有する薄膜トランジスタ。
[14] [13]に記載の薄膜トランジスタを備える電子デバイス。[1] A metal oxide semiconductor precursor film forming step of forming a metal oxide semiconductor precursor film by applying a solution containing zinc and tin as a solvent and a metal component on a substrate;
A conversion step of converting the metal oxide semiconductor precursor film into a metal oxide semiconductor film by performing ultraviolet irradiation while the metal oxide semiconductor precursor film is heated,
Metal oxide in which 80% or more of all metal components in the metal oxide semiconductor precursor film are zinc and tin, and the composition ratio of zinc and tin is 0.7 ≦ Sn / (Sn + Zn) ≦ 0.9 A method for manufacturing a semiconductor film.
[2] The method for producing a metal oxide semiconductor film according to [1], wherein a component ratio of indium in the metal oxide semiconductor precursor film is less than 5%.
[3] The method for producing a metal oxide semiconductor film according to [1] or [2], wherein the temperature of the substrate during ultraviolet irradiation is maintained at 250 ° C. or lower in the conversion step.
[4] The metal oxide according to any one of [1] to [3], wherein, in the conversion step, the ultraviolet ray irradiated to the metal oxide semiconductor precursor film has an illuminance with a wavelength of 300 nm or less of 30 mW / cm 2 or more. A method for manufacturing a semiconductor film.
[5] The method for producing a metal oxide semiconductor film according to any one of [1] to [4], wherein the conversion step is performed in an atmosphere containing 1% by volume or more of oxygen.
[6] The method for producing a metal oxide semiconductor film according to any one of [1] to [5], wherein 95% or more of all metal components in the metal oxide semiconductor precursor film are zinc and tin.
[7] The method for producing a metal oxide semiconductor film according to any one of [1] to [6], wherein the solution is obtained by dissolving a metal salt or metal halide of zinc and tin in a solvent.
[8] The method for producing a metal oxide semiconductor film according to any one of [1] to [7], wherein the solvent is methanol, methoxyethanol, or water.
[9] The method for producing a metal oxide semiconductor film according to any one of [1] to [8], wherein the concentration of the metal component in the solution is 0.01 mol / L to 1.0 mol / L.
[10] A metal oxide semiconductor film produced using the method for producing a metal oxide semiconductor film according to any one of [1] to [9].
[11] The metal oxide semiconductor film according to [10], wherein the carbon concentration in the film by secondary ion mass spectrometry is 1 × 10 19 atoms / cm 3 or more and 1 × 10 20 atoms / cm 3 or less.
[12] The metal oxide semiconductor according to [10] or [11], wherein the hydrogen concentration in the film by secondary ion mass spectrometry is 2 × 10 22 atoms / cm 3 or more and 4 × 10 22 atoms / cm 3 or less. film.
[13] A thin film transistor having an active layer including the metal oxide semiconductor film according to any one of [10] to [12], a source electrode, a drain electrode, a gate insulating film, and a gate electrode.
[14] An electronic device comprising the thin film transistor according to [13].
以下に説明するように、本発明によれば、レアメタルであるインジウムを含まない安価な材料を用いて、簡便に、低温で、かつ、大気圧下で形成可能で、高い半導体特性を有する酸化物半導体膜を形成することができる金属酸化物半導体膜の製造方法、ならびに、金属酸化物半導体膜、薄膜トランジスタおよび電子デバイスを提供することができる。 As described below, according to the present invention, an oxide having high semiconductor characteristics that can be easily formed at a low temperature and under atmospheric pressure using an inexpensive material that does not contain indium which is a rare metal. A metal oxide semiconductor film manufacturing method capable of forming a semiconductor film, and a metal oxide semiconductor film, a thin film transistor, and an electronic device can be provided.
以下、本発明について詳細に説明する。
以下に記載する構成要件の説明は、本発明の代表的な実施態様に基づいてなされることがあるが、本発明はそのような実施態様に限定されるものではない。
なお、本明細書において、「〜」を用いて表される数値範囲は、「〜」の前後に記載される数値を下限値および上限値として含む範囲を意味する。Hereinafter, the present invention will be described in detail.
The description of the constituent elements described below may be made based on typical embodiments of the present invention, but the present invention is not limited to such embodiments.
In the present specification, a numerical range expressed using “to” means a range including numerical values described before and after “to” as a lower limit value and an upper limit value.
<金属酸化物半導体膜の製造方法>
本発明の金属酸化物半導体膜の製造方法(以下、「本発明の製造方法」ともいう)は、溶媒及び金属成分としてスズを主成分とし、少なくとも亜鉛を含む溶液を基板上に塗布して金属酸化物半導体前駆体膜を形成する金属酸化物半導体前駆体膜形成工程と、金属酸化物半導体前駆体膜を加熱した状態で紫外線照射を行うことにより金属酸化物半導体前駆体膜を金属酸化物半導体膜に転化させる転化工程とを有し、金属酸化物半導体前駆体膜中の全金属成分の80%以上が亜鉛およびスズであり、亜鉛とスズとの組成比が0.7≦Sn/(Sn+Zn)≦0.9であることを特徴とする。<Method for producing metal oxide semiconductor film>
The method for producing a metal oxide semiconductor film of the present invention (hereinafter also referred to as “the method of production of the present invention”) is a method in which a solution containing at least zinc as a solvent and a metal component as a main component and at least zinc is applied onto a substrate. A metal oxide semiconductor precursor film forming step for forming an oxide semiconductor precursor film, and the metal oxide semiconductor precursor film is converted into a metal oxide semiconductor by performing ultraviolet irradiation while the metal oxide semiconductor precursor film is heated. A conversion step of converting into a film, wherein 80% or more of all metal components in the metal oxide semiconductor precursor film are zinc and tin, and the composition ratio of zinc and tin is 0.7 ≦ Sn / (Sn + Zn ) ≦ 0.9.
本発明者らの検討によれば、亜鉛とスズとの組成比を適切に選択することによって紫外線照射処理による金属酸化物半導体膜の特性向上効果を極めて高くすることが可能であることを見出した。
具体的には、亜鉛とスズとの組成比を適切に選択することで、金属酸化物半導体膜の結晶化に伴う粒界形成および表面粗さの増大を抑制し、かつ、キャリア密度を適切な範囲に制御可能となるので、紫外線照射処理による金属酸化物半導体膜の特性向上効果を極めて高くすることができる。
本発明の製造方法を用いることで、レアメタルであるインジウムを含まない材料を用いて、大気圧下、250℃以下の低温プロセスで、高い電子伝達特性を有する金属酸化物半導体膜を得ることができる。According to the study by the present inventors, it has been found that the effect of improving the characteristics of the metal oxide semiconductor film by the ultraviolet irradiation treatment can be made extremely high by appropriately selecting the composition ratio of zinc and tin. .
Specifically, by appropriately selecting the composition ratio of zinc and tin, grain boundary formation and surface roughness increase accompanying crystallization of the metal oxide semiconductor film can be suppressed, and the carrier density can be appropriately set. Since the range can be controlled, the effect of improving the characteristics of the metal oxide semiconductor film by the ultraviolet irradiation treatment can be made extremely high.
By using the manufacturing method of the present invention, a metal oxide semiconductor film having high electron transfer characteristics can be obtained at a low temperature process of 250 ° C. or less under atmospheric pressure using a material that does not contain indium which is a rare metal. .
本発明の製造方法は、大気圧下で金属酸化物半導体膜を製造することができるので、大掛かりな真空装置を用いる必要がない。また、250℃以下の低温プロセスで製造することができるので、耐熱性の低い安価な樹脂基板を用いることができる。レアメタルであるインジウムを含まない安価な材料を用いることができる。従って、金属酸化物半導体膜の作製コストを大幅に低減することができる。
また、耐熱性の低い安価な樹脂基板に適用できることからフレキシブルディスプレイ等のフレキシブル電子デバイスを安価に作製することが可能となる。Since the manufacturing method of the present invention can manufacture a metal oxide semiconductor film under atmospheric pressure, it is not necessary to use a large vacuum apparatus. In addition, since it can be manufactured by a low-temperature process of 250 ° C. or less, an inexpensive resin substrate with low heat resistance can be used. An inexpensive material that does not contain indium, which is a rare metal, can be used. Accordingly, the manufacturing cost of the metal oxide semiconductor film can be significantly reduced.
In addition, since it can be applied to an inexpensive resin substrate having low heat resistance, a flexible electronic device such as a flexible display can be manufactured at low cost.
以下、各工程について具体的に説明する。 Hereinafter, each step will be specifically described.
[金属酸化物半導体前駆体膜形成工程]
まず、溶媒及び金属成分としてスズを主成分として少なくとも亜鉛を含む溶液(金属酸化物半導体前駆体溶液)を用意し、基板上に塗布して金属酸化物半導体前駆体膜を形成する。
ここで、本発明においては、金属酸化物半導体前駆体膜形成工程で形成される金属酸化物半導体前駆体膜は、膜中の全金属成分の80%以上が亜鉛およびスズであり、亜鉛とスズとの組成比が、0.7≦Sn/(Sn+Zn)≦0.9である。[Metal oxide semiconductor precursor film forming step]
First, a solution (metal oxide semiconductor precursor solution) containing tin as a main component and at least zinc as a solvent and a metal component is prepared and applied onto a substrate to form a metal oxide semiconductor precursor film.
Here, in the present invention, in the metal oxide semiconductor precursor film formed in the metal oxide semiconductor precursor film forming step, 80% or more of all metal components in the film are zinc and tin, and zinc and tin The composition ratio is 0.7 ≦ Sn / (Sn + Zn) ≦ 0.9.
(基板)
基板の形状、構造、大きさ等については特に制限はなく、目的に応じて適宜選択することができる。基板の構造は単層構造であってもよいし、積層構造であってもよい。(substrate)
There is no restriction | limiting in particular about the shape of a board | substrate, a structure, a magnitude | size, It can select suitably according to the objective. The structure of the substrate may be a single layer structure or a laminated structure.
基板としては特に限定はなく、例えば、YSZ(Yttria−Stabilized Zirconia;イットリウム安定化ジルコニウム)、ガラス等の無機基板、樹脂基板、あるいは、その複合材料等を用いることができる。中でも軽量である点、可撓性を有する点から樹脂基板、その複合材料が好ましい。具体的には、ポリブチレンテレフタレート、ポリエチレンテレフタレート、ポリエチレンナフタレート、ポリブチレンナフタレート、ポリスチレン、ポリカーボネート、ポリスルホン、ポリエーテルスルホン、ポリアリレート、アリルジグリコールカーボネート、ポリアミド、ポリイミド、ポリアミドイミド、ポリエーテルイミド、ポリベンズアゾール、ポリフェニレンサルファイド、ポリシクロオレフィン、ノルボルネン樹脂、ポリクロロトリフルオロエチレン等のフッ素樹脂、液晶ポリマー、アクリル樹脂、エポキシ樹脂、シリコーン樹脂、アイオノマー樹脂、シアネート樹脂、架橋フマル酸ジエステル、環状ポリオレフィン、芳香族エーテル、マレイミドーオレフィン、セルロース、エピスルフィド化合物等の合成樹脂基板、酸化珪素粒子との複合プラスチック材料、金属ナノ粒子、無機酸化物ナノ粒子、無機窒化物ナノ粒子等との複合プラスチック材料、カーボン繊維、カーボンナノチューブとの複合プラスチック材料、ガラスフレーク、ガラスファイバー、ガラスビーズとの複合プラスチック材料、粘土鉱物や雲母派生結晶構造を有する粒子との複合プラスチック材料、薄いガラスと上記単独有機材料との間に少なくとも1回の接合界面を有する積層プラスチック材料、無機層と有機層を交互に積層することで、少なくとも1回以上の接合界面を有するバリア性能を有する複合材料、ステンレス基板或いはステンレスと異種金属を積層した金属多層基板、アルミニウム基板或いは表面に酸化処理(例えば陽極酸化処理)を施すことで表面の絶縁性を向上させた酸化皮膜付きのアルミニウム基板等を用いることが出来る。又、樹脂基板は耐熱性、寸法安定性、耐溶剤性、電気絶縁性、加工性、低通気性、又は低吸湿性等に優れていることが好ましい。上記樹脂基板は、水分や酸素の透過を防止するためのガスバリア層や、樹脂基板の平坦性や下部電極との密着性を向上するためのアンダーコート層等を備えていてもよい。 The substrate is not particularly limited, and for example, an inorganic substrate such as YSZ (Yttria-Stabilized Zirconia), glass, a resin substrate, a composite material thereof, or the like can be used. Among these, a resin substrate and a composite material thereof are preferable in terms of light weight and flexibility. Specifically, polybutylene terephthalate, polyethylene terephthalate, polyethylene naphthalate, polybutylene naphthalate, polystyrene, polycarbonate, polysulfone, polyethersulfone, polyarylate, allyl diglycol carbonate, polyamide, polyimide, polyamideimide, polyetherimide, Fluorine resin such as polybenzazole, polyphenylene sulfide, polycycloolefin, norbornene resin, polychlorotrifluoroethylene, liquid crystal polymer, acrylic resin, epoxy resin, silicone resin, ionomer resin, cyanate resin, crosslinked fumaric acid diester, cyclic polyolefin, Synthetic resin substrates such as aromatic ether, maleimide-olefin, cellulose, episulfide compounds, silicon oxide Composite plastic material with metal, metal nanoparticle, inorganic oxide nanoparticle, composite plastic material with inorganic nitride nanoparticle, etc., carbon fiber, composite plastic material with carbon nanotube, glass flake, glass fiber, glass bead Composite plastic materials, composite plastic materials with clay minerals and particles with mica-derived crystal structure, laminated plastic materials with at least one bonding interface between thin glass and the above single organic material, alternating inorganic and organic layers By laminating, an oxidation treatment (for example, anodizing treatment) is performed on a composite material having a barrier performance having at least one bonding interface, a stainless steel substrate, a metal multilayer substrate in which stainless steel and a dissimilar metal are laminated, an aluminum substrate, or the surface. Oxide film with improved surface insulation It can be used an aluminum substrate or the like. The resin substrate is preferably excellent in heat resistance, dimensional stability, solvent resistance, electrical insulation, workability, low air permeability, low moisture absorption, and the like. The resin substrate may include a gas barrier layer for preventing permeation of moisture and oxygen, an undercoat layer for improving the flatness of the resin substrate and adhesion to the lower electrode, and the like.
また、本発明における基板の厚みに特に制限はないが、50μm以上500μm以下であることが好ましい。基板の厚みが50μm以上であると、基板自体の平坦性がより向上する。又、基板の厚みが500μm以下であると、基板自体の可撓性がより向上し、フレキシブルデバイス用基板としての使用がより容易となる。 Moreover, there is no restriction | limiting in particular in the thickness of the board | substrate in this invention, It is preferable that they are 50 micrometers or more and 500 micrometers or less. When the thickness of the substrate is 50 μm or more, the flatness of the substrate itself is further improved. Further, when the thickness of the substrate is 500 μm or less, the flexibility of the substrate itself is further improved, and the use as a substrate for a flexible device becomes easier.
(溶液)
上記金属酸化物半導体前駆体溶液は、溶媒及び金属成分としてスズを主成分とし、少なくとも亜鉛を含む。ここで、本発明における主成分とは、上記溶液中の全金属成分の50%以上をスズで占めることを意味し、必要に応じて少量の他の金属成分を含んでいてもよい。
また、形成される金属酸化物半導体膜の半導体特性の観点から、亜鉛およびスズの全金属成分中の成分比は、90%以上が好ましく、95%以上がより好ましい。
また、上記溶液は、5%未満の少量のインジウムを含んでいてもよく、1%以下がより好ましい。
ここで、上記溶液中の金属成分は、基本的に、金属酸化物半導体前駆体膜中の金属成分と同じである。従って、本発明においては、上記溶液の亜鉛とスズとの組成比は、0.7≦Sn/(Sn+Zn)≦0.9である。(solution)
The metal oxide semiconductor precursor solution contains tin as a main component as a solvent and a metal component, and contains at least zinc. Here, the main component in the present invention means that 50% or more of the total metal components in the solution are occupied by tin, and may contain a small amount of other metal components as necessary.
In addition, from the viewpoint of semiconductor characteristics of the metal oxide semiconductor film to be formed, the component ratio in the total metal components of zinc and tin is preferably 90% or more, and more preferably 95% or more.
Moreover, the said solution may contain a small amount of indium of less than 5%, and 1% or less is more preferable.
Here, the metal component in the solution is basically the same as the metal component in the metal oxide semiconductor precursor film. Therefore, in the present invention, the composition ratio of zinc and tin in the above solution is 0.7 ≦ Sn / (Sn + Zn) ≦ 0.9.
本発明における溶液は、原料となる溶質を、溶液が所望の濃度となるように秤量し、溶媒中で攪拌、溶解させて得られる。攪拌を行う時間や攪拌中の溶液の温度は溶質が十分に溶解されれば特に制限はない。 The solution in the present invention is obtained by weighing a solute as a raw material so that the solution has a desired concentration, and stirring and dissolving in a solvent. The time for stirring and the temperature of the solution during stirring are not particularly limited as long as the solute is sufficiently dissolved.
上記金属酸化物半導体前駆体溶液は、亜鉛及びスズを含有する化合物を溶解して得られ、亜鉛及びスズの金属塩又は金属ハロゲン化物を用いることが好ましい。金属塩又は金属ハロゲン化物を用いることで、容易に様々な溶媒に溶質を溶かすことが可能となり、かつ、高い電子伝達特性が得られやすい。金属塩としては、硫酸塩、燐酸塩、炭酸塩、酢酸塩、蓚酸塩等、金属ハロゲン化物としては塩化物、ヨウ化物、臭化物等が挙げられる。
なお、本発明における溶液は、溶液中に金属酸化物粒子等の不溶物を含まない溶液を用いることが好ましい。溶液中に金属酸化物粒子等の不溶物を含まない溶液を用いることで金属酸化物半導体膜を形成した際の表面粗さが小さくなり、面内均一性に優れた金属酸化物半導体膜を形成することが出来る。The metal oxide semiconductor precursor solution is obtained by dissolving a compound containing zinc and tin, and it is preferable to use a metal salt or metal halide of zinc and tin. By using a metal salt or a metal halide, it is possible to easily dissolve the solute in various solvents, and it is easy to obtain high electron transfer characteristics. Examples of the metal salt include sulfate, phosphate, carbonate, acetate, oxalate, and examples of the metal halide include chloride, iodide, bromide and the like.
In addition, it is preferable to use the solution which does not contain insoluble matters, such as a metal oxide particle, in the solution in this invention. By using a solution that does not contain insoluble materials such as metal oxide particles in the solution, the surface roughness when forming the metal oxide semiconductor film is reduced, and a metal oxide semiconductor film with excellent in-plane uniformity is formed. I can do it.
本発明における溶液に用いる溶媒は、溶質として用いる亜鉛及びスズを含有する化合物が溶解するものであれば特に制限されるところではなく、例えば、水、アルコール溶媒(メタノール、エタノール、プロパノール、エチレングリコール等)、アミド溶媒(ホルムアミド、N,N−ジメチルホルムアミド等)、ケトン溶媒(アセトン、N−メチルピロリドン、スルホラン、N,N−ジメチルイミダゾリジノン等)、エーテル溶媒(テトラヒドロフラン、メトキシエタノール等)、ニトリル溶媒(アセトニトリル等)、複素環式化合物(ピリジン、チアゾール等)、その他上記以外のヘテロ原子含有溶媒等が挙げられる。特に溶解性、塗れ性の観点からメタノール、メトキシエタノール、又は水を用いることが好ましい。 The solvent used in the solution in the present invention is not particularly limited as long as the compound containing zinc and tin used as a solute dissolves. For example, water, alcohol solvent (methanol, ethanol, propanol, ethylene glycol, etc.) ), Amide solvents (formamide, N, N-dimethylformamide, etc.), ketone solvents (acetone, N-methylpyrrolidone, sulfolane, N, N-dimethylimidazolidinone, etc.), ether solvents (tetrahydrofuran, methoxyethanol, etc.), nitriles Examples include solvents (acetonitrile, etc.), heterocyclic compounds (pyridine, thiazole, etc.), and other heteroatom-containing solvents other than those mentioned above. In particular, it is preferable to use methanol, methoxyethanol, or water from the viewpoints of solubility and paintability.
上記金属酸化物半導体前駆体溶液中の金属成分の濃度は、粘度や得たい膜厚に応じて任意に選択することが出来るが、薄膜の平坦性及び生産性の観点から0.01mol/L以上1.0mol/L以下であることが好ましい。 The concentration of the metal component in the metal oxide semiconductor precursor solution can be arbitrarily selected according to the viscosity and the desired film thickness, but is 0.01 mol / L or more from the viewpoint of the flatness and productivity of the thin film. It is preferable that it is 1.0 mol / L or less.
(塗布)
上記金属酸化物半導体膜前駆体溶液を基板上に塗布する方法としては、例えば、スプレーコート法、スピンコート法、ブレードコート法、ディップコート法、キャスト法、ロールコート法、バーコート法、ダイコート法、ミスト法、インクジェット法、ディスペンサー法、スクリーン印刷法、凸版印刷法、及び凹版印刷法等が挙げられる。特に、微細パターンを容易に形成する観点から、インクジェット法、ディスペンサー法、凸版印刷法、及び凹版印刷法から選択される少なくとも一種の塗布法を用いることが好ましい。(Application)
Examples of the method for applying the metal oxide semiconductor film precursor solution onto the substrate include spray coating, spin coating, blade coating, dip coating, casting, roll coating, bar coating, and die coating. Mist method, ink jet method, dispenser method, screen printing method, relief printing method, intaglio printing method and the like. In particular, from the viewpoint of easily forming a fine pattern, it is preferable to use at least one coating method selected from an inkjet method, a dispenser method, a relief printing method, and an intaglio printing method.
(乾燥)
上記金属酸化物半導体前駆体溶液を基板上に塗布した後、自然乾燥して金属酸化物半導体前駆体膜としてもよいが、加熱処理によって塗布膜を乾燥させ、金属酸化物半導体前駆体膜を得ることが好ましい。乾燥によって、塗布膜の流動性を低減させ、最終的に得られる金属酸化物半導体膜の平坦性を向上させることが出来る。又、適切な乾燥温度(35℃以上100℃以下)を選択することにより、最終的に、より電子伝達特性の高い金属酸化物半導体膜を得られやすい。加熱処理の方法は特に限定されず、ホットプレート加熱、電気炉加熱、赤外線加熱、マイクロ波加熱等から選択することができる。(Dry)
After the metal oxide semiconductor precursor solution is applied on the substrate, it may be naturally dried to form a metal oxide semiconductor precursor film. However, the coating film is dried by heat treatment to obtain a metal oxide semiconductor precursor film. It is preferable. By drying, the fluidity of the coating film can be reduced, and the flatness of the finally obtained metal oxide semiconductor film can be improved. In addition, by selecting an appropriate drying temperature (35 ° C. or more and 100 ° C. or less), it is easy to finally obtain a metal oxide semiconductor film having higher electron transfer characteristics. The method for the heat treatment is not particularly limited, and can be selected from hot plate heating, electric furnace heating, infrared heating, microwave heating, and the like.
上記乾燥は膜の平坦性を均一に保つ観点から、基板上に溶液を塗布後、5分以内に開始することが好ましい。
また、乾燥を行う時間には特に制限はないが、膜の均一性、生産性の観点から15秒以上10分以下であることが好ましい。
また、乾燥における雰囲気には特に制限はないが、製造コスト等の観点から大気圧下、大気中で行うことが好ましい。The drying is preferably started within 5 minutes after applying the solution on the substrate from the viewpoint of keeping the flatness of the film uniform.
The drying time is not particularly limited, but is preferably 15 seconds or longer and 10 minutes or shorter from the viewpoint of film uniformity and productivity.
Moreover, there is no restriction | limiting in particular in the atmosphere in drying, but it is preferable to carry out in air | atmosphere under atmospheric pressure from viewpoints, such as manufacturing cost.
[転化工程]
次いで、上記金属酸化物半導体前駆体膜を加熱した状態で紫外線照射処理を行うことで金属酸化物半導体前駆体膜を金属酸化物半導体膜へと転化する。
ここで、上述のとおり、金属酸化物半導体前駆体膜は、膜中の全金属成分の80%以上が亜鉛およびスズであり、亜鉛とスズとの組成比が、0.7≦Sn/(Sn+Zn)≦0.9であるので、大気圧下で、かつ、250℃以下の低温での紫外線照射処理で、金属酸化物半導体膜の特性向上効果を極めて高くすることが可能である。[Conversion process]
Next, the metal oxide semiconductor precursor film is converted into a metal oxide semiconductor film by performing an ultraviolet irradiation treatment in a state where the metal oxide semiconductor precursor film is heated.
Here, as described above, in the metal oxide semiconductor precursor film, 80% or more of all metal components in the film are zinc and tin, and the composition ratio of zinc and tin is 0.7 ≦ Sn / (Sn + Zn). ) ≦ 0.9, the effect of improving the characteristics of the metal oxide semiconductor film can be extremely enhanced by ultraviolet irradiation treatment at atmospheric pressure and at a low temperature of 250 ° C. or lower.
(加熱処理)
上記金属酸化物半導体膜への転化工程における基板温度は250℃以下とすることが好ましく、120℃超とすることが好ましい。転化工程における基板温度を250℃以下とすれば、熱エネルギーの増大を抑制して製造コストを低く抑えることができ、また、耐熱性の低い樹脂基板への適用が容易となる。また、120℃超とすれば、より短時間で高い電子伝達特性の金属酸化物半導体膜を得ることが出来る。
また、製造コストの観点および樹脂基板への適用の観点から、120℃超、200℃以下がより好ましい。
転化工程における基板に対する加熱手段は特に限定されず、ホットプレート加熱、電気炉加熱、赤外線加熱、マイクロ波加熱等から選択すればよい。(Heat treatment)
The substrate temperature in the conversion step into the metal oxide semiconductor film is preferably 250 ° C. or lower, and more preferably higher than 120 ° C. If the substrate temperature in the conversion step is 250 ° C. or less, an increase in thermal energy can be suppressed to reduce the manufacturing cost, and application to a resin substrate with low heat resistance can be facilitated. In addition, when the temperature is higher than 120 ° C., a metal oxide semiconductor film having high electron transfer characteristics can be obtained in a shorter time.
Moreover, from the viewpoint of manufacturing cost and the viewpoint of application to a resin substrate, more than 120 ° C and 200 ° C or less are more preferable.
The heating means for the substrate in the conversion step is not particularly limited, and may be selected from hot plate heating, electric furnace heating, infrared heating, microwave heating, and the like.
(紫外線照射)
転化工程において、上記金属酸化物半導体前駆体膜に照射する紫外線は波長300nm以下の照度が30mW/cm2以上であることが好ましく、50mW/cm2であることがより好ましい。照度を30mW/cm2以上とすることで高い電子伝達特性の金属酸化物半導体膜を得ることが出来る。なお、照度の上限は、装置コストの観点から500mW/cm2以下であることが好ましい。(UV irradiation)
In the conversion step, the ultraviolet ray applied to the metal oxide semiconductor precursor film preferably has an illuminance with a wavelength of 300 nm or less of 30 mW / cm 2 or more, and more preferably 50 mW / cm 2 . By setting the illuminance to 30 mW / cm 2 or more, a metal oxide semiconductor film having high electron transfer characteristics can be obtained. In addition, it is preferable that the upper limit of illumination intensity is 500 mW / cm < 2 > or less from a viewpoint of apparatus cost.
転化工程における紫外線照射は、金属酸化物半導体前駆体膜が金属酸化物半導体膜に転化するまで行えばよい。前駆体膜の組成、加熱温度、紫外線照度等にもよるが、生産性の観点から、紫外線照射時間は、5分以上120分以下であることが好ましい。 The ultraviolet irradiation in the conversion process may be performed until the metal oxide semiconductor precursor film is converted into the metal oxide semiconductor film. Although depending on the composition of the precursor film, the heating temperature, the ultraviolet illuminance, and the like, the ultraviolet irradiation time is preferably 5 minutes or more and 120 minutes or less from the viewpoint of productivity.
また、転化工程は、大気圧下、大気中で行うことができ、酸素を1体積%以上含む雰囲気中で行うことが好ましい。酸素を含む雰囲気中であれば高い電子伝達特性を示す金属酸化物半導体膜が得られやすい。また、生産コストの観点から大気中での処理が好ましい。 The conversion step can be performed in the atmosphere under atmospheric pressure, and is preferably performed in an atmosphere containing 1% by volume or more of oxygen. In an atmosphere containing oxygen, a metal oxide semiconductor film having high electron transfer characteristics can be easily obtained. Moreover, the process in air | atmosphere is preferable from a viewpoint of production cost.
転化工程における加熱処理中の紫外線照射の光源としては、UVランプやUVレーザー等が挙げられるが、大面積に均一に、安価な設備で紫外線照射を行う観点からUVランプが好ましい。UVランプとしては、例えばエキシマランプ、重水素ランプ、低圧水銀ランプ、高圧水銀ランプ、超高圧水銀ランプ、メタルハライドランプ、ヘリウムランプ、カーボンアークランプ、カドミウムランプ、無電極放電ランプ等が挙げられ、特に低圧水銀ランプを用いると容易に金属酸化物半導体前駆体膜から金属酸化物半導体膜への転化を行えることから好ましい。 Examples of the light source for ultraviolet irradiation during the heat treatment in the conversion step include a UV lamp and a UV laser, and a UV lamp is preferable from the viewpoint of performing ultraviolet irradiation with inexpensive equipment uniformly over a large area. Examples of UV lamps include excimer lamps, deuterium lamps, low pressure mercury lamps, high pressure mercury lamps, ultrahigh pressure mercury lamps, metal halide lamps, helium lamps, carbon arc lamps, cadmium lamps, electrodeless discharge lamps, etc. It is preferable to use a mercury lamp because conversion from a metal oxide semiconductor precursor film to a metal oxide semiconductor film can be easily performed.
ここで、転化工程によって形成された金属酸化物半導体膜に含まれる炭素濃度は1×1019atoms/cm3以上1×1020atoms/cm3以下であることが好ましく、水素濃度が2×1022atoms/cm3以上4×1022atoms/cm3以下であることが好ましい。上記濃度範囲であれば高い電子伝達特性が得られやすい。
なお、金属酸化物半導体膜中の水素濃度および炭素濃度は、二次イオン質量分析法(SIMS(Secondary Ion Mass Spectroscopy))により測定した値である。SIMSは対象物を構成する元素を非常に高感度で検出することができる分析法として知られており、分析対象物にビーム状のイオン(一次イオン)を衝突させ、衝突により対象物を構成する物質をイオン化(二次イオン)させる。この二次イオンを質量分析することで構成元素とその量を検出するものである。Here, the carbon concentration contained in the metal oxide semiconductor film formed by the conversion step is preferably 1 × 10 19 atoms / cm 3 or more and 1 × 10 20 atoms / cm 3 or less, and the hydrogen concentration is 2 × 10. It is preferably 22 atoms / cm 3 or more and 4 × 10 22 atoms / cm 3 or less. When the concentration is within the above range, high electron transfer characteristics are easily obtained.
Note that the hydrogen concentration and the carbon concentration in the metal oxide semiconductor film are values measured by secondary ion mass spectrometry (SIMS (Secondary Ion Mass Spectroscopy)). SIMS is known as an analytical method that can detect an element constituting an object with very high sensitivity, and collides beam-like ions (primary ions) with the object to be analyzed, and forms the object by collision. Ions are ionized (secondary ions). A constituent element and its amount are detected by mass analysis of the secondary ions.
また、本発明の製造方法で作製された金属酸化物半導体膜中の金属成分は、基本的に、金属酸化物半導体前駆体膜中の金属成分と同じである。従って、金属酸化物半導体膜中の全金属成分の80%以上が亜鉛およびスズであり、亜鉛とスズとの組成比は、0.7≦Sn/(Sn+Zn)≦0.9である。
金属酸化物半導体膜中の全金属成分に対する亜鉛およびスズの比率、ならびに、亜鉛とスズとの組成比は、XPS測定(X線光電子分光測定)により、金属酸化物半導体膜の表面における亜鉛、スズ等の金属の原子数を測定し、亜鉛およびスズの比率、亜鉛とスズとの組成比として算出することができる。あるいは、金属酸化物半導体膜を切片化加工し、膜の断面TEM(透過電子顕微鏡)のEDX測定(エネルギー分散型X線分光法)によって、亜鉛とスズの比率、組成比を算出することができる。Moreover, the metal component in the metal oxide semiconductor film produced by the production method of the present invention is basically the same as the metal component in the metal oxide semiconductor precursor film. Therefore, 80% or more of all metal components in the metal oxide semiconductor film are zinc and tin, and the composition ratio of zinc and tin is 0.7 ≦ Sn / (Sn + Zn) ≦ 0.9.
The ratio of zinc and tin to the total metal components in the metal oxide semiconductor film, and the composition ratio of zinc and tin are determined by XPS measurement (X-ray photoelectron spectroscopy) on the surface of the metal oxide semiconductor film. The number of atoms of such metals can be measured and calculated as the ratio of zinc and tin, and the composition ratio of zinc and tin. Alternatively, the metal oxide semiconductor film can be segmented and the ratio of zinc to tin and the composition ratio can be calculated by EDX measurement (energy dispersive X-ray spectroscopy) of a cross-sectional TEM (transmission electron microscope) of the film. .
<薄膜トランジスタ>
本発明の製造方法により作製された金属酸化物半導体膜は高い電子伝達特性を示すことから、薄膜トランジスタ(TFT)の活性層に好適に用いることができる。<Thin film transistor>
Since the metal oxide semiconductor film manufactured by the manufacturing method of the present invention exhibits high electron transfer characteristics, it can be suitably used for an active layer of a thin film transistor (TFT).
以下、本発明の製造方法を用いて作製された金属酸化物半導体膜を薄膜トランジスタの活性層として用いた際の実施形態について説明する。なお、本発明の金属酸化物半導体膜の製造方法及びそれにより製造される金属酸化物半導体膜はTFTの活性層に限定されるものではない。 Hereinafter, an embodiment in which a metal oxide semiconductor film manufactured using the manufacturing method of the present invention is used as an active layer of a thin film transistor will be described. In addition, the manufacturing method of the metal oxide semiconductor film of this invention and the metal oxide semiconductor film manufactured by it are not limited to the active layer of TFT.
本発明に係るTFTの素子構造は特に限定されず、ゲート電極の位置に基づいた、いわゆる逆スタガ構造(ボトムゲート型とも呼ばれる)及びスタガ構造(トップゲート型とも呼ばれる)のいずれの態様であってもよい。又、活性層とソース電極及びドレイン電極(適宜、「ソース・ドレイン電極」という)との接触部分に基づき、いわゆるトップコンタクト型、ボトムコンタクト型のいずれの態様であってもよい。 The element structure of the TFT according to the present invention is not particularly limited, and is either a so-called reverse stagger structure (also referred to as a bottom gate type) or a stagger structure (also referred to as a top gate type) based on the position of the gate electrode. Also good. In addition, based on the contact portion between the active layer and the source and drain electrodes (referred to as “source / drain electrodes” as appropriate), either a so-called top contact type or bottom contact type may be used.
トップゲート型とは、TFTが形成されている基板を最下層としたときに、ゲート絶縁膜の上側にゲート電極が配置され、ゲート絶縁膜の下側に活性層が形成された形態であり、ボトムゲート型とは、ゲート絶縁膜の下側にゲート電極が配置され、ゲート絶縁膜の上側に活性層が形成された形態である。また、ボトムコンタクト型とは、ソース・ドレイン電極が活性層よりも先に形成されて活性層の下面がソース・ドレイン電極に接触する形態であり、トップコンタクト型とは、活性層がソース・ドレイン電極よりも先に形成されて活性層の上面がソース・ドレイン電極に接触する形態である。 The top gate type is a form in which a gate electrode is disposed on the upper side of the gate insulating film and an active layer is formed on the lower side of the gate insulating film when the substrate on which the TFT is formed is the lowermost layer. The bottom gate type is a form in which a gate electrode is disposed below the gate insulating film and an active layer is formed above the gate insulating film. The bottom contact type is a mode in which the source / drain electrodes are formed before the active layer and the lower surface of the active layer is in contact with the source / drain electrodes. The top contact type is the type in which the active layer is the source / drain. In this embodiment, the upper surface of the active layer is in contact with the source / drain electrodes.
図1は、トップゲート構造でトップコンタクト型の本発明に係るTFTの一例を示す模式図である。図1に示すTFT10では、基板12の一方の主面上に活性層14として上述の酸化物半導体膜が積層されている。そして、この活性層14上にソース電極16及びドレイン電極18が互いに離間して設置され、更にこれらの上にゲート絶縁膜20と、ゲート電極22とが順に積層されている。 FIG. 1 is a schematic diagram showing an example of a top contact type TFT according to the present invention having a top gate structure. In the TFT 10 shown in FIG. 1, the above-described oxide semiconductor film is stacked as an active layer 14 on one main surface of the substrate 12. A source electrode 16 and a drain electrode 18 are disposed on the active layer 14 so as to be spaced apart from each other, and a gate insulating film 20 and a gate electrode 22 are sequentially stacked thereon.
図2は、トップゲート構造でボトムコンタクト型の本発明に係るTFTの一例を示す模式図である。図2に示すTFT30では、基板12の一方の主面上にソース電極16及びドレイン電極18が互いに離間して設置されている。そして、活性層14として上述の酸化物半導体膜と、ゲート絶縁膜20と、ゲート電極22と、が順に積層されている。 FIG. 2 is a schematic view showing an example of a bottom contact type TFT according to the present invention having a top gate structure. In the TFT 30 shown in FIG. 2, the source electrode 16 and the drain electrode 18 are disposed on one main surface of the substrate 12 so as to be separated from each other. Then, the above-described oxide semiconductor film, the gate insulating film 20, and the gate electrode 22 are sequentially stacked as the active layer.
図3は、ボトムゲート構造でトップコンタクト型の本発明に係るTFTの一例を示す模式図である。図3に示すTFT40では、基板12の一方の主面上にゲート電極22と、ゲート絶縁膜20と、活性層14として上述の酸化物半導体膜と、が順に積層されている。そして、この活性層14の表面上にソース電極16及びドレイン電極18が互いに離間して設置されている。 FIG. 3 is a schematic diagram showing an example of a top contact type TFT according to the present invention having a bottom gate structure. In the TFT 40 illustrated in FIG. 3, the gate electrode 22, the gate insulating film 20, and the above-described oxide semiconductor film as the active layer 14 are sequentially stacked on one main surface of the substrate 12. A source electrode 16 and a drain electrode 18 are spaced apart from each other on the surface of the active layer 14.
図4は、ボトムゲート構造でボトムコンタクト型の本発明に係るTFTの一例を示す模式図である。図4に示すTFT50では、基板12の一方の主面上にゲート電極22と、ゲート絶縁膜20と、が順に積層されている。そして、このゲート絶縁膜20の表面上にソース電極16及びドレイン電極18が互いに離間して設置され、更にこれらの上に、活性層14として上述の酸化物半導体膜が積層されている。 FIG. 4 is a schematic view showing an example of a bottom contact type TFT according to the present invention having a bottom gate structure. In the TFT 50 shown in FIG. 4, the gate electrode 22 and the gate insulating film 20 are sequentially stacked on one main surface of the substrate 12. A source electrode 16 and a drain electrode 18 are disposed on the surface of the gate insulating film 20 so as to be spaced apart from each other, and the above-described oxide semiconductor film is stacked thereon as the active layer 14.
以下の実施形態としては図1に示すトップゲート型の薄膜トランジスタ10について主に説明するが、本発明の薄膜トランジスタはトップゲート型に限定されることなく、ボトムゲート型の薄膜トランジスタであってもよい。 In the following embodiment, the top gate type thin film transistor 10 shown in FIG. 1 will be mainly described. However, the thin film transistor of the present invention is not limited to the top gate type and may be a bottom gate type thin film transistor.
(活性層)
本実施形態の薄膜トランジスタ10を製造する場合、まず基板12上に上述した金属酸化物半導体前駆体膜形成工程及び転化工程を経て金属酸化物半導体膜を形成し、上記金属酸化物半導体膜を活性層の形状にパターンニングする。パターンニングは上述したインクジェット法、ディスペンサー法、凸版印刷法、及び凹版印刷法のいずれかによって予め活性層のパターンを有する金属酸化物半導体前駆体膜を形成して金属酸化物半導体膜に転化することが好ましい。(Active layer)
When manufacturing the thin film transistor 10 of the present embodiment, first, the metal oxide semiconductor film is formed on the substrate 12 through the above-described metal oxide semiconductor precursor film forming step and conversion step, and the metal oxide semiconductor film is used as an active layer. Pattern to the shape. For patterning, a metal oxide semiconductor precursor film having an active layer pattern is formed in advance by any of the above-described inkjet method, dispenser method, letterpress printing method, and intaglio printing method, and converted to a metal oxide semiconductor film. Is preferred.
活性層14の厚みは、平坦性及び膜形成に要する時間の観点から5nm以上50nm以下であることが好ましい。 The thickness of the active layer 14 is preferably 5 nm or more and 50 nm or less from the viewpoint of flatness and time required for film formation.
また、活性層14上にはソース・ドレイン電極16、18のエッチング時に活性層14を保護するための保護膜(図示せず)を形成することが好ましい。保護膜は成膜方法に特に限定はなく、金属酸化物半導体膜と連続で成膜してもよいし、金属酸化物半導体膜のパターンニング後に形成してもよい。また、保護膜としては金属酸化物層であってもよく、樹脂のような有機材料であってもよい。また、保護層はソース・ドレイン電極形成後に除去しても構わない。 A protective film (not shown) for protecting the active layer 14 is preferably formed on the active layer 14 when the source / drain electrodes 16 and 18 are etched. There is no particular limitation on the protective film formation method, and the protective film may be formed continuously with the metal oxide semiconductor film, or may be formed after patterning of the metal oxide semiconductor film. The protective film may be a metal oxide layer or an organic material such as a resin. The protective layer may be removed after forming the source / drain electrodes.
(ソース・ドレイン電極)
上記活性層14上にソース・ドレイン電極16、18を形成する。ソース・ドレイン電極はそれぞれ電極として機能するように高い導電性を有するものを用い、Al,Mo,Cr,Ta,Ti,Au,Ag等の金属、Al−Nd、Ag合金、酸化錫、酸化亜鉛、酸化インジウム、酸化インジウム錫(ITO)、酸化亜鉛インジウム(IZO)、In−Ga−Zn−O等の金属酸化物導電体薄膜等を用いて形成することが出来る。(Source / drain electrodes)
Source / drain electrodes 16 and 18 are formed on the active layer 14. The source / drain electrodes are made of high conductivity so as to function as electrodes, respectively, and metals such as Al, Mo, Cr, Ta, Ti, Au, Ag, Al—Nd, Ag alloy, tin oxide, zinc oxide , Indium oxide, indium tin oxide (ITO), indium zinc oxide (IZO), metal oxide conductor thin films such as In—Ga—Zn—O, and the like can be used.
ソース・ドレイン電極16、18の形成は、例えば印刷方式、コーティング方式等の湿式方式、真空蒸着法、スパッタリング法、イオンプレーティング法等の物理的方式、CVD、プラズマCVD法等の化学的方式等の中から使用する材料との適性を考慮して適宜選択した方法に従って成膜すればよい。 The source / drain electrodes 16 and 18 are formed by, for example, a wet method such as a printing method or a coating method, a physical method such as a vacuum deposition method, a sputtering method, or an ion plating method, or a chemical method such as CVD or plasma CVD method. The film may be formed according to a method appropriately selected in consideration of suitability with the material to be used.
各電極の膜厚は成膜性、エッチングやリフトオフ法によるパターニング性、導電性等を考慮すると、10nm以上1000nm以下とすることが好ましく、50nm以上100nm以下とすることがより好ましい。 The film thickness of each electrode is preferably 10 nm or more and 1000 nm or less, and more preferably 50 nm or more and 100 nm or less in consideration of film formability, patterning properties by etching or lift-off methods, conductivity, and the like.
ソース・ドレイン電極16、18は、エッチング又はリフトオフ法により所定の形状にパターンニングして形成してもよく、インクジェット法等により直接パターン形成してもよい。この際、ソース・ドレイン電極16、18の全ての層及びこれらの電極に接続する配線を同時にパターンニングすることが好ましい。 The source / drain electrodes 16 and 18 may be formed by patterning into a predetermined shape by etching or a lift-off method, or may be directly formed by an inkjet method or the like. At this time, it is preferable to pattern all layers of the source / drain electrodes 16 and 18 and wirings connected to these electrodes simultaneously.
(ゲート絶縁膜)
ソース・ドレイン電極16、18及び配線を形成した後、ゲート絶縁膜20を形成する。ゲート絶縁膜20は高い絶縁性を有するものが好ましく、例えばSiO2、SiNx、SiON、Al2O3,Y2O3,Ta2O5,HfO2等の絶縁膜、又はこれらの化合物を少なくとも二つ以上含む絶縁膜としてもよく、単層構造であっても積層構造であってもよい。
ゲート絶縁膜20は、印刷方式、コーティング方式等の湿式方式、真空蒸着法、スパッタリング法、イオンプレーティング法等の物理的方式、CVD、プラズマCVD法等の化学的方式等の中から使用する材料との適性を考慮して適宜選択した方法に従って成膜することができる。(Gate insulation film)
After forming the source / drain electrodes 16 and 18 and the wiring, the gate insulating film 20 is formed. The gate insulating film 20 preferably has a high insulating property. For example, an insulating film such as SiO 2 , SiNx, SiON, Al 2 O 3 , Y 2 O 3 , Ta 2 O 5 , HfO 2 , or a compound thereof is at least used. It may be an insulating film including two or more, and may have a single layer structure or a laminated structure.
The gate insulating film 20 is a material used from a wet method such as a printing method or a coating method, a physical method such as a vacuum deposition method, a sputtering method or an ion plating method, or a chemical method such as CVD or plasma CVD method. The film can be formed according to a method appropriately selected in consideration of the suitability of
なお、ゲート絶縁膜20はリーク電流の低下及び電圧耐性の向上のための厚みを有する必要がある一方、ゲート絶縁膜20の厚みが大きすぎると駆動電圧の上昇を招いてしまう。ゲート絶縁膜20の材質にもよるが、ゲート絶縁膜20の厚みは10nm以上10μm以下が好ましく、50nm以上1000nm以下がより好ましく、100nm以上400nm以下が特に好ましい。 Note that the gate insulating film 20 needs to have a thickness for reducing the leakage current and improving the voltage resistance. On the other hand, if the gate insulating film 20 is too thick, the driving voltage is increased. Although depending on the material of the gate insulating film 20, the thickness of the gate insulating film 20 is preferably 10 nm to 10 μm, more preferably 50 nm to 1000 nm, and particularly preferably 100 nm to 400 nm.
(ゲート電極)
ゲート絶縁膜20を形成した後、ゲート電極22を形成する。ゲート電極22は高い導電性を有するものを用い、例えばAl,Mo,Cr,Ta,Ti,Au,Ag等の金属、Al−Nd,Ag合金、酸化錫、酸化亜鉛、酸化インジウム、酸化インジウム錫(ITO)、酸化亜鉛インジウム(IZO)、IGZO等の金属酸化物導電膜等を用いて形成することができる。ゲート電極22としてはこれらの導電膜を単層構造又は2層以上の積層構造として用いることが出来る。(Gate electrode)
After forming the gate insulating film 20, a gate electrode 22 is formed. The gate electrode 22 is made of a material having high conductivity, for example, metal such as Al, Mo, Cr, Ta, Ti, Au, Ag, Al—Nd, Ag alloy, tin oxide, zinc oxide, indium oxide, indium tin oxide. It can be formed using a metal oxide conductive film such as (ITO), zinc indium oxide (IZO), or IGZO. As the gate electrode 22, these conductive films can be used as a single layer structure or a stacked structure of two or more layers.
ゲート電極22は、例えば印刷方式、コーティング方式等の湿式方式、真空蒸着法、スパッタリング法、イオンプレーティング法等の物理的方式、CVD、プラズマCVD法等の化学的方式等の中から使用する材料との適性を考慮して適宜選択した方法に従って成膜する。
ゲート電極22の膜厚は成膜性、エッチングやリフトオフ法によるパターンニング性、導電性等を考慮すると、10nm以上1000nm以下とすることが好ましく、50nm以上200nm以下とすることがより好ましい。
成膜後、エッチング又はリフトオフ法により所定の形状にパターンニングして、ゲート電極22を形成してもよく、インクジェット法等により直接パターン形成してもよい。この際、ゲート電極22及びゲート電極22に接続される配線を同時にパターンニングすることが好ましい。The gate electrode 22 is a material used from, for example, a wet method such as a printing method or a coating method, a physical method such as a vacuum deposition method, a sputtering method, or an ion plating method, or a chemical method such as CVD or plasma CVD method. The film is formed according to a method appropriately selected in consideration of the suitability of
The film thickness of the gate electrode 22 is preferably 10 nm or more and 1000 nm or less, and more preferably 50 nm or more and 200 nm or less in consideration of film forming properties, patterning properties by etching or lift-off methods, conductivity, and the like.
After the film formation, the gate electrode 22 may be formed by patterning into a predetermined shape by an etching or lift-off method, or the pattern may be directly formed by an inkjet method or the like. At this time, it is preferable to pattern the gate electrode 22 and the wiring connected to the gate electrode 22 simultaneously.
以上で説明した本発明の薄膜トランジスタの用途には特に限定はないが、高い輸送特性を示すことから、例えば電気光学装置(例えば液晶表示装置、有機EL(Electro Luminescence)表示装置、無機EL表示装置等の表示装置等)における駆動素子、耐熱性の低い樹脂基板上に形成したフレキシブルディスプレイに用いる場合に好適である。
更に本発明の薄膜トランジスタは、X線センサー等の各種センサー、MEMS(Micro Electro Mechanical System)等、種々の電子デバイスにおける駆動素子(駆動回路)として、好適に用いられる。The use of the thin film transistor of the present invention described above is not particularly limited, but exhibits high transport characteristics. Therefore, for example, an electro-optical device (for example, a liquid crystal display device, an organic EL (Electro Luminescence) display device, an inorganic EL display device, etc.) In a display device, etc.), and a flexible display formed on a resin substrate having low heat resistance.
Furthermore, the thin film transistor of the present invention is suitably used as a driving element (driving circuit) in various electronic devices such as various sensors such as an X-ray sensor and MEMS (Micro Electro Mechanical System).
<液晶表示装置>
本発明の薄膜トランジスタを用いる液晶表示装置の一例について、図5にその一部分の概略断面図を示し、図6に電気配線の概略構成図を示す。<Liquid crystal display device>
FIG. 5 shows a schematic sectional view of a part of an example of a liquid crystal display device using the thin film transistor of the present invention, and FIG. 6 shows a schematic configuration diagram of electrical wiring.
図5に示すように、本実施形態の液晶表示装置100は、図1に示したトップゲート構造でトップコンタクト型のTFT10と、TFT10のパッシベーション層102で保護されたゲート電極22上に画素下部電極104およびその対向上部電極106で挟まれた液晶層108と、各画素に対応させて異なる色を発色させるためのR(赤)G(緑)B(青)のカラーフィルタ110とを備え、TFT10の基板12側およびRGBカラーフィルタ110上にそれぞれ偏光板112a、112bを備えた構成である。 As shown in FIG. 5, the liquid crystal display device 100 according to the present embodiment includes a top contact type TFT 10 having the top gate structure shown in FIG. 1 and a pixel lower electrode on the gate electrode 22 protected by the passivation layer 102 of the TFT 10. 104 and a liquid crystal layer 108 sandwiched between the counter upper electrode 106 and an R (red) G (green) B (blue) color filter 110 for developing different colors corresponding to each pixel. The polarizing plate 112a and 112b are provided on the substrate 12 side and the RGB color filter 110, respectively.
また、図6に示すように、本実施形態の液晶表示装置100は、互いに平行な複数のゲート配線113と、該ゲート配線113と交差する、互いに平行なデータ配線114とを備えている。ここでゲート配線113とデータ配線114は電気的に絶縁されている。ゲート配線113とデータ配線114との交差部付近に、TFT10が備えられている。 As shown in FIG. 6, the liquid crystal display device 100 according to the present embodiment includes a plurality of gate lines 113 that are parallel to each other and data lines 114 that are parallel to each other and intersect the gate lines 113. Here, the gate wiring 113 and the data wiring 114 are electrically insulated. The TFT 10 is provided in the vicinity of the intersection between the gate wiring 113 and the data wiring 114.
TFT10のゲート電極22は、ゲート配線113に接続されており、TFT10のソース電極16はデータ配線114に接続されている。また、TFT10のドレイン電極18はゲート絶縁膜20に設けられたコンタクトホール116を介して(コンタクトホール116に導電体が埋め込まれて)画素下部電極104に接続されている。この画素下部電極104は、接地された対向上部電極106とともにキャパシタ118を構成している。 The gate electrode 22 of the TFT 10 is connected to the gate wiring 113, and the source electrode 16 of the TFT 10 is connected to the data wiring 114. The drain electrode 18 of the TFT 10 is connected to the pixel lower electrode 104 through a contact hole 116 provided in the gate insulating film 20 (a conductor is embedded in the contact hole 116). The pixel lower electrode 104 forms a capacitor 118 together with the grounded counter upper electrode 106.
<有機EL表示装置>
本発明の薄膜トランジスタを用いるアクティブマトリックス方式の有機EL表示装置の一例について、図7に一部分の概略断面図を示し、図8に電気配線の概略構成図を示す。<Organic EL display device>
FIG. 7 shows a schematic sectional view of a part of an example of an active matrix organic EL display device using the thin film transistor of the present invention, and FIG. 8 shows a schematic configuration diagram of electric wiring.
本実施形態のアクティブマトリックス方式の有機EL表示装置200は、図1に示したトップゲート構造のTFT10が、パッシベーション層202を備えた基板12上に、駆動用TFT10aおよびスイッチング用TFT10bとして備えられ、TFT10a,10b上に下部電極208および上部電極210に挟まれた有機発光層212からなる有機EL発光素子214を備え、上面もパッシベーション層216により保護された構成となっている。 The active matrix organic EL display device 200 of the present embodiment includes the TFT 10 having the top gate structure shown in FIG. 1 as a driving TFT 10a and a switching TFT 10b on a substrate 12 having a passivation layer 202. , 10b is provided with an organic EL light emitting element 214 composed of an organic light emitting layer 212 sandwiched between a lower electrode 208 and an upper electrode 210, and the upper surface is also protected by a passivation layer 216.
また、図8に示すように、本実施形態の有機EL表示装置200は、互いに平行な複数のゲート配線220と、該ゲート配線220と交差する、互いに平行なデータ配線222および駆動配線224とを備えている。ここで、ゲート配線220とデータ配線222、駆動配線224とは電気的に絶縁されている。スイッチング用TFT10bのゲート電極22は、ゲート配線220に接続されており、スイッチング用TFT10bのソース電極16はデータ配線222に接続されている。また、スイッチング用TFT10bのドレイン電極18は駆動用TFT10aのゲート電極22に接続されるとともに、キャパシタ226を用いることで駆動用TFT10aをオン状態に保つ。駆動用TFT10aのソース電極16は駆動配線224に接続され、ドレイン電極18は有機EL発光素子214に接続される。 As shown in FIG. 8, the organic EL display device 200 according to the present embodiment includes a plurality of gate wirings 220 that are parallel to each other, and a data wiring 222 and a driving wiring 224 that are parallel to each other and intersect the gate wiring 220. I have. Here, the gate wiring 220, the data wiring 222, and the drive wiring 224 are electrically insulated. The gate electrode 22 of the switching TFT 10 b is connected to the gate wiring 220, and the source electrode 16 of the switching TFT 10 b is connected to the data wiring 222. The drain electrode 18 of the switching TFT 10b is connected to the gate electrode 22 of the driving TFT 10a, and the driving TFT 10a is kept on by using the capacitor 226. The source electrode 16 of the driving TFT 10 a is connected to the driving wiring 224, and the drain electrode 18 is connected to the organic EL light emitting element 214.
なお、図7に示した有機EL表示装置において、上部電極210を透明電極としてトップエミッション型としてもよいし、下部電極208およびTFTの各電極を透明電極とすることによりボトムエミッション型としてもよい。 In the organic EL display device shown in FIG. 7, the upper electrode 210 may be a top emission type using a transparent electrode, or the lower electrode 208 and each electrode of a TFT may be a bottom emission type using a transparent electrode.
<X線センサ>
本発明の薄膜トランジスタを用いるX線センサの一例について、図9にその一部分の概略断面図を示し、図10にその電気配線の概略構成図を示す。<X-ray sensor>
FIG. 9 shows a schematic sectional view of a part of an example of an X-ray sensor using the thin film transistor of the present invention, and FIG. 10 shows a schematic configuration diagram of its electric wiring.
本実施形態のX線センサ300は基板12上に形成されたTFT10およびキャパシタ310と、キャパシタ310上に形成された電荷収集用電極302と、X線変換層304と、上部電極306とを備えて構成される。TFT10上にはパッシベーション膜308が設けられている。 The X-ray sensor 300 of this embodiment includes the TFT 10 and the capacitor 310 formed on the substrate 12, the charge collection electrode 302 formed on the capacitor 310, the X-ray conversion layer 304, and the upper electrode 306. Composed. A passivation film 308 is provided on the TFT 10.
キャパシタ310は、キャパシタ用下部電極312とキャパシタ用上部電極314とで絶縁膜316を挟んだ構造となっている。キャパシタ用上部電極314は絶縁膜316に設けられたコンタクトホール318を介し、TFT10のソース電極16およびドレイン電極18のいずれか一方(図9においてはドレイン電極18)と接続されている。 The capacitor 310 has a structure in which an insulating film 316 is sandwiched between a capacitor lower electrode 312 and a capacitor upper electrode 314. The capacitor upper electrode 314 is connected to one of the source electrode 16 and the drain electrode 18 (the drain electrode 18 in FIG. 9) of the TFT 10 through a contact hole 318 provided in the insulating film 316.
電荷収集用電極302は、キャパシタ310におけるキャパシタ用上部電極314上に設けられており、キャパシタ用上部電極314に接している。
X線変換層304はアモルファスセレンからなる層であり、TFT10およびキャパシタ310を覆うように設けられている。
上部電極306はX線変換層304上に設けられており、X線変換層304に接している。The charge collection electrode 302 is provided on the capacitor upper electrode 314 in the capacitor 310 and is in contact with the capacitor upper electrode 314.
The X-ray conversion layer 304 is a layer made of amorphous selenium, and is provided so as to cover the TFT 10 and the capacitor 310.
The upper electrode 306 is provided on the X-ray conversion layer 304 and is in contact with the X-ray conversion layer 304.
図10に示すように、本実施形態のX線センサ300は、互いに平行な複数のゲート配線320と、ゲート配線320と交差する、互いに平行な複数のデータ配線322とを備えている。ここでゲート配線320とデータ配線322は電気的に絶縁されている。ゲート配線320とデータ配線322との交差部付近に、TFT10が備えられている。 As shown in FIG. 10, the X-ray sensor 300 of this embodiment includes a plurality of gate wirings 320 that are parallel to each other and a plurality of data wirings 322 that intersect with the gate wirings 320 and are parallel to each other. Here, the gate wiring 320 and the data wiring 322 are electrically insulated. The TFT 10 is provided in the vicinity of the intersection between the gate wiring 320 and the data wiring 322.
TFT10のゲート電極22は、ゲート配線320に接続されており、TFT10のソース電極16はデータ配線322に接続されている。また、TFT10のドレイン電極18は電荷収集用電極302に接続されており、さらにこの電荷収集用電極302は、キャパシタ310に接続されている。 The gate electrode 22 of the TFT 10 is connected to the gate wiring 320, and the source electrode 16 of the TFT 10 is connected to the data wiring 322. The drain electrode 18 of the TFT 10 is connected to the charge collecting electrode 302, and the charge collecting electrode 302 is connected to the capacitor 310.
本実施形態のX線センサ300において、X線は図9中、上部電極306側から入射してX線変換層304で電子−正孔対を生成する。X線変換層304に上部電極306によって高電界を印加しておくことにより、生成した電荷はキャパシタ310に蓄積され、TFT10を順次走査することによって読み出される。 In the X-ray sensor 300 of this embodiment, X-rays enter from the upper electrode 306 side in FIG. 9 and generate electron-hole pairs in the X-ray conversion layer 304. By applying a high electric field to the X-ray conversion layer 304 by the upper electrode 306, the generated charge is accumulated in the capacitor 310 and read out by sequentially scanning the TFT 10.
なお、上記実施形態の液晶表示装置100、有機EL表示装置200、及びX線センサ300においては、トップゲート構造のTFTを備えるものとしたが、TFTはこれに限定されず、図2〜図4に示す構造のTFTであってもよい。 In the liquid crystal display device 100, the organic EL display device 200, and the X-ray sensor 300 of the above embodiment, a TFT having a top gate structure is provided. However, the TFT is not limited to this, and FIGS. A TFT having the structure shown in FIG.
以下に実施例に基づいて本発明をさらに詳細に説明する。以下の実施例に示す材料、使用量、割合、処理内容、処理手順等は、本発明の趣旨を逸脱しない限り適宜変更することができる。したがって、本発明の範囲は以下に示す実施例により限定的に解釈されるべきものではない。 Hereinafter, the present invention will be described in more detail based on examples. The materials, amounts used, ratios, processing details, processing procedures, and the like shown in the following examples can be changed as appropriate without departing from the spirit of the present invention. Therefore, the scope of the present invention should not be construed as being limited by the following examples.
[実施例1]
<金属酸化物半導体膜の作製>
以下に示す溶液を基板上に塗布して金属酸化物半導体前駆体膜を形成し、この金属酸化物半導体前駆体膜を加熱した状態で紫外線照射を行うことにより、金属酸化物半導体前駆体膜を金属酸化物半導体膜に転化させて金属酸化物半導体膜を作製した。[Example 1]
<Production of metal oxide semiconductor film>
A metal oxide semiconductor precursor film is formed by applying the following solution on the substrate to form a metal oxide semiconductor precursor film, and then irradiating the metal oxide semiconductor precursor film with ultraviolet rays in a heated state. A metal oxide semiconductor film was formed by converting to a metal oxide semiconductor film.
〔金属酸化物半導体前駆体膜形成工程〕
(溶液)
塩化第二スズ(SnCl4・xH2O、3N、株式会社高純度化学研究所製)及び酢酸亜鉛(Zn(CH3COO)2・2H2O、株式会社高純度化学研究所製)をそれぞれ2−メトキシエタノール(試薬特級、和光純薬工業株式会社製)中に溶解させ、0.3mol/Lの濃度の塩化スズ溶液及び酢酸亜鉛溶液を調製し、その後、塩化スズ溶液と酢酸亜鉛溶液とを9:1の割合で混合することで、金属酸化物半導体前駆体溶液を調製した。
すなわち、上記溶液は、亜鉛及びスズの割合が100%であり、亜鉛とスズとの組成比Sn/(Sn+Zn)が0.9である。[Metal oxide semiconductor precursor film forming step]
(solution)
Stannic chloride (SnCl 4 · xH 2 O, 3N, manufactured by Kojundo Chemical Laboratory Co., Ltd.) and zinc acetate (Zn (CH 3 COO) 2 · 2H 2 O, manufactured by Kojundo Chemical Laboratory Co., Ltd.), respectively Dissolve in 2-methoxyethanol (special grade reagent, manufactured by Wako Pure Chemical Industries, Ltd.) to prepare a tin chloride solution and a zinc acetate solution having a concentration of 0.3 mol / L, and then add a tin chloride solution and a zinc acetate solution. Were mixed at a ratio of 9: 1 to prepare a metal oxide semiconductor precursor solution.
That is, in the above solution, the ratio of zinc and tin is 100%, and the composition ratio Sn / (Sn + Zn) between zinc and tin is 0.9.
(基板)
基板として熱酸化膜付p型シリコン基板を用いた。この基板の熱酸化膜をTFTのゲート絶縁膜として用いる構成とした。(substrate)
A p-type silicon substrate with a thermal oxide film was used as the substrate. The thermal oxide film of this substrate was used as the gate insulating film of the TFT.
(塗布・乾燥)
熱酸化膜付p型シリコン1inch×1inch基板上に、調製した溶液を5000rpmの回転速度で30秒スピンコートした後、60℃に加熱されたホットプレート上で5分間乾燥を行った。(Coating / Drying)
The prepared solution was spin-coated on a p-type silicon 1 inch × 1 inch substrate with a thermal oxide film at a rotational speed of 5000 rpm for 30 seconds, and then dried on a hot plate heated to 60 ° C. for 5 minutes.
〔転化工程〕
得られた金属酸化物半導体前駆体膜を、下記条件で金属酸化物半導体膜への転化を行った。
装置としては低圧水銀ランプを備えたVUVドライプロセッサ(株式会社オーク製作所社製、VUE−3400−F)を用いた。[Conversion process]
The obtained metal oxide semiconductor precursor film was converted into a metal oxide semiconductor film under the following conditions.
As the apparatus, a VUV dry processor (VUE-3400-F, manufactured by Oak Manufacturing Co., Ltd.) equipped with a low-pressure mercury lamp was used.
試料は装置内の、加熱されていないホットプレート上にセットした後、5分間待機した。この間、装置処理室内に20L/minの乾燥空気をフローさせた。
5分間の待機後、装置内のシャッターを開け、30分間で250℃まで昇温し、250℃到達後、60分間温度を保持しながら紫外線照射処理を行うことで金属酸化物半導体膜を得た。加熱処理下での紫外線照射処理の間、20L/minの乾燥空気を常にフローさせた。
試料位置での波長254nmをピーク波長とする紫外線照度を、紫外線積算光量計(浜松ホトニクス株式会社製、コントローラーC9536、センサヘッドH9536−254、200nm超300nm程度の範囲に分光感度を持つ)を用いて測定したところ、51mW/cm2であった。The sample was set on an unheated hot plate in the apparatus and waited for 5 minutes. During this time, 20 L / min of dry air was flowed into the apparatus processing chamber.
After waiting for 5 minutes, the shutter inside the apparatus was opened, the temperature was raised to 250 ° C. in 30 minutes, and after reaching 250 ° C., an ultraviolet irradiation treatment was performed while maintaining the temperature for 60 minutes to obtain a metal oxide semiconductor film. . During the ultraviolet irradiation treatment under heat treatment, dry air of 20 L / min was always flowed.
Ultraviolet illuminance with a peak wavelength of 254 nm at the sample position is measured using an ultraviolet integrated light meter (manufactured by Hamamatsu Photonics Co., Ltd., controller C9536, sensor head H9536-254, with spectral sensitivity in the range of about 200 nm to about 300 nm). It was 51 mW / cm 2 when measured.
〔TFTの作製〕
上記得られた金属酸化物半導体膜上にソース・ドレイン電極を蒸着により成膜し、簡易型TFTを作製した。ソース・ドレイン電極成膜はメタルマスクを用いたパターン成膜にて作製し、Tiを50nm成膜した。ソース・ドレイン電極サイズは各々1mm×1mmとし、電極間距離は0.2mmとした。[Production of TFT]
A source / drain electrode was formed on the metal oxide semiconductor film obtained above by vapor deposition, thereby producing a simple TFT. The source / drain electrodes were formed by pattern film formation using a metal mask, and Ti was formed to a thickness of 50 nm. The source / drain electrode size was 1 mm × 1 mm, respectively, and the distance between the electrodes was 0.2 mm.
[実施例2]
塩化スズ溶液と酢酸亜鉛溶液との混合の割合を7:3として溶液を調製し、金属酸化物半導体前駆体膜の亜鉛とスズとの組成比Sn/(Sn+Zn)を0.7とした以外は、実施例1と同様にして金属酸化物半導体膜を形成して、簡易型TFTを作製した。[Example 2]
The solution was prepared by setting the mixing ratio of the tin chloride solution and the zinc acetate solution to 7: 3, and the composition ratio Sn / (Sn + Zn) of zinc and tin of the metal oxide semiconductor precursor film was set to 0.7. A simple TFT was fabricated by forming a metal oxide semiconductor film in the same manner as in Example 1.
[実施例3]
転化工程における紫外線照射処理の際の基板温度を230℃とした以外は実施例1と同様にして金属酸化物半導体膜を形成して、簡易型TFTを作製した。[Example 3]
A simple TFT was produced by forming a metal oxide semiconductor film in the same manner as in Example 1 except that the substrate temperature during the ultraviolet irradiation treatment in the conversion step was 230 ° C.
[実施例4]
転化工程における紫外線照射処理の際の紫外線光照度を80mW/cm2とした以外は実施例1と同様にして金属酸化物半導体膜を形成して、簡易型TFTを作製した。[Example 4]
A simple TFT was produced by forming a metal oxide semiconductor film in the same manner as in Example 1 except that the ultraviolet light illuminance during the ultraviolet irradiation treatment in the conversion step was 80 mW / cm 2 .
[実施例5]
下記に示す金属酸化物半導体前駆体溶液を用いた以外は実施例1と同様にして金属酸化物半導体膜を形成して、簡易型TFTを作製した。[Example 5]
A simple TFT was produced by forming a metal oxide semiconductor film in the same manner as in Example 1 except that the metal oxide semiconductor precursor solution shown below was used.
硝酸ガリウム(Ga(NO3)3・xH2O、5N、株式会社高純度化学研究所製)及び硝酸インジウム(In(NO3)3・xH2O、4N、株式会社高純度化学研究所製)をそれぞれ2−メトキシエタノール(試薬特級、和光純薬工業株式会社製)中に溶解させ、0.3mol/Lの濃度の硝酸ガリウム溶液及び硝酸インジウム溶液を調製し、その後、硝酸ガリウム溶液と硝酸インジウム溶液とを1:4の割合で混合することで、ガリウムインジウム混合溶液を調整した。その後、実施例1で用いた亜鉛とスズとの組成比Sn/(Sn+Zn)が0.9の溶液と、ガリウムインジウム混合溶液とを4:1の割合で混合することで、金属酸化物半導体前駆体溶液を調製した。
すなわち、上記溶液は、亜鉛及びスズの割合が80%であり、亜鉛とスズとの組成比Sn/(Sn+Zn)が0.9である。Gallium nitrate (Ga (NO 3 ) 3 xH 2 O, 5N, manufactured by Kojundo Chemical Laboratory Co., Ltd.) and indium nitrate (In (NO 3 ) 3 xH 2 O, 4N, manufactured by Kojundo Chemical Laboratory Co., Ltd.) ) In 2-methoxyethanol (special grade reagent, manufactured by Wako Pure Chemical Industries, Ltd.) to prepare a gallium nitrate solution and an indium nitrate solution having a concentration of 0.3 mol / L, and then gallium nitrate solution and nitric acid The gallium indium mixed solution was prepared by mixing the indium solution at a ratio of 1: 4. Then, the metal oxide semiconductor precursor is prepared by mixing the solution of the zinc / tin composition ratio Sn / (Sn + Zn) 0.9 used in Example 1 and the gallium indium mixed solution in a ratio of 4: 1. A body solution was prepared.
That is, in the above solution, the ratio of zinc and tin is 80%, and the composition ratio Sn / (Sn + Zn) between zinc and tin is 0.9.
[実施例6]
実施例1で用いた亜鉛とスズとの組成比Sn/(Sn+Zn)が0.9の溶液と、ガリウムインジウム混合溶液との混合割合を9:1とした以外は、実施例5と同様にして金属酸化物半導体前駆体溶液を調製して、金属酸化物半導体膜を形成し、簡易型TFTを作製した。
すなわち、上記溶液は、亜鉛及びスズの割合が90%であり、亜鉛とスズとの組成比Sn/(Sn+Zn)が0.9である。[Example 6]
Except that the mixing ratio of the zinc / tin composition ratio Sn / (Sn + Zn) 0.9 used in Example 1 and the gallium indium mixed solution was 9: 1, the same procedure as in Example 5 was performed. A metal oxide semiconductor precursor solution was prepared, a metal oxide semiconductor film was formed, and a simple TFT was produced.
That is, in the above solution, the ratio of zinc and tin is 90%, and the composition ratio Sn / (Sn + Zn) between zinc and tin is 0.9.
[比較例1]
溶液として塩化スズ溶液を用いて、金属酸化物半導体前駆体膜の亜鉛とスズとの組成比Sn/(Sn+Zn)を1とした以外は、実施例1と同様にして金属酸化物半導体膜を形成して、簡易型TFTを作製した。[Comparative Example 1]
A metal oxide semiconductor film is formed in the same manner as in Example 1 except that a tin chloride solution is used as a solution and the composition ratio Sn / (Sn + Zn) of zinc and tin of the metal oxide semiconductor precursor film is set to 1. Thus, a simple TFT was produced.
[比較例2]
塩化スズ溶液と酢酸亜鉛溶液との混合の割合を6:4として溶液を調製し、金属酸化物半導体前駆体膜の亜鉛とスズとの組成比Sn/(Sn+Zn)を0.6とした以外は、実施例1と同様にして金属酸化物半導体膜を形成して、簡易型TFTを作製した。[Comparative Example 2]
The solution was prepared by setting the mixing ratio of the tin chloride solution and the zinc acetate solution to 6: 4, except that the composition ratio Sn / (Sn + Zn) of zinc and tin of the metal oxide semiconductor precursor film was 0.6. A simple TFT was fabricated by forming a metal oxide semiconductor film in the same manner as in Example 1.
[比較例3]
転化工程において紫外線の照射を行わない以外は、実施例1と同様にして金属酸化物半導体膜を形成して、簡易型TFTを作製した。[Comparative Example 3]
A simple TFT was fabricated by forming a metal oxide semiconductor film in the same manner as in Example 1 except that no ultraviolet irradiation was performed in the conversion step.
[比較例4]
転化工程において紫外線の照射を行わない以外は、比較例1と同様にして金属酸化物半導体膜を形成して、簡易型TFTを作製した。[Comparative Example 4]
A simple TFT was produced by forming a metal oxide semiconductor film in the same manner as in Comparative Example 1 except that no ultraviolet irradiation was performed in the conversion step.
<SIMS分析>
実施例1および比較例3で作製した金属酸化物半導体膜について、SIMS分析(二次イオン質量分析法)により、膜中の水素濃度および炭素濃度を求めた。
測定装置は、アルバック・ファイ株式会社製 PHI ADEPT−1010を用いた。
測定条件としては、一次イオン種はCs+、一次加速電圧は1.0kV、検出領域は140μm×140μmとした。
SIMS分析によって見積もられた水素および炭素の濃度を表1に示す。なお、深さ方向で濃度に違いが生じたため濃度範囲として示す。<SIMS analysis>
About the metal oxide semiconductor film produced in Example 1 and Comparative Example 3, the hydrogen concentration and carbon concentration in the film were determined by SIMS analysis (secondary ion mass spectrometry).
As a measuring device, PHI ADEPT-1010 manufactured by ULVAC-PHI Co., Ltd. was used.
As measurement conditions, the primary ion species was Cs + , the primary acceleration voltage was 1.0 kV, and the detection region was 140 μm × 140 μm.
Table 1 shows the hydrogen and carbon concentrations estimated by SIMS analysis. In addition, since a difference in density occurs in the depth direction, the density range is shown.
表1の実施例1と比較例3との対比から、本発明の方法で作製した金属酸化物半導体膜は、紫外線照射によって膜中の水素濃度及び炭素濃度が低減していることがわかる。 From the comparison between Example 1 and Comparative Example 3 in Table 1, it can be seen that the hydrogen concentration and carbon concentration in the metal oxide semiconductor film produced by the method of the present invention are reduced by ultraviolet irradiation.
[評価]
<トランジスタ特性>
作製した各簡易型TFTについて、半導体パラメータ・アナライザー4156C(アジレントテクノロジー株式会社製)を用い、トランジスタ特性Vg−Idを測定し、線形移動度を求めた。
トランジスタ特性Vg−Idの測定は、ドレイン電圧(Vd)を+20Vに固定し、ゲート電圧(Vg)を−15V〜+30Vの範囲内で変化させ、各ゲート電圧におけるドレイン電流(Id)を測定することにより行った。
なお、比較例1に関してはオンオフ動作が確認できず、導体の振る舞いを示した。
また、比較例3に関しては電気伝導性を示さず、絶縁体の振る舞いを示した。
評価結果を表2に示す。また、実施例1、2および比較例1、2のトランジスタ特性Vg−Idのグラフを図11に示す。また、比較例1、4のトランジスタ特性Vg−Idのグラフを図12に示す。[Evaluation]
<Transistor characteristics>
For each simplified TFT fabricated using a semiconductor parameter analyzer 4156C (manufactured by Agilent Technologies Inc.), to measure the transistor characteristics V g -I d, it was determined linear mobility.
Measurement of transistor properties V g -I d is the drain voltage (V d) is fixed to + 20V, the gate voltage (V g) is changed within the range of -15V~ + 30V, the drain current (I d in the gate voltage ) Was measured.
In Comparative Example 1, the on / off operation could not be confirmed, and the behavior of the conductor was shown.
Further, Comparative Example 3 did not show electrical conductivity and showed the behavior of the insulator.
The evaluation results are shown in Table 2. Further, a graph of the transistor characteristic V g -I d of Examples 1 and 2 and Comparative Examples 1 and 2 in Figure 11. Further, FIG. 12 shows a graph of the transistor characteristic V g -I d of Comparative Examples 1 and 4.
表2に示す通り、本発明の製造方法で作製された金属酸化物半導体膜を備える実施例の簡易型TFTは、比較例の簡易型TFTに比して線形移動度が大きく、高い半導体特性を有することがわかる。
ここで、実施例1、2および比較例1、2の対比から、金属酸化物半導体前駆体膜の亜鉛とスズとの組成比を0.7≦Sn/(Sn+Zn)≦0.9の範囲とすることで線形移動度を大きくできることがわかる。
また、実施例1と実施例5、6との対比から、全金属成分中のスズおよび亜鉛の割合が高いほど線形移動度を大きくできることがわかる。
また、実施例1と実施例4との対比から、転化工程における紫外線の照度を大きくしても線形移動度はかわらないことがわかる。このことから、金属酸化物半導体前駆体膜の転化に必要十分な照度の紫外線を照射すればよいことがわかる。
また、実施例1〜4から250℃以下の低温の加熱でも線形移動度を大きくできることがわかる。As shown in Table 2, the simple TFT of the example provided with the metal oxide semiconductor film manufactured by the manufacturing method of the present invention has a large linear mobility and high semiconductor characteristics as compared with the simple TFT of the comparative example. You can see that
Here, from the comparison of Examples 1 and 2 and Comparative Examples 1 and 2, the composition ratio of zinc and tin of the metal oxide semiconductor precursor film is in the range of 0.7 ≦ Sn / (Sn + Zn) ≦ 0.9. It can be seen that the linear mobility can be increased.
Moreover, it can be seen from the comparison between Example 1 and Examples 5 and 6 that the higher the ratio of tin and zinc in all metal components, the greater the linear mobility.
Moreover, it turns out that linear mobility does not change even if the illumination intensity of the ultraviolet-ray in a conversion process is enlarged from the comparison with Example 1 and Example 4. FIG. This shows that it is sufficient to irradiate ultraviolet rays having sufficient illuminance to convert the metal oxide semiconductor precursor film.
It can also be seen from Examples 1 to 4 that the linear mobility can be increased by heating at a low temperature of 250 ° C. or lower.
また、図12に示すように、比較例1および比較例4は、いずれも導体の振る舞いを示しているが、紫外線照射を行った比較例1よりも、紫外線照射を行っていない比較例4の方が電子伝達特性が高くなることがわかる。このことから、紫外線照射処理の効果を得るためには、亜鉛とスズとの組成比の範囲を適切に選択する必要があることがわかる。
以上より本発明の効果は明らかである。In addition, as shown in FIG. 12, Comparative Example 1 and Comparative Example 4 both show the behavior of the conductor, but Comparative Example 4 in which ultraviolet irradiation is not performed is more than Comparative Example 1 in which ultraviolet irradiation is performed. It can be seen that the electron transfer characteristics are higher. From this, it can be seen that in order to obtain the effect of the ultraviolet irradiation treatment, it is necessary to appropriately select the range of the composition ratio of zinc and tin.
From the above, the effects of the present invention are clear.
10 薄膜トランジスタ
12 基板
14 活性層(酸化物半導体層)
16 ソース電極
18 ドレイン電極
20 ゲート絶縁膜
22 ゲート電極
30、40、50 薄膜トランジスタ
100 液晶表示装置
102、202、216 パッシベーション層
104 画素下部電極
106 対向上部電極
108 液晶層
110 カラーフィルタ
112a、112b 偏光板
113、220、320 ゲート配線
114、222、322 データ配線
116、318 コンタクトホール
118、310 キャパシタ
200 有機EL表示装置
208 下部電極
210、306 上部電極
212 有機発光層
214 有機EL発光素子
224 駆動配線
300 X線センサ
302 電荷収集用電極
304 X線変換層
308 パッシベーション膜
312 キャパシタ用下部電極
314 キャパシタ用上部電極
316 絶縁膜10 Thin Film Transistor 12 Substrate 14 Active Layer (Oxide Semiconductor Layer)
16 Source electrode 18 Drain electrode 20 Gate insulating film 22 Gate electrode 30, 40, 50 Thin film transistor 100 Liquid crystal display device 102, 202, 216 Passivation layer 104 Pixel lower electrode 106 Opposing upper electrode 108 Liquid crystal layer 110 Color filter 112a, 112b Polarizing plate 113 , 220, 320 Gate wiring 114, 222, 322 Data wiring 116, 318 Contact hole 118, 310 Capacitor 200 Organic EL display device 208 Lower electrode 210, 306 Upper electrode 212 Organic light emitting layer 214 Organic EL light emitting element 224 Drive wiring 300 X-ray Sensor 302 Charge collection electrode 304 X-ray conversion layer 308 Passivation film 312 Capacitor lower electrode 314 Capacitor upper electrode 316 Insulating film
Claims (5)
二次イオン質量分析法による膜中の炭素濃度が1×1019atoms/cm3以上1×1020atoms/cm3以下である金属酸化物半導体膜。 80% or more of all metal components are zinc and tin, and the composition ratio of zinc and tin is 0.7 ≦ Sn / (Sn + Zn) ≦ 0.9,
A metal oxide semiconductor film having a carbon concentration of 1 × 10 19 atoms / cm 3 or more and 1 × 10 20 atoms / cm 3 or less by secondary ion mass spectrometry.
二次イオン質量分析法による膜中の水素濃度が2×10 The hydrogen concentration in the membrane by secondary ion mass spectrometry is 2 × 10 22twenty two atoms/cmatoms / cm 3Three 以上4×104 × 10 or more 22twenty two atoms/cmatoms / cm 3Three 以下である金属酸化物半導体膜。The metal oxide semiconductor film which is the following.
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