JP2013092681A - Display - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem that a voltage written by an off-leak current of a transistor changes after writing a data voltage into a pixel circuit.SOLUTION: A pixel circuit comprises: a current generation circuit for generating a current according to a voltage at a signal input terminal; a transistor including a gate connected to a scan line and including a first current terminal connected to a data line; a first capacitance that is connected between a second current terminal of the transistor and the signal input terminal; and a second capacitance that is connected between the second current terminal of the transistor and a fixed potential. A display transmits the data voltage to the signal input terminal by writing the data voltage and a reference voltage, in this order, into terminals of the first and second capacitances connected to the second current terminal of the transistor, and refreshes the data voltage at the signal input terminal by writing the reference voltage into the terminals again before writing the next data voltage.

Description

  The present invention relates to a display device, and more particularly to a display device including a light emitting element.

  A light-emitting display device typified by an organic electroluminescence (organic EL) display device includes a plurality of pixels each formed of a light-emitting element arranged in a matrix on a substrate. In order to cause the light emitting elements of each pixel to emit light with a luminance corresponding to the image data, the amount of current flowing through each light emitting element must be accurately controlled. In general, a light-emitting display device has an active matrix configuration in which a thin film transistor (TFT) is provided for each pixel in order to control the amount of current flowing through each light-emitting element.

  A TFT formed of polycrystalline silicon (polysilicon, hereinafter referred to as P-Si) has higher carrier mobility and a higher ON current than a TFT formed of amorphous silicon (amorphous silicon, hereinafter referred to as A-Si). It is more suitable as a transistor used for a high-definition display device. However, TFTs formed of polycrystalline silicon have a problem that electrical characteristics are likely to vary due to defects in crystal grain boundaries. Patent Document 1 proposes a circuit that corrects variations in threshold voltage of TFTs.

  FIG. 14 is a timing chart showing (A) the pixel circuit exemplified in Patent Document 1 and (B) its operation. In this pixel circuit, first, in the period (I), the transistor 105 is turned on to supply a constant voltage (reference voltage) of the data line 101 to one terminal of the storage capacitor 109 (the terminal connected to the gate of the transistor 106). Tell the other side. The transistors 107 and 108 are both turned on in the period (II) to turn on the transistor 106, and then the transistor 108 is turned off in the period (III). The drain current of the transistor 106 flows through the transistor 107 to the other terminal of the storage capacitor 109 (the one connected to the gate of the transistor 106). This current raises the gate potential of the transistor 106, and when the gate-source voltage of the transistor 106 eventually reaches the threshold voltage, the current stops there. As a result, the threshold voltage of the transistor 106 is held in the storage capacitor 109. Although the transistor 107 is turned off during the period (IV), the voltage across the storage capacitor 109 does not change.

  After that, when the voltage of the data line 101 is switched to a data voltage lower than the reference voltage so far during the period (V), the gate potential of the transistor 106 also drops by the same voltage. Even if the transistor 105 is turned off during the period (VI), the terminal voltage on the data line side of the storage capacitor 109 is held by the parasitic capacitor 113 that is parasitic between the gate and the source of the first transistor, the wiring, etc. The gate voltage of 106 does not change. As a result, the gate-source voltage of the transistor 106 becomes a value obtained by adding the data voltage to the threshold voltage. When the transistor 108 is turned on in (VIII), the drain current corresponding to the data voltage is output from the transistor 106 to the EL element. 110 flows. Since this current does not depend on the threshold voltage of the transistor 106, the pixel circuit in FIG. 14 is a circuit that compensates for variations in threshold voltage.

JP 2010-244067 A

When a TFT is used as a switching element, it is desirable that no current flow at the time of off, but in practice an off current (hereinafter referred to as Ioff) of about 10 ⁻¹² to 10 ⁻¹⁴ A flows.

  In the pixel circuit of FIG. 14, after the transistor 105 is turned off at the timing of (VI), the data line side terminal of the storage capacitor 109 should hold the data voltage by the parasitic capacitor 113. However, when the pixel circuit is formed of a TFT, the terminal current changes because the off-current of the transistor 105 flows into the parasitic capacitance 113. Since the data line is at a reference voltage higher than the data voltage for most of the period, the off-current flows in the direction from the data line toward the parasitic capacitance 113, and the voltage at the data line side terminal of the storage capacitor 109 increases. As a result, the gate voltage of the transistor 106 also increases, and the luminance of the EL element 110 decreases.

  When the off-current varies from pixel to pixel, luminance unevenness such as roughness in the image occurs in addition to luminance reduction, and the image quality deteriorates. If the parasitic capacitance 113 is set to a large value as the second storage capacitor, the voltage hardly changes even when an off-current flows. However, in order to increase the second storage capacitor, it is necessary to increase the area of the pixel circuit, which makes it difficult to miniaturize the pixel.

  An object of the present invention is to provide a method for driving a display device that suppresses a change in voltage of a storage capacitor due to an off current while using a pixel circuit with a small area.

The present invention includes a plurality of light emitting elements arranged in a row direction and a column direction, a scanning line and a reset line provided in each row of the light emitting elements, a data line provided in each column of the light emitting elements, and a power supply line A pixel circuit that is connected to the scan line, reset line, data line, and power supply line and supplies a current to the light emitting element; a row drive circuit that supplies voltage signals to the scan line and reset line; and the data line A display device including a column driving circuit for supplying a voltage signal to
The pixel circuit includes:
A current generation circuit comprising a signal input terminal, generating a current according to the voltage of the signal input terminal, and resetting the voltage of the signal input terminal by a reset signal of the reset line;
A first transistor having a gate connected to the scan line and a first current terminal connected to the data line;
A first capacitor connected between a second current terminal of the first transistor and the signal input terminal of the current generation circuit;
A second capacitor connected between the second current terminal of the first transistor and a fixed potential;
Contains
While the row driving circuit applies a reset signal to the reset line in order to reset the voltage at the signal input terminal of the current generation circuit, and while the column driving circuit applies a data voltage to the data line The row driving circuit applies a main selection signal to the scanning line in a row in which a reset signal is applied to the reset line to turn on the first transistor, so that the first and second capacitors Holding the data voltage at a terminal connected to the second current terminal of the first transistor;
The column driver circuit applies a reference voltage to the data line a plurality of times within a period from when the main selection signal is applied to one of the scanning lines to when the main selection signal is applied to the same scanning line. And the row driving circuit applies a sub-selection signal to the scanning line to turn on the first transistor, and the second current terminal of the first transistor of the first and second capacitors. The reference voltage is held at a terminal connected to the terminal.

  In a driving method of a display device in which two types of voltages, a data voltage and a reference voltage, are written to a pixel, the reference voltage is refreshed by writing the reference voltage a plurality of times, even if the written reference voltage fluctuates due to transistor leakage. Is possible. As a result, the capacity for holding the reference voltage in the pixel can be reduced. Alternatively, it is possible to use a low-cost process with a large transistor leakage current.

3 is a pixel circuit of a display device of the present invention. 2 is a timing chart illustrating an operation of the pixel circuit in FIG. 1. It is a timing chart which shows the operation | movement in a matrix display. It is a timing chart which shows the operation | movement in a matrix display. It is a timing chart which shows the operation | movement in a matrix display. It is a figure which shows the pixel circuit of the display apparatus of a 1st Example. 1 is an overall view of a display device according to a first embodiment. 3 is a timing chart showing the operation of the pixel circuit of the first embodiment. It is a graph which shows the Vg-Id characteristic of a common transistor. It is a figure which shows the other example of the pixel circuit of the display apparatus which is the 1st Example of this invention. It is a figure which shows the pixel circuit of the display apparatus of a 2nd Example. It is a timing chart which shows operation | movement of the pixel circuit of a 2nd Example. 1 is a block diagram showing an overall configuration of a digital still camera system of the present invention. It is a timing chart which shows the conventional pixel circuit and its operation.

  FIG. 1 shows a pixel circuit used in the display device of the present invention. The pixel circuit in FIG. 1 is specifically the pixel circuit shown in FIG. 14 and the following embodiments.

  1 includes a current generation circuit 10 having a signal input terminal IN, a first transistor Tr1 having a gate G connected to a scanning line SEL and a drain D connected to a data line DATA, and a first transistor. A first capacitor C1 connected between the source S of Tr1 and the signal input terminal IN of the current generation circuit 10, and a second capacitor C2 connected between the source S of the first transistor Tr1 and the power supply line VCC. Including.

  Here, of the source and drain of the first transistor Tr1, the one connected to the data line DATA is called the drain, and the one connected to the first and second capacitors C1 and C2 is called the source. The transistor becomes conductive when the voltage between the gate and the source exceeds a threshold value. In the N-channel type, current flows from the source to the drain, and in the P-channel type, current flows from the source to the drain. It can be said that the position of the source and the drain is determined by the direction in which the current flows, and the voltage between the source and the gate determined thereby determines the magnitude of the current.

  A transistor that operates so that current flows in both directions, such as the first transistor in FIG. 1, has its source and drain positions reversed depending on the direction of the current. However, since this is troublesome, a transistor in which current flows in both directions is usually called with the position of the source and drain fixed to either one for convenience. In the following description, the drain connected to the data line and the source connected to the first and second capacitors are used. When the names of the source and the drain are compatible, they may be called a first current terminal and a second current terminal instead.

  The first transistor Tr1 is an N-channel transistor and functions as a first switch that connects the data line 8 to one end of the first capacitor C1 and one end of the second capacitor C1.

  The first transistor Tr1 becomes conductive when the P1 control signal becomes H (HIGH) level, and takes in the potential of the data line 8 (which is switched between the data voltage Vdata and the reference voltage Vref) into the pixel circuit. For convenience, a terminal connected to the data line 8 is called a source, one end of the first capacitor C1 and a terminal connected to one end of the second capacitor C2 are called a drain.

  The current generation circuit 10 generates a current corresponding to the voltage at the signal input terminal IN, and supplies this to the light emitting element EL from the output terminal OUT. The voltage at the signal input terminal IN is supplied from the data line DATA via the first transistor Tr1 and the first capacitor C1 when a selection signal is input to the scanning line SEL. This voltage is held by the first capacitor C1 and the second capacitor C2 even after the first transistor Tr1 is turned off. Since the other terminal of the second capacitor C2 only needs to be set to a fixed potential, it is connected to the power supply line in FIG. 1, but may be grounded.

  When a reset signal is input to the reset line RES, the voltage of the signal input terminal IN is reset to a voltage that does not depend on the voltage of the data line DATA. The reset operation and the reset voltage Vres generated at the signal input terminal IN as a result vary depending on the specific configuration of the current generation circuit 10, and will be described in detail in a later embodiment.

  2 shows a voltage signal input to each of the scanning line SEL, the reset line RES, and the data line DATA to which the pixel circuit 11 of FIG. 1 is connected, the voltage of the source S of the first transistor Tr1, and a current generation circuit. It is a timing chart which shows the time change of the voltage of the voltage input terminal IN.

  Between times T0 and T1, a reset signal (High level, hereinafter referred to as H level) is applied to the reset line RES, thereby setting the voltage at the signal input terminal IN to the reset voltage Vres. A period from time T0 to T1 is referred to as a reset period TR. In the reset period TR, a selection signal (H level) is applied to the scanning line SEL, and the data voltage Vdata is taken from the data line DATA to the terminals connected to the sources of the first capacitor C1 and the second capacitor C2. The first capacitor C1 holds the difference between the data voltage Vdata and the reset voltage Vres, and the second capacitor C2 holds the difference between the data voltage Vdata and the power supply voltage Vcc.

  After writing the data voltage in the reset period TR, the reset signal ends at time T1, and the voltage of the reset line RES returns to the L (Low) level. As a result, the signal input terminal IN is in a high impedance state, that is, a state in which no current flows and no current flows from anywhere in the operation of the circuit.

  The scanning line SEL maintains the selection signal (H level) as it is, and when the voltage of the data line DATA is switched from the data voltage Vdata to the reference voltage Vref, the sources of the first transistors of the first capacitor C1 and the second capacitor C2 The terminal S connected to the reference voltage Vref becomes the reference voltage Vref, and the signal input terminal IN of the current generation circuit 10 receives the same voltage change through the first capacitor C1. The signal input terminal IN becomes a voltage (Vres + Vref−Vdata) obtained by adding the difference between the reference voltage Vref and the data voltage Vdata to the reset voltage Vres.

  As described above, the data voltage is transmitted to the signal input terminal IN of the current generation circuit 10 in the period TS of the time T1-T2. In response to this voltage, the current generation circuit generates a current and supplies it to the light emitting element EL. In this way, the light emitting element EL emits light with a luminance corresponding to the data voltage Vdata.

  Even when the selection signal of the scanning line SEL ends at time T2 and the first transistor Tr1 is turned off, the reference voltage Vref is held in the second capacitor C2, and thus the signal input terminal voltage IN of the current generation circuit 10 is It does not change. As a result, light emission is maintained.

  However, if there is a leakage current between the source and the drain even when the first transistor Tr1 is off, the voltage at the source S of the first transistor Tr1 gradually changes. Even when the selection period of the pixel circuit ends at time T2, the data voltage of the other pixel circuit is applied to the data line at a later time, so the potential of the data line is not constant. As shown in FIG. 2, when the voltage of the data line DATA is higher than the reference voltage Vref on average, a leakage current flows from the drain D to the source S of the first transistor Tr1, and the voltage of the source S increases. Accordingly, the voltage of the signal input terminal voltage IN of the current generation circuit 10 also increases. In the opposite case, the voltage drops. In either case, the luminance of the light emitting element changes.

  Therefore, the data line DATA is connected to the reference voltage Vref with respect to the pixel circuit 11 after the reference voltage Vref is written to the terminal connected to the source S of the first transistor Tr1 of the first capacitor C1 and the second capacitor C2. The timing (T4-T5) is provided, and the selection voltage (H level) is applied to the scanning line SEL in synchronization therewith to turn on the first transistor Tr1 again. As a result, the voltage S at the data line side terminal of the storage capacitor returns to the reference voltage Vref, so that the signal input terminal voltage Vin of the current generation circuit also returns to the original value, and as a result, the luminance of the light emitting element is recovered. If this operation is repeated as necessary, for example, by providing a similar operation during the period from T6 to T7, the change in the signal input terminal voltage due to the leakage current can be suppressed to an arbitrary level.

  In order to write the data voltage Vdata to the pixel circuit 11, the scanning line SEL becomes the selection level also in the period of time T0-T1 in synchronization with the reset signal (H level) of the reset line. Hereinafter, the scanning line selection signal synchronized with the reset signal (H level) is referred to as a main selection signal 12, and scanning synchronized with the data line reference voltage Vref, such as times T1-T2, T4-T5, T6-T7, and the like. The line selection signal is called a sub selection signal 13. In the timing chart of FIG. 2, the main selection signal 12 of T0-T1 and the sub-selection signal 13 of T1-T2 are one continuous pulse. The application period of the main selection signal 12 is also a period in which the data voltage Vdata is applied to the data line. Further, the application period of the sub selection signal 13 is also a period in which the reference voltage Vref is applied to the data line.

  Of the plurality of sub-selection signals 13, the first sub-selection signal 13-1 applied in the TS period (T1-T2) immediately after the data voltage Vdata is written is applied to the signal input terminal of the current generation circuit. Is provided to communicate. Accordingly, the light emitting element starts to emit light. The second and subsequent sub selection signals 13-2 and 13-3 applied in the period TT (T4-T5, T6-T7) are applied to restore the voltage change at the signal input terminal due to the leakage current. . The period TT is a refresh period, and the second and subsequent sub selection signals are also called refresh signals. In order to perform refresh with a certain light emission time, the second and subsequent sub-selection signals are preferably applied at equal time intervals so as to equally divide the light emission period within one frame.

  In the matrix display, since the data line supplies the data voltage to the plurality of pixel circuits in one column, the operation from time T0 to T2 is repeated in other pixel circuits after time T2. Therefore, the data voltage and the reference voltage are alternately applied to the data line DATA. In FIG. 2, the various data voltages Vdata appear on the data line DATA after time T3 because the data voltages are written to other pixel circuits. The refresh operation may be performed using the timing of applying the reference voltage Vref accompanying the write operation of such another pixel circuit.

  3 to 5 illustrate timing charts in the case of a matrix display. A scanning line SEL and a reset line RES (1-16 in parentheses indicate a row number) of each row and a voltage change of a typical data line are shown. The main selection signal 12 of the scanning line SEL is represented by a white pulse, and the sub-selection signal 13 is represented by a hatched pulse.

  t0-t16 is one frame period, and the next frame is repeated with t16 as t0. One frame period is a period assigned to display one image. In this period, a reset signal and a main selection signal are sequentially applied to the reset line and the scanning line of each row, and the data voltage is written from the data line. It is. Here, a matrix display with a total of 16 rows is taken as an example, but the same is true for a larger number of rows.

  FIG. 3 is a timing chart when the sub selection signal 13-1 is continuously applied immediately after the main selection signal 12 of each scanning line, as in FIG. In the first half TR of the period from t0 to t1, first, the reset line RES (1) of the first row becomes H level, and at the same time, the main selection signal (H level) is applied to the scanning line SEL (1), and the data line DATA is supplied. The data voltage Vdata is applied. Next, in the second half TS period, the reset line RES (1) returns to the L level, and the scanning line SEL (1) remains at the H level by the subsequent sub-selection signal. At this time, the data line DATA becomes the reference voltage Vref. As a result, the light emitting elements in the first row start to emit light. During the period from t1 to t2, the same H level signal is applied to the scanning line SEL (2) and the reset line RES (2) in the second row, data is written, and the light emitting elements in the second row start to emit light. Thereafter, scanning for starting writing and light emission is sequentially performed in each row.

  In the TS period from time t8 to t9 when the ninth row is selected, the second scanning line is applied to the first scanning line in synchronization with the application of the sub-selection signal to the ninth scanning line SEL (9). A sub-select signal is applied. As a result, the state of the pixel circuit in the first row is refreshed. This refresh operation is performed sequentially, such as the second row during the next period t9-t10 and the third row during the period t10-t11. The sub selection signal is applied to each scanning line twice within one frame period.

  FIG. 4 is a timing chart when the main selection signal of the scanning line and the first sub selection signal are separated. The first sub selection signal of each row is applied immediately after the main selection signal is applied to the scanning line of the next row. Increasing the interval between the main selection signal and the first sub-selection signal shortens the light emission period and lowers the overall luminance. This can be used to adjust the brightness of the display.

  FIG. 5 shows a case where the sub-selection signal is applied in all TS periods after the main selection signal is applied. When refreshing is performed at such a short time interval, voltage change due to leakage current hardly occurs.

  Conventionally, it is necessary to hold the voltage of the second capacitor C2 over one frame period, and C2 cannot be reduced. Since the voltage fluctuation of the data line is transmitted to the signal input terminal of the current generation circuit with attenuation of C1 / (C1 + C2), increasing C2 lowers the accuracy of the signal. For this reason, C2 is often set to approximately the same size as C1.

  In the display device of the present invention, the necessary voltage holding time can be shortened by performing a refresh operation within one frame period, and accordingly, C2 can be made much smaller than C1. When nine refresh operations are performed in one frame period, the required voltage holding time becomes 1/10 of one frame, and the size of C2 is also about one digit smaller than C1. If the number of refreshes is increased, it can be further reduced.

  As described above, the pixel circuit 11 includes a current generation circuit having a signal input terminal, a transistor having a gate connected to the sub-scan line and a drain connected to the data line, a source of the transistor, and a signal of the current generation circuit. As long as it includes a first capacitor connected between the input terminals and a second capacitor connected between the source of the same transistor and the power supply, the signal input terminal of the current generation circuit can be reset. Good. In the following description, the light-emitting element is an organic EL element. However, the display device of the present invention is not limited to this, and the display device uses other light-emitting elements such as inorganic EL elements and LEDs. Can be applied.

  The display device of the present invention is attached to an information device such as a mobile phone, a portable computer, a still camera, or a video camera, or a composite information device having a plurality of each of these functions. These information devices include an information input unit in addition to the display device. For example, in the case of a mobile phone, the information input unit includes an antenna. In the case of a PDA or a portable PC, the information input unit includes an interface unit for the network. In the case of a still camera or a movie camera, the information input unit includes a sensor unit such as a CCD or CMOS.

1. Configuration of Pixel Circuit FIG. 6 is a specific example of the circuit of FIG. 1 and shows a pixel circuit used in the display device of this embodiment and signal lines around it. The same parts as those in FIG. In FIG. 6, the current generation circuit 10 includes a light emitting element EL, a pixel circuit 11 including the current generation circuit 10, a first control signal line (scanning line) P <b> 1 that transmits a signal thereto, and a second control signal line (reset line). ) Connections of P2, data line 8, and power supply line 9 for supplying power supply voltage are shown.

  The first transistor Tr1 and the first and second capacitors C1 and C2 are arranged in the same manner as in FIG. The other end of the second capacitor C2 may be connected to a power supply line that is different from the power supply line 9.

  A portion surrounded by a broken line corresponds to the current generation circuit 10 of FIG. 1, and includes a second transistor Tr2 and third and fourth transistors Tr3 and Tr4 functioning as switches. The gate of the second transistor Tr2 is a signal input terminal of the current generation circuit 10.

  The second transistor Tr2 is arranged in series with the light emitting element El with respect to the power supply, generates a drain current determined by the voltage of the signal input terminal, and supplies the drain current to the light emitting element. Since the driving current is supplied to the light emitting element, the second transistor is hereinafter referred to as a driving transistor.

  The drive transistor Tr2 has a source connected to the power supply line 9, a drain connected to the drain of the third transistor Tr3, and simultaneously connected to the drain of the fourth transistor Tr4. The gate is connected to the other end of the first capacitor C1 and the source of the third transistor Tr3. Here, the drive transistor Tr2 is a P-channel MOS-FET.

  The third transistor Tr3 is also an N-channel transistor, and is disposed between the gate and drain of the drive transistor Tr2, and becomes conductive when the P2 control signal becomes H level. The third transistor Tr3 is a switch (first switch) provided for auto zero operation described later.

  The fourth transistor Tr4 is also an N-channel transistor, the source is connected to the anode of the light emitting element EL, and the gate is connected to the ILM line. Conduction occurs when the P3 control signal of the ILM line becomes H level. The fourth transistor Tr4 functions as a switch (second switch) that cuts off a current flowing through the light emitting element.

The light emitting element EL includes two electrodes, an anode and a cathode, and an organic EL light emitting layer sandwiched between them. One of the anode and the cathode serves as an electrode terminal connected to the pixel circuit 11. In FIG. 6, the anode is connected to the source terminal of Tr4 of the pixel circuit 11, and the cathode is connected to the ground potential GND.
All voltages are based on the ground potential GND of the light emitting element electrode on the side facing the pixel circuit.

  A power supply line 9 is connected to the pixel circuit 11, and a constant voltage VCC is supplied to the power supply line 9. The power supply voltage VCC is distributed to each pixel circuit 11 by a power supply line 9 extending in the row direction or the column direction.

2. Configuration of Display Device FIG. 7 is a diagram showing a pixel and a wiring group connected thereto in the display device according to the first embodiment of the present invention.

  The pixels 1 are arranged in a two-dimensional matrix of m rows × n columns to constitute an active matrix display device. The pixel 1 includes the pixel circuit 11 and the light emitting element EL shown in FIG.

  The pixel 1 is connected by three control signal lines 5, 6, and 7 extending in the row direction, and connected by one data line 8 in the column direction. The control signal lines 5, 6, and 7 correspond to the three control signal lines SEL, RES, and ILM in FIG. 6, respectively. The data line 8 corresponds to the data line DATA in FIG.

  The pixel 1 is actually composed of three light emitting elements EL that respectively emit three colors of red (R), green (G), and blue (B), and three pixel circuits 11 that supply current to them. Has been. Although one data line 8 is drawn for each pixel column, in practice, three R, G, and B data lines are arranged in each pixel column.

A row driving circuit 3 and a column driving circuit 4 are arranged around the pixel array. From the row drive circuit 3, P1 (1) to P1 (m) are applied to the control signal line 5 of each row, P2 (1) to P2 (m) are applied to the control signal line 6, and P3 (1) to P3 are applied to the control signal line 7. The control signal (m) is output.
Although not shown in FIG. 7, the power supply line 9 is also arranged along the row or column of the pixel circuit.

  Data voltage Vdata and reference voltage Vref are alternately output from all 3n output terminals of the column drive circuit 4. The data voltage Vdata is a voltage corresponding to the gradation level, and the reference voltage Vref is a constant voltage regardless of the data voltage. These signals are input to the pixel circuits in each column via the data line 8.

3. Circuit Operation FIG. 8 is a timing chart showing the operation of the pixel circuit 11 of FIG. It is assumed that the pixel circuit is in the i-th row, and in order from the top, (a) the voltage of the data line 8, (b) the control signal P1 (i) of the control signal line 5 of i row, (c) the control signal line of i row 6 control signal P2 (i), (d) control signal P3 (i) of control signal line 7 of i row, (e) gate voltage Vg (i) of second transistor Tr2 of pixel circuit of i row, (F) Control signal P1 (j) of control signal line 5 in j row, (g) Control signal P2 (j) of control signal line 6 in j row, (h) Control signal P3 in control signal line 7 of j row (J), (i) The gate voltage Vg (j) of the second transistor Tr2 of the pixel circuit in the j-th row is depicted.

  A period from writing image data to a pixel until writing next image data is one frame period. One frame period is divided into a program period and a light emission period. The program period is a period for writing a data voltage to the pixel circuit, and is divided into three periods: (A) a precharge period, (B) a reset period, and (C) a reference voltage set period. The light emission period is a period in which a current is supplied to the EL element to emit light, and is divided into two periods: (D) a light emission holding period and (E) a refresh period.

Hereinafter, the operation during each period of (A) to (E) will be described.
(A) Precharge Period First, in the i-th row precharge period (A), the control signals P2 (i) and P3 (i) are set to the H level, and the third transistor Tr3 (first switch) and the fourth transistor The transistor Tr4 (second switch) is turned on. The source voltage (Vs) of the drive transistor Tr2 is VCC. The gate and drain of the drive transistor Tr2 are short-circuited to form a diode connection. A current flows from the drive transistor Tr2 to the EL element, and the gate voltage of the drive transistor Tr2 becomes equal to the anode voltage of the EL element. As described above, the precharge period is a period in which the memory of the light emission state so far is erased and the pixel circuit is initialized.

  In FIG. 8, P1 (i) is also at the H level and the first transistor Tr1 is turned on, but this is not necessarily a necessary operation. During the precharge period, P1 (i) may be at a low level (hereinafter referred to as L level) and the first transistor Tr1 may be off. Further, any voltage may be applied to the data line during this period.

(B) Autozero & Sampling Period In the next autozero & sampling period (B), P2 (i) remains at the H level, P1 (i) is set to the H level, and P3 (i) is set to the L level. The first transistor Tr1 and the third transistor Tr3 (first switch) are turned on, and the fourth transistor Tr4 (second switch) is turned off. A data voltage Vdata = V (i) for the pixel (in the i-th row) is applied from the column drive circuit 4 to the data line. The drain current of the driving transistor Tr2 charges the capacitor C1 through the third transistor Tr2. As a result, the gate voltage of the drive transistor Tr2 increases, and as a result, the drain current decreases. After a certain time, the gate-source voltage of the drive transistor Tr2 converges to the threshold voltage Vth, and the drain current becomes almost zero. The process in which the gate-source voltage converges to the threshold voltage Vth by the current flowing through the driving transistor Tr2 is called auto-zero operation.

  When the drain current becomes almost zero, the capacitor C1 has a difference between the data voltage V (i) of the data line 8 and the gate voltage VCC−Vth of the drive transistor Tr2, that is, (VCC−Vth) −V (i ) Is held. Thus, during the reset period, Vgs of the drive transistor Tr2 is reset to the threshold voltage, and at the same time, the threshold voltage is applied to one end (the terminal connected to the drive transistor Tr2) of the capacitor C1 and the other end (first The data voltage is written to the terminal connected to the transistor Tr1.

(C) Reference Voltage Set Period In the next reference voltage set period (C), P2 (i) is set to L level to insulate the gate of the drive transistor Tr2. The data voltage Vdata of the data line is switched from V (i) to Vref.

  As the data line voltage changes, the gate potential of the drive transistor Tr2 changes through the capacitor C1, and the gate-source voltage Vgs of the drive transistor Tr2 becomes V (i) −Vref larger than Vth. Thus, the drive transistor Tr2 is set so as to generate a current determined by the data voltage V (i), which is not related to variations in threshold voltage or changes with time.

  In this way, in the reference voltage setting period (C), the voltage at one end is switched from the data voltage V (i) to the reference voltage Vref while the voltage at both ends of the capacitor C1 is constant, so that the data voltage V (i) is driven by the drive transistor. This is the period for transmission to the gate of Tr2. The voltage applied to both ends of the capacitor C2 is VCC-Vref, and the capacitor C2 holds this voltage thereafter.

(D) Light Emission Holding Period After the data voltage is programmed in the above (A)-(C), P1 (i) is set to L level in the light emission holding period (D1), and the first transistor Tr1 is turned off. Become. As a result, the pixel voltage and the data line are disconnected, and the gate voltage of the drive transistor Tr2 does not vary even if the data line subsequently varies. P3 (i) is set to H level, the transistor Tr4 (second switch) is turned on, and light emission is started.
At this time, the first transistor Tr1 is in an OFF state, but actually a very small leakage current (Ioff) flows.

  FIG. 9 is a graph showing Vg-Id characteristics of general transistor characteristics. Id does not become zero even in a region where Vgs = 0 or Vgs <0. Due to this Ioff, the potential at both ends of C1 gradually changes with time. In this embodiment, when Vdata> Vref and Vdata ≠ Vref, a current flows through Tr1, and the potential on the data line side of the capacitor C1 rises as shown in FIG. At the same time, the gate potential (Vg) of the drive transistor Tr2 also rises through the capacitor C1. Therefore, the drain current of the driving transistor Tr2 decreases and the current flowing through the light emitting element also decreases, so that the luminance decreases. Here, the capacitance C2 works so as to suppress the potential change of the capacitance C1 as the capacitance value increases.

(E) Reference voltage resetting period In the reference voltage resetting period (E), the potential of the data line is set to the reference voltage in the middle of the light emission period, and the first transistor Tr1 is turned on to set the reference voltage of the data line to the capacitor C2. This is a period for transmission to one end. When the reference voltage is reset only once, a period for that purpose is provided in the middle of one frame period, and the lengths of the two light emission holding periods (D1 and D2) divided thereby are approximately the same. Set.

  It is not necessary to provide the reference voltage resetting period separately from the periods (A) to (C). The reference voltage can be efficiently reset by matching the timing of the reference voltage reset period (E) of the i-th row with the first sub-selection period (C) of the other row (j-th row). Can do.

  In the reference voltage resetting period (E), P1 (i) is set to the H level, and the first transistor Tr1 is turned on. Thereby, the pixel and the data line are connected again. Since the reset period (E) is also the reset period (C) of another row (jth row), the data line is at the reference voltage Vref. Therefore, the terminal on the first transistor Tr1 side of the capacitor C1 is reset to the reference voltage Vref from the voltage that has changed due to the leakage current during the light emission holding period (D1). As a result, the gate potential (Vg) of the drive transistor Tr2 again returns to the voltage set in the (C) reference voltage setting period through the capacitor C1. Since the drain current of the driving transistor Tr2 that has decreased is also restored, the reduced luminance of the light emitting element can be restored.

  In this embodiment, the auto zero & sampling period (B) is a reset period (TR in FIG. 2) for resetting the current generation circuit 10. During this period, P1 (i) corresponds to the main selection signal and P2 (i) corresponds to the reset signal.

  Further, the period corresponding to the first sub-selection signal application period (TS in FIG. 2) is that P2 (i) is L level, P1 (i) is H level, and the reference voltage Vref is applied to the data line. Reference voltage setting period (C). Next, the reference voltage reset period (E) in which P1 (i) becomes H level again is the refresh period (TT in FIG. 2).

  Since refresh is performed by applying the reference voltage Vref instead of the data voltage V (i) to the data line, it is not necessary to supply the data voltage V (i) once written to the data line again for refresh. It is also possible to simultaneously perform refresh by simultaneously applying sub-selection signals to a plurality of scanning lines.

  If the charge of the capacitor C1 has changed due to the leakage current of the third transistor Tr3, etc., the gate potential of the drive transistor Tr2 does not recover even if the reference voltage Vref is applied from the data line. The gate potential of the drive transistor Tr2 varies more easily as the capacitance C1 is smaller. The capacitance value of the capacitor C1 is preferably increased to such an extent that a voltage change within one frame period due to the leakage current of the third transistor Tr3 can be ignored. Conversely, the capacitance C2 may be small, and the parasitic capacitance of the first transistor Tr1 may be used as C2.

  In this embodiment, the reference voltage reset period (E) is set once in one frame. However, it can be set a plurality of times. The timing is possible whenever the data line voltage is at Vref. Further, when the reference voltage resetting period (E) is provided a plurality of times, the effect of the present invention can be best obtained by providing the light emission holding period at a timing that is equally divided.

  According to this embodiment, even when the data line side potential of the capacitor C1 changes due to the off-leakage of the transistor, the change in luminance can be suppressed by returning to the reference voltage Vref during the reference voltage resetting period. As a result, the value of the capacitor C2 can be designed to be small, and the pixel circuit can be made finer and higher definition, and the degree of freedom in circuit pattern layout can be improved.

  FIG. 10 shows an example in which the drive transistor Tr2 in FIG. 6 is an N-channel transistor. The connection position of the third transistor Tr3 arranged between the gate and drain of the driving transistor Tr2 is also changed, and the fourth transistor Tr4 is arranged between the driving transistor Tr2 and the power supply line. The second electrode of the capacitor C2 is connected to GND instead of VCC. Other configurations are exactly the same. The present invention can also be applied to a pixel circuit as shown in FIG.

  FIG. 11 is a pixel circuit according to the second embodiment of the present invention, and FIG. 12 is a timing chart of each signal applied thereto.

  In the pixel circuit of this embodiment, the fourth transistor Tr4 serving as a light emission period control switch is changed to a P-channel type with respect to the pixel circuit 11 of the first embodiment shown in FIG. A common gate signal is applied to the first transistor Tr1 and the fourth transistor Tr4. The third control signal line (ILM) for controlling the light emission period is not necessary.

  The timing chart of FIG. 12 differs from FIG. 8 in that P1 (i) is set to L level and only P2 (i) is set to H level in the precharge period (A). When the third transistor Tr3 and the fourth transistor Tr4 are turned on, the driving transistor Tr2 is diode-connected and precharge is performed.

  When both P1 (i) and P2 (i) are set to H level in the auto zero & sampling period (B), the first transistor Tr1 and the third transistor Tr3 are turned on, and the fourth transistor Tr4 is turned off. As a result, the voltage Vdata = V (i) of the data line 8 is set to the source of the first transistor Tr1, and the gate of the drive transistor Tr2 is reset to Vcc−Vth.

  In the reference voltage setting period (C), by setting P2 (i) to L level while P1 (i) remains at H level, the first transistor Tr1 is turned on, and the third transistor Tr3 and the fourth transistor Tr4 are turned on. Turn off. The data line 8 becomes the reference voltage Vref, and this voltage is taken into the capacitors C1 and C2, thereby setting the data voltage V (i) at the gate of the drive transistor Tr2.

  In the light emission holding period (D1, D2), P1 (i) is returned to the L level to turn off the first transistor Tr1 and turn on the fourth transistor Tr4. Thereby, the current generated by the drive transistor Tr2 flows through the light emitting element EL.

  In the reference voltage reset period (E), only P1 (i) is set to H level and P2 (i) is left at L level. The first transistor Tr1 is turned on and the fourth transistor Tr4 is turned off. The voltage of the capacitor C2 is restored to the reference voltage Vref, and the gate voltage of the drive transistor Tr2 is also restored. During the reference voltage resetting period, the current supply to the light emitting element is stopped, but the luminance does not change because the original current flows in the light emission holding period (D2) after the end.

Also in the present embodiment, the auto zero & sampling period (B) in which P1 and P2 are both H level and the first transistor Tr1 and the third transistor Tr3 are turned on is the reset period for resetting the current generation circuit 10 (FIG. 2 TR). During this period, P1 corresponds to the main selection signal, and P2 corresponds to the reset signal.
The reference voltage set period (C) in which the P2 signal line is turned off while the P1 signal line remains on and the reference voltage is applied to the data line is the first sub-selection signal application period (TS in FIG. 2), the reference voltage The reset period (E) is the refresh period TT.

  FIG. 13 is a block diagram of a digital still camera system 50 incorporating the display device of the present invention. The video captured by the imaging unit 51 or the video recorded in the memory 54 can be signal-processed by the video signal processing circuit 52 and viewed on the display panel 53. The CPU 55 controls the photographing unit 51, the memory 54, the video signal processing circuit 52, and the like according to the input from the operation unit 56, and performs photographing, recording, reproduction, and display suitable for the situation.

1 pixel 3 row drive circuit 4 column drive circuit 8 data line 9 power supply line 10 current generation circuit 11 pixel circuit EL light emitting element SEL scanning line RES reset line C1 first capacitor C2 second capacitor Tr1 (first) transistor

Claims (8)

A plurality of light emitting elements arranged in a row direction and a column direction, a scanning line and a reset line provided in each row of the light emitting elements, a data line provided in each column of the light emitting elements, a power supply line, and the scanning A pixel circuit that is connected to a line, a reset line, a data line, and a power supply line and supplies a current to the light emitting element; a row driving circuit that supplies a voltage signal to the scanning line and the reset line; and a voltage signal to the data line A display device including a column driving circuit for providing,
The pixel circuit includes:
A current generation circuit comprising a signal input terminal, generating a current according to the voltage of the signal input terminal, and resetting the voltage of the signal input terminal by a reset signal of the reset line;
A first transistor having a gate connected to the scan line and a first current terminal connected to the data line;
A first capacitor connected between a second current terminal of the first transistor and the signal input terminal of the current generation circuit;
A second capacitor connected between the second current terminal of the first transistor and a fixed potential;
Contains
While the row driving circuit applies a reset signal to the reset line in order to reset the voltage at the signal input terminal of the current generation circuit, and while the column driving circuit applies a data voltage to the data line The row driving circuit applies a main selection signal to the scanning line in a row in which a reset signal is applied to the reset line to turn on the first transistor, so that the first and second capacitors Holding the data voltage at a terminal connected to the second current terminal of the first transistor;
The column driver circuit applies a reference voltage to the data line a plurality of times within a period from when the main selection signal is applied to one of the scanning lines to when the main selection signal is applied to the same scanning line. And the row driving circuit applies a sub-selection signal to the scanning line to make the transistor conductive, and is connected to the second current terminal of the first transistor of the first and second capacitors. A display device in which the reference voltage is held in a terminal.   Immediately after the application of the reset signal to the reset line is completed, the column driving circuit applies the reference voltage to the data line, and the row driving circuit applies the first sub-selection signal to the scanning line. The display device according to claim 1.   The sub-selection signal is applied to the scanning lines at equal time intervals within a period from when the main selection signal is applied to one of the scanning lines until the main selection signal is applied to the same scanning line. The display device according to claim 1, wherein the display device is a display device.   3. The row selection circuit applies the sub-selection signal to the scanning line during all periods in which the column driving circuit applies the reference voltage to the data line. Display device.   5. The display device according to claim 1, wherein the column driving circuit alternately applies the data voltage and the reference voltage for each of the pixel circuits to the data line. 6.   The current generation circuit includes a second transistor connected in series to the light emitting element with respect to the power source, a first switch connecting a gate and a drain of the second transistor, the second transistor, 6. The display device according to claim 1, further comprising: a second switch that connects a light emitting element, wherein the gate of the second transistor is the signal input terminal.   The display device according to claim 6, wherein the reset signal is a signal for turning on the first switch and turning off the second switch.   The display device according to claim 1, wherein the second capacity is smaller than the first capacity.

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