JP2013090273A - Electronic component and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make wiring, formed by forming a plating film on a through hole provided at an insulation layer, robust and equalize the thickness of the plating layer formed at a position higher than the through hole.SOLUTION: An electronic component includes: an IDT electrode 2 and a pad electrode 3 which are formed on an upper surface of a piezoelectric substrate 1; a support layer 4 and a first cover layer 5 which have a through hole reaching the pad electrode 3; a via electrode 6 connecting with the pad electrode 3; a wiring base layer 7 which is formed on the first cover layer 5 so as to connect with an upper part of the via electrode 6 and has a hole provided so as to be positioned at the upper inner side of the via electrode 6; a wiring layer 8 integrally formed with the via electrode 6 on the wiring base layer 7; a second cover layer 9 covering the wiring layer 8; an under-bump metal 10 penetrating through the second cover layer 9 and connecting with the wiring layer; and a bump 11 provided on the under-bump metal 10.

Description

  The present invention relates to an electronic component and a manufacturing method thereof, and more particularly to an electronic component such as a wafer level-chip size package type (WL-CSP type) surface acoustic wave device and a manufacturing method thereof.

  In recent years, a wafer level-chip size package (WL-CSP) type surface acoustic wave device in which a package is reduced to the element size has been developed.

  For example, JP 2006-352430 A (Patent Document 1) describes an example of the surface acoustic wave device described above.

  As shown in FIG. 6, in the surface acoustic wave filter described in Patent Document 1, a conductive pattern including an IDT (Interdigital Traderducer) electrode 12 and a pad electrode 13 on the upper surface 1 </ b> A that is one main surface of the piezoelectric substrate 1. Is formed. A first insulating layer 20 is formed around the IDT electrode 12. The first insulating layer 20 is also formed on the pad electrode 13. A second insulating layer 22 is disposed at a distance from the piezoelectric substrate 1 by the first insulating layer 20. The outer edge of the second insulating layer 22 extends substantially along the outer edge of the piezoelectric substrate 1. A sealing space 19 that covers the periphery of the IDT electrode 12 is formed by the first and second insulating layers 20 and 22 that are insulating members. Further, an outer resin 24 is formed so as to cover the entire area from the top of the second insulating layer 22 to the outer edge of the piezoelectric substrate 11. The external terminal 18 is exposed above the outer resin 24. The external terminal 18 is electrically connected to the pad electrode 13 through a through hole formed in the first insulating layer 20, the second insulating layer 22 and the outer resin 24.

  A connecting member 15 is formed in the through hole of the first insulating layer 20 and the second insulating layer 22. The connection member 15 is formed by growing a plating film on the pad electrode 13. Since the wiring layer 14 is formed on the second insulating layer 22 so as to be in contact with the periphery of the opening of the through hole, when the plating film reaches the wiring layer 14, the plating layer is also formed on the wiring layer 14. grow up. Therefore, since the connection member 15 is integrally formed, it becomes a strong wiring, is not easily disconnected, and the reliability is improved.

JP 2006-352430 A

  However, since the through hole is formed by a laser or the like, burrs are generated at the periphery of the opening, and the shape is not smooth. Therefore, there is a portion where the plating grown from the through hole cannot contact the wiring layer 14, and the thickness of the plating film grown on the wiring layer 14 varies.

  The present invention has been made in view of the above problems, and an object of the present invention is to strengthen a wiring formed by forming a plating film in a through hole provided in an insulating layer. Another object of the present invention is to provide an electronic component capable of making the thickness of the plating layer formed above the through hole uniform and a method for manufacturing the same.

  An electronic component according to the present invention includes a substrate having a pair of opposing main surfaces, a conductive pattern formed on one main surface of the substrate, including a functional part and a pad electrode, and covering the conductive pattern to reach the pad electrode. A first insulating layer having a through hole, a first via electrode filled in the through hole and connected to the pad electrode, and on the first insulating layer so as to be connected to an upper portion of the first via electrode A wiring base layer having a hole formed so as to be positioned inside the upper portion of the first via electrode; a wiring layer formed on the wiring base layer integrally with the first via electrode; and a wiring layer A second insulating layer covering the first insulating layer, a second via electrode penetrating the second insulating layer and connected to the wiring layer, and an external terminal provided on the second via electrode.

  In one embodiment, in the electronic component, the wiring base layer is formed so as to cover the outer periphery of the opening of the through hole.

  In one embodiment, in the electronic component, the substrate includes a piezoelectric substrate, the functional unit includes an IDT electrode that forms a surface acoustic wave device, and the first insulating layer is a hollow that forms a sealed space of the IDT electrode. Part.

  An electronic component manufacturing method according to the present invention includes a step of preparing a substrate having a pair of opposed main surfaces, a step of forming a conductive pattern including a functional part and a pad electrode on one main surface of the substrate, and a conductive pattern. Forming a first insulating layer having a through hole reaching the pad electrode, forming a first via electrode filled in the through hole and connected to the pad electrode, and a first via Forming a wiring base layer having a hole provided on the inner side of the upper portion of the electrode on the first insulating layer; and wiring layer on the wiring base layer so as to be integrated with the first via electrode Forming a second insulating layer covering the wiring layer, forming a second via electrode penetrating the second insulating layer and connected to the wiring layer, Forming an external terminal on the via electrode.

  In one embodiment, in the electronic component manufacturing method, the first via electrode and the wiring layer are formed by electrolytic plating.

  In one embodiment, in the electronic component manufacturing method, the wiring base layer is formed by a lift-off method.

  According to the present invention, when forming the plating film in the through hole provided in the insulating layer, the wiring base layer is formed by forming the wiring base layer having a hole located inside the opening of the through hole. Since the peripheral edge is covered and is sufficiently in contact with the plating film in the through hole, the plating film can be uniformly grown on the wiring base layer. In addition, since the plating film is integrally formed through the hole, the plating layer becomes a strong wiring, is not easily disconnected, and has high reliability.

It is sectional drawing (the 1) which shows each process of the manufacturing method of the electronic component which concerns on one embodiment of this invention. It is sectional drawing (the 2) which shows each process of the manufacturing method of the electronic component which concerns on one embodiment of this invention. It is sectional drawing (the 3) which shows each process of the manufacturing method of the electronic component which concerns on one embodiment of this invention. 3 is a bird's eye view showing a via electrode 6 and a wiring base layer 7 shown in FIG. It is sectional drawing which shows the electronic component which concerns on one embodiment of this invention. It is sectional drawing which shows an example of the conventional electronic component.

  Embodiments of the present invention will be described below. Note that the same or corresponding portions are denoted by the same reference numerals, and the description thereof may not be repeated.

  Note that in the embodiments described below, when referring to the number, amount, and the like, the scope of the present invention is not necessarily limited to the number, amount, and the like unless otherwise specified. In the following embodiments, each component is not necessarily essential for the present invention unless otherwise specified.

  1 to 3 show a method for manufacturing a WL-CSP type surface acoustic wave device according to one embodiment of the present invention.

  First, as shown in FIG. 1A, a “first conductive pattern” including an IDT electrode 2 is formed on one main surface (hereinafter referred to as “upper surface”) of a piezoelectric substrate 1 (first step). .

  Next, as shown in FIG. 1B, a “second conductive pattern” including the pad electrode 3 is formed on the upper surface of the piezoelectric substrate 1 (second step). The pad electrode 3 is electrically connected to the IDT electrode 2. The pad electrode 3 is also electrically connected to a power supply line (not shown) used in a process related to electrolytic plating described later. The power supply line is included in the “first conductive pattern” or the “second conductive pattern”.

  As shown in FIG. 1C, a photosensitive resin such as polyimide is applied to the upper surface of the piezoelectric substrate 1 by a spine coating method (third step). Then, an insulating support layer 4 is formed by patterning a photosensitive resin by photolithography so that the IDT electrode 2 is exposed and the pad electrode 3 is covered.

  Further, as shown in FIG. 1D, an insulating first cover layer 5 is formed on the support layer 4 by bonding a non-photosensitive resin sheet made of polyimide or the like by a roll laminating method or the like. (4th process). Thereby, a sealed space 4 </ b> A is formed on the IDT electrode 2.

  As shown in FIG. 2E, a through-hole 5A that penetrates the support layer 4 and the first cover layer 5 is formed by laser, dry etching, or the like so that a part of the pad electrode 3 is exposed ( (5th process). Since the support layer 4 is made of a photosensitive resin, the through hole 5A may be formed in advance. Moreover, the inside of the through hole 5A is cleaned as necessary.

  As shown in FIG. 2F, a via electrode 6 made of Cu or Ni is formed (sixth step). The via electrode 6 is formed by growing a plating layer from the pad electrode 3 at the bottom of the through hole 5A to the opening of the through hole 5A by electrolytic plating. Here, the via electrode 6 is formed such that the upper portion thereof does not exceed the upper surface of the first cover layer 5.

  As shown in FIG. 2G, the wiring base layer 7 patterned into a desired shape is formed on the upper surface of the first cover layer 5 (seventh step). The wiring underlayer 7 is formed by depositing a metal on a pattern formed of a resist, removing the resist, and leaving a metal pattern only in a portion without the resist (lift-off method).

  As shown in FIG. 4, a circular hole is formed in the wiring base layer 7 so that a part of the upper portion of the via electrode 6 is exposed. That is, the hole portion of the wiring base layer 7 is formed so as to have a smaller diameter than the upper portion of the via electrode 6 and is located on the inner side of the upper portion of the via electrode 6. Thereby, the outer periphery of the hole of the wiring base layer 7 is in contact with the via electrode 6 beyond the periphery of the opening of the through hole 5A.

  Next, as shown in FIG. 2H, a wiring layer 8 is formed on the wiring base layer 7 from the via electrode 6 exposed from the hole of the wiring base layer 7 (eighth step). Similar to the via electrode 6, the wiring layer 8 is formed by growing a plating layer by electrolytic plating. Therefore, the via electrode 6 and the wiring layer 8 are integrally formed by the plating layer. Further, as described above, since the outer periphery of the hole portion of the wiring base layer 7 is sufficiently in contact with the via electrode 6, the wiring layer 8 is formed without variation in film thickness.

  Further, as shown in FIG. 3I, the second cover layer 9 is formed by covering the upper surface of the first cover layer 5 and the wiring layer 8 with a photosensitive thermosetting resin by using a printing method or the like. Is formed (9th step). Then, through holes are provided in the second cover layer 9 so that a part of the wiring layer 8 is exposed by photolithography.

  As shown in FIG. 3J, the under bump metal 10 is formed by filling the through hole of the second cover layer 9 with electrolytic plating or electroless plating (tenth process). . The under bump metal 10 may be composed of a plated layer formed in the order of Cu / Ni / Au from the bottom, or may be composed of a plated layer formed in the order of Ni / Au. In either case, Au is provided to prevent oxidation of Ni. Therefore, Au only needs to have a thickness of about 0.1 to 0.3 μm.

  As shown in FIG. 3 (k), a solder paste such as Sn-Ag-Cu is printed on the under bump metal 10 and reflowed to form bumps 11 as external terminals (11th step).

  In the above description using FIGS. 1 to 4, the process of manufacturing one WL-CSP type surface acoustic wave device has been described for convenience. In practice, a plurality of surface acoustic wave elements are formed on a piezoelectric substrate. A plurality of WL-CSP type surface acoustic wave devices are fabricated by dicing the piezoelectric substrate.

  The structure of the WL-CSP type surface acoustic wave device thus fabricated is as shown in FIG. That is, the piezoelectric substrate 1 having a pair of opposing main surfaces, the conductive pattern formed on one main surface of the piezoelectric substrate, including the IDT electrode 2 (functional unit) and the pad electrode 3, and the IDT electrode 2 are exposed. A support layer 4 that covers one main surface of the piezoelectric substrate and the conductive pattern, and a first cover layer 5 that covers the support layer 4 (the “first insulating layer” together with the support layer 4 and the cover layer 5); The via electrode 6 (first via electrode) that passes through the support layer 4 and the first cover layer 5 and is connected to a part of the pad electrode 3 is connected to the upper portion of the via electrode 6. A wiring base layer 7 which is formed in a desired shape on the cover layer 5 and has a hole provided in the wiring base layer 7 so as to be located inside the upper portion of the via electrode 6, and the wiring base layer integrally with the via electrode 6 7, the wiring layer 8 formed on the first cover layer 5, and the first cover layer 5 and A second cover layer 9 (second insulating layer) covering the wiring layer 8 and an under bump metal 10 (second via electrode) passing through the second cover layer 9 and connected to the wiring layer 8 And a surface acoustic wave device provided with bumps 11 (external terminals) provided on the under bump metal 10.

  According to the surface acoustic wave device according to the present embodiment, the position of the external terminal can be freely determined regardless of the shape of the conductive pattern provided on the piezoelectric substrate. In addition, since the via electrode and the wiring layer can be formed integrally, the wiring becomes strong, is not easily disconnected, and the reliability is improved.

  By the way, although the surface acoustic wave device as an example of the electronic component has been described in the present embodiment, the electronic component according to the present invention includes other piezoelectric devices such as boundary acoustic wave devices and bulk acoustic wave devices, semiconductor devices, and the like. The electric element may be used. The surface acoustic wave element requires a sealing space on the IDT electrode, which is a functional part, but in the case of an electrical element that does not require a sealing space on the functional part, the support layer 4 is the first cover layer. 5 may be integrated.

  Although the embodiments of the present invention have been described above, the embodiments disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  DESCRIPTION OF SYMBOLS 1 Piezoelectric substrate, 2,12 IDT electrode, 3,13 Pad electrode, 4 Support layer, 4A Sealing space, 5 1st cover layer, 5A Through-hole, 6 Via electrode, 7 Wiring base layer, 8, 14 Wiring layer , 9 Second cover layer, 10 Under bump metal, 11 Bump, 15 Connecting member, 18 External terminal, 19 Sealing space, 20 First insulating layer, 22 Second insulating layer, 24 Outer resin.

Claims (6)

A substrate having a pair of opposing main surfaces;
A conductive pattern formed on one main surface of the substrate and including a functional part and a pad electrode;
A first insulating layer covering the conductive pattern and having a through hole reaching the pad electrode;
A first via electrode filled in the through hole and connected to the pad electrode;
A wiring base layer formed on the first insulating layer so as to be connected to an upper portion of the first via electrode, and having a hole provided so as to be positioned inside the upper portion of the first via electrode; ,
A wiring layer formed on the wiring base layer integrally with the first via electrode;
A second insulating layer covering the wiring layer;
A second via electrode penetrating the second insulating layer and connected to the wiring layer;
An electronic component comprising: an external terminal provided on the second via electrode.   The electronic component according to claim 1, wherein the wiring base layer is formed so as to cover an outer periphery of the opening of the through hole. The substrate includes a piezoelectric substrate;
The functional unit includes an IDT electrode constituting a surface acoustic wave device,
The electronic component according to claim 1, wherein the first insulating layer includes a hollow portion that forms a sealed space of the IDT electrode. Preparing a substrate having a pair of opposing main surfaces;
Forming a conductive pattern including a functional part and a pad electrode on one main surface of the substrate;
Forming a first insulating layer covering the conductive pattern and having a through hole reaching the pad electrode;
Forming a first via electrode filled in the through hole and connected to the pad electrode;
Forming a wiring base layer having a hole provided on the inner side of the upper portion of the first via electrode on the first insulating layer;
Forming a wiring layer on the wiring base layer so as to be integrated with the first via electrode;
Forming a second insulating layer covering the wiring layer;
Forming a second via electrode penetrating the second insulating layer and connected to the wiring layer;
And a step of forming an external terminal on the second via electrode.   The method of manufacturing an electronic component according to claim 4, wherein the first via electrode and the wiring layer are formed by electrolytic plating.   The method for manufacturing an electronic component according to claim 4, wherein the wiring base layer is formed by a lift-off method.

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