CN109065701B - Chip packaging structure with single cofferdam, metal column and soldering tin and manufacturing method thereof - Google Patents
Chip packaging structure with single cofferdam, metal column and soldering tin and manufacturing method thereof Download PDFInfo
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- CN109065701B CN109065701B CN201810911188.3A CN201810911188A CN109065701B CN 109065701 B CN109065701 B CN 109065701B CN 201810911188 A CN201810911188 A CN 201810911188A CN 109065701 B CN109065701 B CN 109065701B
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- 239000002184 metal Substances 0.000 title claims abstract description 72
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 72
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 238000005476 soldering Methods 0.000 title claims abstract description 22
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 title claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 243
- 238000000034 method Methods 0.000 claims abstract description 43
- 238000007747 plating Methods 0.000 claims description 109
- 229910000679 solder Inorganic materials 0.000 claims description 66
- 229920002120 photoresistant polymer Polymers 0.000 claims description 24
- 238000009713 electroplating Methods 0.000 claims description 14
- 230000008569 process Effects 0.000 abstract description 12
- 239000000126 substance Substances 0.000 abstract description 9
- 239000010949 copper Substances 0.000 description 71
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 68
- 229910052802 copper Inorganic materials 0.000 description 68
- 238000000465 moulding Methods 0.000 description 26
- 239000000463 material Substances 0.000 description 12
- 230000005540 biological transmission Effects 0.000 description 8
- 230000000694 effects Effects 0.000 description 8
- 230000006872 improvement Effects 0.000 description 8
- 229920006336 epoxy molding compound Polymers 0.000 description 6
- 238000010897 surface acoustic wave method Methods 0.000 description 6
- 230000007704 transition Effects 0.000 description 6
- 238000012858 packaging process Methods 0.000 description 5
- 239000000919 ceramic Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000003466 welding Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N30/00—Piezoelectric or electrostrictive devices
- H10N30/80—Constructional details
- H10N30/88—Mounts; Supports; Enclosures; Casings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N30/00—Piezoelectric or electrostrictive devices
- H10N30/01—Manufacture or treatment
- H10N30/02—Forming enclosures or casings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N30/00—Piezoelectric or electrostrictive devices
- H10N30/01—Manufacture or treatment
- H10N30/06—Forming electrodes or interconnections, e.g. leads or terminals
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N30/00—Piezoelectric or electrostrictive devices
- H10N30/80—Constructional details
- H10N30/87—Electrodes or interconnections, e.g. leads or terminals
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
The invention discloses a chip packaging structure with a single cofferdam, metal columns and soldering tin and a manufacturing method thereof, wherein the packaging structure comprises the following components: the packaging substrate is provided with a plurality of external pins on one side of the lower surface of the substrate; the filter chip is provided with a plurality of electrodes on the lower surface; the cofferdam is matched with the lower surface of the chip and the upper surface of the substrate to form a cavity; the packaging substrate is provided with a plurality of through holes for a plurality of interconnection structures to pass through, the cofferdam is positioned on the inner sides of the plurality of through holes, the interconnection structures comprise metal column structures, soldering tin and electroplated layer structures, the metal column structures are conducted with electrodes, the electroplated layer structures are conducted with external pins, and the soldering tin is used for conducting the metal column structures and the electroplated layer structures. According to the invention, the cofferdam is arranged to form the cavity, so that the influence on the normal use of the filter chip caused by the fact that external substances enter the cavity in the manufacturing process of the packaging structure or in the use process of the packaging structure can be effectively avoided, and the overall performance of the packaging structure is improved.
Description
Technical Field
The invention relates to the field of semiconductor packaging, in particular to a chip packaging structure with a single cofferdam, metal columns and soldering tin and a manufacturing method thereof.
Background
Radio Frequency Integrated Circuits (RFICs) are widely used in wireless devices, such as cellular telephones.
RFIC incorporates transmission lines, matching networks and discrete components such as inductors, resistors, capacitors, and transistors on a substrate to provide a subsystem capable of transmitting and receiving high frequency signals, for example, in the range of about 0.1 to 100 gigahertz (GHz), the packaging of the RFIC differs significantly from that of digital integrated circuits because the packaging tends to be part of the radio frequency circuitry, and because the complex radio frequency electric and/or magnetic fields of the RFIC can interact with any nearby insulators and conductors, in order to meet the increasing demands of the wireless industry, the RFIC packaging development seeks to provide smaller, cheaper, higher performance devices that can accommodate multi-die radio frequency modules while providing higher reliability and using lead free solder and other "green" materials. Single chip packages, in which single or multi-die RFICs are individually packaged, are straightforward solutions to address the small size and low cost requirements of RFICs, and are now being used for most RFICs.
Microelectromechanical Systems (MEMS) permit controlled conversion between micro-scale mechanical motion and specified electrical signals, for example, consistent with specified frequencies, MEMS are being widely used in RFICs.
Based on mechanical motion, rf MEMS can achieve excellent signal quality with respect to rf band filters, e.g., SAW filters convert an electrical signal into a mechanical wave that is delayed as it propagates along the piezoelectric crystal substrate before being converted back into an electrical signal; BAW filters use bulk motion to achieve the desired special resonance; whereas in RF switches, an electrical signal is used to control the motion of the microelectrode, opening or closing the switch.
MEMS technology has evolved from semiconductor fabrication processes, however, the mechanical motion requirements associated with MEMS are quite different from the packaging configuration and requirements of conventional semiconductor integrated circuits, and in particular, some materials must be free to move undisturbed inside all MEMS integrated circuits, and therefore, MEMS integrated circuits must be shielded around moving materials to form small vacuum or air pockets to allow them to move while protecting them.
In the prior art, a closed and reliable cavity cannot be formed to protect a circuit or other structures.
Disclosure of Invention
The invention aims to provide a chip packaging structure with a single cofferdam, metal columns and soldering tin and a manufacturing method thereof.
In order to achieve one of the above objects, an embodiment of the present invention provides a chip package structure with a single dam, a metal pillar and solder, comprising:
the packaging substrate is provided with a substrate upper surface and a substrate lower surface which are oppositely arranged, and one side of the substrate lower surface is provided with a plurality of external pins;
the filter chip is provided with a chip upper surface and a chip lower surface which are oppositely arranged, the chip lower surface and the substrate upper surface are arranged face to face, and the chip lower surface is provided with a plurality of electrodes;
a plurality of interconnection structures for conducting a plurality of electrodes and a plurality of external pins;
the cofferdam is matched with the lower surface of the chip and the upper surface of the substrate to form a cavity in a surrounding manner;
the packaging substrate is provided with a plurality of through holes for a plurality of interconnection structures to pass through, the cofferdam is positioned on the inner sides of the plurality of through holes, the interconnection structures comprise metal column structures, soldering tin and electroplated layer structures, the metal column structures conduct the electrodes, the electroplated layer structures conduct the external pins, and the soldering tin is used for conducting the metal column structures and the electroplated layer structures.
As a further improvement of an embodiment of the present invention, the metal pillar structure includes a metal pillar and a UBM layer for conducting the metal pillar and the electrode, the plating layer structure includes a plating seed layer covering the inner wall of the through hole and extending to the upper surface of the substrate and the lower surface of the substrate, and a plating layer located outside the plating seed layer and matching with the plating seed layer, and the solder coats the metal pillar and extends to the through hole to conduct the plating layer on the inner wall of the through hole.
As a further improvement of an embodiment of the present invention, a width of the plating layer structure extending to the upper surface of the substrate is smaller than a width of the plating layer structure extending to the lower surface of the substrate.
As a further improvement of an embodiment of the present invention, the outer ring area of the upper surface of the solder is flush with the upper surface of the plating structure.
As a further improvement of an embodiment of the present invention, the upper surface of the plating layer structure and the lower surface of the electrode have an overlap region and a gap therebetween.
As a further improvement of an embodiment of the invention, gaps are arranged between the cofferdam and the through holes.
As a further improvement of an embodiment of the present invention, the package structure further includes a plastic layer located on a side of the package substrate away from the lower surface of the substrate, the plastic layer simultaneously covers the outer area of the dam and the filter chip, and the package structure further includes a solder mask layer disposed on the lower surface of the substrate and exposing the external pins.
In order to achieve one of the above objects, an embodiment of the present invention provides a method for manufacturing a chip package structure with a single dam, a metal pillar and solder, comprising the steps of:
S1: providing a filter chip, wherein the filter chip is provided with a chip upper surface and a chip lower surface which are oppositely arranged, and the chip lower surface is provided with a plurality of electrodes;
s2: forming a metal column structure on the lower surface of the electrode;
s3: providing a packaging substrate, wherein the packaging substrate is provided with a substrate upper surface and a substrate lower surface which are oppositely arranged;
s4: forming a plurality of through holes on the packaging substrate;
s5: forming a plating layer structure on the inner wall of the through hole, the upper surface of the substrate connected with the inner wall of the through hole and the lower surface of the substrate;
s6: forming a cofferdam on the upper surface of the substrate;
s7: assembling the filter chip to the packaging substrate, wherein the lower surface of the chip and the upper surface of the substrate are arranged face to face, the cofferdam is positioned at the inner sides of the through holes, and the cofferdam is matched with the lower surface of the chip and the upper surface of the substrate to form a cavity;
s8: forming soldering tin for conducting the metal column structure and the electroplated layer structure on the periphery of the metal column structure;
s9: and forming external pins under the electroplated layer structure.
As a further improvement of one embodiment of the present invention,
the step S2 specifically comprises the following steps:
sequentially forming a UBM layer and a metal column on the lower surface of the electrode;
The step S5 specifically comprises the following steps:
forming an electroplating seed layer on the inner wall of the through hole, the upper surface of part of the substrate connected with the inner wall of the through hole and the lower surface of all the substrates;
forming a second photoresist film below the electroplating seed layer on the lower surface of the substrate, and exposing and developing the second photoresist film to form a plurality of second holes, wherein the second holes expose the through holes and the electroplating seed layer;
forming a plating layer on the exposed plating seed layer;
removing the second photoresist film;
the exposed electroplating seed layer is removed.
As a further improvement of an embodiment of the present invention, the steps S8 and S9 specifically include:
forming a plastic layer on one side of the packaging substrate, which is far away from the lower surface of the substrate, wherein the plastic layer simultaneously covers the cofferdam outer side area and the filter chip, and a plurality of metal columns extend towards a plurality of through holes;
forming soldering tin on the periphery of the metal column, wherein the soldering tin extends to the through hole and is connected with a plating layer on the inner wall of the through hole;
forming a solder mask layer on the lower surface of the substrate, wherein the solder mask layer simultaneously covers the lower surface of the substrate, the electroplated layer and the soldering tin;
exposing and developing the solder mask layer to form a plurality of third holes, wherein the third holes expose the electroplated layer;
And forming a ball grid array in the third holes.
Compared with the prior art, the invention has the beneficial effects that: according to the embodiment, the cofferdam is arranged to form the cavity, so that the influence on the normal use of the filter chip caused by the fact that external substances enter the cavity in the manufacturing process of the packaging structure or the use process of the packaging structure can be effectively avoided, and the overall performance of the packaging structure is improved.
Drawings
Fig. 1 is a cross-sectional view of a package structure according to a first embodiment of the present invention;
FIG. 2 is a schematic view of a package substrate and a dam according to a first embodiment of the present invention;
fig. 3 is a step diagram of a method for manufacturing a package structure according to a first embodiment of the present invention;
FIGS. 4 a-4 v are flowcharts illustrating a method for fabricating a package structure according to a first embodiment of the present invention;
fig. 5 is a cross-sectional view of a package structure according to a second embodiment of the present invention;
FIG. 6 is a schematic view of a package substrate and a dam according to a second embodiment of the present invention;
fig. 7 is a step diagram of a method for manufacturing a package structure according to a second embodiment of the present invention;
FIGS. 8 a-8 w are flowcharts illustrating a method for fabricating a package structure according to a second embodiment of the present invention;
fig. 9 is a cross-sectional view of a package structure according to a third embodiment of the present invention;
FIG. 10 is a schematic view of a package substrate and a dam according to a third embodiment of the present invention;
Fig. 11 is a step diagram of a method for manufacturing a package structure according to a third embodiment of the present invention;
fig. 12 a-12 w are flowcharts illustrating a method for fabricating a package structure according to a third embodiment of the present invention.
Detailed Description
The present invention will be described in detail below with reference to specific embodiments shown in the drawings. These embodiments are not intended to limit the invention and structural, methodological, or functional modifications of these embodiments that may be made by one of ordinary skill in the art are included within the scope of the invention.
In the various illustrations of the present application, certain dimensions of structures or portions may be exaggerated relative to other structures or portions for convenience of illustration, and thus serve only to illustrate the basic structure of the subject matter of the present application.
In addition, terms such as "upper", "above", "lower", "below", and the like, used herein to denote spatially relative positions are used for convenience of description to describe one element or feature relative to another element or feature as illustrated in the figures. The term spatially relative position may be intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
Referring to fig. 1, a cross-sectional view of a chip package structure 100 with a single dam according to a first embodiment of the present invention is shown.
The package structure 100 includes a package substrate 10, a filter chip 20, a plurality of interconnect structures 30, and a dam 40.
The package substrate 10 has a substrate upper surface 11 and a substrate lower surface 12 disposed opposite to each other, and one side of the substrate lower surface 12 has a plurality of external pins 121.
Here, the package substrate 10 is a carrier plate for carrying chips, and the package substrate 10 may be a printed circuit board made of an organic resin, a glass substrate, a ceramic substrate, or the like.
The external pins 121 may be Ball Grid Array (BGA), pads, etc., and the package structure 100 may be electrically connected to other chips or substrates through the external pins 121, where the external pins 121 take the BGA 121 as an example, and the external pins 121 protrude from the lower surface of the package structure 100.
The filter chip 20 has a chip upper surface 21 and a chip lower surface 22 disposed opposite to each other, the chip lower surface 22 being disposed opposite to the substrate upper surface 11, the chip lower surface 22 having a plurality of electrodes 221.
Here, the filter chip 20 may be a surface acoustic wave filter chip (Surface Acoustic Wave, SAW) or a bulk acoustic wave filter chip (Bulk Acoustic Wave, BAW), but not limited thereto, an Active Zone (Active Zone) on the surface of the filter chip 20 needs to be able to work normally without contact or coverage of foreign objects, that is, a cavity needs to be formed under the filter chip 20 to protect the Active Zone.
The electrode 221 protrudes from the chip lower surface 22 in a direction away from the chip upper surface 21, but is not limited thereto.
In general, the size of the filter chip 20 is smaller than the size of the package substrate 10.
The interconnect structures 30 are used to conduct the electrodes 221 and the external pins 121.
The dam 40 cooperates with the chip lower surface 22 and the substrate upper surface 11 to define a cavity S corresponding to the active area of the surface of the filter chip 20.
Here, the package substrate 10 has a plurality of through holes 13 through which the plurality of interconnection structures 30 pass, and the dam 40 is located inside the plurality of through holes 13.
It should be noted that "the package substrate 10 has a plurality of through holes 13 through which the plurality of interconnection structures 30 pass" means that at least part of the structures of the interconnection structures 30 pass through the corresponding through holes 13, thereby realizing interconnection of the electrodes 221 and the external pins 121.
In this embodiment, the cofferdam 40 is provided to form the cavity S, so that the influence of the external substances entering the cavity S during the manufacturing process of the package structure or the use process of the package structure on the normal use of the filter chip 20 can be effectively avoided, thereby improving the overall performance of the package structure 100.
Referring to fig. 2, a plurality of through holes 13 are distributed on the upper surface 11 of the substrate in an array, and a space is provided between two rows of through holes 13, wherein a cofferdam 40 is located in the space, and the cofferdam 40 is located inside the plurality of through holes 13.
The dam 40 is a closed ring structure, the lower surface 22 of the chip covers the upper surface of the dam 40, and the upper surface 11 of the substrate covers the lower surface of the dam 40, so that the dam 40, the lower surface 22 of the chip and the upper surface 11 of the substrate cooperate with each other to form a closed cavity S.
The cofferdam 40 has gaps with the through holes 13.
The bank 40 is made of a photosensitive insulating material, but is not limited thereto.
In this embodiment, the package structure 100 further includes a plastic layer 50 that encapsulates the outer region of the dam 40 and the filter chip 20, and the plastic layer 50 is located on a side of the package substrate 10 away from the substrate lower surface 12.
Here, the "region outside the dam 40" refers to all open regions on the side of the dam 40 away from the cavity S, that is, all open regions around the filter chip 20 are covered by the plastic layer 50, and the plastic layer 50 is located above the package substrate 10.
The plastic layer 50 can be a EMC (Epoxy Molding Compound) plastic layer, and since the cofferdam 40 is utilized to block external substances from entering the cavity S in this embodiment, whether the plastic layer 50 will affect the protection area in the cavity S due to material problem is not required, so the selection range of the plastic layer 50 material is greatly enlarged, and further the selection of specific plastic material can be avoided, the plastic packaging process window is greatly widened, and the cost is effectively reduced.
In this embodiment, the package structure 100 further includes a solder mask layer 60 disposed on the lower surface 12 of the substrate and exposing the external leads 121.
With continued reference to fig. 1 and 2, in the present embodiment, the interconnect structure 30 includes a metal pillar structure 31 and a metal layer structure 32 that are cooperatively interconnected, the metal pillar structure 31 is connected to the electrode 221, and the metal layer structure 32 is connected to the external pin 121.
Specifically, the metal pillar structure 31 includes a metal pillar 311 and a UBM layer 312 that conducts the metal pillar 311 and the electrode 221, the metal layer structure 32 includes a metal layer 321 and a plating seed layer 322 that conducts the metal layer 321 and the metal pillar 311, the metal layer structure 32 fills the inner region of the via hole 13 and extends to the lower surface 12 of the substrate, and the lower portion of the metal layer 321 is connected to the external pin 121.
The outer contours of the plating seed layer 322 and the metal layer 321 are matched with each other, the plating seed layer 322 extends along the inner wall of the through hole 13 towards the lower surface 12 of the substrate, the metal layer 321 fills the through hole 13 and extends along the lower surface 12 of the substrate, and the lower surface of the metal layer 321 is a plane.
The region of the lower surface 12 of the substrate away from the through hole 13 is also provided with a plating seed layer 322, a metal layer 321, and external leads 121.
Here, the metal pillar 311 is a copper pillar 311, the metal layer 321 is a copper layer 321, and the ubm layer 312 and the plating seed layer 322 may be Ti/Cu layers, but not limited thereto.
The UBM layer 312 is used as a transition layer between the copper pillar 311 and the electrode 221, which can effectively reduce the molding difficulty of the copper pillar 311, improve the molding and fixing effects of the copper pillar 311, and improve the electrical transmission performance between the copper pillar 311 and the electrode 221.
Similarly, the plating seed layer 322 is used as a transition layer between the copper pillar 311 and the copper layer 321 and between the copper layer 321 and the package substrate 10, so as to effectively reduce the molding difficulty of the copper layer 321, improve the molding and fixing effects of the copper layer 321, and improve the electrical transmission performance between the copper pillar 311 and the copper layer 321.
The upper surface of the metal layer structure 32 has a recess 323 accommodating the metal pillar structure 31, and in this embodiment, the recess 323 accommodates only a portion of the copper pillar 311, and the ubm layer 312 is located outside the recess 323.
Here, the recess 323 may be a structure with an opening at the upper portion and closed all around, and the copper pillar 311, the recess 323 and the through hole 13 are disposed in a matching manner: (1) The grooves 323 and the copper columns 311 are mutually aligned, the grooves 323 play a limiting role on the copper columns 311, the alignment precision and the final product yield in the packaging process are improved, the difficulty of the packaging process is reduced, and the position of the filter chip 20 is fixed at the moment, so that the problem of chip drift is avoided; (2) The copper post 311 occupies a part of the space of the through hole 13, so that the electroplating amount of the copper layer 321 can be reduced when the copper layer 321 is electroplated in the through hole 13, the electroplating process difficulty is reduced, the electroplating time is shortened, and the electroplating productivity is further improved; (3) The copper pillar 311 has a remarkable appearance, and can be used as a recognition part to improve recognition efficiency, thereby facilitating automatic appearance detection and possible defect recognition.
In the present embodiment, the outer ring region of the upper surface of the metal layer structure 32 is flush with the substrate upper surface 11.
That is, the upper surface of the plating seed layer 322 is located in the same plane as the substrate upper surface 11 except for the recessed areas 323.
The upper surface of the metal layer structure 32 and the lower surface of the electrode 221 have an overlap region and a gap therebetween, and the cross-sectional area of the UBM layer 312 is smaller than the surface area of the electrode 221, and the cross-sectional area of the copper pillar 311 is equal to the cross-sectional area of the UBM layer 312.
It can be seen that the UBM layer 312 is disposed in the middle region of the electrode 221, the copper pillar 311 is disposed corresponding to the UBM layer 312, and at this time, a gap is formed between the upper surface of the plating seed layer 322 and the lower surface of the electrode 221, and the gap and the extension thereof are filled with the molding layer 50.
An embodiment of the present invention further provides a method for manufacturing a chip package structure with a single dam, and the method for manufacturing the chip package structure with the single dam includes the following steps, in combination with the description of the chip package structure with the single dam 100 and fig. 3, 4a to 4 v:
s1: referring to fig. 4a, a filter chip 20 is provided, which has a chip upper surface 21 and a chip lower surface 22 disposed opposite to each other, the chip lower surface 22 having a plurality of electrodes 221;
S2: referring to fig. 4b to 4g, a plurality of first interconnection structures are formed on the lower surfaces of the plurality of electrodes 221;
the method comprises the following steps:
referring to fig. 4b, a UBM layer 312 is formed on the lower surface 22 of the chip;
referring to fig. 4c, a first photoresist film 70 is formed under the UBM layer 312;
referring to fig. 4d, a plurality of first holes 71 are formed in the first photoresist film 70 by exposure and development, the first holes 71 correspond to the electrodes 221, and the UBM layer 312 is exposed by the first holes 71;
referring to fig. 4e, a plurality of copper pillars 311 are formed in the plurality of first holes 71;
referring to fig. 4f, the first photoresist film 70 is removed;
referring to fig. 4g, the exposed UBM layer 312 is removed.
S3: referring to fig. 4h, a package substrate 10 is provided, which has a substrate upper surface 11 and a substrate lower surface 12 disposed opposite to each other;
s4: referring to fig. 4i, a plurality of through holes 13 are formed on the package substrate 10;
s5: referring to fig. 4j and 4k, a dam 40 is formed on the upper surface 11 of the substrate;
the method comprises the following steps:
referring to fig. 4j, a photosensitive insulating film 80 is disposed on the upper surface 11 of the substrate;
referring to fig. 4k, the exposure and development form a bank 40, the bank 40 being located inside the plurality of through holes 13 with a gap between the bank 40 and the through holes 13.
It should be noted that, since the individual package substrate 10 may be formed by dividing a wafer-level large substrate, when the dam 40 is formed, a plurality of the dams 40 may be directly formed on the large substrate, and then dividing the large substrate to obtain a single package substrate 10 with a single dam 40, so that the package efficiency may be greatly improved, and of course, the dam 40 may also be formed on the filter chip 20.
S6: referring to fig. 4l, the filter chip 20 is assembled to the package substrate 10, the lower surface 22 of the chip is arranged face to face with the upper surface 11 of the substrate, the cofferdam 40 is located at the inner side of the plurality of through holes 13, and the cofferdam 40 is matched with the lower surface 22 of the chip and the upper surface 11 of the substrate to form a cavity S;
s7: referring to fig. 4m to 4s, a second interconnect structure is formed to conduct the first interconnect structure, at least part of the first interconnect structure and the second interconnect structure passing through the via hole 13;
the method comprises the following steps:
referring to fig. 4m, a plastic layer 50 is formed on one side of the package substrate 10 away from the substrate lower surface 12, the plastic layer 50 simultaneously covers the outer area of the dam 40 and the filter chip 20, and a plurality of copper pillars 311 extend towards a plurality of through holes 13;
referring to fig. 4n, a continuous plating seed layer 322 is formed along the lower surface 12 of the substrate, the inner wall of the via hole 13, and the copper pillar 311;
referring to fig. 4o, a second photoresist film 90 is formed under the plating seed layer 322;
referring to fig. 4p, a plurality of second holes 91 are formed in the second photoresist film 90 by exposure and development, and the second holes 91 expose the through holes 13 and the plating seed layer 322;
referring to fig. 4q, a copper layer 321 is electroplated and filled in the second holes 91;
referring to fig. 4r, the second photoresist film 90 is removed;
referring to fig. 4s, the exposed plating seed layer 322 is removed.
S8: referring to fig. 4t to 4v, the external pins 121 are formed under the second interconnection structure.
The method comprises the following steps:
referring to fig. 4t, a solder mask layer 60 is formed on the lower surface 12 of the substrate, and the solder mask layer 60 covers the lower surface 12 of the substrate and the copper layer 321 at the same time;
referring to fig. 4u, a plurality of third holes 61 are formed in the solder mask layer 60 by exposure and development, and the third holes 61 expose the copper layer 321;
referring to fig. 4v, a ball grid array 121 is formed in the third holes 61.
Other descriptions of the method for manufacturing the package structure of the present embodiment may refer to the description of the package structure 100, and will not be repeated here.
Referring to fig. 5, a cross-sectional view of a package structure 100a according to a second embodiment of the present invention is shown.
For convenience of description, the structures of the present embodiment that are the same as or similar to those of the first embodiment are denoted by like numerals, and of course, the structures of the like numerals may have different roles, and other embodiments are required to be described below according to actual situations, which will not be repeated.
The package structure 100a includes a package substrate 10a, a filter chip 20a, a plurality of interconnect structures 30a, and a dam 40a.
The package substrate 10a has a substrate upper surface 11a and a substrate lower surface 12a disposed opposite to each other, and one side of the substrate lower surface 12a has a plurality of external leads 121a.
Here, the package substrate 10a is a carrier plate for carrying chips, and the package substrate 10a may be a printed circuit board made of an organic resin, a glass substrate, a ceramic substrate, or the like.
The external pins 121a may be Ball Grid Array (BGA), pads, etc., and the package structure 100a may be electrically connected to other chips or substrates through the external pins 121a, where the external pins 121a take the BGA 121a as an example, and the external pins 121a protrude from the lower surface of the package structure 100 a.
The filter chip 20a has a chip upper surface 21a and a chip lower surface 22a disposed opposite to each other, the chip lower surface 22a being disposed opposite to the substrate upper surface 11a, the chip lower surface 22a having a plurality of electrodes 221a.
Here, the filter chip 20a may be a surface acoustic wave filter chip (Surface Acoustic Wave, SAW) or a bulk acoustic wave filter chip (Bulk Acoustic Wave, BAW), but not limited thereto, an Active Zone (Active Zone) on the surface of the filter chip 20a needs to be in contact with or covered by no foreign object to work normally, that is, a cavity needs to be formed under the filter chip 20a to protect the Active Zone.
The electrode 221a protrudes from the chip lower surface 22a in a direction away from the chip upper surface 21a, but is not limited thereto.
In general, the size of the filter chip 20a is smaller than the size of the package substrate 10 a.
The interconnect structures 30a are used to conduct the electrodes 221a and the external pins 121a.
The bank 40a cooperates with the chip lower surface 22a and the substrate upper surface 11a to define a cavity S corresponding to the active area of the surface of the filter chip 20 a.
Here, the package substrate 10a has a plurality of through holes 13a through which the plurality of interconnection structures 30a pass, the dam 40a is located inside the plurality of through holes 13a, the interconnection structures 30a include solder structures 33a and plating structures 32a that are mutually matched and interconnected, the solder structures 33a conduct the electrodes 221a, and the plating structures 32a conduct the external pins 121a.
In this embodiment, the cofferdam 40a is provided to form the cavity S, so that the influence of the external substances entering the cavity S during the manufacturing process of the package structure or the use process of the package structure on the normal use of the filter chip 20a can be effectively avoided, thereby improving the overall performance of the package structure 100 a.
Referring to fig. 6, a plurality of through holes 13a are distributed on the upper surface 11a of the substrate in an array, and a space is formed between two rows of through holes 13a, wherein a cofferdam 40a is located in the space, and the cofferdam 40a is located inside the plurality of through holes 13 a.
The dam 40a is a closed ring structure, the lower surface 22a of the chip covers the upper surface of the dam 40a, and the upper surface 11a of the substrate covers the lower surface of the dam 40a, so that the dam 40a, the lower surface 22a of the chip, and the upper surface 11a of the substrate cooperate with each other to form a closed cavity S.
The bank 40a has gaps with the plurality of through holes 13 a.
The bank 40a is made of a photosensitive insulating material, but is not limited thereto.
In this embodiment, the package structure 100a further includes a molding layer 50a that encapsulates the outer region of the dam 40a and the filter chip 20a, and the molding layer 50a is located on a side of the package substrate 10a away from the substrate lower surface 12 a.
Here, the "outer region of the dam 40 a" means all open regions on the side of the dam 40a away from the cavity S, that is, the molding layer 50a covers all open regions around the filter chip 20a, and the molding layer 50a is located above the package substrate 10 a.
The plastic layer 50a may be a EMC (Epoxy Molding Compound) plastic layer, and since the cofferdam 40a is utilized to block external substances from entering the cavity S in this embodiment, whether the plastic layer 50a will affect the protection area in the cavity S due to material problems is not considered, so the selection range of the material of the plastic layer 50a is greatly enlarged, and further the selection of specific plastic materials can be effectively avoided, the plastic packaging process window is greatly widened, and the cost is reduced.
In this embodiment, the package structure 100a further includes a solder mask layer 60a disposed on the lower surface 12a of the substrate and exposing the external leads 121a.
With continued reference to fig. 5 and 6, in the present embodiment, the solder structure 33a includes the solder 331a and the UBM layer 312a for conducting the solder 331a and the electrode 221a, the plating layer structure 32a includes the plating seed layer 322a covering the inner wall of the through hole 13a and extending to the upper surface 11a of the substrate and the lower surface 12a of the substrate, and the plating layer 321a located outside the plating seed layer 322a and matching with the plating seed layer 322a, the solder 331a extends to the through hole 13a for conducting the plating layer 321a of the inner wall of the through hole 13a, and the lower portion of the plating layer 321a is connected to the external pin 121a.
The plating seed layer 322a and the plating layer 321a have outer contours matching each other, the plating seed layer 322a extends from the inner wall of the through hole 13a to the substrate upper surface 11a and the substrate lower surface 12a, respectively, and the plating layer 321a also extends from the inner wall of the through hole 13a to the substrate upper surface 11a and the substrate lower surface 12a, respectively, according to the arrangement region of the plating seed layer 322a, and the lower surface of the plating layer 321a is a plane.
The region of the lower surface 12a of the substrate away from the through hole 13a is also provided with a plating seed layer 322a, a plating layer 321a, and external leads 121a.
Here, the plating layer 321a is a copper layer 321a, and the ubm layer 312a and the plating seed layer 322a may be Ti/Cu layers, but not limited thereto.
The UBM layer 312a is used as a transition layer between the solder 331a and the electrode 221a, which can effectively reduce the molding difficulty of the solder 331a, improve the molding and fixing effects of the solder 331a, and improve the electrical transmission performance between the solder 331a and the electrode 221 a.
Similarly, the electroplating seed layer 322a is used as a transition layer between the copper layer 321a and the package substrate 10a, so that the molding difficulty of the copper layer 321a can be effectively reduced, and the molding and fixing effects of the copper layer 321a can be improved.
Here, the solder paste 331a extends from the UBM layer 312a into the through hole 13a, and contacts the copper layer 321a on the inner wall of the through hole 13a to realize electrical connection, so that the electrode 221a and the external pin 121a can be conducted.
The advantage of providing solder 331a and via 13a is: (1) The solder 331a is in a molten state during the reflow process, so that the through hole 13a can be filled and combined with the UBM layer 312a conveniently and effectively, and the combination effect is better; (2) The solder 331a can be in contact with the copper layer 321a of the whole inner peripheral wall of the through hole 13a, the contact area is large, the electrical transmission performance can be improved, and the bonding firmness of the solder 331a and the copper layer 321a can be improved; (3) The reflow soldering process for soldering 331a is simple, the production efficiency is high, the production cost can be greatly reduced, and the product delivery period can be shortened.
In the present embodiment, the width of the plating layer structure 32a extending to the substrate upper surface 11a is smaller than the width of the plating layer structure 32a extending to the substrate lower surface 12 a.
Here, on the one hand, the upper surface 11a and the lower surface 12a of the substrate are provided with the plating layer structure 32a, so that the bonding firmness of the plating layer structure 32a and the package substrate 10a can be improved; on the other hand, the width of the plating structure 32a on the lower surface 12a of the substrate is greater than the width of the plating structure 32a on the upper surface 11a of the substrate, so that the external pins 121a on the lower surface 12a of the substrate are far away from the through holes 13a, thereby facilitating the subsequent interconnection of the package structure 100a with other chips or other substrates.
The upper surface of the plating layer structure 32a and the lower surface of the UBM layer 312a have an overlapping area and a gap, and the cross-sectional area of the solder paste 331a is smaller than the cross-sectional area of the UBM layer 312 a.
It can be seen that UBM layer 312a is disposed on the lower surface area of electrode 221a, and solder paste 331a is disposed only on the middle area of UBM layer 312a, and at this time, there is a gap between the upper surface of copper layer 321a on the upper surface 11a of the substrate and UBM layer 312a, and the gap and its extension are filled with molding layer 50a.
An embodiment of the present invention further provides a method for manufacturing a package structure, and the method for manufacturing the package structure includes the following steps, in combination with the description of the package structure 100a and fig. 7, 8a to 8 w:
S1: referring to fig. 8a, a filter chip 20a is provided, which has a chip upper surface 21a and a chip lower surface 22a disposed opposite to each other, the chip lower surface 22a having a plurality of electrodes 221a;
s2: referring to fig. 8b to 8f, a UBM layer 312a is formed on the lower surface of the electrode 221a;
the method comprises the following steps:
referring to fig. 8b, a UBM layer 312a is formed on the lower surface 22a of the chip;
referring to fig. 8c, a first photoresist film 70a is formed under the UBM layer 312a;
referring to fig. 8d, a plurality of first holes 71a are formed in the first photoresist film 70a by exposure and development, the first holes 71a correspond to other areas of the removal electrode 221a, and the UBM layer 312a is exposed by the first holes 71 a;
referring to fig. 8e, the UBM layer 312a exposed by the first hole 71a is etched;
referring to fig. 8f, the first photoresist film 70a is removed.
S3: referring to fig. 8g, a package substrate 10a is provided, which has a substrate upper surface 11a and a substrate lower surface 12a disposed opposite to each other;
s4: referring to fig. 8h, a plurality of through holes 13a are formed on the package substrate 10 a;
s5: referring to fig. 8i to 8n, a plating layer structure 32a is formed on the inner wall of the through hole 13a and the upper surface 11a and the lower surface 12a of the substrate connected to the inner wall of the through hole 13a;
the method comprises the following steps:
referring to fig. 8i, a plating seed layer 322a is formed on a part of the upper surface 11a of the substrate and the entire lower surface 12a of the substrate connected to the inner wall of the through hole 13a;
Referring to fig. 8j, a second photoresist film 90a is formed under the plating seed layer 322a of the lower surface 12a of the substrate;
referring to fig. 8k, a plurality of second holes 91a are formed in the second photoresist film 90a by exposure and development, and the second holes 91a expose the through holes 13a and the plating seed layer 322a;
referring to fig. 8l, a copper layer 321a is formed on the exposed plating seed layer 322a;
referring to fig. 8m, the second photoresist film 90a is removed;
referring to fig. 8n, the exposed plating seed layer 322a is removed.
S6: referring to fig. 8o and 8p, a bank 40a is formed on the upper surface 11a of the substrate;
the method comprises the following steps:
referring to fig. 8o, a photosensitive insulating film 80a is disposed on the upper surface 11a of the substrate;
referring to fig. 8p, the exposure and development form the bank 40a, the bank 40a is located inside the plurality of through holes 13a with a gap between the bank 40a and the through holes 13 a.
It should be noted that, since the individual package substrate 10a may be formed by dividing a wafer-level large substrate, when the dam 40a is formed, a plurality of the dams 40a may be directly formed on the large substrate, and then dividing the large substrate to obtain the single package substrate 10a having the single dam 40a, so that the package efficiency may be greatly improved, and of course, the dam 40a may also be formed on the filter chip 20 a.
S7: referring to fig. 8q, the filter chip 20a is assembled to the package substrate 10a, the lower surface 22a of the chip is disposed opposite to the upper surface 11a of the substrate, the dam 40a is located inside the plurality of through holes 13a, and the dam 40a is matched with the lower surface 22a of the chip and the upper surface 11a of the substrate to form a cavity S;
s8: referring to fig. 8r to 8t, a conductive electrode 221a and a solder 331a of the plating layer structure 32a are formed on the UBM layer 312a;
the method comprises the following steps:
referring to fig. 8r, a molding layer 50a is formed on a side of the package substrate 10a away from the substrate lower surface 12a, the molding layer 50a simultaneously covers the outer area of the dam 40a and the filter chip 20a, and a plurality of UBM layers 312a are aligned to a plurality of through holes 13a;
referring to fig. 8s, the molding layer 50a is etched to expose the UBM layer 312a;
referring to fig. 8t, solder 331a is formed on the UBM layer 312a, and the solder 331a extends to the via hole 13a and conducts the copper layer 321a on the inner wall of the via hole 13 a.
S9: referring to fig. 8u to 8w, external pins 121a are formed under the plating structure 32 a.
The method comprises the following steps:
referring to fig. 8u, a solder mask layer 60a is formed on the lower surface 12a of the substrate, and the solder mask layer 60a covers the lower surface 12a of the substrate, the copper layer 321a and the solder 331a;
referring to fig. 8v, a plurality of third holes 61a are formed in the solder mask layer 60a by exposure and development, and the third holes 61a expose the copper layer 321a;
Referring to fig. 8w, a ball grid array 121a is formed in the third holes 61 a.
Other descriptions of the method for manufacturing the package structure 100a in this embodiment may refer to the above description of the package structure 100a, and will not be repeated here.
Referring to fig. 9, a cross-sectional view of a package structure 100b according to a third embodiment of the present invention is shown.
The package structure 100b includes a package substrate 10b, a filter chip 20b, a plurality of interconnect structures 30b, and a dam 40b.
The package substrate 10b has a substrate upper surface 11b and a substrate lower surface 12b disposed opposite to each other, and one side of the substrate lower surface 12b has a plurality of external leads 121b.
Here, the package substrate 10b is a carrier plate for carrying chips, and the package substrate 10b may be a printed circuit board made of an organic resin, a glass substrate, a ceramic substrate, or the like.
The external pins 121b may be Ball Grid Array (BGA), pads, etc., and the package structure 100b may be electrically connected to other chips or substrates through the external pins 121b, where the external pins 121b take the BGA 121b as an example, and the external pins 121b protrude from the lower surface of the package structure 100 b.
The filter chip 20b has a chip upper surface 21b and a chip lower surface 22b which are disposed opposite to each other, the chip lower surface 22b is disposed opposite to the substrate upper surface 11b, and the chip lower surface 22b has a plurality of electrodes 221b.
Here, the filter chip 20b may be a surface acoustic wave filter chip (Surface Acoustic Wave, SAW) or a bulk acoustic wave filter chip (Bulk Acoustic Wave, BAW), but not limited thereto, an Active Zone (Active Zone) on the surface of the filter chip 20b needs to be in contact with or covered by no foreign object to work properly, that is, a cavity needs to be formed under the filter chip 20b to protect the Active Zone.
The electrode 221b protrudes from the chip lower surface 22b in a direction away from the chip upper surface 21b, but is not limited thereto.
In general, the size of the filter chip 20b is smaller than the size of the package substrate 10 b.
The interconnect structures 30b are used to conduct the electrodes 221b and the external pins 121b.
The bank 40b cooperates with the chip lower surface 22b and the substrate upper surface 11b to define a cavity S corresponding to the active area of the surface of the filter chip 20 b.
Here, the package substrate 10b has a plurality of through holes 13b through which the plurality of interconnection structures 30b pass, the dam 40b is located inside the plurality of through holes 13b, the interconnection structures 30b include a metal pillar structure 31b, a solder 331b and a plating layer structure 32b, the metal pillar structure 31b conducts the electrode 221b, the plating layer structure 32b conducts the external pin 121b, and the solder 331b is used for conducting the metal pillar structure 31b and the plating layer structure 32b.
In this embodiment, the cofferdam 40b is provided to form the cavity S, so that the influence of the external substances entering the cavity S during the manufacturing process of the package structure or the use process of the package structure on the normal use of the filter chip 20b can be effectively avoided, thereby improving the overall performance of the package structure 100 b.
Referring to fig. 10, a plurality of through holes 13b are distributed on the upper surface 11b of the substrate in an array, and a space is formed between two rows of through holes 13b, wherein a cofferdam 40b is located in the space, and the cofferdam 40b is located inside the plurality of through holes 13 b.
The dam 40b is a closed ring structure, the lower surface 22b of the chip covers the upper surface of the dam 40b, and the upper surface 11b of the substrate covers the lower surface of the dam 40b, so that the dam 40b, the lower surface 22b of the chip, and the upper surface 11b of the substrate cooperate with each other to form a closed cavity S.
The bank 40b has gaps with the plurality of through holes 13 b.
The bank 40b is made of a photosensitive insulating material, but is not limited thereto.
In this embodiment, the package structure 100b further includes a plastic layer 50b that covers the outer area of the dam 40b and the filter chip 20b, and the plastic layer 50b is located on a side of the package substrate 10b away from the substrate lower surface 12 b.
Here, the "outer region of the dam 40 b" means all open regions on the side of the dam 40b away from the cavity S, that is, the molding layer 50b covers all open regions around the filter chip 20b, and the molding layer 50b is located above the package substrate 10 b.
The plastic layer 50b may be a EMC (Epoxy Molding Compound) plastic layer, and since the cofferdam 40b is utilized to block external substances from entering the cavity S in this embodiment, whether the plastic layer 50b will affect the protection area in the cavity S due to material problems is not considered, so the selection range of the material of the plastic layer 50b is greatly enlarged, and further the selection of specific plastic materials can be effectively avoided, the plastic packaging process window is greatly widened, and the cost is reduced.
In this embodiment, the package structure 100b further includes a solder mask layer 60b disposed on the lower surface 12b of the substrate and exposing the external leads 121b.
With continued reference to fig. 9 and 10, in the present embodiment, the metal pillar structure 31b includes the metal pillar 311b, the UBM layer 312b for conducting the metal pillar 311b and the electrode 221b, the plating layer structure 32b includes the plating seed layer 322b covering the inner wall of the via hole 13b and extending to the upper surface 11b of the substrate and the lower surface 12b of the substrate, and the plating layer 321b located outside the plating seed layer 322b and matching with the plating seed layer 322b, the solder 331b covers the metal pillar 311b and extends to the via hole 13b for conducting the plating layer 321b of the inner wall of the via hole 13b, and the external pin 121b is connected below the plating layer 321 b.
The plating seed layer 322b and the plating layer 321b have outer contours matching each other, the plating seed layer 322b extends from the inner wall of the through hole 13b to the substrate upper surface 11b and the substrate lower surface 12b, respectively, and the plating layer 321b also extends from the inner wall of the through hole 13b to the substrate upper surface 11b and the substrate lower surface 12b, respectively, according to the arrangement region of the plating seed layer 322b, and the lower surface of the plating layer 321b is a plane.
The region of the lower surface 12b of the substrate away from the through hole 13b is also provided with a plating seed layer 322b, a plating layer 321b, and an external lead b.
Here, the metal pillar 311b is a copper pillar 311b, the plating layer 321b is a copper layer 321b, the ubm layer 312b and the plating seed layer 322b may be Ti/Cu layers, but not limited thereto.
The UBM layer 312b is used as a transition layer between the copper pillar 311b and the electrode 221b, which can effectively reduce the molding difficulty of the copper pillar 311b, improve the molding and fixing effects of the copper pillar 311b, and improve the electrical transmission performance between the copper pillar 311b and the electrode 221 b.
Similarly, the electroplating seed layer 322b is used as a transition layer between the copper layer 321b and the package substrate 10b, so that the molding difficulty of the copper layer 321b can be effectively reduced, and the molding and fixing effects of the copper layer 321b can be improved.
Here, the solder 331b is coated on the outer portion of the lower end region of the copper pillar 311b, and the solder 331b extends downward into the through hole 13b and contacts the copper layer 321b on the inner wall of the through hole 13b to electrically connect the electrode 221b and the external pin 121b.
The advantages of providing the copper pillars 311b, solder 331b, and vias 13b are: (1) The solder 331b is in a molten state in the reflow process, so that the through hole 13b can be conveniently and effectively filled and combined with the copper column 311b, and the combination effect is better; (2) The solder 331b can be in contact with the copper layer 321b of the whole inner peripheral wall of the through hole 13b, the contact area is large, the electrical transmission performance can be improved, and the bonding firmness of the solder 331b and the copper layer 321b can be improved; (3) The copper column 311b occupies a part of the space of the through hole 13b, so that the raw material consumption of the solder 331b can be reduced when the solder 331b is arranged in the through hole 13b, the welding process difficulty of the solder 331b is reduced, the welding time is shortened, and the welding productivity is further improved; (4) The copper pillar 311b has a remarkable appearance, and can be used as a recognition part to improve recognition efficiency, thereby facilitating automatic appearance detection and possible defect recognition.
In the present embodiment, the width of the plating layer structure 32b extending to the substrate upper surface 11b is smaller than the width of the plating layer structure 32b extending to the substrate lower surface 12 b.
Here, on the one hand, the upper surface 11b and the lower surface 12b of the substrate are provided with the plating layer structure 32b, so that the bonding firmness of the plating layer structure 32b and the package substrate 10b can be improved; on the other hand, the width of the plating structure 32b on the lower surface 12b of the substrate is greater than the width of the plating structure 32b on the upper surface 11b of the substrate, so that the outer pins 121b on the lower surface 12b of the substrate are far away from the through holes 13b, thereby facilitating the subsequent interconnection of the package structure 100b with other chips or other substrates.
The outer ring area of the upper surface of the solder 331b is flush with the upper surface of the plating layer structure 32b, an overlapping area is provided between the upper surface of the plating layer structure 32b and the lower surface of the electrode 221b, the cross-sectional area of the UBM layer 312b is smaller than the surface area of the electrode 221b, and the cross-sectional area of the copper pillar 311b is equal to the cross-sectional area of the UBM layer 312 b.
It can be seen that the UBM layer 312b is disposed in the middle region of the electrode 221b, the copper pillar 311b is disposed corresponding to the UBM layer 312b, and at this time, a gap is formed between the upper surface of the copper layer 321b on the upper surface 11b of the substrate and the lower surface of the electrode 221b, and the gap and the extension thereof are filled with the molding layer 50b.
An embodiment of the present invention further provides a method for manufacturing a package structure, with reference to the description of the package structure 100b and fig. 11, 12a to 12w, the method includes the steps of:
s1: referring to fig. 12a, a filter chip 20b is provided, which has a chip upper surface 21b and a chip lower surface 22b disposed opposite to each other, the chip lower surface 22b having a plurality of electrodes 221b;
s2: referring to fig. 12b to 12g, a metal pillar structure 31b is formed on the lower surface of the electrode 221b;
the method comprises the following steps:
referring to fig. 12b, a UBM layer 312b is formed on the lower surface 22b of the chip;
referring to fig. 12c, a first photoresist film 70b is formed under the UBM layer 312b;
referring to fig. 12d, a plurality of first holes 71b are formed in the first photoresist film 70b by exposure and development, the first holes 71b correspond to the electrodes 221b, and the first holes 71b expose the UBM layer 312b;
referring to fig. 12e, a plurality of copper pillars 311b are formed in the plurality of first holes 71 b;
referring to fig. 12f, the first photoresist film 70b is removed;
referring to fig. 12g, the exposed UBM layer 312b is removed.
S3: referring to fig. 12h, a package substrate 10b is provided, which has a substrate upper surface 11b and a substrate lower surface 12b disposed opposite to each other;
s4: referring to fig. 12i, a plurality of through holes 13b are formed on the package substrate 10 b;
s5: referring to fig. 12j to 12o, a plating layer structure 32b is formed on the inner wall of the through hole 13b and the upper surface 11b and the lower surface 12b of the substrate connected to the inner wall of the through hole 13b;
The method comprises the following steps:
referring to fig. 12j, a plating seed layer 322b is formed on a part of the upper surface 11b of the substrate and the entire lower surface 12b of the substrate connected to the inner wall of the through hole 13 b;
referring to fig. 12k, a second photoresist mold 90b is formed under the plating seed layer 322b of the lower surface 12b of the substrate;
referring to fig. 12l, a plurality of second holes 91b are formed in the second photoresist mold 90b by exposure and development, and the second holes 91b expose the through holes 13b and the plating seed layer 322b;
referring to fig. 12m, a copper layer 321b is formed on the exposed plating seed layer 322b;
referring to fig. 12n, the second photoresist mold 90b is removed;
referring to fig. 12o, the exposed plating seed layer 322b is removed.
S6: referring to fig. 12p and 12q, a bank 40b is formed on the upper surface 11b of the substrate;
the method comprises the following steps:
referring to fig. 12p, a photosensitive insulating film 80b is disposed on the upper surface 11b of the substrate;
referring to fig. 12q, the exposure and development form a bank 40b, the bank 40b being located inside the plurality of through holes 13b with a gap between the bank 40b and the through holes 13 b.
It should be noted that, since the individual package substrate 10b may be formed by dividing a wafer-level large substrate, when the dam 40b is formed, a plurality of the dams 40b may be directly formed on the large substrate, and then dividing the large substrate to obtain a single package substrate 10b having a single dam 40b, so that the package efficiency may be greatly improved, and naturally, the dam 40b may also be formed on the filter chip 20 b.
S7: referring to fig. 12r, the filter chip 20b is assembled to the package substrate 10b, the lower surface 22b of the chip and the upper surface 11b of the substrate are arranged face to face, the cofferdam 40b is located at the inner side of the plurality of through holes 13b, and the cofferdam 40b is matched with the lower surface 22b of the chip and the upper surface 11b of the substrate to form a cavity S;
s8: referring to fig. 12s and 12t, solder 331b is formed on the periphery of the metal pillar structure 31b to conduct the metal pillar structure 31b and the plating layer structure 32 b;
the method comprises the following steps:
referring to fig. 12s, a molding layer 50b is formed on a side of the package substrate 10b away from the substrate lower surface 12b, the molding layer 50b simultaneously covers the outer area of the dam 40b and the filter chip 20b, and a plurality of copper pillars 311b extend toward a plurality of through holes 13 b;
referring to fig. 12t, solder 331b is formed on the periphery of the copper pillar 311b, and the solder 331b extends to the through hole 13b and conducts the copper layer 321b on the inner wall of the through hole 13 b.
S9: referring to fig. 12u to 12w, external pins 121b are formed under the plating structure 32 b.
The method comprises the following steps:
referring to fig. 12u, a solder mask layer 60b is formed on the lower surface 12b of the substrate, and the solder mask layer 60b covers the lower surface 12b of the substrate, the copper layer 321b and the solder 331b;
referring to fig. 12v, a plurality of third holes 61b are formed in the solder mask layer 60b by exposure and development, and the third holes 61b expose the copper layer 321b;
Referring to fig. 12w, a ball grid array 121b is formed in the third holes 31 b.
Other descriptions of the method for manufacturing the package structure 100b in this embodiment may refer to the description of the package structure 100b, and will not be repeated here.
The dam 40 (and 40a, 40 b) of the present invention is located inside the through hole 13, in other embodiments, the dam 40 may be located inside the through hole 13 and outside the through hole 13, and the outer edge of the dam 40 may be flush with the outer edge of the filter chip 20, or the outer edge of the dam 40 may be flush with the outer edge of the package substrate 10, or the outer edge of the dam 40 is located between the outer edge of the filter chip 20 and the outer edge of the package substrate 10, and so on.
In summary, the cavity S is formed by the cofferdam 40 in the present embodiment, which can effectively avoid the influence of the external substances entering the cavity S during the manufacturing process of the package structure or the use process of the package structure on the normal use of the filter chip 20, thereby improving the overall performance of the package structure 100; in addition, the interconnect structure 30 of the present embodiment has various forms, which can effectively improve the electrical transmission performance and the stability of the entire package structure 100.
It should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a separate embodiment, and that this description is for clarity only, and that the skilled artisan should recognize that the embodiments may be combined as appropriate to form other embodiments that will be understood by those skilled in the art.
The above list of detailed descriptions is only specific to practical embodiments of the present invention, and they are not intended to limit the scope of the present invention, and all equivalent embodiments or modifications that do not depart from the spirit of the present invention should be included in the scope of the present invention.
Claims (10)
1. A chip package structure with single dam, metal column and solder, comprising:
the packaging substrate is provided with a substrate upper surface and a substrate lower surface which are oppositely arranged, and one side of the substrate lower surface is provided with a plurality of external pins;
the filter chip is provided with a chip upper surface and a chip lower surface which are oppositely arranged, the chip lower surface and the substrate upper surface are arranged face to face, and the chip lower surface is provided with a plurality of electrodes;
A plurality of interconnection structures for conducting a plurality of electrodes and a plurality of external pins;
the cofferdam is matched with the lower surface of the chip and the upper surface of the substrate to form a cavity in a surrounding manner;
the packaging substrate is provided with a plurality of through holes for a plurality of interconnection structures to pass through, the cofferdam is positioned on the inner sides of the plurality of through holes, the interconnection structures comprise metal column structures, soldering tin and electroplated layer structures, the metal column structures conduct the electrodes, the electroplated layer structures conduct the external pins, and the soldering tin is used for conducting the metal column structures and the electroplated layer structures.
2. The package structure of claim 1, wherein the metal pillar structure comprises a metal pillar and a UBM layer for conducting the metal pillar and the electrode, the plating layer structure comprises a plating seed layer covering the inner wall of the through hole and extending to the upper surface of the substrate and the lower surface of the substrate, and a plating layer located outside the plating seed layer and matched with the plating seed layer, and the solder coats the metal pillar and extends to the through hole for conducting the plating layer on the inner wall of the through hole.
3. The package structure of claim 2, wherein a width of the plating structure extending to the upper surface of the substrate is less than a width of the plating structure extending to the lower surface of the substrate.
4. The package structure of claim 2, wherein an outer ring region of an upper surface of the solder is flush with an upper surface of the plated structure.
5. The package structure of claim 2, wherein an upper surface of the plating structure has an overlap region with a lower surface of the electrode and has a gap therebetween.
6. The package structure of claim 1, wherein gaps are provided between the dam and the plurality of through holes.
7. The package structure of claim 1, further comprising a plastic layer on a side of the package substrate away from the substrate lower surface, the plastic layer surrounding both the dam outer region and the filter chip, and further comprising a solder mask layer disposed on the substrate lower surface and exposing the external leads.
8. A method for manufacturing a chip packaging structure with a single cofferdam, metal columns and soldering tin is characterized by comprising the following steps:
s1: providing a filter chip, wherein the filter chip is provided with a chip upper surface and a chip lower surface which are oppositely arranged, and the chip lower surface is provided with a plurality of electrodes;
s2: forming a metal column structure on the lower surface of the electrode;
S3: providing a packaging substrate, wherein the packaging substrate is provided with a substrate upper surface and a substrate lower surface which are oppositely arranged;
s4: forming a plurality of through holes on the packaging substrate;
s5: forming a plating layer structure on the inner wall of the through hole, the upper surface of the substrate connected with the inner wall of the through hole and the lower surface of the substrate;
s6: forming a cofferdam on the upper surface of the substrate;
s7: assembling the filter chip to the packaging substrate, wherein the lower surface of the chip and the upper surface of the substrate are arranged face to face, the cofferdam is positioned at the inner sides of the through holes, and the cofferdam is matched with the lower surface of the chip and the upper surface of the substrate to form a cavity;
s8: forming soldering tin for conducting the metal column structure and the electroplated layer structure on the periphery of the metal column structure;
s9: and forming external pins under the electroplated layer structure.
9. The method of manufacturing a package as claimed in claim 8, wherein,
the step S2 specifically comprises the following steps:
sequentially forming a UBM layer and a metal column on the lower surface of the electrode;
the step S5 specifically comprises the following steps:
forming an electroplating seed layer on the inner wall of the through hole, the upper surface of part of the substrate connected with the inner wall of the through hole and the lower surface of all the substrates;
Forming a second photoresist film below the electroplating seed layer on the lower surface of the substrate, and exposing and developing the second photoresist film to form a plurality of second holes, wherein the second holes expose the through holes and the electroplating seed layer;
forming a plating layer on the exposed plating seed layer;
removing the second photoresist film;
the exposed electroplating seed layer is removed.
10. The method of manufacturing a package structure according to claim 9, wherein the steps S8 and S9 specifically include:
forming a plastic layer on one side of the packaging substrate, which is far away from the lower surface of the substrate, wherein the plastic layer simultaneously covers the cofferdam outer side area and the filter chip, and a plurality of metal columns extend towards a plurality of through holes;
forming soldering tin on the periphery of the metal column, wherein the soldering tin extends to the through hole and is connected with a plating layer on the inner wall of the through hole;
forming a solder mask layer on the lower surface of the substrate, wherein the solder mask layer simultaneously covers the lower surface of the substrate, the electroplated layer and the soldering tin;
exposing and developing the solder mask layer to form a plurality of third holes, wherein the third holes expose the electroplated layer;
and forming a ball grid array in the third holes.
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