JP2013089827A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which forms more improved pattern shapes of a resist layer, an intermediate layer, and a resist layer.SOLUTION: A semiconductor device manufacturing method comprises: forming a lower layer photoresist 7, an intermediate layer 8 of an inorganic material, and an upper layer photoresist 9; patterning the upper layer photoresist 9 to form an upper layer resist pattern 9a; installing a semiconductor substrate 1 in a chamber on a lower electrode; introducing a first reaction gas having a sulfur dioxide gas and an oxygen gas into the chamber to generate plasma and cutting off supply of a high-frequency power to the lower electrode to trim the upper layer resist pattern 9a; replacing the first reaction gas with a second reaction gas and supplying a high-frequency power to the lower electrode to etch the intermediate layer 8 by using the upper layer resist pattern 9a as a mask to form an intermediate layer pattern 8a; and replacing the second reaction gas with a third reaction gas to generate plasma and supplying a high-frequency power to the lower electrode to etch the lower layer photoresist layer 7 by using the intermediate layer pattern 8a as a mask.

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  In a semiconductor device such as a system LSI, complicated circuits having different wiring densities are formed on one chip. In addition, with the progress of miniaturization of semiconductor devices, it is required to pattern wirings and electrodes with high processing accuracy.

  Various techniques are known as a method for forming a mask used for patterning a conductive film or a semiconductor film with high accuracy.

  For example, after a lower resist layer, an intermediate layer, and an upper resist layer are sequentially applied and formed on a silicon film on a semiconductor substrate, a mask is formed by patterning the lower resist layer from the upper resist layer, and the mask is used. It is known to etch a silicon film. When forming the mask, first, the upper resist layer is patterned, the intermediate portion is etched using the pattern of the upper resist layer as a mask, and then the lower resist is etched using the intermediate layer as a mask. A mask is formed. As the intermediate layer, for example, an organic silicon layer, a silicon oxide film, or the like is formed. Further, a mixed gas of oxygen, sulfur dioxide, or oxygen gas is used as a reactive gas for etching the lower resist layer.

  As another mask formation method, after forming a polysilicon film, an antireflection film, and a resist pattern in order on a semiconductor substrate, the resist pattern is trimmed at the same time when the antireflection film is dry-etched. It is known to form. The pattern of the polysilicon film formed by sequentially etching the antireflection film and the polysilicon film using the mask is used as the gate electrode. In this case, oxygen and sulfur dioxide are used as the resist pattern trimming gas, and overetching conditions for trimming are determined in advance.

  As another mask forming method, a mask layer is formed by sequentially forming a two-layer mask layer and a resist pattern on a metal film on a semiconductor substrate, and then etching the two mask layers exposed from the resist pattern. The method is known. As a result, the metal film exposed from the two patterned mask layers is etched, and the patterned metal film is used as a wiring, a gate electrode, or the like.

  Of the two mask layers, a carbon-based resist layer is formed as a lower mask layer, and a siloxane layer is formed as an upper mask layer. Further, when etching the carbon resist layer under the siloxane layer pattern as a mask, a mixed gas of oxygen, sulfur oxide and helium is used as an etching gas. Further, in order to adjust the CD amount in the sparse and dense regions of the device pattern, the over-etching amounts of the two mask layers are changed, and the etching gas flow rate is changed.

JP 2002-372787 A JP 2005-26292 A JP 2010-98176 A

  When the three-layer structure of the lower photoresist layer, intermediate layer, and upper photoresist layer is used as a patterning mask formation method as described above, the line width is controlled by changing the etching conditions of the lower photoresist layer. Then, it becomes difficult to control the pattern shape of the lower resist layer.

  An object of the present invention is to provide a semiconductor device manufacturing method including a step of further improving the pattern shape in a step of forming a mask by patterning a three-layer structure of a resist layer, an intermediate layer, and a resist layer. It is in.

According to one aspect of the present embodiment, a lower photoresist layer, an intermediate layer of an inorganic material, and an upper photoresist layer are sequentially formed above a semiconductor substrate, and the upper photoresist layer is patterned to form an upper resist pattern. Forming a semiconductor substrate; placing the semiconductor substrate on a lower electrode in an etching chamber; and introducing a first reaction gas having sulfur dioxide gas and oxygen gas into the etching chamber to generate plasma. Cutting the supply of high-frequency power to the lower electrode and trimming the upper resist pattern; replacing the first reaction gas in the etching chamber with a second reaction gas; and Supply high frequency power, etch the intermediate layer using the upper resist pattern as a mask Forming an intermediate layer pattern; replacing the second reactive gas in the etching chamber with a third reactive gas to generate plasma; supplying the high-frequency power to the lower electrode; and masking the intermediate layer pattern And a step of etching the lower photoresist layer to form a lower resist pattern, and a method of manufacturing a semiconductor device is provided. Examples of inorganic materials include a silicon-containing antireflection film and a silicon oxide film. Further, helium may be included in the first reaction gas.
The objects and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims. It is understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not intended to limit the invention.

In this embodiment, in the step of forming a mask from a three-layer structure of a lower layer photoresist layer, an intermediate layer, and an upper layer photoresist layer, after patterning the upper layer photoresist layer to form an upper layer resist pattern, the upper layer resist pattern is trimmed. doing. In the trimming, a gas containing oxygen and sulfur dioxide is introduced into the chamber, and the supply of high-frequency power to the lower electrode on the side where the semiconductor substrate is placed in the chamber is cut off. Thus, trimming is performed by isotropic etching while forming a protective film of a sulfur compound that slows the etching rate on the surface of the upper resist pattern.
Therefore, excessive reduction of the upper resist pattern can be suppressed, trimming can be performed with good controllability by fine adjustment of the etching, and etching isotropic for trimming, so that the shape after trimming is from the initial shape. It becomes a similar shape and the pattern transferability is good.
When etching the intermediate layer and the lower layer photoresist layer using the upper layer resist pattern as a mask, a gas containing oxygen and sulfur dioxide is introduced into the chamber and high frequency power is supplied to the lower electrode in the chamber. . Thereby, anisotropic etching can be performed by increasing the etching component perpendicular to the semiconductor substrate surface.
Therefore, by etching the intermediate layer and the lower layer photoresist layer using the upper layer resist pattern as a mask, it is possible to control the fine line width and transfer the planar shape of the upper layer resist pattern to the intermediate layer and the lower layer photoresist layer in a good shape. can do.

1A and 1B are cross-sectional views illustrating a part of the method for manufacturing the semiconductor device according to the embodiment. 1C and 1D are cross-sectional views illustrating a part of the method for manufacturing the semiconductor device according to the embodiment. 1E and 1F are cross-sectional views illustrating a part of the method for manufacturing the semiconductor device according to the embodiment. 1G and 1H are cross-sectional views illustrating a part of the method for manufacturing the semiconductor device according to the embodiment. 1I and 1J are cross-sectional views illustrating a part of the method for manufacturing the semiconductor device according to the embodiment. 1K and 1L are cross-sectional views illustrating a part of the method for manufacturing the semiconductor device according to the embodiment. FIG. 2 is a cross-sectional view showing an example of an etching apparatus used for mask formation in the semiconductor device manufacturing method according to the embodiment. FIG. 3 is a plan view of a sparse pattern region and a dense pattern region of an upper resist pattern used in the method for manufacturing a semiconductor device according to the embodiment. FIG. 4 is a diagram illustrating a difference in CD shift amount depending on whether or not sulfur dioxide gas is added in trimming a resist pattern in the method for manufacturing a semiconductor device according to the embodiment. FIG. 5 is a diagram illustrating a relationship between the flow rate of sulfur dioxide gas and the CD shift amount in trimming a resist pattern in the method for manufacturing a semiconductor device according to the embodiment. FIG. 6 shows the CD shift amount of the sparse pattern region and the CD shift amount of the sparse pattern region / dense pattern region caused by the difference in the flow rate of the sulfur dioxide gas in the resist pattern trimming in the semiconductor device manufacturing method according to the embodiment. It is a figure which shows the relationship with the difference of. 7A to 7C are cross-sectional views illustrating a part of the method for manufacturing the semiconductor device according to the comparative example. FIG. 8 is a diagram showing the relationship between the overetching rate of the intermediate layer and the CD shift amount in the step of forming a mask from the three-layer structure in the method for manufacturing a semiconductor device according to the comparative example. FIG. 9 is a diagram showing the relationship between the over-etching rate of the lower photoresist layer and the CD shift amount in the step of forming a mask from a three-layer structure in the semiconductor device manufacturing method according to the comparative example. FIG. 10 is a diagram showing the relationship between the over-etching rate of the lower photoresist layer and the CD shift amount in the step of forming a mask from a three-layer structure in the semiconductor device manufacturing method according to the comparative example. FIG. 11 is a diagram showing the relationship between the CD shift amount of the lower photoresist layer and the sulfur dioxide gas flow rate in the step of forming a mask from a three-layer structure in the method of manufacturing a semiconductor device according to the embodiment and the comparative example. FIG. 12 is a diagram showing a relationship between plasma emission intensity and time of etching of the lower layer photoresist in the step of forming a mask from a three-layer structure in the method for manufacturing a semiconductor device according to the embodiment. FIG. 13 is a diagram illustrating the relationship between the etching shift amount of the lower photoresist and the protrusion amount of the element isolation region layer in the step of forming a mask from the three-layer structure in the method for manufacturing a semiconductor device according to the embodiment.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. In the drawings, similar components are given the same reference numerals.

  1A to 1I are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the embodiment. Next, steps required until a structure shown in FIG. 1A is formed will be described.

  First, a silicon oxide film 2a and a silicon nitride film 2b are sequentially formed as a hard mask film 2 on a silicon substrate 1 which is a semiconductor substrate by a CVD method, and a resist pattern (not shown) is formed thereon. Subsequently, the hard mask film 2 is etched using the resist pattern as a mask, thereby forming an opening 2c in the element isolation region. Further, the silicon substrate 1 is etched by, for example, a reactive ion etching method through the opening 2c of the hard mask film 2 to form an element isolation groove 1a.

  Subsequently, after forming a silicon oxide layer as the element isolation insulating layer 3 in the element isolation trench 1a and on the hard mask film 3, the element isolation insulating layer 3 is polished by chemical mechanical polishing (CMP) to form the element on the hard mask film 2. And is left as shallow trench isolation (STI) in the element isolation trench 1a. Thereafter, the hard mask film 2 is removed by wet etching. In the state where the hard mask layer 2 is removed, the element isolation insulating layer 3 protrudes from the upper surface of the silicon substrate 1. The amount of protrusion is adjusted by wet etching the element isolation insulating layer 3 through the opening 2c of the hard mask 2 before removal. The silicon substrate 1 has a dense pattern region I having a high density of gate electrodes and wirings, which will be described later, and a sparse pattern region II having a low density of gate electrodes and wirings.

Subsequently, steps required until the structure illustrated in FIG. 1B is formed will be described.
First, p-type impurities such as boron are ion-implanted into the silicon substrate 1 to form P wells 4a to 4f in the n-type MOS transistor formation region. In the p-type MOS transistor formation region, an n-type impurity is ion-implanted to form an N well (not shown). In these cases, the n-type or p-type ion-implanted region is covered with a resist pattern (not shown). Similarly, impurities are ion-implanted for adjusting the impurity concentration in the channel regions of the n-type MOS transistor formation region and the p-type MOS transistor formation region.

  After that, after a silicon oxide film is formed as a gate insulating film 5 on the silicon substrate 1 by a thermal oxidation method or a CVD method, for example, a polysilicon film 6 is formed as a patterning film on the gate insulating film 5 by a CVD method, for example. It is formed to a thickness of about 105 nm. Subsequently, a lower photoresist layer 7, an intermediate layer 8, and an upper photoresist layer 9 are formed on the polysilicon film 6.

  As the lower photoresist layer 7, for example, an i-line resist photoresist is applied on the polysilicon film 5 to a thickness of, for example, about 120 nm to 200 nm. Further, as the intermediate layer 8, an inorganic material layer, for example, a siloxane layer that is a silicon-containing layer is applied by spin coating, and is formed to a thickness of, for example, about 30 nm. Further, as the upper photoresist layer 9, for example, a photoresist for ArF excimer laser is applied on the intermediate layer 7 to a thickness of, for example, 130 nm. The upper photoresist layer 9, the lower photoresist layer 7, and the intermediate layer 8 are baked as necessary after coating.

  Subsequently, as illustrated in FIG. 1C, the upper photoresist layer 9 above the silicon substrate 1 is exposed using an exposure apparatus (not shown), and a latent image of electrodes and wiring shapes is formed on the upper photoresist layer 9. To form. Thereafter, the upper photoresist layer 9 is developed. Note that baking and cleaning of the upper resist 9 before or after development are appropriately performed.

  Thus, the upper photoresist layer 9 is patterned into an upper resist pattern 9a having the basic shape of the gate electrode in the MOS transistor formation region and the basic shape of the wiring in the wiring region (not shown).

  Next, the silicon substrate 1 is put into an etching apparatus, and the processes from trimming the upper resist pattern 9a to patterning the lower photoresist layer 7 are continuously performed. As an etching apparatus, an inductively coupled plasma (ICP) etching apparatus, a parallel electrode type plasma etching apparatus, or another etching apparatus is used. Hereinafter, the ICP etching apparatus shown in FIG. 2 will be described as an example of the etching apparatus.

  The ICP etching apparatus 51 has a structure as illustrated in FIG. In FIG. 2, an induction coil 54 is disposed above the chamber 52 via a quartz plate or a ceramic plate 53. The induction coil 54 is connected to a high frequency power source for generating plasma, for example, a high frequency (RF) source power source 55 having a frequency of 13, 56 MHz. In the chamber 52, a lower electrode 56 is attached so as to be opposed to the quartz plate or the ceramic plate 53 at an interval. The lower electrode 56 is connected to a high frequency power source for drawing plasma toward the substrate, for example, an RF bias power source 57 having a frequency of 13.56 MHz.

  The lower electrode 56 is attached to the inside of the electrostatic chuck 58 on the substrate stage 59, for example. A substrate temperature control unit (not shown) is attached in the substrate stage 59 below the electrostatic chuck 58. In FIG. 2, reference numeral 60 denotes a quartz window attached to the side wall of the chamber 52, reference numeral 61 denotes a gas source that supplies gas into the chamber 52, and reference numeral 62 denotes a DC power source that applies a potential to the electrostatic chuck 58. Show. In addition, supply / stop of gas supplied from the gas source 61, gas flow rate adjustment, on / off of the RF source power supply 55, RF bias power supply 57 and DC power supply 62, power adjustment, pressure control in the chamber 52, etc. Each is performed by a control device (not shown).

  The silicon substrate 1 which is a semiconductor wafer is transferred into the chamber 52 of the ICP etching apparatus 51 having such a structure, and is further placed on the lower electrode 56 via the electrostatic chuck 58. The temperature of the electrostatic chuck 58 is set within a range of, for example, 15 to 45 ° C., more preferably 20 to 40 ° C.

  In the chamber 52, first, as illustrated in FIG. 1D, the upper resist pattern 9a is trimmed to reduce its width and height. Trimming is performed, for example, in order to make the pattern width narrower than the exposure limit dimension of the upper photoresist layer 9. In this embodiment, the high frequency power supplied from the RF bias power source 57 to the lower electrode 56 is cut by a switch, for example, under the following conditions.

From the gas source 61 into the chamber 52, oxygen (O ₂ ) gas is, for example, ₂ to 100 sccm, sulfur dioxide (SO ₂ ) gas is, for example, 5 to 100 sccm, and helium (He) gas is inert gas. Is introduced at a flow rate of, for example, 0 to 200 sccm. In this case, the ratio x / y of the flow rate y of the O ₂ gas to the flow rate x of the SO ₂ gas is set in a range of 1 or more and 2 or less. Further, the pressure in the chamber 52 is set to 5 to 20 mTorr (0.165 to 2.67 Pa), for example, and the power of the RF source power supply 55 is set to 200 to 500 W and supplied to the induction coil 54. As a result, plasma is generated in the chamber 52, and the upper resist pattern 9a is trimmed in such a plasma atmosphere under the control of a time of about 5 seconds to 30 seconds.

In this case, since the intermediate layer 8 is formed of an inorganic material, it is hardly etched. The polymer of the sulfur-containing compounds on the surface of the upper resist pattern 9a is formed by the reaction of organic matter and SO ₂ contained in the upper resist pattern 9a. As a result, the etching rate is reduced as compared with the case where SO ₂ is not included in the etching gas. In addition, since the RF bias power at the time of etching is not supplied to the lower electrode 56, the movement of the etchant in the vertical direction with respect to the surface of the silicon substrate 1 is relaxed, and etching is performed more isotropically. Thereby, the trimming of the upper resist pattern 9a is performed with good controllability, and the pattern is reduced to a shape almost similar to the initial state.

  Next, as illustrated in FIGS. 1E and 1F, the trimmed upper resist pattern 9a is used as a mask, and the intermediate layer 8 is etched under the following conditions, for example.

The first reaction gas introduced from the gas source 61 into the chamber 52 is replaced with the second reaction gas. As the second reaction gas, for example, methane (CF ₄ ) gas is introduced at a flow rate of, for example, 50 to 200 sccm. In this case, trifluoromethane (CHF ₃ ) gas may be added to methane gas at a flow rate of, for example, 100 sccm or less, and He gas, for example, at a flow rate of, for example, 200 sccm or less. The pressure in the chamber 52 is set to 3 to 20 mTorr (0.399 to 2.67 Pa), for example.

  Further, the power of the RF source power supply 55 is set to 200 to 1000 W, and the power of the RF bias power supply 57 is set to 50 to 300 W. The respective powers are supplied to the induction coil 54 and the lower electrode 56. Under such conditions, plasma is generated in the chamber 52 and the intermediate layer 8 is etched. In the etching of the intermediate layer 7, a change in the plasma emission intensity is detected through the quartz window 60 and, for example, overetching of about 30 to 50% is performed. In this case, since high frequency power is supplied to the lower electrode 56, the number of etchants in the moving direction perpendicular to the surface of the silicon substrate 1 increases.

  By etching the intermediate layer 8, the planar shape of the upper resist pattern 9a is transferred to the intermediate layer 8, and the intermediate layer pattern 8a is formed. The upper resist pattern 9a remains on the intermediate layer pattern 8a.

  Subsequently, as illustrated in FIGS. 1F and 1G, the lower photoresist layer 7 is etched under the following conditions, for example, using the intermediate layer pattern 8a as a mask.

The second reaction gas introduced from the gas source 61 into the chamber 52 is replaced with the third reaction gas. As the third reaction gas, for example, O ₂ gas is introduced at a flow rate of, for example, ₅ to 100 sccm, SO ₂ gas is introduced at, for example, 5 to 100 sccm, and He gas that is an inert gas is introduced at a flow rate of, for example, 0 to 200 sccm. The ratio x / y of the O ₂ gas flow rate y to the SO ₂ gas flow rate x is set in the range of 1.0 to 2.0. Furthermore, the pressure in the chamber 52 is set to 5 to 20 mTorr, for example. The power of the RF source power supply 55 is set to 200 to 500 W, and the power of the RF bias power supply 57 is set to 50 to 300 W. The power is supplied to the induction coil 54 and the lower electrode 56, respectively. Under such conditions, plasma is generated in the chamber 52, and the lower resist layer 7 is etched. In this case, since high frequency power is supplied to the lower electrode 56, the number of etchants in the moving direction perpendicular to the surface of the silicon substrate 1 increases.

In the etching of the lower photoresist layer 7, when SO ₂ gas is not used, the sulfur-containing polymer is not formed on the side wall, so that the shape after the etching of the lower photoresist layer 7 tends to be a constricted overhang shape, for example. . Accordingly, the use of SO ₂ gas improves the shape maintenance and the mask transferability.

  In the etching of the lower photoresist layer 7, the end point is detected by a decrease in the plasma emission intensity, and overetching is performed from the end point detection time point. The overetching includes, for example, additional overetching for 2 to 5 seconds corresponding to the protruding amount of the element isolation insulating layer 3 in addition to the normal overetching.

  The patterned lower photoresist layer 7 becomes the lower resist pattern 7a. The upper resist pattern 9a on the intermediate layer pattern 8a is etched and removed simultaneously with the lower resist layer 7.

  Next, the silicon substrate 1 is taken out from the ICP etching apparatus 51, and further transferred to a chamber of another etching apparatus through a vacuum space. As another etching apparatus, for example, an ICP etching apparatus having the same structure as shown in FIG. 2 will be described. However, another plasma etching apparatus may be used.

  First, the silicon substrate 1 is placed on the lower electrode 56 via the electrostatic chuck 58 in the chamber 52 of the ICP etching apparatus 51. In this case, the temperature (first temperature) of the electrostatic chuck 58, that is, the substrate temperature, is the processing temperature (first temperature) from trimming the upper resist pattern 9a to forming the lower resist pattern 7a as illustrated in FIGS. 1C to 1G. 2 temperature), for example, about 60 ° C.

Subsequently, as illustrated in FIG. 1H, the polysilicon film 5 is etched halfway using the lower resist pattern 7a and the intermediate layer pattern 8a as a mask. As the etching conditions, for example, CF ₄ gas is introduced into the chamber 52 from the gas source 61 at a flow rate of, for example, 50 to 200 sccm, and sulfur hexafluoride (SF ₆ ) gas, for example, at a flow rate of 5 to 20 sccm. In this case, nitrogen (N ₂ ) gas may be introduced into the chamber 52 at a flow rate of 30 sccm or less and He gas, for example, at a flow rate of 100 sccm or less, and nitrogen trifluoride (NF _{3) is used} as an alternative gas for N _2. ) May be introduced at a flow rate of 20 sccm or less. Further, the pressure in the chamber 52 is set to 2 to 10 mTorr (0.266 to 1.33 Pa), for example, the power of the RF source power supply 55 is set to 300 to 600 W, and the power of the RF bias power supply 57 is set to 50 to 150 W. Each power is supplied to the induction coil 54 and the lower electrode 56. In this case, the etching is controlled in time, for example, about 45 seconds. In this case, in the etching of the polysilicon film 5, the intermediate layer pattern 8a is also etched and removed.

Next, as illustrated in FIG. 1I, the remaining polysilicon film 6 is etched using the lower resist pattern 7a as a mask. As an etching condition, for example, hydrogen bromide (HBr) gas is introduced into the chamber 52 from the gas source 61 at a flow rate of, for example, 200 to 400 sccm and oxygen (O ₂ ) gas of ₂ to 10 sccm. Further, the pressure in the chamber 52 is set to, for example, 5 to 50 mTorr (0.665 to 6.65 Pa), the power of the RF source power supply 55 is set to 200 to 500 W, and the power of the RF bias power supply 57 is set to 50 to 150 W. Each power is supplied to the induction coil 54 and the lower electrode 56. The etching is controlled based on the observation of the change in the plasma emission intensity, and proceeds to the next step. The etching time is about 10 seconds, for example.

Subsequently, the polysilicon film 6 is over-etched using the lower resist pattern 7a as a mask. As the over-etching condition, for example, HBr gas is introduced into the chamber 52 from the gas source 61 at a flow rate of, for example, 100 to 300 sccm, oxygen O ₂ gas is ₂ to 10 sccm, and He gas is 100 to 400 sccm. Further, the pressure in the chamber 52 is set to 60 to 120 mTorr (7.98 to 16.0 Pa), for example, the power of the RF source power supply 55 is set to 300 to 600 W, and the power of the RF bias power supply 57 is set to 10 to 300 W. Each power is supplied to the induction coil 54 and the lower electrode 56. The etching time is about 30 seconds, for example.

Thereby, the polysilicon film 6 left under the lower resist pattern 7a on each of the P wells 4a to 4f in the dense pattern region I and the sparse pattern region II becomes the gate electrodes 6a to 6a.
Used as 6f. Thereafter, the silicon substrate 1 is transferred to an ashing apparatus, and the lower resist pattern 7a is removed as shown in FIG. 1J.

Next, steps required until a structure shown in FIG. 1K is formed will be described.
First, n-type impurities such as arsenic or phosphorus are ion-implanted into the P wells 4a to 4f using the gate electrodes 6a to 6f above the P wells 4a to 4f surrounded by the element isolation insulating layer 3 as a mask. N-type extension regions 11a to 16a and 11b to 16b are formed. In this case, the N well (not shown) is covered with a resist pattern.
Subsequently, a p-type extension region (not shown) is formed in an N well (not shown) surrounded by the element isolation region 3. In this case, the P wells 4a to 4f are covered with a resist pattern (not shown).

Next, steps required until a structure shown in FIG. 1L is formed will be described.
First, after an insulating film, for example, a silicon oxide film is formed on the entire upper surface of the silicon substrate 1 by the CVD method, the insulating film is etched back and left as side walls 10a to 10f on the side surfaces of the gate electrodes 6a to 6f.

  Thereafter, n-type impurities are ion-implanted into the P wells 4a to 4f using the gate electrodes 6a to 6f and the side walls 10a to 10f as masks to form n-type source / drain regions 11s, 12s, 13s, 14s, and 15s. , 16s, 11d, 12d, 13d, 14d, 15d, and 16d. In this case, the N well (not shown) is covered with a resist pattern.

  Subsequently, using a gate electrode (not shown) and sidewall (not shown) above the N well (not shown) as a mask, p-type impurities are ion-implanted into the N well to form a p-type source / drain region ( (Not shown). In this case, the P wells 4a to 4f are covered with a resist pattern.

Thus, n-type MOS transistors T _{1 to} T ₆ are formed around the P wells 4 a to 4 f and the periphery thereof, and a p-type MOS transistor (not shown) is formed in the N well (not shown). Thereafter, although not particularly shown, an interlayer insulating film is formed on the silicon substrate 1, and conductive contact plugs connected to the n-type source / drain regions 11s to 16s and 11d to 16d are formed on the interlayer insulating film. Further, a multilayer wiring structure is formed thereon.

As described above, the present embodiment includes the step of forming a mask by patterning the three-layer structure of the lower resist layer 7, the intermediate layer 8, and the upper resist layer 9 in order from the top. As a mask forming step, first, the upper resist layer 9 is exposed and developed to form an upper resist pattern 9a, and then plasma is generated in an atmosphere in which SO ₂ and O ₂ are introduced using an etching apparatus. Thus, the upper resist pattern 9a is trimmed in the atmosphere as shown in FIG. 1D. The trimming is performed in a plasma atmosphere generated by cutting off the high frequency power supplied to the lower electrode 56 from the RF bias power source 57 shown in FIG. 2 and further supplying high frequency power to the induction coil 54. The flow rate of O ₂ gas is set to 1 to 2 times the flow rate of SO ₂ gas.

When the supply of high-frequency power to the lower electrode 56 is cut off in this way, the etching component in the direction perpendicular to the upper surface of the silicon substrate 1 is reduced. As a result, the trimming of the upper resist pattern 9a is more isotropic than in the prior art, and the upper resist layer 9 is prevented from becoming sharply thin. Moreover, since SO ₂ and O ₂ are included in the trimming gas, a polymer serving as a protective film is generated on the surface of the rising resist pattern 9a, and the surface shrinkage rate is prevented from increasing. In particular, when the upper layer resist pattern 9a is formed of an ArF resist, the controllability of trimming becomes important because the plasma resistance of the ArF photoresist is inferior to that of a KrF photoresist or i-line photoresist.

  However, if high frequency power is supplied to the lower electrode 56 during the trimming, the incident energy of the etchant to the upper photoresist layer 9 and the balance of the etchant reflected from the intermediate layer 8 of the inorganic material are lost. Thereby, the difference in the pattern shift amount between the dense pattern region I and the sparse pattern region II tends to increase. Further, since etching (trimming) is performed under the condition that the intermediate layer 8 is not substantially etched, there is no film to be etched other than the upper photoresist layer 9, and the etchant is consumed only for etching the upper photoresist layer 9. The As a result, the etching rate at the time of trimming of the upper resist pattern 9a as shown in FIG. 1D is increased, it becomes difficult to control the line width shift by trimming, and a desired shape cannot be obtained.

  Further, if the shape of the upper resist pattern 9a is poor, when the intermediate layer 8 and the lower photoresist layer 7 are etched using the upper resist pattern 9a as a mask, the pattern shape when the upper resist pattern 9a disappears fluctuates, resulting in a pattern edge. Roughness (LER: Line-Edge-Roughness) gets worse.

  On the other hand, according to the present embodiment in which high frequency power is not supplied to the lower electrode 56, the residual film shape and the residual film amount of the upper resist pattern 9a are stable, trimming is performed with high accuracy, and the pattern is almost the same as the initial shape. It can be reduced with high accuracy to be a similar shape. Further, when the intermediate layer 8 is etched using the upper resist pattern 9a as a mask to etch the intermediate layer pattern 8a and the lower photoresist layer 7, the disappearance of the upper resist pattern 9a is stabilized and the LER is improved.

By the way, when SO ₂ is added to O ₂ when trimming the upper layer resist pattern 9a, a thin protective layer is formed on the surface of the upper layer resist pattern 9a, thereby preventing rapid progress of etching. In addition, when SO ₂ is added when the lower photoresist film 7 is etched, a thin protective layer is formed on the surface of the upper resist pattern 9a, thereby preventing the etching from proceeding rapidly. For example, as illustrated in FIG. 3, in a trimming process for forming line or electrode-shaped resist patterns 21 and 22 in the dense pattern region I and the sparse pattern region II, SO ₂ gas is used as the O ₂ gas. When the case of adding and the case of not adding are compared, the test results illustrated in FIG. 4 are obtained.

According to FIG. 4, the trimming amounts ΔC / 2, ΔA, and ΔB at the sides and the tips of the resist patterns 21 and 22 in the dense pattern region I and the sparse pattern region II can be made substantially the same. Therefore, it can be seen that it is preferable to supply both the SO ₂ gas and the O ₂ gas to the plasma generation region when the resist patterns 21 and 22 are trimmed and etched.

  After trimming the upper resist pattern 9a thus formed, high frequency power is supplied to the lower electrode 56 to increase the number of etchants that move in the direction perpendicular to the surface of the silicon substrate 1. Thereby, the etching of the intermediate layer 8 and the lower photoresist layer 7 has high anisotropy in the vertical direction, and the sidewalls of the intermediate layer pattern 8a and the lower resist pattern 7a are substantially perpendicular to the surface of the silicon substrate 1. It becomes.

Further, in the process from trimming the upper resist pattern 9a to forming the lower resist pattern 7a, the temperature of the electrostatic chuck 58 is set within a relatively low temperature range of 15 to 45 ° C. And the controllability of the trimming amount and etching amount over time is improved. Furthermore, according to such a temperature of the electrostatic chuck 58, disappearance of the protective layer formed on the surfaces of the resist patterns 7a and 9a by the SO ₂ gas can be suppressed.

Next, the ratio of the gas flow rates of SO ₂ and O ₂ will be described.
When the O ₂ contained in the reaction gas supplied into the chamber 52 is kept constant and the SO ₂ gas flow rate is increased, the dense pattern region I and the sparse pattern are increased as the SO ₂ gas flow rate increases as illustrated in FIG. The difference in the CD shift amount of each resist pattern in region II is reduced. That is, as the flow rate of SO ₂ increases, the difference in the CD shift amount on the side of each resist pattern in the dense pattern region I and the sparse pattern region II decreases. The CD shift amount is a value obtained by subtracting the width of the mask from the width of the film pattern when the film pattern is formed by etching the film using the mask. The CD shift amount is also called a CD bias.

  When the relationship between the CD shift amount difference between the dense pattern region I and the sparse pattern region II and the CD shift amount of the sparse pattern region II is obtained based on FIG. 5, the relationship illustrated in FIG. 6 is obtained.

According to FIG. 6, it can be seen that the difference in the CD shift amount between the dense pattern region I and the sparse pattern region II becomes smaller as the proportion of the flow rate of the SO ₂ gas increases. Further, if the characteristic line shown in FIG. 6 is Y = αX + β, the inclination α is the case where the flow rate ratio of O ₂ gas and SO ₂ gas is 1, and the high frequency power supplied to the lower electrode 56 is 0 W. In this case, -0.182. Also, when supplied in the case the flow rate of O ₂ gas to SO ₂ gas is 2 a high-frequency power to the lower electrode 56, the slope α of the characteristic line becomes -0.353.

If the characteristic inclination α is reduced, even if the CD shift amount of the sparse pattern region II changes, the difference in the CD shift amount between the dense pattern region I and the sparse pattern region II can be reduced and stabilized. In order to achieve this, it is preferable not to supply high frequency power to the lower electrode 56 and to make the gas flow ratio of SO _{2 to} O ₂ close to 1. Further, since the etching rate decreases when the SO ₂ gas flow rate increases, the flow rate ratio of the SO ₂ gas to the O ₂ gas is preferably 2 or less.

  Next, as a comparative example, a process of patterning the intermediate layer 9 and the lower photoresist layer 7 without trimming the upper resist pattern 9a will be described.

  First, as illustrated in FIG. 7A, the upper resist pattern 9a is used as it is as an etching mask for the intermediate layer 8 without trimming, and the intermediate layer 8 is etched to form the intermediate layer pattern 8b. The layer pattern 8b is over-etched. Subsequently, as illustrated in FIG. 6B, the lower resist layer 7 is etched by using the upper resist pattern 9a and the intermediate layer pattern 8b as a mask to form the lower resist pattern 7b. Over-etching is performed to narrow the width of the lower layer resist pattern 7b, thereby reducing the thickness.

  In such a process, the etching time from the start of etching of the intermediate layer 8 in the region not covered by the upper resist pattern 9a to the exposure of the upper surface of the lower photoresist layer 7 below is 100%. In this case, the relationship between the subsequent overetching of the intermediate layer pattern 8b and the CD shift amount is the test result illustrated in FIG. Incidentally, the adjustment of the pattern width required by over-etching is, for example, about 10 nm. Therefore, according to FIG. 8, in order to set the CD shift amount of the intermediate pattern 8b to 10 nm, the overetching of the intermediate layer 8 is set to 192%, and the throughput is lowered. Therefore, adjusting the CD shift amount by overetching is not practical. In this embodiment, overetching is performed after the formation of the intermediate pattern 8a, but it is not such a long time.

Further, the etching of the lower resist layer 7 is started using the intermediate layer pattern 8b as a mask, and then the etching time until the polysilicon film 6 is exposed is set to 100%. The relationship is examined as shown in FIG. Here, the adjustment of the pattern width required by over-etching is about 10 nm, and in order to increase the CD shift amount by 10 nm, it is necessary to set the over-etching to 130%. In this embodiment, overetching is performed after the formation of the lower resist pattern 7a, but it is not such a long time.

  When the over-etching time is lengthened, the width of the lower resist pattern 7b becomes narrower, but the side surface of the pattern becomes an inversely tapered shape and the cross section becomes an inverted trapezoidal shape as shown in FIG. 7C. When the polysilicon film 6 is etched using the lower resist pattern 7b of the inverted trapezoidal shape as a mask, the upper shape of the gate electrode 6g becomes oblique and does not become a rectangular shape as shown by the wavy line in FIG. 7C. . Therefore, line width control by over-etching of the lower resist layer 7 is not preferable.

Further, when the total flow rate of SO ₂ gas and O ₂ gas used for forming the lower resist pattern 7b is made constant and the ratio of the flow rate of SO ₂ gas and O ₂ gas is changed, the characteristics shown in FIG. 10 are obtained. It is done. In FIG. 10, the wavy line indicates the CD shift amount of the dense pattern region I, and the solid line indicates the CD shift amount of the sparse pattern region II. According to FIG. 10, in order to increase the CD shift amount of the sparse pattern region by 10 nm, it is necessary to increase the SO ₂ gas flow rate by 7.3 sccm. Further, according to FIG. 10, the CD shift amount of the dense pattern region I and the sparse pattern region II can be matched or brought close by adjusting the SO ₂ gas flow rate. The CD shift amount to be performed does not necessarily become a desired line width. Therefore, it is preferable to narrow the line width by trimming the upper resist pattern 9a under the above conditions according to the present embodiment.

FIG. 11 shows the relationship between the flow rate of the SO ₂ gas and the CD shift amount with the total gas flow rate of O ₂ and SO ₂ used for etching the lower photoresist layer 7 being constant. In FIG. 11, the one-dot chain line and the two-dot chain line indicate the case where the flow rate ratio of O ₂ and SO ₂ is SO ₂ / O ₂ = x / (45−x), respectively, and the solid line is the flow ratio of O ₂ and SO ₂ . Is shown as SO ₂ / O ₂ = x / (30−x).

According to the slopes of the characteristic lines of the one-dot chain line and the two-dot chain line shown in FIG. 11, the CD shift amount with respect to the change in the flow rate of SO ₂ gas can be increased by 0.19 to 0.20 nm for every 0.1 sccm increase. In contrast, according to the gradient of the solid characteristic line, CD shift to the flow rate change of the SO ₂ gas, since it is possible to 0.14nm increasing the flow rate of the SO ₂ gas to each increased by 0.1 sccm, SO _The CD shift amount can be easily controlled by adjusting the flow rate of the _two gases. However, if the ratio of O ₂ is too low, the controllability is improved, but the etching (trimming) speed is reduced, so it is desirable that the flow rate of O ₂ with respect to SO ₂ is increased by 1 to 2 times.

  Incidentally, as described above, the over-etching after the formation of the lower resist pattern 7a is additionally over-etched according to the protrusion amount of the element isolation insulating layer 3 from the silicon substrate 1 for the following reason. is there.

  When the element isolation insulating layer 3 occupying about 50% or more of the upper surface of the silicon substrate 1 protrudes from the upper surface of the silicon substrate 1, the upper surface of the polysilicon film 6 on the silicon substrate 1 is reflected by the shape of the underlying layer to have irregularities. appear. Further, since the lower photoresist layer 7 is applied by spin coating, the upper surface thereof is formed almost flat. For this reason, the lower photoresist layer 7 is thinner in the region above the element isolation insulating layer 3 than in other regions.

In the case where the upper end of the element isolation insulating layer 3 and the upper surface of the silicon substrate 1 are flat, the lower photoresist layer 8 is not covered by the intermediate layer pattern 8a when etching of the lower photoresist layer 7 is completed. There is virtually no remaining. For this reason, as shown by the wavy line in FIG. 12, the plasma emission intensity of the predetermined wavelength rapidly decreases at the end of the etching, so that the over-etching can be completed in the original time.

On the other hand, when the element isolation insulating layer 3 protrudes from the silicon substrate 1, in the region that is not covered with the intermediate layer pattern 8a, as the etching of the lower photoresist layer 7 proceeds, the element isolation insulating layer 3 is first The polysilicon film 6 is exposed in this region. Following this, the polysilicon film 6 in other regions is exposed. Therefore, as shown by the solid line in FIG. 12, the plasma emission intensity gradually decreases until the polysilicon film 6 in the other region is exposed after the polysilicon film 6 above the element isolation insulating layer 3 is exposed. to continue.
For this reason, after the start of the decrease in the plasma emission intensity, after performing additional over-etching in a time corresponding to the protruding amount of the element isolation insulating layer 3, if the original over-etching is performed for a predetermined time, there is no protrusion. A similar CD shift amount can be obtained. In the over-etching, the O ₂ gas flow rate is set larger than the SO ₂ gas flow rate. For example, the O ₂ flow rate is set to 20 sccm, for example, and the SO ₂ flow rate is set to 10 sccm, for example.

  FIG. 13 shows the relationship between the protrusion amount of the element isolation insulating layer 3 and the CD shift amount when no additional overetching is performed. The larger the protrusion amount, the smaller the CD shift amount becomes, and the overetching becomes insufficient. Show.

  By the way, the apparatus used for trimming the upper resist pattern 9a and etching the intermediate layer 8 and the lower photoresist layer 7 is not limited to the ICP etching apparatus as shown in FIG. For example, a parallel plate type plasma etching apparatus may be used. In the parallel plate type plasma etching apparatus, a high frequency power source of 50 to 150 MHz, for example, is connected to the upper electrode disposed in the chamber. In addition, a high frequency power source of about several kHz to several tens of MHz is connected to the lower electrode on the side on which the substrate is placed in the chamber. When trimming the upper resist pattern 9a, the high frequency power to the lower electrode is connected. Is cut off and connected during etching of the intermediate layer 8 and the lower photoresist layer 7.

  Further, when using an apparatus that can greatly change the temperature of the electrostatic chuck, batch processing from trimming to polysilicon etching can be performed in one chamber. What is necessary is just to process the optimal temperature in that case similarly to the above.

  All examples and conditional expressions given here are intended to help the reader understand the inventions and concepts that have contributed to the promotion of technology, such examples and It is interpreted without being limited to the conditions, and the organization of such examples in the specification is not related to showing the superiority or inferiority of the present invention. While embodiments of the present invention have been described in detail, it will be understood that various changes, substitutions and variations can be made thereto without departing from the spirit and scope of the invention.

Next, features of the embodiment of the present invention will be described.
(Additional remark 1) The process of forming a lower layer photoresist layer, the intermediate | middle layer of an inorganic material, and an upper layer photoresist layer in order above a semiconductor substrate, the process of patterning the said upper layer photoresist layer, and forming the upper layer resist pattern, Placing a semiconductor substrate on the lower electrode in the etching chamber; introducing a first reactive gas having sulfur dioxide gas and oxygen gas into the etching chamber to generate plasma; Cutting the supply of high-frequency power and trimming the upper layer resist pattern; replacing the first reaction gas in the etching chamber with a second reaction gas; and supplying the high-frequency power to the lower electrode; Using the upper layer resist pattern as a mask, the intermediate layer is etched to form the intermediate layer pattern. Forming a plasma by generating a plasma by replacing the second reaction gas in the etching chamber with a third reaction gas, and using the intermediate layer pattern as a mask, And a step of etching the lower photoresist layer to form a lower resist pattern.
(Additional remark 2) The said 3rd reaction gas is a gas which has sulfur dioxide and oxygen, The manufacturing method of the semiconductor device of Additional remark 1 characterized by the above-mentioned.
(Additional remark 3) The manufacturing method of the semiconductor device of Additional remark 1 or Additional remark 2 characterized by the inert gas being contained in the said 1st reaction gas.
(Additional remark 4) Any one of Additional remark 1 thru | or Additional remark 3 characterized by the to-be-patterned film formed under the said lower layer photoresist layer including the process etched at least using the said lower layer resist pattern as a mask The manufacturing method of the semiconductor device as described in any one of.
(Supplementary note 5) The supplementary note 4 is characterized in that the first temperature of the semiconductor substrate during etching of the film to be patterned is set higher than the second temperature of the semiconductor substrate during trimming of the upper resist pattern. The manufacturing method of the semiconductor device of description.
(Additional remark 6) The said 2nd temperature is 15 to 45 degreeC, The manufacturing method of the semiconductor device of Additional remark 5 characterized by the above-mentioned.
(Appendix 7) The gas flow rate of the oxygen introduced into the etching chamber is 1 to 2 times the gas flow rate of the sulfur dioxide, according to any one of appendices 1 to 6. Semiconductor device manufacturing method.
(Additional remark 8) The said upper layer photoresist layer is formed from the material exposed by ArF laser, The manufacturing method of the semiconductor device as described in any one of additional remark 1 thru | or appendix 7 characterized by the above-mentioned.
(Supplementary note 9) The method for manufacturing a semiconductor device according to any one of supplementary notes 1 to 8, wherein an electrostatic chuck is arranged between the lower electrode and the semiconductor substrate.

1 Silicon substrate (semiconductor substrate)
3 element isolation insulating layers 4a to 4f P well
5 Gate insulating film 6 Polysilicon (film to be etched)
6a to 6f Gate electrode 7 Lower photoresist layer 8 Intermediate layer 9 Upper photoresist layer 10a to 10f Side walls 11a, 12a, 13a, 14a, 15a, 16a n-type extension regions 11b, 12b, 13b, 14b, 15b, 16b n Mold extension region 51 ICP etching device 52 chamber 53 quartz plate 54 induction coil 55 RF source power source 56 lower electrode 57 RF bias power source 58 electrostatic chuck 60 quartz window 61 gas source

Claims (5)

Forming a lower photoresist layer, an intermediate layer of an inorganic material, and an upper photoresist layer in order above the semiconductor substrate;
Patterning the upper photoresist layer to form an upper resist pattern;
Placing the semiconductor substrate on a lower electrode in an etching chamber;
Introducing a first reactive gas containing sulfur dioxide gas and oxygen gas into the etching chamber to generate plasma and cutting off the supply of high-frequency power to the lower electrode, and trimming the upper resist pattern;
The first reaction gas in the etching chamber is replaced with a second reaction gas, the high frequency power is supplied to the lower electrode, the upper layer resist pattern is used as a mask, and the intermediate layer is etched to form an intermediate layer Forming a pattern;
The second reaction gas in the etching chamber is replaced with a third reaction gas to generate plasma, the high-frequency power is supplied to the lower electrode, the intermediate layer pattern is used as a mask, and the lower photoresist layer Etching to form a lower resist pattern,
A method for manufacturing a semiconductor device, comprising:   The method for manufacturing a semiconductor device according to claim 1, wherein the third reaction gas is a gas containing sulfur dioxide and oxygen.   3. The semiconductor device manufacturing method according to claim 1, wherein the film to be patterned formed under the lower photoresist layer includes a step of etching using at least the lower resist pattern as a mask. Method.   4. The semiconductor according to claim 3, wherein a first temperature of the semiconductor substrate during etching of the patterning film is set higher than a second temperature of the semiconductor substrate during trimming of the upper layer resist pattern. Device manufacturing method.   The method of manufacturing a semiconductor device according to claim 4, wherein the second temperature is 15 ° C. to 45 ° C. 6.

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