JP2013084834A - Solid-state imaging element and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide: a solid-state imaging element that suppresses noise in a generated image and is easy to manufacture; and a method of manufacturing the solid-state imaging element.SOLUTION: A transfer transistor 3 includes: a p-type substrate 10; an n-type light receiving part 21 that is formed in the substrate 10, and stores electrons generated by photo-electric conversion; an n-type floating diffusion region 4 having a higher concentration of n-type impurities than the light receiving part 21 formed in the substrate 10; an insulating layer 31 disposed on the substrate 10; and an n-type gate electrode 32 disposed on the insulating layer 31 and at least between the light receiving part 21 and the floating diffusion region 4. The gate electrode 32 has a higher concentration of n-type impurities as going toward the floating diffusion region 4, and has a lower concentration of the n-type impurities as going toward the light receiving part 21.

Description

  The present invention relates to a solid-state image sensor represented by a complementary metal oxide semiconductor (CMOS) image sensor.

  In recent years, solid-state imaging devices such as CMOS image sensors have been installed not only in imaging devices such as digital video cameras and digital still cameras, but also in various electronic devices equipped with imaging functions such as mobile phones and PDAs (Personal Digital Assistants). ing. Further, such a solid-state imaging device is required to improve image quality by reducing noise in a generated image.

  One cause of the noise is, for example, dark current. The dark current is generated by the discharge of charges (for example, electrons) trapped at the interface state at the interface between the substrate and the insulating layer, and causes a white spot in the image. The dark current can be eliminated by canceling the charge released from the interface state, but a predetermined potential (for example, a negative potential) is separately required to generate a charge (for example, a hole) for canceling. This necessitates problems such as a complicated configuration of the solid-state imaging device and increased power consumption.

  Therefore, for example, Patent Document 1 proposes a CMOS image sensor that generates holes for canceling electrons forming a dark current without applying a negative potential to the gate electrode. This CMOS image sensor will be described with reference to the drawings. 9 and 10 are schematic cross-sectional views showing transfer transistors provided in a conventional CMOS image sensor. FIG. 9 shows the non-conducting state of the transfer transistor, and FIG. 10 shows the conducting state of the transfer transistor. FIG. 10 also shows a graph showing the potential of the transfer transistor in the conductive state.

As shown in FIGS. 9 and 10, the transfer transistor 100 of the conventional CMOS image sensor temporarily includes a substrate 101 made of a p-type (p-well) semiconductor, and a region in the substrate 101 that temporarily generates electrons generated by photoelectric conversion. Light receiving portion 102 made of an n-type (n) semiconductor, and a p-type (p ⁺ ) semiconductor formed on the light receiving portion 102 and having a higher p-type impurity concentration than the substrate 101. A pinning region 103 made of, a floating diffusion region 104 made of an n-type (n ⁺ ) semiconductor that is a region in the substrate 101 and has a higher n-type impurity concentration than the light receiving portion 102, and insulation formed on the upper surface of the substrate 101 Layer 105, gate electrode 106 formed on insulating layer 105 and between light receiving portion 102 and floating diffusion region 104, and silicide layer formed on gate electrode 106 107, a side wall 108 formed on the light receiving portion 102 side of the gate electrode 106, a side wall 109 formed on the floating diffusion region 104 side of the gate electrode 106, and a region in the substrate 101 that is directly below the side wall 109. And a low-concentration region 110 made of an n-type (n ⁻ ) semiconductor having a lower n-type impurity concentration than the floating diffusion region 104.

The gate electrode 106 of the transfer transistor 100 is made of polysilicon, the region 106a on the light receiving unit 102 side is made of a p-type (p ⁺ ) semiconductor, and the region 106b on the floating diffusion region 104 side is made of an n-type (n ⁺ ) semiconductor. ing.

  As shown in FIG. 9, when a potential of 0 V is applied to the silicide layer 107 in order to make the transfer transistor 100 nonconductive, electrons that form a dark current are formed on the surface of the substrate 101 under the region 106a in the gate electrode 106. Holes h that cancel out are collected. Therefore, the transfer transistor 100 can reduce dark current without applying a negative potential to the silicide layer 107 in a non-conductive state.

  Further, as shown in FIG. 10, when a positive potential + V is applied to the silicide layer 107 in order to make the transfer transistor 100 conductive, a positive potential is supplied to both the region 106a and the region 106b in the gate electrode 106, and the light receiving portion A potential monotonously decreasing from 102 to the floating diffusion region 104 is formed. Therefore, the transfer transistor 100 can efficiently read electrons e from the light receiving unit 102 to the floating diffusion region 104 in the conductive state.

JP 2008-166607 A

  In the transfer transistor 100 described above, the gate electrode 106 includes two regions 106a and 106b having different conductivity types. Therefore, it is necessary to separately provide a conductive layer (silicide layer 107) that is electrically connected to each of the two regions 106a and 106b. Furthermore, it is necessary to separately implant two types of impurities having different conductivity types into the two regions 106 a and 106 b of the gate electrode 106. Therefore, the number of processes inevitably increases, and the manufacturing process becomes complicated, and the number of necessary materials and instruments (for example, photomasks) increases, resulting in high costs.

  Further, since the silicide layer 107 needs to be electrically connected to each of the two regions 106a and 106b having different conductivity types, the silicide layer 107 is provided so as to cover the entire surface of the gate electrode 106. The formation of the silicide layer 107 requires a metal element. However, the metal element can contaminate the solid-state imaging device such as diffusing into the substrate 101. Accordingly, the contamination causes noise such as white spots in the image generated by the solid-state imaging device, which is a problem.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a solid-state imaging device that can be easily manufactured while suppressing noise in an image to be generated, and a manufacturing method thereof.

To achieve the above object, the present invention includes a substrate made of a first conductivity type semiconductor,
A light receiving portion made of a semiconductor of a second conductivity type different from the first conductivity type, which is formed in the substrate and accumulates electric charges generated by photoelectric conversion;
A floating diffusion region formed in the substrate, made of the second conductivity type semiconductor, and having a higher concentration of the second conductivity type impurity than the light receiving portion;
An insulating layer provided on the substrate;
A gate electrode of the second conductivity type provided on the insulating layer and at least between the light receiving portion and the floating diffusion region,
The gate electrode has a higher concentration of the second conductivity type impurity toward the floating diffusion region and a lower concentration of the second conductivity type impurity toward the light receiving portion. .

  In this solid-state imaging device, a potential that is larger toward the light receiving portion side and smaller toward the floating diffusion region side is formed under the gate electrode. Therefore, the electric charge generated under the gate electrode easily flows into the floating diffusion region along the potential gradient. Therefore, when accumulating charges in the light receiving portion (when the light receiving portion and the floating diffusion region are made non-conductive), it is possible to efficiently remove the charge forming the dark current under the gate electrode to the floating diffusion region. Become. Note that the charge eliminated in the floating diffusion region is excluded from the floating diffusion region to the outside by resetting the floating diffusion region. Thus, in this solid-state imaging device, dark current is reduced by a method different from that of the solid-state imaging device shown in FIG.

  Furthermore, this inclined potential can be formed simply by injecting a second conductivity type impurity into the gate electrode. Therefore, it is possible to suppress an increase in the number of processes accompanying the implantation of impurities into the gate electrode. Therefore, the complexity of the manufacturing process and the increase in cost can be suppressed. Further, in this solid-state imaging device, it is not necessary to provide a conductive layer (for example, the silicide layer 107 shown in FIGS. 9 and 10) covering the entire surface on the gate electrode. Therefore, it is possible to suppress contamination due to metal elements and the like contained in the conductive layer.

  Furthermore, in the solid-state imaging device having the above characteristics, the gate electrode is on the light receiving unit side and the floating diffusion region side, and the concentration of the second conductivity type impurity is higher than that of the first region. It is preferable to provide a high second region.

  In this solid-state imaging device, the implantation of the second conductivity type impurity into the gate electrode can be performed in two steps. Therefore, it is possible to suppress an increase in the number of processes accompanying the implantation of impurities into the gate electrode. Further, the second conductivity type impurity is simultaneously injected into the first region and the light receiving portion, or the second conductivity type impurity is simultaneously injected into the second region and the floating diffusion region, thereby reducing the number of steps. It is possible to implant the second conductivity type impurity into the gate electrode without increasing.

  Furthermore, it is preferable that the solid-state imaging device having the above characteristics further includes a contact plug electrically connected to the second region of the gate electrode.

  In this solid-state imaging device, a potential is applied to the second region via the contact plug, and a potential is also applied to the first region via the second region. Therefore, it is possible to apply a potential to both the first region and the second region simply by electrically connecting the contact plug to the second region.

Furthermore, in the solid-state imaging device having the above characteristics, the concentration of the second conductivity type impurity in the gate electrode is in the range of 1 × 10 ¹⁶ cm ^{−3 to} 5 × 10 ²⁰ cm ^−3. ,preferable.

  Furthermore, in the solid-state imaging device having the above characteristics, it is preferable that the gate electrode is made of polysilicon.

In addition, the method for manufacturing a solid-state imaging device according to the present invention includes a gate electrode forming step of forming an insulating layer on a substrate made of a first conductivity type semiconductor, and forming a gate electrode on the insulating layer.
A light receiving portion that accumulates charges generated by photoelectric conversion is implanted by injecting an impurity of a second conductivity type different from the first conductivity type into a region in the substrate on one end side of the gate electrode. A light receiving portion forming step to be formed;
Injecting the second conductivity type impurity into the region in the substrate on the other end side of the gate electrode so that the concentration of the second conductivity type impurity is higher than that of the light receiving portion, A floating diffusion region forming step for forming a floating diffusion region;
In the gate electrode, the concentration of the second conductivity type impurity is higher toward the floating diffusion region side, and the concentration of the second conductivity type impurity is lower toward the light receiving portion side. And a gate electrode impurity implantation step for implanting.

  In this method for manufacturing a solid-state imaging device, it is possible to manufacture a solid-state imaging device in which a potential that is larger toward the light receiving portion side and smaller toward the floating diffusion region side is formed under the gate electrode. In the solid-state imaging device, charges generated under the gate electrode easily flow into the floating diffusion region along the potential gradient. Therefore, when the solid-state imaging device accumulates charges in the light receiving portion (when the light receiving portion and the floating diffusion region are made non-conductive), the charge forming the dark current under the gate electrode is efficiently transferred to the floating diffusion region. It is possible to eliminate. Note that the charge eliminated in the floating diffusion region is excluded from the floating diffusion region to the outside by resetting the floating diffusion region. As described above, in the solid-state imaging device obtained by the manufacturing method of the solid-state imaging device, the dark current is reduced by a method different from the solid-state imaging device shown in FIG.

  Furthermore, in this method for manufacturing a solid-state imaging device, the above-described inclined potential is formed only by injecting a second conductivity type impurity into the gate electrode. Therefore, it is possible to suppress an increase in the number of processes accompanying the implantation of impurities into the gate electrode. Therefore, the complexity of the manufacturing process and the increase in cost can be suppressed. Further, in this method for manufacturing a solid-state imaging device, a conductive layer (silicide layer 107 shown in FIGS. 9 and 10) covering the entire surface on the gate electrode is not provided. Therefore, it is possible to suppress contamination due to metal elements and the like contained in the conductive layer.

Furthermore, in the method for manufacturing a solid-state imaging device having the above characteristics, the gate electrode impurity implantation step includes:
A first region impurity implantation step for implanting the second conductivity type impurity into the first region on the light receiving unit side;
The second conductivity type impurity is formed in the second region on the floating diffusion region side so as to be higher than the concentration of the second conductivity type impurity implanted into the first region in the first region impurity implantation step. It is preferable to include a second region impurity implantation step of implanting.

  In this solid-state imaging device manufacturing method, the gate electrode impurity implantation step can be performed in two steps. Therefore, it is possible to suppress an increase in the number of processes accompanying the implantation of the second conductivity type impurity into the gate electrode.

Furthermore, in the method for manufacturing a solid-state imaging device having the above characteristics, a first injection method for simultaneously performing the first region impurity injection step and the light receiving portion formation step
It is preferable to execute at least one of the second implantation method in which the second region impurity implantation step and the floating diffusion region formation step are performed simultaneously.

  In this solid-state imaging device manufacturing method, the second conductivity type impurity is also implanted into the gate electrode in conjunction with the implantation of the second conductivity type impurity into the floating diffusion region and the light receiving portion. Therefore, the second conductivity type impurity can be implanted into the gate electrode without increasing the number of steps.

  Furthermore, it is preferable that the method for manufacturing a solid-state imaging device of the above characteristics further includes a contact plug forming step of forming a contact plug electrically connected to the second region of the gate electrode.

  In this method of manufacturing a solid-state imaging device, it is possible to manufacture a solid-state imaging device that can apply a potential to both the first region and the second region simply by electrically connecting a contact plug to the second region. it can.

  Furthermore, it is preferable that the method for manufacturing a solid-state imaging device of the above characteristics further includes a heat treatment step of performing a heat treatment after the gate electrode impurity implantation step.

  In the transfer transistor 100 shown in FIGS. 9 and 10 described above, two regions 106 a and 106 b having different conductivity types are formed adjacent to the gate electrode 106. Therefore, since it is necessary to prevent compensation due to diffusion of impurities contained in the respective regions 106a and 106b, various problems arise, such as heat treatment being restricted and insufficient activation of impurities. However, in the method for manufacturing a solid-state imaging device having the above characteristics, only one kind of impurity is injected into the gate electrode. Therefore, even if the impurity is diffused by heat treatment, the concentration gradient is only moderated. Therefore, in this method for manufacturing a solid-state imaging element, it is possible to eliminate (or reduce) restrictions such as heat treatment.

  Furthermore, in the method for manufacturing a solid-state imaging device having the above characteristics, it is preferable that the heat treatment step is a heat treatment performed at 800 ° C. or higher.

  The first conductivity type and the second conductivity type described above are p-type and n-type. For example, if the semiconductor forming the substrate is p-type, the semiconductor forming the light receiving portion is n-type. For example, if the semiconductor forming the substrate is n-type, the semiconductor forming the light receiving portion is p-type. The “conductivity type of the semiconductor forming the substrate” is “conductivity type of the portion where the element structure of the substrate is formed”, and is not limited to indicating the conductivity type of the entire substrate, but indicating the conductivity type of the well. Is naturally included.

  The solid-state imaging device manufactured by the solid-state imaging device having the above characteristics and the manufacturing method of the above-described characteristics can reduce dark current generated during charge accumulation, and thus can suppress noise in the generated image. . Furthermore, the solid-state imaging device can be easily manufactured because one type of impurity is injected into the gate electrode of the transfer transistor.

FIG. 3 is a circuit diagram illustrating a schematic configuration example of one pixel circuit provided in the solid-state imaging device according to the embodiment of the present invention. 1 is a schematic cross-sectional view showing an example of a structure of a transfer transistor provided in a solid-state imaging device according to an embodiment of the present invention. The graph which shows the relationship between the density | concentration of the p-type impurity and n type impurity which are inject | poured into a polysilicon, and a work function. The graph which shows the potential of the transfer transistor in a non-conduction state. The graph which shows the potential of the transfer transistor in a conductive state. FIG. 3 is a schematic cross-sectional view showing an example of a method for manufacturing the transfer transistor shown in FIG. 2. FIG. 3 is a schematic cross-sectional view showing an example of a method for manufacturing the transfer transistor shown in FIG. 2. The top view of the transfer transistor which shows an example of the position of the opening area | region of a photoresist. FIG. 10 is a schematic cross-sectional view showing a non-conduction state of a transfer transistor provided in a conventional CMOS image sensor. FIG. 6 is a schematic cross-sectional view showing a conduction state of a transfer transistor provided in a conventional CMOS image sensor.

<Outline of pixel circuit>
First, a schematic configuration example and a schematic operation example of one pixel circuit provided in a solid-state imaging device (CMOS image sensor) according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram illustrating a schematic configuration example of one pixel circuit provided in a solid-state imaging device according to an embodiment of the present invention.

  A pixel circuit 1 illustrated in FIG. 1 includes a photodiode 2 whose anode is grounded and generates electrons by photoelectric conversion, a transfer transistor 3 whose source is connected to the cathode of the photodiode 2, and a drain of the transfer transistor 3. The floating diffusion region 4 connected, the reset transistor 5 whose source is connected to the floating diffusion region 4 and supplied with the power supply potential VDD to the drain, and the power supply potential VDD supplied to the drain and the gate electrode electrically connected to the floating diffusion region 4 , A selection transistor 7 having a drain connected to the source of the source follower transistor 6, and a signal line 8 to which the source of the selection transistor 7 is connected.

  In the pixel circuit 1 illustrated in FIG. 1, each element constituting the pixel circuit 1 is formed on a p-type substrate, and a photodiode 2 accumulates electrons generated by photoelectric conversion (light receiving unit, details will be described later). ) Is n-type, and the channel formed in each of the transfer transistor 3, the reset transistor 5, the source follower transistor 6 and the selection transistor 7 is n-type. The “p-type substrate” means “a substrate on which an element structure is formed is a p-type substrate”, and is not limited to a p-type substrate as a whole. Of course, a certain substrate (for example, a substrate in which a p-type well is partially formed by implanting p-type impurities into a substrate that is entirely n-type) is also included. However, in the following, for simplification of description, the entire substrate is illustrated and described as if it is p-type.

  Further, silicon can be used as a material for the substrate. In this case, boron or the like can be used as the p-type impurity. In this case, phosphorus, arsenic, or the like can be used as the n-type impurity. Further, these impurities can be implanted into the substrate by applying a method such as ion implantation. In the following, for the sake of concrete explanation, a case where impurity implantation is performed by ion implantation is illustrated.

  Next, a schematic operation example of the pixel circuit 1 will be described with reference to FIG. First, when light enters the photodiode 2, electrons and holes are generated by photoelectric conversion, and the electrons are accumulated in the n-type light receiving portion. At this time, the transfer transistor 3 is in a non-conductive state by applying a low level potential to the gate electrode.

  Thereafter, when a high-level potential is applied to the gate electrode of the transfer transistor 3, the transfer transistor 3 becomes conductive, so that electrons accumulated in the light receiving portion of the photodiode 2 are read out to the floating diffusion region 4. Thereby, the potential of the floating diffusion region 4 becomes a potential corresponding to the number of electrons read from the photodiode 2 (that is, the amount of incident light).

  However, before electrons are read from the photodiode 2 to the floating diffusion region 4, a high-level potential is applied to the gate electrode of the reset transistor 5 to make the reset transistor 5 conductive, so that the floating diffusion region 4 becomes predetermined. It is assumed that the potential is set (reset). As a result, the potential of the floating diffusion region 4 after electrons are read from the photodiode 2 is decreased from the predetermined potential by a magnitude corresponding to the number of read electrons.

  When a high level potential is applied to the gate electrode of the selection transistor 7 and the selection transistor 7 becomes conductive, the source follower transistor 6 amplifies a signal based on the potential of the floating diffusion region 4 applied to the gate electrode. . The signal amplified by the source follower transistor 6 is output to the signal line 8 via the selection transistor 7.

<Structure of transfer transistor>
Next, an example of the structure of the transfer transistor 3 provided in the pixel circuit 1 described above will be described with reference to the drawings. FIG. 2 is a schematic cross-sectional view showing an example of the structure of the transfer transistor provided in the solid-state imaging device according to the embodiment of the present invention.

As shown in FIG. 2, the transfer transistor 3 includes a substrate 10 made of a p-type (p-well) semiconductor and an n-type (n ⁻ ) semiconductor that is a region in the substrate 10 and corresponds to the source of the transfer transistor 3. A light receiving portion 21, a region in the substrate 10, a pinning region 22 formed on the light receiving portion 21 and made of a p-type (p ⁺ ) semiconductor having a higher p-type impurity concentration than the substrate 10, and a region in the substrate 10 The floating diffusion region 4 made of an n-type (n ⁺ ) semiconductor, which corresponds to the drain of the transfer transistor 3 and has a higher concentration of n-type impurities than the light receiving portion 21, an insulating layer 31 provided on the substrate 10, and an insulating layer A gate electrode 32 provided on 31, a first sidewall 33 formed on the light receiving portion 21 side of the gate electrode 32, and a second sidewall 34 formed on the floating diffusion region 4 side of the gate electrode 32. , A low concentration p-type p-type impurity than the formed pinning regions 22 immediately below the first side wall 33 is an area of the substrate within 10 (p ^-) and the first low-concentration region 35 of semiconductor substrate 10 A second low-concentration region 36 made of an n-type (n ⁻ ) semiconductor having a lower concentration of n-type impurities than the floating diffusion region 4, and an upper surface of the substrate 10. Formed in the interlayer insulating film 11, formed in the interlayer insulating film 11 and electrically connected to the gate electrode 32, and formed in the interlayer insulating film 11 and floating in the interlayer insulating film 11. A floating diffusion region contact plug 13 electrically connected to the diffusion region 4.

The gate electrode 32 is provided at least between the light receiving portion 21 and the floating diffusion region 4 and is made of, for example, polysilicon. The gate electrode 32 has a higher n-type impurity concentration toward the floating diffusion region 4 side and a lower n-type impurity concentration toward the light receiving portion 21 side. In other words, the concentration gradient of the n-type impurity in the gate electrode 32 monotonously decreases from the floating diffusion region 4 side to the light receiving unit 21 side. Further, for example, the concentration of the n-type impurity in the gate electrode 32 varies within a range of 1 × 10 ¹⁶ cm ⁻³ or more and 5 × 10 ²⁰ cm ⁻³ or less.

  Although details will be described later, such a gate electrode 32 is formed so that the second region 32b on the floating diffusion region 4 side has a higher n-type impurity concentration than the first region 32a on the light receiving unit 21 side. It is obtained by implanting n-type impurities into 32. The gate electrode contact plug 12 is electrically connected to the second region 32b of the gate electrode 32 on the floating diffusion region 4 side.

  Next, the characteristics of the gate electrode 32 will be described with reference to FIG. FIG. 3 is a graph showing the relationship between the concentration of p-type impurities and n-type impurities implanted into polysilicon and the work function. The graph showing the relationship between the concentration of the p-type impurity and the work function in the drawing is not directly related to the gate electrode 32 of this example in which the n-type impurity is implanted. However, as will be described later, it is also possible to inject a p-type impurity into the gate electrode 32 instead of the n-type impurity, in which case the graph concerned is relevant. In addition, the graph shown in FIG. 3 is disclosed as FIG. 2 of Unexamined-Japanese-Patent No. 2001-156288, for example.

  As shown in FIG. 3, when the concentration of the n-type impurity of the polysilicon forming the gate electrode 32 is increased, the work function is decreased, and therefore the potential under the gate electrode 32 is decreased. Therefore, when the concentration gradient of the n-type impurity of the gate electrode 32 is monotonously decreased from the floating diffusion region 4 side to the light receiving unit 21 side as described above, the potential under the gate electrode 32 becomes the opposite, and from the light receiving unit 21 side. It inclines so as to monotonously decrease toward the floating diffusion region 4 side.

  Next, an example of the operation of the transfer transistor 3 will be described with reference to the drawings. FIG. 4 is a graph showing the potential of the transfer transistor in the non-conductive state, and FIG. 5 is a graph showing the potential of the transfer transistor in the conductive state.

  As shown in FIG. 4, when the transfer transistor 3 is non-conductive, the potential below the gate electrode 32 is larger than the bottom of the light receiving unit 21. Therefore, the electrons e generated by photoelectric conversion and accumulated in the light receiving unit 21 are not read out to the floating diffusion region 4.

  Further, when the transfer transistor 3 is in a non-conducting state, electrons e that form a dark current can be emitted under the gate electrode 32 from, for example, the interface between the substrate 10 and the insulating layer 31. However, as described above, since the potential under the gate electrode 32 is inclined so as to monotonously decrease from the light receiving unit 21 side to the floating diffusion region 4 side, the electrons e forming the dark current are efficiently transferred to the floating diffusion region 4. Can be eliminated. At this time, since the reset transistor 5 is in the conductive state as described above, the electrons e excluded in the floating diffusion region 4 can be excluded from the floating diffusion region 4 via the reset transistor 5.

  On the other hand, as shown in FIG. 5, when the transfer transistor 3 is in a conductive state, the potential below the gate electrode 32 is smaller than the bottom of the light receiving unit 21. Therefore, the electrons e generated by photoelectric conversion and accumulated in the light receiving unit 21 are read out to the floating diffusion region 4. At this time, since the potential under the gate electrode 32 is inclined so as to monotonously decrease from the light receiving unit 21 side to the floating diffusion region 4 side as described above, the electrons e accumulated in the light receiving unit 21 are efficiently used. It is possible to read the floating diffusion region 4 well.

  The inclined potential can be formed simply by injecting an n-type conductivity impurity into the gate electrode 32. Therefore, it is possible to suppress an increase in the number of processes accompanying the impurity implantation into the gate electrode 32. Therefore, the complexity of the manufacturing process and the increase in cost can be suppressed.

  Further, in the transfer transistor 3 of this example, it is not necessary to provide a conductive layer (for example, the silicide layer 107 shown in FIGS. 9 and 10) covering the entire surface of the gate electrode 32. Therefore, it is possible to suppress contamination due to metal elements and the like contained in the conductive layer.

  As described above, in the solid-state imaging device according to the embodiment of the present invention, the dark current generated when electrons e are accumulated can be reduced, so that noise in the generated image can be suppressed.

<Transfer Transistor Manufacturing Method>
Next, an example of a method for manufacturing the transfer transistor 3 described above will be described with reference to the drawings. 6 and 7 are schematic cross-sectional views showing an example of a method for manufacturing the transfer transistor shown in FIG. 6 and 7 show the same cross section as the cross section shown in FIG. 2, and FIG. 6 (a), FIG. 6 (b), FIG. 6 (c), FIG. FIG. 7B shows a state in which the manufacturing process of the transfer transistor 3 proceeds in the order of FIG. 7B and FIG.

First, as shown in FIG. 6A, a p-type substrate 10 is obtained by implanting p-type impurities into a substrate 10 made of silicon. Next, as shown in FIG. 6B, an insulating layer 31 made of silicon oxide (SiO ₂ ) is formed on the upper surface of the substrate 10, and a gate electrode 32 made of polysilicon is formed on the upper surface. For example, the insulating layer 31 is formed by oxidizing the substrate 10. For example, the gate electrode 32 is formed by a CVD (Chemical Vapor Deposition) method or the like. At this time, unnecessary portions of the respective films made of silicon oxide and polysilicon that do not constitute the insulating layer 31 and the gate electrode 32 are removed by etching or the like. The film thickness of the gate electrode 32 is, for example, about 200 nm.

Next, as illustrated in FIG. 6C, a photoresist R <b> 1 is formed except for the portion directly above the first region 32 a on the light receiving portion 21 side of the gate electrode 32 and the portion directly above the light receiving portion 21. Further, n-type impurity ions are implanted using the photoresist R1 as a mask. As a result, n-type impurities are simultaneously implanted into both the first region 32 a on the light receiving unit 21 side of the gate electrode 32 and the light receiving unit 21. At this time, for example, ion implantation is performed at a dose of 1 × 10 ¹² cm ⁻² or more and 1 × 10 ¹³ cm ⁻² or less. As shown in FIG. 6 and FIG. 8 to be described later, a part of the photoresist R1 may be overlapped on the region where the light receiving portion 21 is formed. The photoresist R1 is removed after the implantation of the n-type impurity.

  Next, as shown in FIG. 7A, the gate electrode 32 and the substrate 10 are oxidized, for example, so that the first sidewall 33 and the second side wall are formed on the light receiving unit 21 side and the floating diffusion region 4 side of the gate electrode 32. Sidewalls 34 are formed. At this time, unnecessary portions of the film made of silicon oxide that do not constitute the first sidewall 33 and the second sidewall 34 are removed by etching or the like.

  Next, as illustrated in FIG. 7B, a photoresist R <b> 2 is formed except for the portion directly above the first sidewall 33 on the light receiving portion 21 side of the gate electrode 32 and the portion directly above the light receiving portion 21. Further, p-type impurity ions are implanted using the photoresist R2 as a mask. Thereby, the pinning region 22 and the first low concentration region 35 are formed on the surface of the substrate 10 on the light receiving unit 21. Since the first sidewall 33 is formed immediately above the first low concentration region 35, the concentration of the p-type impurity is lower than that of the pinning region 22. The photoresist R2 is removed after the implantation of the p-type impurity.

Next, as shown in FIG. 7C, except for the portion directly above the second region 32 b on the floating diffusion region 4 side of the gate electrode 32, the portion directly above the second sidewall 34, and the portion directly above the floating diffusion region 4. A photoresist R3 is formed. Further, n-type impurity ions are implanted using the photoresist R3 as a mask. As a result, n-type impurities are simultaneously implanted into the second region 32 b of the gate electrode 32 on the floating diffusion region 4 side, the second low-concentration region 36, and the floating diffusion region 4. For example, ion implantation is performed with a dose of 1 × 10 ¹³ cm ⁻² or more and 1 × 10 ¹⁵ cm ⁻² or less (a dose greater than that in FIG. 6C). Since the second sidewall 34 is formed immediately above the second low concentration region 36, the concentration of the n-type impurity is lower than that of the floating diffusion region 4. Note that the photoresist R3 is removed after the implantation of the n-type impurity.

  After forming the structure of FIG. 7C, heat treatment is performed to activate the implanted impurities. For example, heat treatment is performed at a temperature of 800 ° C. or higher. In the transfer transistor 100 shown in FIGS. 9 and 10, since the two regions 106a and 106b having different conductivity types are formed adjacent to the gate electrode 106, impurities contained in the respective regions 106a and 106b Since it is necessary to prevent compensation by diffusion, various problems arise such as heat treatment being restricted and impurity activation being insufficient. However, in the transfer transistor 3 of this example, since only one type of impurity is implanted into the gate electrode, even if the n-type impurity is diffused by the heat treatment, the concentration gradient only becomes gentle. Therefore, in the transfer transistor 3 of this example, it is possible to eliminate (or reduce) restrictions such as heat treatment.

  Then, after the heat treatment, an interlayer insulating film 11 is formed on the upper surface of the substrate 10, and further, a gate electrode contact plug 12 and a floating diffusion region contact plug 13 are formed, thereby transferring the structure shown in FIG. Transistor 3 is obtained.

  In addition, the position of the opening regions of the photoresists R1 and R3 in the method for manufacturing the transfer transistor 3 described above will be described with reference to the drawings. FIG. 8 is a top view of the transfer transistor showing an example of the position of the opening region of the photoresist. In FIG. 8, the light receiving unit 21, the gate electrode 32 (first region 32a, second region 32b), the first sidewall 33, the second sidewall 34, the floating diffusion region 4, and the gate electrode are used. The respective positions of the contact plug 12 and the floating diffusion region contact plug 13 are indicated by solid lines. An area inside the outermost solid line is an active area, and an element isolation structure such as STI (Shallow Trench Isolation) is provided outside the active area.

  In FIG. 8, the position of the opening region of the photoresist R1 is indicated by a thick alternate long and short dash line RO1. That is, the above-described n-type impurities are simultaneously injected into a region inside the alternate long and short dash line RO1. In FIG. 8, the position of the opening region of the photoresist R3 is indicated by a thick broken line RO3. That is, the above-described n-type impurities are simultaneously injected into a region inside the broken line RO3.

  The opening region RO1 of the photoresist R1 includes not only the light receiving unit 21 but also the first region 32a of the gate electrode 32. Similarly, the opening region RO3 of the photoresist R3 includes not only the floating diffusion region 4 but also the second region 32b of the gate electrode 32.

  Thus, the implantation of the n-type impurity into the gate electrode 32 of the transfer transistor 3 can be performed in two steps. For this reason, it is possible to suppress an increase in the number of processes accompanying the implantation of the n-type impurity into the gate electrode 32.

  In particular, the n-type impurity can be implanted into the first region 32 a and the second region 32 b of the gate electrode 32 in conjunction with the implantation of the n-type impurity into the floating diffusion region 4 and the light receiving unit 21. Therefore, it is possible to implant n-type impurities into the gate electrode 32 without increasing the number of steps.

  As described above, in the method for manufacturing a solid-state imaging device according to the embodiment of the present invention, since one kind of impurity is injected into the gate electrode 32 of the transfer transistor 3, the solid-state imaging device can be easily manufactured. .

  An n-type impurity is simultaneously implanted into the light receiving portion 21 and the first region 32a of the gate electrode 32, and an n-type impurity is simultaneously implanted into the floating diffusion region 4 and the second region 32b of the gate electrode 32. Although the manufacturing method has been exemplified, the n-type impurity may be implanted at the same time for one of the sets, and the n-type impurity may be separately implanted for the other set. Further, an n-type impurity is simultaneously implanted into the light receiving portion 21 and the first region 32a of the gate electrode 32, and thereafter, an n-type impurity is simultaneously implanted into the floating diffusion region 4 and the second region 32b of the gate electrode 32. The manufacturing method is exemplified, but this order may be reversed.

<Deformation, etc.>
The conductivity type and the charge polarity of the semiconductor constituting the solid-state imaging device may be the reverse of the above-described example. Specifically, for example, the substrate 10 is n-type, the light receiving unit 21, the floating diffusion region 4, the gate electrode 32, and the second low-concentration region 36 are p-type, and the pinning region 22 and the first low-concentration region 35 are n-type. It may be a mold, and the light receiving unit 21 may accumulate holes generated by photoelectric conversion.

  The configuration of the pixel circuit 1 shown in FIG. 1 is merely an example, and any other configuration may be used. Further, although the embodiment in which the present invention is applied to the CMOS image sensor has been described, the present invention may be applied to other solid-state imaging devices.

  The solid-state imaging device according to the present invention can be suitably used for, for example, a CMOS image sensor mounted on various electronic devices having an imaging function.

1: Pixel circuit 2: Photodiode 21: Light receiving unit 22: Pinning region 3: Transfer transistor 31: Insulating layer 32: Gate electrode 32a: First region 32b: Second region 33: First sidewall 34: Second sidewall 35: first low concentration region 36: second low concentration region 4: floating diffusion region 5: reset transistor 6: source follower transistor 7: selection transistor 8: signal line 10: substrate 11: interlayer insulating film 12: contact for gate electrode Plug 13: Contact plug for floating diffusion region

Claims (11)

A substrate made of a first conductivity type semiconductor;
A light receiving portion made of a semiconductor of a second conductivity type different from the first conductivity type, which is formed in the substrate and accumulates electric charges generated by photoelectric conversion;
A floating diffusion region formed in the substrate, made of the second conductivity type semiconductor, and having a higher concentration of the second conductivity type impurity than the light receiving portion;
An insulating layer provided on the substrate;
A gate electrode of the second conductivity type provided on the insulating layer and at least between the light receiving portion and the floating diffusion region,
The solid-state imaging device, wherein the gate electrode has a higher concentration of the second conductivity type impurity toward the floating diffusion region and a lower concentration of the second conductivity type impurity toward the light receiving portion.   The gate electrode includes: a first region on the light receiving unit side; and a second region on the floating diffusion region side and having a concentration of the impurity of the second conductivity type higher than that of the first region. The solid-state imaging device according to claim 1. A contact plug electrically connected to the second region of the gate electrode;
The solid-state imaging device according to claim 2, further comprising: The concentration of the second conductivity type impurity in the gate electrode is in the range of 1 × 10 ¹⁶ cm ^{−3 to} 5 × 10 ²⁰ cm ⁻³ . The solid-state imaging device according to item 1.   The solid-state imaging device according to claim 1, wherein the gate electrode is made of polysilicon. Forming an insulating layer on a substrate made of a first conductivity type semiconductor, and forming a gate electrode on the insulating layer;
A light receiving portion that accumulates charges generated by photoelectric conversion is implanted by injecting an impurity of a second conductivity type different from the first conductivity type into a region in the substrate on one end side of the gate electrode. A light receiving portion forming step to be formed;
Injecting the second conductivity type impurity into the region in the substrate on the other end side of the gate electrode so that the concentration of the second conductivity type impurity is higher than that of the light receiving portion, A floating diffusion region forming step for forming a floating diffusion region;
In the gate electrode, the concentration of the second conductivity type impurity is higher toward the floating diffusion region side, and the concentration of the second conductivity type impurity is lower toward the light receiving portion side. A gate electrode impurity implantation step for implanting,
A method for manufacturing a solid-state imaging device. The gate electrode impurity implantation step comprises:
A first region impurity implantation step for implanting the second conductivity type impurity into the first region on the light receiving unit side;
The second conductivity type impurity is formed in the second region on the floating diffusion region side so as to be higher than the concentration of the second conductivity type impurity implanted into the first region in the first region impurity implantation step. A second region impurity implantation step of implanting
The manufacturing method of the solid-state image sensor of Claim 6 characterized by the above-mentioned. A first implantation method for simultaneously performing the first region impurity implantation step and the light receiving portion formation step;
A second implantation method for simultaneously performing the second region impurity implantation step and the floating diffusion region formation step;
The method of manufacturing a solid-state imaging device according to claim 7, wherein at least one of the following is executed. Forming a contact plug electrically connected to the second region of the gate electrode;
The method for manufacturing a solid-state imaging device according to claim 7, further comprising: A heat treatment step of performing a heat treatment after completion of the gate electrode impurity implantation step;
The method for manufacturing a solid-state imaging device according to claim 6, further comprising:   The method of manufacturing a solid-state imaging device according to claim 10, wherein the heat treatment step is a heat treatment performed at 800 ° C. or higher.

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