CN114864615A - Method for manufacturing image sensor - Google Patents
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14689—MOS based technologies
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- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
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Abstract
The invention provides a manufacturing method of an image sensor, which sequentially comprises the following steps: providing a substrate, wherein the substrate comprises a pixel area and a logic area; forming a silicon oxide layer covering the pixel region and the logic region on the surface of the substrate; forming a silicon nitride layer covering the silicon oxide layer; forming shallow trench isolation in the silicon nitride layer, the silicon oxide layer and the substrate; removing the silicon nitride layer covering the logic area and reserving the silicon nitride layer covering the pixel area; performing an ion implantation process of the logic region; removing the silicon nitride layer covering the pixel region; and performing an ion implantation process of the pixel region. The method removes the silicon nitride layer covering the logic area, reserves the silicon nitride layer covering the pixel area, removes the silicon nitride layer covering the pixel area after the ion implantation process of the logic area is completed, and utilizes the silicon nitride layer reserved in the pixel area as a protective layer, thereby effectively reducing the pollution and physical damage of the processing procedure of the logic area to the pixel area and improving the quality of the image sensor.
Description
Technical Field
The invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a manufacturing method of an image sensor.
Background
A CMOS image sensor is a semiconductor device that converts an optical image into an electrical signal. CMOS image sensors are integrated on metal oxide semiconductor materials and widely used in the fields of digital cameras, camera phones, digital video cameras, medical imaging devices (e.g., gastroscopes), vehicle imaging devices, and the like.
CMOS image sensors typically include a pixel area and a peripheral logic area, and for CMOS image sensors, the characteristics of the pixel area used for light sensing directly determine the performance of the final image sensor. The performance parameters of the image sensor include quantum efficiency, dark current, dynamic range, signal-to-noise ratio, and the like. Therefore, the fabrication of the pixel region is crucial, and the pixel region is completely exposed when the conventional process is used for processing the logic region, or only a thin silicon oxide layer is protected on the surface of the pixel region. The contamination and physical damage caused by the logic area process inevitably affect the pixel area, thereby causing pixel defects (e.g., dead pixel, noise, etc.).
Disclosure of Invention
The invention aims to provide a manufacturing method of an image sensor, which reduces the pollution and physical damage of a logic area processing procedure to a pixel area and improves the quality of the image sensor.
The invention provides a manufacturing method of an image sensor, which comprises the following steps:
providing a substrate, wherein the substrate comprises a pixel area and a logic area; forming a silicon oxide layer covering the pixel region and the logic region on the surface of the substrate; forming a silicon nitride layer covering the silicon oxide layer; forming shallow trench isolation in the silicon nitride layer, the silicon oxide layer and the substrate;
removing the silicon nitride layer covering the logic area, and reserving the silicon nitride layer covering the pixel area;
performing an ion implantation process of the logic region;
removing the silicon nitride layer covering the pixel region;
and performing an ion implantation process of the pixel region.
Further, after the shallow trench isolation is formed, the method further includes:
forming a first protective layer covering the silicon nitride layer and the surface of the shallow trench isolation;
in the step of removing the silicon nitride layer covering the logic region, the first protective layer covering the logic region is also removed, and the first protective layer covering the pixel region is left.
Further, the first protection layer includes at least one of a silicon nitride layer, a stacked layer of a silicon nitride layer-a silicon oxide layer-a silicon nitride layer, and a polysilicon layer.
Further, after the shallow trench isolation is formed, the method further includes:
forming an isolation layer, wherein the isolation layer covers the surfaces of the silicon nitride layer and the shallow trench isolation, and the isolation layer is made of a silicon oxide layer and/or a silicon oxynitride layer;
in the step of removing the silicon nitride layer covering the logic region, the isolation layer covering the logic region is also removed, and the isolation layer covering the pixel region is left.
Further, removing the silicon nitride layer covering the logic region and reserving the silicon nitride layer covering the pixel region specifically includes:
forming a first light resistance layer, wherein the first light resistance layer covers the pixel area and exposes the logic area;
and removing the silicon nitride layer covering the logic area by using the first photoresist layer as a mask through dry etching or wet etching.
Further, the logic area includes a first logic area and a second logic area; the method for executing the ion implantation process of the logic area specifically comprises the following steps:
forming a second photoresist layer, wherein the second photoresist layer covers the pixel area and the second logic area to expose the first logic area, and performing P-type ion implantation on the first logic area by taking the second photoresist layer as a mask to form a P-type well region in the first logic area; removing the second photoresist layer;
forming a third photoresist layer, wherein the third photoresist layer covers the pixel area and the first logic area, exposes the second logic area, and performs N-type ion implantation on the second logic area by taking the third photoresist layer as a mask to form an N-type well region in the second logic area; and removing the third photoresist layer.
Further, the performing of the ion implantation process of the pixel region specifically includes: performing P-type ion implantation on the pixel region to form a P-type well region on one side of the shallow trench isolation;
and carrying out N-type ion implantation on the pixel region to form a photodiode N region on the other side of the shallow trench isolation.
Further, the method also comprises the following steps:
forming gates corresponding to different transistors in the pixel region and the logic region;
and performing ion implantation in the substrate at two sides of the grid to form a source electrode and a drain electrode corresponding to each transistor and a surface P area of the photodiode.
The invention also provides a manufacturing method of the image sensor, which sequentially comprises the following steps:
providing a substrate, wherein the substrate comprises a pixel area and a logic area; forming a silicon oxide layer covering the pixel region and the logic region on the surface of the substrate; forming a silicon nitride layer covering the silicon oxide layer; forming shallow trench isolation in the silicon nitride layer, the silicon oxide layer and the substrate;
removing the silicon nitride layer covering the logic region and the pixel region;
forming a second protective layer, wherein the second protective layer covers the surfaces of the silicon oxide layer and the shallow trench isolation;
removing the second protective layer covering the logic area, and reserving the second protective layer covering the pixel area;
performing an ion implantation process of the logic region;
removing the second protective layer covering the pixel region;
and performing an ion implantation process of the pixel region.
Further, the second protective layer includes at least one of a silicon nitride layer, a stacked layer of a silicon nitride layer-a silicon oxide layer-a silicon nitride layer, and a polysilicon layer.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a manufacturing method of an image sensor, which sequentially comprises the following steps: providing a substrate, wherein the substrate comprises a pixel area and a logic area; forming a silicon oxide layer covering the pixel region and the logic region on the surface of the substrate; forming a silicon nitride layer covering the silicon oxide layer; forming shallow trench isolation in the silicon nitride layer, the silicon oxide layer and the substrate; removing the silicon nitride layer covering the logic area and reserving the silicon nitride layer covering the pixel area; performing an ion implantation process of the logic region; removing the silicon nitride layer covering the pixel region; and performing an ion implantation process of the pixel region. The method removes the silicon nitride layer covering the logic area, reserves the silicon nitride layer covering the pixel area, removes the silicon nitride layer covering the pixel area after the ion implantation process of the logic area is finished, and utilizes the silicon nitride layer reserved in the pixel area as a protective layer, thereby effectively reducing the pollution and physical damage of the processing procedure of the logic area to the pixel area and improving the quality of the image sensor.
Drawings
Fig. 1 is a schematic flow chart illustrating a method for manufacturing an image sensor according to an embodiment of the invention.
Fig. 2a to 9 are schematic diagrams illustrating steps of a manufacturing method of an image sensor according to a first embodiment of the invention.
Fig. 10 is a circuit diagram of an image sensor according to the present invention.
Fig. 11 to 12 are schematic diagrams illustrating a manufacturing method of an image sensor according to a second embodiment of the invention.
Fig. 13 to 14 are schematic views illustrating another method for fabricating an image sensor according to the present invention.
Wherein the reference numbers are as follows:
10-a substrate; 11-shallow trench isolation; 12-a silicon oxide layer; 13-a silicon nitride layer; 13 a-a silicon nitride layer of the pixel region; 13 b-a silicon nitride layer of the logic region; 14-a first photoresist layer; 15-a second photoresist layer; 16-a third photoresist layer; 17-a fourth photoresist layer; 18-photodiode N region; 19-photodiode surface P region (pinning layer); an X-pixel region; an L-logic area; i-a first logical area; II-a second logical area; a 21-P type well region; a 22-N type well region; 23-P type well region; 24-an isolation layer; 31. 32, 33, 34-gates; 25-a first protective layer; 45-a second protective layer; 41. 43, 44-source; 42. 51, 53, 54-drain.
Detailed Description
The embodiment of the invention provides a manufacturing method of an image sensor. The invention is described in further detail below with reference to the figures and specific examples. The advantages and features of the present invention will become more apparent from the following description. It is to be noted, however, that the drawings are designed in a simplified form and are not to scale, but rather are to be construed in an illustrative and descriptive sense only and not for purposes of limitation.
For ease of description, some embodiments of the present application may use spatially relative terms such as "above …," "below …," "top," "below," etc. to describe one element or component's relationship to another element (or other) or component as illustrated in the various figures of the embodiments. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or components described as "below" or "beneath" other elements or components would then be oriented "above" or "over" the other elements or components. The terms "first," "second," and the like in the following description are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances.
The embodiment of the invention provides a manufacturing method of an image sensor, which comprises the following steps in sequence as shown in fig. 1:
step S1, providing a substrate, wherein the substrate comprises a pixel area and a logic area; forming a silicon oxide layer covering the pixel region and the logic region on the surface of the substrate; forming a silicon nitride layer covering the silicon oxide layer; forming shallow trench isolation in the silicon nitride layer, the silicon oxide layer and the substrate;
step S2, removing the silicon nitride layer covering the logic area and reserving the silicon nitride layer covering the pixel area;
step S3, performing an ion implantation process of the logic region;
step S4, removing the silicon nitride layer covering the pixel area;
and step S5, performing an ion implantation process of the pixel region.
Fig. 2a to 9 are schematic diagrams illustrating steps of a method for manufacturing an image sensor according to a first embodiment of the invention. Fig. 10 is a circuit diagram of an image sensor according to an embodiment of the invention. The steps of the wafer processing method according to the embodiment of the invention will be described in detail with reference to fig. 2 to 10.
FIG. 2a is a schematic top view of an image sensor according to a first embodiment of the present invention; FIG. 2b is a schematic cross-sectional view at AA' of FIG. 2 a. As shown in fig. 2a and 2b, a substrate 10 is provided, the substrate 10 includes a pixel region X and a logic region L, which illustratively surrounds the pixel region X. A silicon oxide layer 12 covering the pixel region X and the logic region L is formed on the surface of the substrate 10, a silicon nitride layer 13 is formed on the surface of the silicon oxide layer 12, and correspondingly, the silicon nitride layer 13 includes a silicon nitride layer 13a of the pixel region and a silicon nitride layer 13b of the logic region. The silicon nitride layer 13, the silicon oxide layer 12 and the substrate 10 with partial thickness are etched to form a trench, oxide is filled in the trench to form a Shallow Trench Isolation (STI)11, and Chemical Mechanical Polishing (CMP) is carried out to make the upper surfaces of the Shallow Trench Isolation (STI)11 and the silicon nitride layer 13 flush.
As shown in fig. 3a, a first photoresist layer 14 is formed, and the first photoresist layer 14 covers the pixel region X and exposes the logic region L. The first photoresist layer 14 is used as a mask to remove the silicon nitride layer 13b covering the logic region by dry or wet etching, for example, hot phosphoric acid (H) can be used 3 PO 4 ) And removing the silicon nitride layer 13b in the logic area by wet etching. In other examples, the silicon nitride layer 13b of the logic region may be removed by dry etching using reactive ion etching using a mixed gas containing fluorine gas and oxygen gas. In other embodiments, before the first photoresist layer 14 is formed, the silicon nitride layer 13 may be thinned integrally according to actual needs, for example, in the case that the thickness of the silicon nitride layer 13 is thicker, the thinning is performed to a suitable thickness for facilitating the etching process.
As shown in fig. 3a and 3b, optionally, after the Shallow Trench Isolation (STI)11 and the silicon nitride layer 13 are leveled by Chemical Mechanical Polishing (CMP), an isolation layer 24 may be further formed, the isolation layer 24 covers the upper surfaces of the silicon nitride layer 13 and the Shallow Trench Isolation (STI)11, and then a first photoresist layer 14 is formed on the isolation layer 24, and the silicon nitride layer 13b in the logic region is removed by using the first photoresist layer 14 as a mask. In one example, the isolation layer 24 may be formed by a regrown silicon oxide layer or silicon oxynitride layer; in another example, the isolation layer 24 may be formed by oxidizing the surface of the silicon nitride layer 13. The isolation layer 24 serves as an isolation between the silicon nitride layer 13 and the first photoresist layer 14 and an anti-reflection function during photolithography. The isolation layer 24 and the silicon nitride layer 13b covering the logic region are etched away.
As shown in fig. 3a and 4, the first photoresist layer 14 is removed by an ashing process, and a wet cleaning process is performed to remove particle impurities or residues formed by the ashing and/or etching processes.
As shown in fig. 5, the logic region L may form an NMOS transistor formed in the P-well region and a PMOS transistor formed in the N-well region. The logic area L includes a first logic area I and a second logic area II. The first logic region I is used to form a P-type well region, for example, and the second logic region is used to form an N-type well region, for example. In other embodiments, the first logic region can be used to form an N-well region, and the second logic region can be used to form a P-well region. Forming a second photoresist layer 15, wherein the second photoresist layer 15 covers the pixel region X and the second logic region II of the logic region to expose the first logic region I of the logic region. Using the second photoresist layer 15 as a mask, ion implantation is performed on the first logic region I, for example, high-energy boron ions are implanted to form a P-type well region 21 for manufacturing an NMOS transistor, and then the second photoresist layer 15 is removed by an ashing process.
As shown in fig. 6, a third photoresist layer 16 is formed, and the third photoresist layer 16 covers the pixel region X and the first logic region I of the logic region, exposing the second logic region II of the logic region. Performing ion implantation on the second logic region II by using the third photoresist layer 16 as a mask, for example, implanting N-type ions to form an N-type well region 22 for manufacturing a PMOS transistor; the N-type ions may be, but are not limited to, arsenic ions or phosphorus ions. The third photoresist layer 16 is then removed by an ashing process.
As shown in fig. 7, the silicon nitride layer 13a in the pixel region is removed by a wet or dry process, such as etching with hot phosphoric acid (H) 3 PO 4 ) The silicon nitride layer 13a of the pixel region is removed by wet etching. In other examples, the silicon nitride layer 13a in the pixel region may be removed by dry etching using reactive ion etching using a mixed gas containing fluorine gas and oxygen gas.
As shown in fig. 8, an ion implantation process of the pixel region is performed. Specifically, a fourth photoresist layer 17 is formed, and the fourth photoresist layer 17 covers a partial region of the logic region L and the pixel region X. And performing ion implantation on the pixel region X, for example, performing P-type ion implantation on the pixel region by using the fourth photoresist layer 17 as a mask, to form a P-type well region 23 located on one side of the shallow trench isolation 11. And performing N-type ion implantation on the pixel region to form a photodiode N region 18 on the other side of the shallow trench isolation 11.
As shown in fig. 9, a gate electrode and a source drain electrode are formed, and specifically, a gate layer, such as a polysilicon layer, is formed on the silicon oxide layer 12. The gate layer is formed into gates (e.g., 31, 32, 33, 34) of different transistors using a photolithography process. And performing ion implantation on the source and drain regions on two sides of the grid to form a source electrode and a drain electrode corresponding to the transistor. For example, N-type ion implantation (doping) is performed on the pixel region X to form the source 41, the drain 51, and the drain 42. The pixel region X is subjected to P-type ion implantation (doping) to form a photodiode surface P region (pinning layer) 19. The gate electrode 31, the source electrode 41 and the drain electrode 51 constitute an NMOS transistor of the pixel region X. Illustratively, N-type ion implantation is performed on a first logic region I of the logic regions to form a source electrode 43 and a drain electrode 53; the gate 33, the source 43 and the drain 53 constitute, for example, an NMOS transistor of the first logic region I. Performing P-type ion implantation on a second logic region II of the logic region to form a source 44 and a drain 54; the gate 34, the source 44 and the drain 54 constitute, for example, a PMOS transistor of the second logic region II. In other examples, a PMOS transistor may be formed in the first logic area I, and an NMOS transistor may be formed in the second logic area II, and the configuration is according to actual needs.
As shown in fig. 9 and 10, the pixel region X includes a plurality of transistors in the substrate 10, and fig. 9 shows only a part of the transistors. Wherein the plurality of transistors in the pixel region include transistors formed from an N-type doped layer in the substrate of the pixel region. The photodiode PD and various types of transistors such as a transfer transistor TX, a reset transistor RST, a source follower transistor SF, a row select transistor RS, a conversion gain control transistor, and the like may be included in the pixel region. The photodiode PD may be a buried photodiode.
During operation, photo-charges generated by the photodiode PD respond to incident light during exposure. The transfer transistor TX is connected to a transfer signal that controls the transfer transistor TX to transfer the charges accumulated in the photodiode PD to a floating diffusion region (FD), that is, a drain 42. The gate 32, the drain 42, and the photodiode N region 18 in fig. 9 constitute the transmission transistor TX in fig. 10, and the photodiode N region 18 is the source of the transmission transistor TX. The transmission transistor TX may be a MOSFET (metal oxide semiconductor field effect transistor). The reset transistor RST is connected between VDD and the floating diffusion region (i.e., drain 42) and is responsive to a reset signal to reset the pixel circuit, e.g., discharge or charge the floating diffusion region and photodiode PD to a present voltage. The floating diffusion region (FD) is connected to the source follower transistor SF. The source follower transistor SF is connected between VDD and the row select transistor RS, amplifying the signal in response to the potential of the floating diffusion region (i.e., drain 42). The row select transistor RS connects the pixel circuit output to the readout column, or BIT line BIT, from the source follower transistor SF in response to a row select control signal.
The incident light causes electric charges to be generated in the photodiode PD. As the light-generated electrons in the photodiode PD gradually accumulate, its voltage increases (electrons are negative charges). The voltage or charge of the photodiode PD indicates the intensity incident to the photodiode PD during exposure. Charge is transferred from the photodiode PD to the floating diffusion region (i.e., drain 42) through transfer transistor TX such that the voltage of the floating diffusion region is proportionally reduced by the accumulation of photo-generated electrons on the photodiode PD during exposure.
FIGS. 11 to 12 are views showing images according to a second embodiment of the present inventionThe sensor manufacturing method is shown schematically. In the second embodiment, as shown in fig. 2b and fig. 11, a silicon oxide layer 12 and a silicon nitride layer 13 are sequentially formed on the surface of the substrate 10; after forming a Shallow Trench Isolation (STI)11 on the substrate 10 and performing Chemical Mechanical Polishing (CMP) to make the upper surfaces of the Shallow Trench Isolation (STI)11 and the silicon nitride layer 13 flush, a first protection layer 25 may be further formed, and the first protection layer 25 covers the surfaces of the silicon nitride layer 13 and the Shallow Trench Isolation (STI) 11. The first protective layer 25 may include a silicon nitride layer (Si) 3 N 4 ) Silicon nitride layer-silicon oxide layer-silicon nitride layer (Si) 3 N 4 -SiO 2 -Si 3 N 4 ) And at least one of a polysilicon layer. As shown in fig. 12, a fifth photoresist layer 19 is formed, and the fifth photoresist layer 19 covers the first passivation layer 25 in the pixel region X to expose the logic region L. And etching and removing the first protective layer 25 and the silicon nitride layer 13b in the logic region L by using the fifth photoresist layer 19 as a mask, wherein the first protective layer and the silicon nitride layer can be removed by adopting a dry process or a wet process. For example, hot phosphoric acid (H) 3 PO 4 ) The first protective layer 25 and the silicon nitride layer 13b in the logic region are removed by wet etching. Then, the pixel region X has the first protective layer 25 and the silicon nitride layer 13a as a protective layer, and the ion implantation process of the logic region L is performed; the ion implantation of the logic region L includes a plurality of photolithography-ion implantation cycles such as N-well, P-well, and channel regions of IO (input and/or output) devices and core devices. Next, the first protective layer 25 and the silicon nitride layer 13a covering the pixel region X are removed. And performing an ion implantation process of the pixel region X, wherein the ion implantation of the pixel region X comprises a photosensitive region and photoetching-ion implantation circulation of each transistor well region and each channel region which form a pixel unit. And then forming a grid electrode and a source and drain region of the device. In the second embodiment, the first protection layer 25 and the silicon nitride layer 13a of the pixel region jointly protect the pixel region X, so that the protection of the pixel region is enhanced to further reduce the pollution and damage of the logic region processing technology to the pixel region, and the quality of the image sensor is improved.
The invention also provides another manufacturing method of the image sensor, which sequentially comprises the following steps:
providing a substrate, wherein the substrate comprises a pixel area and a logic area; forming a silicon oxide layer covering the pixel region and the logic region on the surface of the substrate; forming a silicon nitride layer covering the silicon oxide layer; forming shallow trench isolation in the silicon nitride layer, the silicon oxide layer and the substrate;
removing the silicon nitride layer covering the logic area and the pixel area;
forming a second protective layer, wherein the second protective layer covers the surfaces of the silicon oxide layer and the shallow trench isolation;
removing the second protective layer covering the logic area, and reserving the second protective layer covering the pixel area;
performing an ion implantation process of the logic region;
removing the second protective layer covering the pixel region;
and performing an ion implantation process of the pixel region.
Fig. 13 to 14 are schematic views illustrating another method for fabricating an image sensor according to the present invention. As shown in fig. 2b and fig. 13, a silicon oxide layer 12 and a silicon nitride layer 13 are sequentially formed on the surface of the substrate 10; etching the silicon nitride layer 13, the silicon oxide layer 12 and the substrate 10 with partial thickness to form a trench, filling oxide in the trench to form a Shallow Trench Isolation (STI)11, performing Chemical Mechanical Polishing (CMP) to make the upper surfaces of the STI 11 and the silicon nitride layer 13 flush, and then removing the silicon nitride layer 13 covering the logic region X and the pixel region L. As shown in fig. 14, the second protection layer 45 is formed again, the second protection layer 45 covers the surfaces of the silicon oxide layer 12 and the Shallow Trench Isolation (STI)11, the top surface of the second protection layer 45 is leveled by Chemical Mechanical Polishing (CMP), and the CMP top surface of the second protection layer 45 is higher than the top surface of the Shallow Trench Isolation (STI)11, that is, the second protection layer 45 covers the top of the Shallow Trench Isolation (STI) 11. The second protective layer 45 may include a silicon nitride layer (Si) 3 N 4 ) Silicon nitride layer-silicon oxide layer-silicon nitride layer (Si) 3 N 4 -SiO 2 -Si 3 N 4 ) And at least one of a polysilicon layer.
The STI trench is formed by an etching process and a Chemical Mechanical Polishing (CMP) process, the thickness uniformity and quality of the originally formed silicon nitride layer 13 are reduced, the second protective layer 45 is formed again by removing the silicon nitride layer 13, the good quality and uniformity of the second protective layer 45 can be ensured, and the top of the trench isolation (STI)11 can be wrapped to enhance the anti-pollution capability. In other examples, the silicon oxide layer 12 may be removed and a silicon oxide layer may be regrown, and similarly, during the trench process for forming the STI through the etching process, the silicon oxide layer 12 may be damaged to some extent, and a silicon oxide layer may be regrown to ensure the quality of the silicon oxide layer on the surface of the substrate 10.
Then, removing the second protection layer 45 covering the logic area L, and reserving the second protection layer 45 covering the pixel area X; performing an ion implantation process of the logic region L; removing the second protective layer 45 covering the pixel region; and performing an ion implantation process of the pixel region X.
According to the embodiment of the invention, the second protective layer is formed again by removing the silicon nitride layer covering the logic area and the pixel area, so that the good quality and uniformity of the second protective layer can be ensured; removing the second protective layer covering the logic area, and reserving the second protective layer covering the pixel area; in the process of executing the ion implantation process of the logic area, the pixel area is protected by the second protective layer, so that the pollution and the physical damage of the logic area processing procedure to the pixel area are effectively reduced, and the quality of the image sensor is improved.
In summary, the present invention provides a method for manufacturing an image sensor, which sequentially includes the following steps: providing a substrate, wherein the substrate comprises a pixel area and a logic area; forming a silicon oxide layer covering the pixel region and the logic region on the surface of the substrate; forming a silicon nitride layer covering the silicon oxide layer; forming shallow trench isolation in the silicon nitride layer, the silicon oxide layer and the substrate; removing the silicon nitride layer covering the logic area and reserving the silicon nitride layer covering the pixel area; performing an ion implantation process of the logic region; removing the silicon nitride layer covering the pixel region; and performing an ion implantation process of the pixel region. The method removes the silicon nitride layer covering the logic area, reserves the silicon nitride layer covering the pixel area, removes the silicon nitride layer covering the pixel area after the ion implantation process of the logic area is completed, and utilizes the silicon nitride layer reserved in the pixel area as a protective layer, thereby effectively reducing the pollution and physical damage of the processing procedure of the logic area to the pixel area and improving the quality of the image sensor.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the method disclosed by the embodiment, the description is relatively simple because the method corresponds to the device disclosed by the embodiment, and the relevant points can be referred to the description of the method part.
The above description is only for the purpose of describing the preferred embodiments of the present invention and is not intended to limit the scope of the claims of the present invention, and any person skilled in the art can make possible the variations and modifications of the technical solutions of the present invention using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention, and therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention belong to the protection scope of the technical solutions of the present invention.
Claims (10)
1. The manufacturing method of the image sensor is characterized by sequentially comprising the following steps of:
providing a substrate, wherein the substrate comprises a pixel area and a logic area; forming a silicon oxide layer covering the pixel region and the logic region on the surface of the substrate; forming a silicon nitride layer covering the silicon oxide layer; forming shallow trench isolation in the silicon nitride layer, the silicon oxide layer and the substrate;
removing the silicon nitride layer covering the logic area, and reserving the silicon nitride layer covering the pixel area;
performing an ion implantation process of the logic region;
removing the silicon nitride layer covering the pixel region;
and performing an ion implantation process of the pixel region.
2. The method of claim 1, wherein after forming the shallow trench isolation, further comprising:
forming a first protective layer covering the silicon nitride layer and the surface of the shallow trench isolation;
in the step of removing the silicon nitride layer covering the logic region, the first protective layer covering the logic region is also removed, and the first protective layer covering the pixel region is left.
3. The method of claim 2, wherein the first protective layer comprises at least one of a silicon nitride layer, a stacked layer of a silicon nitride layer-a silicon oxide layer-a silicon nitride layer, and a polysilicon layer.
4. The method of claim 1, wherein after forming the shallow trench isolation, further comprising:
forming an isolation layer, wherein the isolation layer covers the surfaces of the silicon nitride layer and the shallow trench isolation, and the isolation layer is made of a silicon oxide layer and/or a silicon oxynitride layer;
in the step of removing the silicon nitride layer covering the logic region, the isolation layer covering the logic region is also removed, and the isolation layer covering the pixel region is left.
5. The method according to any one of claims 1 to 4, wherein removing the silicon nitride layer covering the logic region and leaving the silicon nitride layer covering the pixel region comprises:
forming a first light resistance layer, wherein the first light resistance layer covers the pixel area and exposes the logic area;
and removing the silicon nitride layer covering the logic area by using the first photoresist layer as a mask through dry etching or wet etching.
6. The method for manufacturing an image sensor according to any one of claims 1 to 4, wherein the logic region includes a first logic region and a second logic region; the method for executing the ion implantation process of the logic area specifically comprises the following steps:
forming a second photoresist layer, wherein the second photoresist layer covers the pixel area and the second logic area to expose the first logic area, and performing P-type ion implantation on the first logic area by taking the second photoresist layer as a mask to form a P-type well region in the first logic area; removing the second photoresist layer;
forming a third photoresist layer, wherein the third photoresist layer covers the pixel area and the first logic area, exposes the second logic area, and performs N-type ion implantation on the second logic area by taking the third photoresist layer as a mask to form an N-type well region in the second logic area; and removing the third photoresist layer.
7. The method according to any one of claims 1 to 4, wherein performing an ion implantation process on the pixel region specifically comprises:
performing P-type ion implantation on the pixel region to form a P-type well region on one side of the shallow trench isolation;
and carrying out N-type ion implantation on the pixel region to form a photodiode N region on the other side of the shallow trench isolation.
8. The method of claim 7, further comprising:
forming gates corresponding to different transistors in the pixel region and the logic region;
and performing ion implantation in the substrate at two sides of the grid to form a source electrode and a drain electrode corresponding to each transistor and a surface P area of the photodiode.
9. The manufacturing method of the image sensor is characterized by sequentially comprising the following steps of:
providing a substrate, wherein the substrate comprises a pixel area and a logic area; forming a silicon oxide layer covering the pixel region and the logic region on the surface of the substrate; forming a silicon nitride layer covering the silicon oxide layer; forming shallow trench isolation in the silicon nitride layer, the silicon oxide layer and the substrate;
removing the silicon nitride layer covering the logic region and the pixel region;
forming a second protective layer, wherein the second protective layer covers the surfaces of the silicon oxide layer and the shallow trench isolation;
removing the second protective layer covering the logic area, and reserving the second protective layer covering the pixel area;
performing an ion implantation process of the logic region;
removing the second protective layer covering the pixel region;
and performing an ion implantation process of the pixel region.
10. The method of claim 9, wherein the second protective layer comprises at least one of a silicon nitride layer, a stacked layer of a silicon nitride layer-a silicon oxide layer-a silicon nitride layer, and a polysilicon layer.
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