JP2013080841A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2013080841A
JP2013080841A JP2011220350A JP2011220350A JP2013080841A JP 2013080841 A JP2013080841 A JP 2013080841A JP 2011220350 A JP2011220350 A JP 2011220350A JP 2011220350 A JP2011220350 A JP 2011220350A JP 2013080841 A JP2013080841 A JP 2013080841A
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electrode
prevention groove
film
barrier metal
semiconductor device
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JP5882014B2 (en
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Shinjiro Kato
伸二郎 加藤
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Seiko Instruments Inc
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Seiko Instruments Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that can be used under high-temperature environment.SOLUTION: A wire connection region composed of a stack of a first inner electrode and a second inner electrode is isolated from a first outer electrode and a second outer electrode by alloying prevention grooves so that the development of an Au-Al alloy layer grown from a wire-bonding interface is suppressed, thereby preventing cracks of a passivation film on a surface of a semiconductor device.

Description

本発明は、高温環境で使用する半導体装置のボンディングパッドに関する。   The present invention relates to a bonding pad of a semiconductor device used in a high temperature environment.

半導体装置におけるワイヤーボンディングは、アルミ系材料からなるボンディングパッドとＡｕ系材料からなるボンディングワイヤーを合金化させることによってボンディング強度が得られているが、一般にＡｌとＡｕが合金化すると体積が膨張する。半導体装置が高温環境に長時間放置される場合、合金化は進行し、合金化部の体積が膨張することによって、ボンディングパッド周辺のパッシベーション膜にクラックを生じさせる不具合が発生することがある。この課題に対し、ボンディングパッドをアルミ層／バリア層とすることでＡｕ−Ａｌ合金層の下地層への成長を阻止することが提案されている（例えば、特許文献１参照）。また、ボンディングパッド下層の隣接する配線間の短絡防止のために下層配線と層間絶縁膜とを離間することが提案されている（例えば、特許文献２参照）。   In wire bonding in a semiconductor device, bonding strength is obtained by alloying a bonding pad made of an aluminum-based material and a bonding wire made of an Au-based material, but generally the volume expands when Al and Au are alloyed. When the semiconductor device is left in a high temperature environment for a long time, alloying proceeds, and the volume of the alloyed portion expands, which may cause a defect that causes a crack in the passivation film around the bonding pad. In response to this problem, it has been proposed to prevent the growth of the Au—Al alloy layer on the underlayer by using an aluminum layer / barrier layer as the bonding pad (see, for example, Patent Document 1). In addition, in order to prevent a short circuit between adjacent wirings below the bonding pad, it has been proposed to separate the lower wiring and the interlayer insulating film (for example, see Patent Document 2).

特開２００２−７６０５１号公報Japanese Patent Laid-Open No. 2002-76051 特開２００３−１００７６６号公報Japanese Patent Laid-Open No. 2003-1000076

ボンディングパッドを構成する最上層アルミ膜はボンディングパッドの他にも最上層アルミ配線の形成にも用いられるが、半導体装置表面はボンディングパッドの一部のみが開口されるようにパッシベーション膜によって覆われ、最上層アルミ配線もパッシベーション膜による被覆の対象である。しかしながら、前述の特許文献１および特許文献２においてはＡｕ−Ａｌ合金層のパッシベーション膜への影響は述べられていない。ボンディングパッド開口端部はパッシベーション膜端部と同一であり、通常、パッシベーション膜端部はボンディングパッド上に位置する。ここで、Ａｕ−Ａｌ合金層が横方向に成長すると、被覆するパッシベーション膜にはクラックが生じ内部のアルミ配線の腐食に至るなど半導体装置にとっては重大な問題が発生する。   The uppermost aluminum film constituting the bonding pad is used for forming the uppermost aluminum wiring in addition to the bonding pad, but the surface of the semiconductor device is covered with a passivation film so that only a part of the bonding pad is opened, The uppermost aluminum wiring is also covered by the passivation film. However, in Patent Document 1 and Patent Document 2 described above, the influence of the Au—Al alloy layer on the passivation film is not described. The bonding pad opening end is the same as the passivation film end, and usually the passivation film end is located on the bonding pad. Here, when the Au—Al alloy layer grows in the lateral direction, a serious problem occurs for the semiconductor device, such as a crack in the passivation film to be coated and corrosion of the internal aluminum wiring.

本発明は、Ａｕ−Ａｌ合金層の横方向への進行を抑制し、半導体装置表面のパッシベーション膜のクラックを防止することを目的とするものである。   An object of the present invention is to suppress the progress of the Au—Al alloy layer in the lateral direction and prevent cracks in the passivation film on the surface of the semiconductor device.

上記課題を解決するために本発明においては下記の半導体装置構造とした。
まず、シリコン基板上に絶縁膜を介して設けられた第１インナーバリアメタルと第１インナーアルミ電極と第２インナーバリアメタルと第２インナーアルミ電極とが順に積層したワイヤー接続領域と、第１インナーバリアメタルおよび第１インナーアルミ電極の周囲に設けられた第１合金化防止溝と、第２インナーバリアメタルおよび第２インナーアルミ電極の周囲に設けられた第２合金化防止溝と、第１合金化防止溝によって第１インナーバリアメタルおよび第１インナーアルミ電極と離間した第１アウターバリアメタルおよび第１アウターアルミ電極と、第２合金化防止溝によって第２インナーバリアメタルおよび第２インナーアルミ電極と離間した第２アウターバリアメタルおよび第２アウターアルミ電極とからなり、第１インナーバリアメタルおよび第１インナーアルミ電極と第１アウターバリアメタルおよび第１アウターアルミ電極は第１合金化防止溝に埋め込まれた第２アウターバリアメタルおよび第２アウターアルミ電極によって電気的に接続され、パッシベーション膜はワイヤー接続領域の外側に位置する第１合金化防止溝および第２合金化防止溝よりもさらに外側も設けられている半導体装置とした。 In order to solve the above problems, the present invention has the following semiconductor device structure.
First, a wire connection region in which a first inner barrier metal, a first inner aluminum electrode, a second inner barrier metal, and a second inner aluminum electrode are sequentially stacked on a silicon substrate via an insulating film; A first alloying prevention groove provided around the barrier metal and the first inner aluminum electrode, a second alloying prevention groove provided around the second inner barrier metal and the second inner aluminum electrode, and the first alloy A first outer barrier metal and a first outer aluminum electrode separated from the first inner barrier metal and the first inner aluminum electrode by an anti-oxidation groove; and a second inner barrier metal and a second inner aluminum electrode separated by a second alloying prevention groove The first inner bar comprises a second outer barrier metal and a second outer aluminum electrode spaced apart from each other. The ametal and the first inner aluminum electrode and the first outer barrier metal and the first outer aluminum electrode are electrically connected by the second outer barrier metal and the second outer aluminum electrode embedded in the first alloying prevention groove, and the passivation film The semiconductor device is provided with an outer side further than the first alloying prevention groove and the second alloying prevention groove located outside the wire connection region.

また、シリコン基板上に絶縁膜を介して設けられた第１インナーバリアメタルと第１インナーアルミ電極と第２インナーバリアメタルと第２インナーアルミ電極とが順に積層したワイヤー接続領域と、第１インナーバリアメタルおよび第１インナーアルミ電極の周囲に設けられた第１合金化防止溝と、第２インナーバリアメタルおよび第２インナーアルミ電極の周囲に設けられた第２合金化防止溝と、第１合金化防止溝によって第１インナーバリアメタルおよび第１インナーアルミ電極と離間した第１アウターバリアメタルおよび第１アウターアルミ電極と、第２合金化防止溝によって第２インナーバリアメタルおよび第２インナーアルミ電極と離間した第２アウターバリアメタルおよび第２アウターアルミ電極とからなり、第１インナーバリアメタルおよび第１インナーアルミ電極と第１アウターバリアメタルおよび第１アウターアルミ電極は第１合金化防止溝に埋め込まれた第２インナーバリアメタルおよび第２インナーアルミ電極によって電気的に接続され、パッシベーション膜はワイヤー接続領域の外側に位置する第１合金化防止溝および第２合金化防止溝よりもさらに外側も設けられている半導体装置とした。   A wire connection region in which a first inner barrier metal, a first inner aluminum electrode, a second inner barrier metal, and a second inner aluminum electrode, which are provided on a silicon substrate via an insulating film, are sequentially stacked; A first alloying prevention groove provided around the barrier metal and the first inner aluminum electrode, a second alloying prevention groove provided around the second inner barrier metal and the second inner aluminum electrode, and the first alloy A first outer barrier metal and a first outer aluminum electrode separated from the first inner barrier metal and the first inner aluminum electrode by an anti-oxidation groove; and a second inner barrier metal and a second inner aluminum electrode separated by a second alloying prevention groove The first inner bar comprises a second outer barrier metal and a second outer aluminum electrode spaced apart from each other. The ametal and the first inner aluminum electrode and the first outer barrier metal and the first outer aluminum electrode are electrically connected by the second inner barrier metal and the second inner aluminum electrode embedded in the first alloying prevention groove, and the passivation film The semiconductor device is provided with an outer side further than the first alloying prevention groove and the second alloying prevention groove located outside the wire connection region.

上記のような半導体装置構造とすることにより、ボンディングワイヤーとボンディングパッド界面から横方向に成長するＡｕ−Ａｌ合金層の進行を抑制し、半導体装置表面のパッシベーション膜のクラックを防止することができる。   By adopting the semiconductor device structure as described above, it is possible to suppress the progress of the Au—Al alloy layer that grows laterally from the interface between the bonding wire and the bonding pad, and to prevent the passivation film from cracking on the surface of the semiconductor device.

本発明の第１の実施形態に係るボンディングパッドの断面図であるIt is sectional drawing of the bonding pad which concerns on the 1st Embodiment of this invention. 本発明の第１の実施形態を示す半導体装置の製造フローを示す図である。It is a figure which shows the manufacturing flow of the semiconductor device which shows the 1st Embodiment of this invention. 図２に続く、本発明の第１の実施形態を示す半導体装置の製造フローを示す図である。FIG. 3 is a diagram illustrating a manufacturing flow of the semiconductor device showing the first embodiment of the present invention, following FIG. 2; 図３に続く、本発明の第１の実施形態を示す半導体装置の製造フローを示す図である。FIG. 4 is a diagram illustrating a manufacturing flow of the semiconductor device showing the first embodiment of the present invention, following FIG. 3; 本発明の第２の実施形態に係るボンディングパッドの断面図である。It is sectional drawing of the bonding pad which concerns on the 2nd Embodiment of this invention.

以下、本発明を実施するための最良の形態について、図面に基づいて説明する。   The best mode for carrying out the present invention will be described below with reference to the drawings.

本発明の第１の実施形態について図１を用いて説明する。
図１は半導体装置のボンディングパッド１００の断面図である。
ワイヤー接続領域３はボンディング電極となる第２インナーアルミ系電極１４とボンディングワイヤー６が接続する領域である。ワイヤー接続領域３を含んで、かつワイヤー接続領域３を囲むようにビアホール領域２が設けられ、そして、ビアホール領域２を含んで、かつビアホール領域２を囲むようにボンディングパッド領域１が設けられている。更には、ボンディングパッド領域１の外周には保護膜領域が設けられている。 A first embodiment of the present invention will be described with reference to FIG.
FIG. 1 is a cross-sectional view of a bonding pad 100 of a semiconductor device.
The wire connection region 3 is a region where the second inner aluminum electrode 14 serving as a bonding electrode and the bonding wire 6 are connected. A via hole region 2 is provided so as to include the wire connection region 3 and surround the wire connection region 3, and a bonding pad region 1 is provided so as to include the via hole region 2 and surround the via hole region 2. . Further, a protective film region is provided on the outer periphery of the bonding pad region 1.

ボンディングパッド領域１はパッシベーション膜１６およびポリイミド膜１７の無い領域であり、外側の保護膜領域はパッシベーション膜１６およびポリイミド膜１７によって被覆されている。ビアホール領域２は層間絶縁膜１２の有無によって規定され、ビアホール領域２内は層間絶縁膜１２の無い領域である。ビアホール領域２の内方にはワイヤー接続領域３が設けられ、ワイヤー接続領域３内の第２インナー電極を構成する第２インナーバリアメタル１３と第２インナーアルミ系電極１４は、その外側の領域の第２アウターバリアメタル２０と第２アウターアルミ系電極２１とからなる第２アウター電極との間に第２合金化防止溝５を有して互いに分離されている。第２インナー電極の下には第１インナーバリアメタル９と第１インナーアルミ系電極１０の積層である第１インナー電極が第２インナー電極よりも大きく形成され、第１インナー電極は第２合金化防止溝５を越え、第２アウター電極に達して電気的に接続している。   The bonding pad region 1 is a region without the passivation film 16 and the polyimide film 17, and the outer protective film region is covered with the passivation film 16 and the polyimide film 17. The via hole region 2 is defined by the presence or absence of the interlayer insulating film 12, and the via hole region 2 is a region without the interlayer insulating film 12. A wire connection region 3 is provided inside the via hole region 2, and the second inner barrier metal 13 and the second inner aluminum-based electrode 14 constituting the second inner electrode in the wire connection region 3 are formed in the outer region. Between the second outer electrode composed of the second outer barrier metal 20 and the second outer aluminum electrode 21, a second alloying prevention groove 5 is provided and separated from each other. Under the second inner electrode, a first inner electrode, which is a laminate of the first inner barrier metal 9 and the first inner aluminum-based electrode 10, is formed larger than the second inner electrode, and the first inner electrode is formed into a second alloy. It passes over the prevention groove 5 and reaches the second outer electrode to be electrically connected.

ワイヤー接続領域３の外側のビアホール領域２内において、ワイヤー接続領域３の近くに位置する第１インナー電極を構成する第１インナーバリアメタル９および第１インナーアルミ系電極１０とワイヤー接続領域３から遠くに位置する第１アウター電極を構成する第１アウターバリアメタル１８および第１アウターアルミ系電極１９との間には第１合金化防止溝４が設けられ、その溝によって第１電極は内外に分離されるが、第１合金化防止溝４には第２アウター電極が入り込み、分離された第１インナー電極と第１アウター電極を電気的に接続している。   In the via hole region 2 outside the wire connection region 3, the first inner barrier metal 9 and the first inner aluminum-based electrode 10 constituting the first inner electrode located near the wire connection region 3 are far from the wire connection region 3. A first alloying prevention groove 4 is provided between the first outer barrier metal 18 and the first outer aluminum-based electrode 19 constituting the first outer electrode located in the first outer electrode, and the first electrode is separated into the inside and outside by the groove. However, the second outer electrode enters the first alloying prevention groove 4 and electrically connects the separated first inner electrode and first outer electrode.

なお、第２合金化防止溝５は第１合金化防止溝４よりも内側に位置し、両者は重ならないように配置されている。ビアホール領域２の外側の領域では第１アウター電極の上に第１反射防止膜１１と層間絶縁膜１２と第２アウター電極が順に積層され、保護膜領域では第２アウター電極の上に第２反射防止膜１５とパッシベーション膜１６とポリイミド膜１７が更に積層されている。   In addition, the 2nd alloying prevention groove | channel 5 is located inside the 1st alloying prevention groove | channel 4, and is arrange | positioned so that both may not overlap. In the region outside the via hole region 2, the first antireflection film 11, the interlayer insulating film 12, and the second outer electrode are sequentially stacked on the first outer electrode, and in the protective film region, the second reflection is performed on the second outer electrode. A prevention film 15, a passivation film 16 and a polyimide film 17 are further laminated.

次に、上記構造の半導体装置におけるパッシベーション膜のクラック防止のメカニズムについて説明する。ワイヤー接続領域３の第２インナーアルミ系電極１４にボンディングワイヤー６が接合すると両者の界面にＡｕ−Ａｌ合金層が形成されるが、同時に第２インナーアルミ系電極１４の下の第２インナーバリアメタル１３にダメージを与える。この状態で半導体装置を１５０〜２００℃という高温環境下に放置するとＡｕ−Ａｌ合金層がダメージを受けた第２インナーバリアメタル１３を介して第１インナーアルミ系電極１０まで成長するが、第１合金化防止溝４によってＡｕ−Ａｌ合金層の成長は抑制できる。このため、Ａｕ−Ａｌ合金層が成長して第１アウターアルミ系電極１９を体積膨張させて上層のパッシベーション膜１６にクラックを発生させることにはならない。また、第２インナーアルミ系電極１４から横方向に成長した場合も第２合金化防止溝５によって成長が止められ、パッシベーション膜１６のクラックには至らない。   Next, a mechanism for preventing cracks in the passivation film in the semiconductor device having the above structure will be described. When the bonding wire 6 is joined to the second inner aluminum electrode 14 in the wire connection region 3, an Au—Al alloy layer is formed at the interface between them, and at the same time, the second inner barrier metal below the second inner aluminum electrode 14. Damage 13 If the semiconductor device is left in a high temperature environment of 150 to 200 ° C. in this state, the Au—Al alloy layer grows up to the first inner aluminum-based electrode 10 through the damaged second inner barrier metal 13. The growth of the Au—Al alloy layer can be suppressed by the alloying prevention groove 4. For this reason, the Au—Al alloy layer does not grow and the first outer aluminum-based electrode 19 is volume-expanded to cause cracks in the upper passivation film 16. Further, even when grown in the lateral direction from the second inner aluminum-based electrode 14, the growth is stopped by the second alloying prevention groove 5, and the passivation film 16 does not crack.

次に、本発明の第１の実施形態を示す半導体装置の製造フローを示す図２乃至図４を用いて製造方法について説明する。   Next, a manufacturing method will be described with reference to FIGS. 2 to 4 showing a manufacturing flow of the semiconductor device showing the first embodiment of the present invention.

例えば抵抗が２０〜３０ΩcnのＰ型の半導体基板１の表面上に、絶縁膜２として膜厚８０００Åの熱酸化膜と膜厚１２００ÅのＴＥＯＳ膜と膜厚６０００ÅのＢＰＳＧ膜の積層膜を堆積させる。次に、第１バリアメタル９、１８として例えばＴｉ／ＴｉＮ積層膜を膜厚１７００Åとなるようにスパッタ法により堆積させる。次に、第１アルミ系電極１０、１９として例えばＡｌ−Ｓｉ−Ｃｕ膜を膜厚５０００Åでスパッタ法により堆積させ、さらに、第１反射防止膜１１としてＴｉＮ膜を膜厚２５０Åでスパッタ法により堆積させる。   For example, a laminated film of a thermal oxide film having a thickness of 8000 mm, a TEOS film having a thickness of 1200 mm, and a BPSG film having a thickness of 6000 mm is deposited as the insulating film 2 on the surface of a P-type semiconductor substrate 1 having a resistance of 20 to 30 Ωcn. Next, for example, a Ti / TiN laminated film is deposited as the first barrier metals 9 and 18 by a sputtering method so as to have a film thickness of 1700 mm. Next, for example, an Al—Si—Cu film is deposited as a first aluminum electrode 10, 19 by a sputtering method with a film thickness of 5000 mm, and a TiN film is deposited as a first antireflection film 11 by a sputtering method with a film thickness of 250 mm. Let

次に、第１反射防止膜１１の上にレジストパターニングして第１反射防止膜１１と第１アルミ系電極と第１バリアメタルをエッチングして第１合金化防止溝４を形成し、第１インナー電極と第１アウター電極に分離する。次に、第１合金化防止溝４を埋め、かつ第１反射防止膜１１を被覆するように層間絶縁膜１２としてＴＥＯＳ膜７０００ÅをＣＶＤ法にて堆積する（図２参照）。   Next, resist patterning is performed on the first antireflection film 11, the first antireflection film 11, the first aluminum-based electrode, and the first barrier metal are etched to form the first alloying prevention groove 4, and the first antireflection film 11 is formed. Separated into an inner electrode and a first outer electrode. Next, a TEOS film 7000Å is deposited by CVD as an interlayer insulating film 12 so as to fill the first alloying prevention groove 4 and cover the first antireflection film 11 (see FIG. 2).

次いで、フォトリソグラフィー法とエッチング法を用い、ビアホール領域２に相当する部分の層間絶縁膜１２と第１反射防止膜１１を除去する。 第２バリアメタル１３，２０として例えばＴｉ／ＴｉＮ積層膜を膜厚１７００Åとなるようにスパッタ法により堆積させる。次に、第２アルミ系電極１４、２１として例えばＡｌ−Ｓｉ−Ｃｕ膜を膜厚８０００Åでスパッタ法により堆積させ、さらに、第２反射防止膜１５としてＴｉＮ膜を膜厚２５０Åでスパッタ法により堆積させる。   Next, the interlayer insulating film 12 and the first antireflection film 11 corresponding to the via hole region 2 are removed by using a photolithography method and an etching method. As the second barrier metals 13 and 20, for example, a Ti / TiN laminated film is deposited by sputtering so as to have a film thickness of 1700 mm. Next, for example, an Al-Si-Cu film is deposited as the second aluminum-based electrodes 14 and 21 by a sputtering method with a film thickness of 8000 mm, and a TiN film is deposited as a second antireflection film 15 by a sputtering method with a film thickness of 250 mm. Let

次に、第２反射防止膜１５の上にレジストパターニングして第２反射防止膜１５と第２アルミ系電極と第２バリアメタルをエッチングして第２合金化防止溝５を形成し、第２インナー電極と第２アウター電極に分離する。この結果、ワイヤー接続領域３となる第２インナー電極が第１インナー電極の上に形成される。また、第２アウター電極は第１インナー電極の一部から第１合金化防止溝４と第２インナー電極の一部に、そして層間絶縁膜１２の一部を覆うように形成される（図３参照）。   Next, resist patterning is performed on the second antireflection film 15 to etch the second antireflection film 15, the second aluminum-based electrode, and the second barrier metal, thereby forming the second alloying prevention groove 5. Separated into an inner electrode and a second outer electrode. As a result, the second inner electrode that becomes the wire connection region 3 is formed on the first inner electrode. The second outer electrode is formed so as to cover a part of the first inner electrode, a part of the first alloying prevention groove 4 and the second inner electrode, and a part of the interlayer insulating film 12 (FIG. 3). reference).

次に、半導体ウェハ全面を覆うように、第２反射防止膜１５の上にパッシベーション膜１６として膜厚１００００ÅのＳｉＮ膜をCVD法により堆積させ、次いでポリイミド膜１７を例えば膜厚１２μｍとしてスピン塗布した後、ボンディングパッド領域１の内側のポリイミド膜１７をフォトリソ法で除去する（図４を参照）。次に、ポリイミド膜１７をマスクとしてパッシベーション膜１６と第２反射防止膜１５をエッチング除去する。
以上述べた製造方法により、図１に示した本発明の半導体装置を製造することができる。 Next, a SiN film having a film thickness of 10,000 mm is deposited as a passivation film 16 on the second antireflection film 15 by the CVD method so as to cover the entire surface of the semiconductor wafer, and then a polyimide film 17 is spin-coated to a film thickness of 12 μm, for example. Thereafter, the polyimide film 17 inside the bonding pad region 1 is removed by photolithography (see FIG. 4). Next, the passivation film 16 and the second antireflection film 15 are removed by etching using the polyimide film 17 as a mask.
The semiconductor device of the present invention shown in FIG. 1 can be manufactured by the manufacturing method described above.

本発明の第２の実施形態について図５を用いて説明する。
図５は半導体装置のボンディングパッド１０１の断面図である。
ワイヤー接続領域３はボンディング電極となる第２インナーアルミ系電極１４とボンディングワイヤー６が接続する領域である。ワイヤー接続領域３を含んで、かつワイヤー接続領域３を囲むようにビアホール領域２が設けられ、そして、ビアホール領域２を含んで、かつビアホール領域２を囲むようにボンディングパッド領域１が設けられている。更には、ボンディングパッド領域１の外周には保護膜領域が設けられている。 A second embodiment of the present invention will be described with reference to FIG.
FIG. 5 is a cross-sectional view of the bonding pad 101 of the semiconductor device.
The wire connection region 3 is a region where the second inner aluminum electrode 14 serving as a bonding electrode and the bonding wire 6 are connected. A via hole region 2 is provided so as to include the wire connection region 3 and surround the wire connection region 3, and a bonding pad region 1 is provided so as to include the via hole region 2 and surround the via hole region 2. . Further, a protective film region is provided on the outer periphery of the bonding pad region 1.

ボンディングパッド領域１はパッシベーション膜１６およびポリイミド膜１７の無い領域であり、外側の保護膜領域はパッシベーション膜１６およびポリイミド膜１７によって被覆されている。ビアホール領域２は層間絶縁膜１２の有無によって規定され、ビアホール領域２内は層間絶縁膜１２の無い領域である。ビアホール領域２の内方にはワイヤー接続領域３が設けられ、ワイヤー接続領域３内の第１インナー電極を構成する第１インナーバリアメタル９と第１インナーアルミ系電極１０は、その外側の領域の第１アウターバリアメタル１８と第１アウターアルミ系電極１９とからなる第１アウター電極との間に第１合金化防止溝４を有して互いに分離されている。   The bonding pad region 1 is a region without the passivation film 16 and the polyimide film 17, and the outer protective film region is covered with the passivation film 16 and the polyimide film 17. The via hole region 2 is defined by the presence or absence of the interlayer insulating film 12, and the via hole region 2 is a region without the interlayer insulating film 12. A wire connection region 3 is provided on the inner side of the via hole region 2, and the first inner barrier metal 9 and the first inner aluminum-based electrode 10 constituting the first inner electrode in the wire connection region 3 are located in the outer region. Between the first outer electrode composed of the first outer barrier metal 18 and the first outer aluminum electrode 19, the first alloying prevention groove 4 is provided and separated from each other.

上述の第１の実施形態においてはボンディングワイヤー６先端のボールと第２インナー電極が平面視的に重畳して略同等の面積、あるいは第２インナー電極がボールよりも幾分大きくなるように構成していたが、第２の実施形態においてはボンディングワイヤー６先端のボールと第１インナー電極が平面視的に重畳して略同等の面積か、あるいは第１インナー電極がボールよりも幾分大きくなるように構成されている。   In the first embodiment described above, the ball at the tip of the bonding wire 6 and the second inner electrode overlap each other in plan view so that the area is substantially equal, or the second inner electrode is somewhat larger than the ball. However, in the second embodiment, the ball at the tip of the bonding wire 6 and the first inner electrode overlap each other in plan view so that they have substantially the same area, or the first inner electrode is somewhat larger than the ball. It is configured.

第１インナー電極および第１合金化分離溝４の全てを覆い、かつ第１アウター電極の一部を覆うように第２インナー電極を設ける。なお、第２インナー電極は第２インナーバリアメタル１３と第２インナーアルミ系電極１４の積層構造である。   A second inner electrode is provided so as to cover all of the first inner electrode and the first alloying separation groove 4 and a part of the first outer electrode. The second inner electrode has a laminated structure of the second inner barrier metal 13 and the second inner aluminum electrode 14.

第２インナー電極は、第２アウターバリアメタル２０と第２アウターアルミ系電極２１との積層である第２アウター電極との間に第２合金化防止溝５を設けている。第１の実施形態との違いは第１合金化防止溝４が第２合金化防止溝５よりも内側、すなわちワイヤー接続領域３に近く位置する点であり、このほかの構成については第１の実施形態に準ずる。   The second inner electrode is provided with a second alloying prevention groove 5 between the second outer electrode, which is a laminate of the second outer barrier metal 20 and the second outer aluminum-based electrode 21. The difference from the first embodiment is that the first alloying prevention groove 4 is located on the inner side of the second alloying prevention groove 5, that is, near the wire connection region 3. According to the embodiment.

本実施例においても、第１合金化防止溝４と第２合金化防止溝５と第２インナーバリアメタル１３によってＡｕ−Ａｌ合金層の進行を抑制することは明らかである。   Also in this embodiment, it is obvious that the progress of the Au—Al alloy layer is suppressed by the first alloying prevention groove 4, the second alloying prevention groove 5, and the second inner barrier metal 13.

以上、説明したように、本発明の半導体装置の構成であれば、ワイヤーボンディング界面から成長したＡｕ−Ａｌ合金層の進行を抑制し、半導体装置表面のパッシベーション膜のクラックを防止することができる。   As described above, according to the configuration of the semiconductor device of the present invention, the progress of the Au—Al alloy layer grown from the wire bonding interface can be suppressed, and the crack of the passivation film on the surface of the semiconductor device can be prevented.

１ ボンディングパッド領域
２ ビアホール領域
３ ワイヤー接続領域
４ 第１合金化防止溝
５ 第２合金化防止溝
６ ボンディングワイヤー
７ 半導体基板
８ 絶縁膜
９ 第１インナーバリアメタル
１０ 第１インナーアルミ系電極
１１ 第１反射防止膜
１２ 層間絶縁膜
１３ 第２インナーバリアメタル
１４ 第２インナーアルミ系電極
１５ 第２反射防止膜
１６ パッシベーション膜
１７ ポリイミド膜
１８ 第１アウターバリアメタル
１９ 第１アウターアルミ系電極
２０ 第２アウターバリアメタル
２１ 第２アウターアルミ系電極
１００ 本発明の第１の実施形態に係るボンディングパッド
１０１ 本発明の第２の実施形態に係るボンディングパッド DESCRIPTION OF SYMBOLS 1 Bonding pad area | region 2 Via-hole area | region 3 Wire connection area | region 4 1st alloying prevention groove | channel 5 2nd alloying prevention groove | channel 6 Bonding wire 7 Semiconductor substrate 8 Insulating film 9 1st inner barrier metal 10 1st inner aluminum type electrode 11 1st Antireflection film 12 Interlayer insulating film 13 Second inner barrier metal 14 Second inner aluminum electrode 15 Second antireflection film 16 Passivation film 17 Polyimide film 18 First outer barrier metal 19 First outer aluminum electrode 20 Second outer barrier Metal 21 Second outer aluminum-based electrode 100 Bonding pad 101 according to the first embodiment of the present invention Bonding pad according to the second embodiment of the present invention

Claims (4)

半導体基板上に絶縁膜を介して、積層されて設けられた第１バリアメタルおよび第１アルミ電極と、
前記第１バリアメタルおよび第１アルミ電極を第１インナー電極と第１アウター電極とに分離している第１合金化防止溝と、
前記第１アウター電極の上に設けられた層間絶縁膜と、
前記第１インナー電極、前記第１アウター電極および前記層間絶縁膜の上に設けられているとともに、前記第１合金化防止溝に入り込み前記第１インナー電極と前記第１アウター電極とを電気的に接続している、積層された第２バリアメタルおよび第２アルミ電極と、
前記第２バリアメタルおよび第２アルミ電極をワイヤー接続領域である第２インナー電極と第２アウター電極とに分離している、前記第１合金化防止溝と異なる位置に設けられた第２合金化防止溝と、
前記第２アウター電極の上に設けられ、開口部がボンディングパッド領域を規定するパッシベーション膜と、
からなる半導体装置。 A first barrier metal and a first aluminum electrode which are stacked on the semiconductor substrate via an insulating film;
A first alloying prevention groove separating the first barrier metal and the first aluminum electrode into a first inner electrode and a first outer electrode;
An interlayer insulating film provided on the first outer electrode;
The first inner electrode, the first outer electrode, and the interlayer insulating film are provided, and the first inner electrode and the first outer electrode are electrically connected to the first alloying prevention groove. A stacked second barrier metal and second aluminum electrode connected,
The second barrier metal and the second aluminum electrode are separated into a second inner electrode and a second outer electrode, which are wire connection regions, and a second alloy is provided at a position different from the first alloying prevention groove. Prevention groove,
A passivation film provided on the second outer electrode, the opening defining a bonding pad region;
A semiconductor device comprising: 前記第２合金化防止溝は前記第１合金化防止溝のさらに内側に設けられていることを特徴とする請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein the second alloying prevention groove is provided further inside the first alloying prevention groove. 前記第１合金化防止溝は前記第２合金化防止溝のさらに内側に設けられていることを特徴とする請求項１に記載の半導体装置。   2. The semiconductor device according to claim 1, wherein the first alloying prevention groove is provided further inside the second alloying prevention groove. 前記第１インナー電極は平面視的にボンディングワイヤーのボールを含んで重なるように形成されることを特徴とする請求項１乃至３のいずれか１項に記載の半導体装置。   4. The semiconductor device according to claim 1, wherein the first inner electrode is formed so as to overlap with a ball of a bonding wire in a plan view.
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