JP2013077689A - Quantum infrared imaging device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent contact between adjacent bumps caused by difference of thermal expansion coefficients between a first substrate and a second substrate constituted by silicon substrates etc. without affecting the second substrate formed of HgCdTe etc., in a quantum infrared heat sensitive device including the first substrate having a readout circuit and the second substrate having a photodetector in bump connection.SOLUTION: The quantum imaging device includes: a first substrate having a readout circuit; a second substrate having a photodetector and electrically connected to the first substrate by flip chip bonding (FCB); a conductor bump group for electrically connecting the first substrate to the second substrate by FCB; and an insulation wall which is existent to surround the periphery of each bump and fixed to only the first substrate side, and has a gap between with the second substrate.

Description

  The present invention relates to a quantum infrared imaging device and a method for manufacturing the same.

  A light receiving element is formed on a substrate of a compound semiconductor such as HgCdTe (mercury cadmium telluride), a readout circuit is formed on a substrate of Si (silicon), etc., and these substrates are flip-chip bonded (FCB: Flip-Chip-Bonding). An electrically connected quantum infrared imaging device is known.

  In such a quantum infrared imaging device, a light-receiving device such as HgCdTe that is excited by receiving infrared rays emits free electrons, so that a current flows in the readout circuit and infrared rays can be detected. Yes.

  However, when the quantum infrared imaging device is operated under room temperature conditions, the light receiving device is excited without receiving infrared rays, and free electrons are emitted regardless of the presence or absence of infrared rays, resulting in noise. Therefore, it is necessary to operate under a low temperature condition of around 77K.

  Although there are restrictions as described above in operation, the quantum infrared imaging device is capable of more sensitive observation than an uncooled infrared detector, and therefore requires high-accuracy infrared observation. Widely used.

  These quantum infrared imaging devices are not always cooled, but are cooled to around 77K using liquid nitrogen when used, but are usually stored without cooling when not in use. It is exposed to repeated temperature changes between an extremely low temperature of about 77K and a room temperature when not in use.

  For this reason, the bumps used in the FCB are distorted and deformed due to the stress caused by the difference in thermal expansion coefficient between the compound semiconductor substrate on which the light receiving element is formed and the silicon substrate on which the readout circuit is formed. As a result, contact between adjacent bumps may occur.

  When a bump contact occurs, a large current flows through the two bumps with low electrical resistance and almost no current flows through the other. As a result, the pixels corresponding to both bumps are invalid pixels. End up.

  For this reason, this problem is particularly problematic in a quantum infrared imaging device in which the number of pixels is increasing and the pitch is being reduced.

  As a general method of preventing such contact between adjacent bumps, for example, in the semiconductor mounting field, it is possible to ensure insulation between adjacent bumps while increasing bump strength by filling a thermosetting resin between the bumps. A technique called “underfill” is known.

  In addition, there is known a method of trying to avoid a short circuit between bumps by providing an insulating wall-like structure such as a resin between adjacent bumps (see, for example, Patent Documents 1 and 2).

Japanese Patent Laid-Open No. 6-236981 JP-A-8-288335

  Since the quantum infrared imaging device has a narrow pitch and high density bump arrangement as compared with a general semiconductor device, voids (bubbles) are likely to occur when the resin is filled when the underfill method is applied to prevent bump contact.

  In addition, since compound semiconductors such as HgCdTe are very fragile, they have technical problems such that cracks are likely to occur due to stress of the underfill resin.

  In addition, when an insulating wall structure in which both ends are fixed to the light receiving element substrate and the silicon substrate is installed between adjacent bumps instead of the underfill resin, a crack is generated in the light receiving element substrate due to stress from the insulating wall. Sometimes.

  The present invention has been made in order to solve the above-described problem, and in a quantum infrared detection device in which a first substrate having a readout circuit and a second substrate having a light receiving element are bump-connected, an HgCdTe Quantum infrared imaging device for preventing contact between adjacent bumps due to a difference in thermal expansion coefficient between the first substrate and the second substrate without affecting the second substrate composed of, for example, and a method for manufacturing the same The purpose is to provide.

  In order to achieve the above object, a quantum infrared imaging device according to the present invention is a first substrate provided with a readout circuit for a quantum infrared light receiving device, electrically connected by the first substrate and the FCB, A second substrate provided with a light receiving element, a conductor bump group that electrically connects the first substrate and the second substrate by FCB, and so as to surround each bump, only on the first substrate side And an insulating wall fixed and provided with a gap between the second substrate.

  In the present invention, an insulating partition structure fixed only on the first substrate side is provided between the bumps, thereby preventing contact between adjacent bumps due to bump deformation caused by a thermal cycle.

  In addition, since the insulating wall is fixed only to the first substrate and is not fixed to the second substrate, the second substrate does not receive stress from the resin wall.

The schematic cross section which showed the example of a structure of the quantum type external line image sensor. The schematic diagram which showed the procedure from application | coating of insulating resin to the thermosetting process of the resin wall in 1st embodiment. The schematic diagram which showed the difference in the vapor deposition shape of a bump resulting from the difference in the shape of a resist. The schematic diagram which showed the procedure from application | coating of the resist of the 1st layer to vapor deposition of indium in 1st embodiment. The schematic diagram which showed the procedure from the removal of a resist to the flip chip bonding of a light receiving element board | substrate in 1st embodiment. The schematic diagram which showed the procedure from film-forming of a plating seed layer to image development of photosensitive polyimide in 2nd embodiment. The schematic diagram which showed the procedure from the heat processing of photosensitive polyimide to indium plating in 2nd embodiment. The schematic diagram which showed the procedure from the removal of a resist to the flip chip bonding of a light receiving element board | substrate in 2nd embodiment. The schematic diagram which illustrated the planar structure of the insulating wall in common with the 1st, 2nd Example.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  First, FIG. 1 is a schematic diagram showing the configuration of a quantum infrared imaging device used in the present invention. The first substrate has a readout circuit formed on a silicon substrate, and the second substrate has a light receiving element formed on a compound semiconductor substrate.

  FIG. 1 shows not the region where the readout circuit is formed, but the electrode formation region where flip chip bonding is performed. In each substrate, the electrodes are configured as follows.

  The electrode on the first substrate side has a three-layer structure formed by, for example, a first Al—Si layer 4, a second Al—Si layer 5, and a Ti—Pd layer 6 from the side of the silicon substrate 1 provided with a readout circuit, It is disposed on the insulating film 2.

For example, SiO ₂ or PSG (Phospho-Silicate Glass) can be used as the interlayer insulating film 2. Further, the periphery of the first substrate side electrode is covered with a protective film 3 composed of, for example, a SiO ₂ / SiN layer from the silicon substrate 1 side.

The electrode on the second substrate side has a four-layer structure formed by, for example, the first Au layer 11, the Mo layer 12, the Pt layer 13, and the second Au layer 14 from the side of the HgCdTe substrate 8 including the light receiving element, and n ⁺ junk Connected to John 9.

  The second substrate side electrode is made of ZnS, for example, and is covered with a protective film 10 formed on the light receiving element substrate 8. Further, the first substrate side electrode and the second substrate side electrode are electrically connected by bumps 7 formed of a metal such as indium.

  The configuration of the quantum infrared imaging device is only an example, and other structures and materials may be used as long as the effects necessary for the quantum infrared imaging device can be obtained.

  Next, based on FIG. 2 thru | or FIG. 5, 1st embodiment in this invention is described. The first substrate 101 has a configuration in which a readout circuit is formed on a silicon substrate by a known method.

  However, in FIGS. 2 to 5, the first substrate 101 schematically represents the entire substrate including a circuit, the configuration of the readout circuit is omitted, and only the electrode 102 used for bonding is described.

  FIG. 2A is a schematic cross-sectional view showing a state where an insulating resin such as photosensitive polyimide is applied on the first substrate 101. For example, photosensitive polyimide 103 is applied as an insulating resin on the first substrate 101 on which the electrode 102 is formed by a method such as spin coating or spray coating.

  At this time, the film thickness at the time of applying the photosensitive polyimide 103 is set so as to finally have a desired insulating wall height in consideration of film reduction during the development process and heat shrinkage during heat curing (curing). To do.

  Specifically, the photosensitive polyimide is applied at a thickness of about 100% to 110% of the distance between both substrates in the insulating wall forming region. When the distance between the two substrates is designed to be about 10 μm, photosensitive polyimide having a thickness of about 10 to 11 μm may be applied.

  Next, as shown in FIG. 2B, the exposure light 105 is irradiated to the photosensitive polyimide 103 using a mask 104 in which a mask pattern corresponding to an insulating wall structure of a desired pattern such as a lattice shape or a cylindrical shape is formed. Do.

  Of the coated photosensitive polyimide 103, the physical properties change only in the portion 103B that has been exposed to light by exposure, and the physical properties of the non-exposed portion 103A do not change.

  In the case of a positive type photosensitive polyimide as illustrated in FIG. 2B, only the portion having changed physical properties is dissolved by the developer, so that the photosensitive polyimide 103 is subjected to development processing after exposure. A predetermined insulating wall pattern as illustrated in 2 (c) is formed.

  Subsequently, the polyimide is subjected to thermosetting (curing) at a temperature of about 250 ° C. to 300 ° C. FIG. 2D is a schematic diagram showing the change of the resin wall before and after the heat treatment.

  The resin wall 106 represented by the dotted line shrinks and cures at a constant rate like the insulating wall 107 by heat treatment. Depending on the resin used, it is possible to accelerate curing by irradiating with ultraviolet rays. After curing, the oxide film on the surface of the electrode 102 may be removed by means such as ion milling.

  Next, a resist pattern for forming bumps is formed. When bumps are formed by vapor deposition lift-off, it is preferable that the resist has a ridge structure 204 as exemplified in FIG. The reason will be described below.

  FIG. 3A is a schematic diagram illustrating the result of bump deposition using a resist pattern having a ridge structure, and FIG. 3B is a schematic view illustrating the result of performing a similar action using a resist pattern having no ridge structure. FIG.

  When there is no ridge structure, when the bump 207 is deposited, the resist 206 is covered with the deposited metal as shown in FIG. 3B, and it becomes difficult to remove the resist 206.

  However, by providing the resist with a ridge structure, the resist 206 can be exposed to the outside even after the bump 207 is deposited as shown in FIG.

  A resist pattern forming procedure using two-step exposure will be described below as a method of giving the resist a ridge structure.

  FIGS. 4A and 4B are schematic views illustrating a procedure for creating a resist having a ridge structure by two-step exposure. First, a first layer of resist is applied on the first substrate 101, and the exposure light 109 is irradiated through the mask 108.

  The resist in the portion exposed to the exposure light 109 is denatured. The resist at the non-exposed portion is represented by 110A, and the resist at the exposed portion is represented by 110B.

  Next, a new resist is applied as a second-layer resist so as to overlap the applied resists 110A and 110B, and the exposure light 109 is irradiated through a mask 111 having a smaller width than the mask 108.

  The resist exposed to the light is similarly modified. The resist at the non-exposed portion is denoted by 112A, and the resist at the exposed portion is denoted by 112B. The exposed portions of the resists 110B and 112B are removed by the developer, and a resist pattern having a ridge structure as illustrated in FIG. 4C is formed.

  Note that the entire resist having a ridge structure (a general term for the resist 110A and the resist 112A) is defined as a resist 113, and will be described hereinafter.

  The horizontal projection length of the ridge structure in this embodiment is about 3 μm on one side, but this value varies depending on the apparatus used, the vapor deposition source, the film thickness, etc., and the description here limits the length of the ridge structure at all. Not what you want.

  After the resist pattern is formed, metal used as bumps is deposited. In the present embodiment, indium is used as a bump.

  Since indium is soft, it can serve as a buffer material that absorbs a certain amount of deformation, has a low melting point, and has characteristics such as moderate bonding to other metals (for example, Au). For this reason, the consistency with the manufacturing process of the quantum infrared imaging device is good.

  Therefore, indium is generally used for the bumps of the quantum infrared imaging device, but metals other than indium can also be used, and the description here limits the material of the bumps to only indium. It is not a thing.

  FIG. 4D is a schematic view illustrating the state after indium deposition. Indium is deposited on the electrode 102 and the resist 113, respectively. After indium deposition, lift-off cleaning is performed with a stripping solution such as acetone. FIG. 5A is a schematic view illustrating the state after lift-off cleaning.

  At the same time as the resist 113 is removed by the stripping solution, the indium 114 formed on the resist 113 is also removed, and only the indium 115 formed on the electrode 102 remains on the first substrate 101 (on the electrode 102).

  Further, since the insulating wall 107 made of polyimide is subjected to thermosetting treatment, it remains on the first substrate 101 without being dissolved by the lift-off stripping solution.

  Next, indium 115 is reflowed at about 200 ° C. FIG. 5B is a schematic view illustrating a state where indium is reflowed. The heat resistance of the cured photosensitive polyimide resin wall 107 is 300 ° C. or more, and is not affected by the reflow treatment at about 200 ° C.

  Next, as shown in FIG. 5C, after the reflow of the bump 115, the electrode 118 on the second substrate 117 side and the reflowed bump 116 are flip-chip bonded. When heat and a load are applied at the time of flip chip bonding, mutual diffusion occurs at the interface between indium and the electrode, and the bump and the electrode are bonded.

  The second substrate 117 has a configuration in which a light receiving element region is formed on the HgCdTe substrate by a well-known method, and an electrode 118 for connecting to a readout circuit formed on the first substrate is formed in advance. .

  However, in the drawing, the second substrate 117 schematically represents the entire substrate including the light receiving element, the configuration of the light receiving element is omitted, and only the electrode 118 used for bonding is described.

  As shown in FIG. 5C, the electrode 102 on the first substrate 101 side and the electrode 118 on the second substrate 117 side are electrically connected by the bump 116, and the insulating wall 107 partitioning adjacent bumps is the first wall. It is fixed only on the substrate 101 side and does not contact the second substrate 117 side.

  The height of the insulating wall is preferably as high as possible as long as it is basically not in contact with the second substrate made of the HgCdTe substrate or the like on which the light receiving element is formed.

  However, considering that errors may occur at the time of bump creation, the height that does not contact the second substrate and can function as an insulation wall that prevents contact between bumps, for example, formation of an insulation wall after FCB About 70 to 90% of the distance between both substrates in the region is considered to be sufficient.

  By adopting such a configuration, according to the present embodiment, insulation between adjacent bumps can be secured without physically affecting the second substrate, so that the quality and durability of the device can be improved.

  In the case of using the structure disclosed in Japanese Patent Application Laid-Open No. 6-236981 as Patent Document 1, it is necessary to install the resin wall also on the side of the HgCdTe substrate which is a light receiving element substrate.

  However, since the HgCdTe substrate is vulnerable to heat and denatures at about 100 ° C., it is difficult to thermoset the insulating resin without affecting the light receiving element.

  In addition, the contact between adjacent bumps often occurs in the central portion of the gap between the substrates, but it is difficult to think that the insulating wall can sufficiently exhibit the effect because that portion is a gap. However, according to the present embodiment, it is possible to cope with such a problem.

  Further, when the structure disclosed in Japanese Patent Laid-Open No. 8-288335 described above as Patent Document 2 is used, fine dust is easily generated due to the movement of the insulating wall, which causes contamination.

  In addition to this, there may be a problem that the insulating wall collides with the HgCdTe substrate, which causes a crack, but according to the present embodiment, it is possible to cope with such a problem. .

  Next, a method for manufacturing a quantum infrared imaging device according to the second embodiment of the present invention will be described with reference to FIGS.

  In the first embodiment, indium bumps are formed by a vapor deposition lift-off method. In the second embodiment, indium bumps are formed not by vapor deposition lift-off but by pattern plating.

  The first substrate 301 has a configuration in which a readout circuit is formed by a known method. However, in FIGS. 6 to 8, the first substrate 301 schematically represents the entire substrate including the circuit, the configuration of the readout circuit is omitted, and only the electrode 302 used for bonding is described.

  FIG. 6A is a schematic cross-sectional view illustrating a state in which a plating seed film is formed on the first substrate 301. First, similarly to the first embodiment, after forming the electrode 302 on the first substrate 301 provided with the readout circuit, the plating seed layer 303 is formed.

  Here, as the material of the plating seed layer, for example, a Ti / Cu layered structure from the first substrate side may be used. The structure and materials that the first substrate side electrode 302 can take are the same as those in the first embodiment.

  The process up to the formation of the insulating wall structure is performed in the same procedure as in the first embodiment. FIG. 6B is a schematic view illustrating a state in which an insulating resin 304 is applied on the first substrate 301 on which the plating seed layer 303 is formed.

  For example, an insulating resin such as photosensitive polyimide is applied onto the plating seed layer 303 by a method such as spin coating or spray coating.

  The film thickness when applying the photosensitive polyimide 304 is set so as to be the final height of the insulating wall in consideration of film reduction by the development process and thermal shrinkage during curing, as in the first embodiment. It is the same.

  Specifically, the photosensitive polyimide is applied at a thickness of about 100% to 110% of the distance between both substrates in the insulating wall forming region. When the distance between the two substrates is designed to be about 10 μm, photosensitive polyimide having a thickness of about 10 to 11 μm may be applied.

  The height of the insulating partition is preferably as high as possible as long as it is basically not in contact with the second substrate made of the HgCdTe substrate or the like on which the light receiving element is formed.

  However, considering that errors may occur during bump formation, the height that does not contact the second substrate and functions as an insulating wall that prevents contact between the bumps, for example, an insulating wall forming region after FCB It is considered that 70 to 90% of the distance between the two substrates in FIG.

  Next, as shown in FIG. 6C, the exposure light 306 is irradiated to the photosensitive polyimide 304 using a mask 305 in which a mask pattern corresponding to an insulating wall structure of a desired pattern such as a lattice shape or a cylindrical shape is formed. I do.

  Of the applied photosensitive polyimide 304, the physical property changes only in the portion 304B that has been exposed to the exposure light 306, and the physical property of the non-exposed portion 304A does not change.

  In the case of a positive type photosensitive polyimide as illustrated in FIG. 3, only a portion having changed physical properties is dissolved by a developing solution. Therefore, development processing is performed on the photosensitive polyimide 304 after exposure, so that FIG. A predetermined insulating wall pattern as exemplified in FIG.

  As in the first embodiment, the polyimide is subsequently thermoset at a temperature of about 250 ° C. to 300 ° C. FIG. 7A is a schematic diagram showing the change of the resin wall before and after the heat treatment.

  The resin wall 307 represented by the dotted line shrinks at a constant rate as indicated by 308 by heat treatment and is cured. Depending on the resin used, curing may be accelerated by irradiation with ultraviolet rays. After curing, the oxide film on the surface of the seed layer 303 may be removed by means such as ion milling.

  Next, a resist pattern for forming bumps is formed. FIG. 7B and FIG. 7C are schematic views showing an example of a resist pattern forming procedure by pattern plating.

  First, a resist 311 is applied on the first substrate 301, and the exposure light 310 is irradiated through a photomask 309 adjusted so that light passes only at positions corresponding to the electrodes 302.

  The resist 311 in the portion exposed to the exposure light 310 is denatured. The resist at the non-exposed portion is represented by 311A, and the resist at the exposed portion is represented by 311B.

  The exposed portion of the resist 311B is removed by the developer, and a resist pattern in which the upper portion of the electrode 302 is exposed as shown in FIG. 7C is formed.

  The resist pattern can be created even when a negative resist is used. In the case of using a negative resist, the exposure light 310 is irradiated through a photomask adjusted to block light only at a position corresponding to the electrode 302.

  The portion of the resist that has not been modified by exposure is removed by the developer, and a resist pattern in which the upper portion of the electrode 302 is exposed is formed.

  After the resist pattern is formed, metal used as a bump such as indium is plated. FIG. 7D is a schematic view illustrating the state after plating.

  Indium 312 adheres only on the plating seed layer 303 above the electrode 302 that is not covered with the resist 311A, and a bump is formed.

  After indium plating, the resist is removed. FIG. 8A is a schematic diagram showing a state after the resist is removed. The resist 311A is removed by the resist stripping solution, and the indium bumps 312 and the insulating wall structure 308 remain on the first substrate 301.

  Thereafter, the excess seed layer 303 is removed by ion milling or the like. The state after removing the seed layer is illustrated in FIG.

  The indium bump 312 is reflowed at about 200 ° C. FIG. 8C is a schematic view illustrating a state where indium is reflowed. The cured photosensitive polyimide resin wall 308 has a heat resistance of 300 ° C. or higher, and is not affected by the reflow treatment at about 200 ° C.

  FIG. 8D is a schematic view illustrating the state after flip chip bonding. After the reflow of the indium bump 312, the electrode 314 on the second substrate 315 side and the reflowed indium bump 313 are flip-chip bonded.

  The second substrate 315 has a configuration in which a light receiving element region is formed on the HdCdTe substrate by a well-known method, and an electrode 314 for connecting to a readout circuit formed on the first substrate 301 is formed in advance. .

  However, in the drawing, the second substrate 315 schematically represents the entire substrate including the light receiving element, the configuration of the light receiving element is omitted, and only the electrode 314 used for bonding is described.

  As shown in FIG. 8D, the electrode 302 on the first substrate 301 side and the electrode 314 on the second substrate 315 side are electrically connected by bumps 313, and the insulating wall 308 that partitions adjacent bumps is the first. It is fixed only on the substrate 301 side and does not contact the second substrate 315 side.

  FIG. 9 is a schematic view illustrating the planar structure of the insulating wall. Thus, in both the first embodiment and the second embodiment, the insulating wall pattern has a lattice shape (FIG. 9A), a circular structure surrounding the bump periphery (FIG. 9B), and an adjacent bump. A planar structure such as a wall-like structure (FIG. 9C) between them may be used.

  In both the first embodiment and the second embodiment, the insulating wall is formed before the indium bump is formed. This is because, depending on the type of insulator used for the bump spacing wall such as photosensitive polyimide, the temperature of the heat treatment during the formation of the insulator (for example, thermosetting treatment of photosensitive polyimide) may be higher than the melting point of the indium bump. In addition, when the insulating resin is applied after the bumps are formed, large irregularities are generated, and it is difficult to secure a sufficient exposure focus margin.

  In the first and second embodiments, the insulating wall pattern is created using positive photosensitive polyimide, but it can also be created using negative photosensitive polyimide.

  In the case of using a negative photosensitive polyimide, the physical properties change only in the portion exposed to light by exposure and are not dissolved by the developer.

  Therefore, it is sufficient to irradiate the photosensitive polyimide with exposure light using a mask in which a mask pattern that allows light to pass through only a portion that is desired to remain as a resin wall is used.

  In the first embodiment and the second embodiment, the procedure for creating the insulating wall structure by photolithography using photosensitive polyimide is exemplified, but the method for creating the insulating wall pattern is not limited to this.

  For example, a similar structure can be formed by applying photolithography using a photoresist to a non-photosensitive insulating resin.

DESCRIPTION OF SYMBOLS 1 Silicon substrate provided with read-out circuit 2 Interlayer insulating film 3 Protective film 4 1st Al-Si layer 5 2nd Al-Si layer 6 Ti-Pd layer 7 Bump 8 Substrate provided with light receiving element 9 n ⁺ junction 10 Protective film 11 First Au layer 12 Mo layer 13 Pt layer 14 Second Au layer 101 First substrate 102 equipped with readout circuit First substrate side electrode 103 Insulating resin 103A such as photosensitive polyimide Non-exposed portion 103B of photosensitive polyimide Photosensitive Polyimide exposed portion 104 photomask 105 exposure light 106 resin wall 107 before heat treatment insulating wall 108 first photomask 109 exposure light 110 first layer resist 110A first layer resist non-exposed portion 110B first layer Exposed portion 111 of the second resist Second photomask 112 having a smaller width to transmit light than the first photomask Second resist 112A Second resist Non-exposed portion 112B Exposed portion 113 of second layer resist 113 Resist 114 having ridge structure Indium 115 formed on resist Indium 116 formed on electrode Indium bump (after reflow)
117 Second substrate 118 provided with light receiving element Second substrate side electrode 201 First substrate 202 provided with readout circuit First substrate side electrode 203 Resin wall 204 Resist 205 having ridge structure Bonded with resist No bump 206 レ ジ ス ト No resist 207 Resist bonded bump 301 First substrate 302 with readout circuit First substrate side electrode 303 Plating seed layer 304 Insulating resin 304A such as photosensitive polyimide Non-sensitive polyimide Exposed portion 304B Exposed portion of photosensitive polyimide 305 Photomask 306 Exposure light 307 Resin wall 308 before heat treatment Resin wall 309 Photomask 310 Exposure light 311 Resist 311A Non-exposed portion of resist 311B Resist exposed portion 312 Indium bump 313 Indium bump ( After reflow)
314 Second substrate side electrode 315 Second substrate provided with light receiving element

401 Resin wall 402 Indium bump

Claims (11)

A first substrate provided with a readout circuit for the quantum infrared light receiving element;
A second substrate having a quantum infrared light receiving element electrically connected to the first substrate by flip chip bonding;
A plurality of conductive bump groups electrically connecting the first substrate and the second substrate by flip chip bonding;
An insulating wall that is formed so as to surround each bump, is fixed only to the first substrate side, and has an air gap between the second substrate,
A quantum infrared imaging device.   2. The quantum infrared imaging device according to claim 1, wherein the first substrate is made of a silicon substrate, and the second substrate is made of a compound semiconductor.   The quantum infrared imaging device according to claim 1, wherein the second substrate is made of HdCdTe.   4. The quantum infrared imaging device according to claim 1, wherein the conductor bump is made of indium. 5.   5. The quantum infrared imaging device according to claim 1, wherein the insulating wall is made of photosensitive polyimide. 6.   The height of the insulating wall is in a range of 70 to 90% of a distance between the second substrate and the first substrate in the insulating wall forming region. A quantum infrared imaging device according to claim 1. Applying an insulating resin on a first substrate provided with a readout circuit for the quantum infrared light receiving element, and patterning to form a desired insulating wall structure so as to surround the electrode region;
Thermally curing the patterned insulating wall structure; and
A procedure for forming a conductor bump on the electrode on the first substrate side;
Reflowing the formed conductor bumps;
Flip chip bonding the first substrate and a second substrate having a light receiving element with the bumps;
A method of manufacturing a quantum infrared imaging device, comprising:   8. The method of manufacturing a quantum image element according to claim 7, wherein the bump is formed by vapor deposition lift-off.   The method for manufacturing a quantum infrared imaging device according to claim 7, wherein the bump is formed by pattern plating.   The method for manufacturing a quantum infrared imaging device according to any one of claims 7 to 9, wherein the insulating resin is photosensitive polyimide, and the photosensitive polyimide is patterned by photolithography.   11. The method of manufacturing a quantum infrared imaging device according to claim 10, wherein a film thickness when applying the photosensitive polyimide is 100% to 110% of a distance between both substrates in the insulating wall forming region.

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