JP2013077628A - Manufacturing method of multi-chip laminated body - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a multi-chip laminated body which manufactures a multi-chip laminated body using TSV mounting process which allows a continuity inspection of a non-board chip laminated body to be conducted in a conventional inspection apparatus.SOLUTION: Multiple test electrodes 130 and multiple exterior electrodes 131 are formed on a surface of a chip 110 formed by dividing a wafer. The chip 110 is provided with multiple silicon through holes 111 which establish electrical continuity between the external electrodes 131 and the test electrodes 130. Next, a non-board chip laminated body 100 is fixed onto an adhesive tape 252 and a filling seal body 150 is formed on the adhesive tape 252. Then, a tape carrier 250 supporting the adhesive tape 252 is fixed to the interior of a wafer test tray 260. In a continuity inspection, the non-board chip laminated body 100 is mounted in the interior of a wafer inspection apparatus 270 with the adhesive tape 252 adhering thereto, the quality of the conduction of the non-board chip laminated body 100 is determined by multiple probes 271 of the wafer inspection apparatus 270.

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a multichip stacked body.

  In a multi-chip stacked mounting method, which is a new high-density mounting technology, a large number of stacked chips are mounted in a package. When inspecting the multi-chip laminate manufactured in this way, the chips are stacked one by one on the substrate, and then a continuity test is performed by applying a probe to the electrode on the chip. At this time, the multi-chip laminate increases in size because the surface bonding area and thickness of the multi-chip laminate are increased by the substrate on which the chips are laminated. Japanese Patent Application Laid-Open No. 2011-071441 describes a semiconductor device manufacturing method for manufacturing a substrate-free chip stack by a wafer level chip stacking method that does not use a substrate in order to reduce the size of the multi-chip stack.

JP 2011-071441 A

  However, in the method of manufacturing a semiconductor device described in Patent Document 1, when a defective chip whose position is not fixed is generated in the wafer, inspection is performed using a wafer-based aiming method. Will increase. Further, in the multi-chip laminated body, the interval between the external connection electrode and the test electrode is reduced from about several hundred μm to 100 μm or less, so that the continuity test cannot be performed with the probe of the conventional inspection apparatus. On the other hand, although the method of implementing a continuity test after installing a non-substrate chip laminated body on a substrate can be considered, in this method, the quality of the contact between the laminated chips cannot be determined in advance. In addition, there is a method in which the non-substrate chip stack is bonded to a transfer substrate made of silicon having a fan-out circuit and a fan-in terminal before the non-substrate chip stack is installed on the substrate, and a continuity test is performed. Such a manufacturing method has a complicated process and high cost.

  An object of the present invention is to provide a manufacturing method of a multi-chip stacked body manufactured by using a TSV (Through Silicon Via) mounting process in which a continuity test of a substrate-free chip stacked body can be performed by a conventional inspection apparatus.

  Another object of the present invention is to provide a multi-chip capable of preventing the use of a non-standard substrate-free chip stack at a low cost by determining the quality of the substrate-free chip stack before being mounted on a substrate. It is providing the manufacturing method of a laminated body.

  The manufacturing method of the multichip laminated body according to claim 1 includes the following five steps from the first step to the fifth step. In the first step, there is provided a substrate-free chip stacked body having a plurality of test electrodes on the surface of a chip group consisting of a plurality of stacked chips and forming a chip stacking gap between adjacent chips. In the second step, an adhesive tape is fixed to the surface opposite to the surface on which the test electrode of the substrate-free chip stack is formed. In the third step, a filling sealing body is formed on the adhesive tape so as to fill the chip stacking gap. In the fourth step, a tape carrier that forms an opening for supporting the adhesive tape is fixed to the wafer test tray. In the fifth step, the test electrode group on the substrate-free chip stacked body introduced into the wafer inspection apparatus while being bonded to the adhesive tape using a plurality of probes of the wafer inspection apparatus is searched, and the connection of the substrate-free chip stacked body is conducted. Conduct an inspection.

  The method for manufacturing a multi-chip laminate according to claim 2 further includes a step of detaching the tape carrier from the wafer test tray.

  In the manufacturing method of the multichip laminated body according to claim 3, the wafer test tray is larger than the tape carrier, and the shapes of both are different.

  According to a fourth aspect of the present invention, the wafer test tray includes a base made of copper, iron, or an alloy thereof.

  According to a fifth aspect of the present invention, the wafer test tray has a plurality of fixing portions provided on the base, and the fixing portion group fixes the tape carrier at a predetermined position.

  In the manufacturing method of the multichip laminated body of Claim 6, a fixing | fixed part group fixes the some corner | angular part of a tape carrier.

  In the manufacturing method of the multichip laminated body according to claim 7, the base of the wafer test tray has a fixed surface and an opening formed in the fixed surface, and the shape of the opening is the same shape as the peripheral edge of the tape carrier.

  In the manufacturing method of the multichip laminated body according to claim 8, the filling sealing body forming step further includes an overflow resin removing step of removing the filling sealing body at the resin overflow portion exceeding the non-substrate chip laminated body.

  In the manufacturing method of the multichip laminated body according to the ninth aspect, the filling sealing body covers a plurality of side surfaces of the chip group after the overflow resin removing step.

  In the manufacturing method of the multichip laminated body according to the tenth aspect, a plurality of silicon through holes are provided in the chip, and a plurality of interconnection electrodes are installed in the chip lamination gap group of the non-substrate chip laminated body. At this time, the interconnecting electrode group is electrically connected to the silicon through hole group.

It is sectional drawing which shows the step of the manufacturing method of the multichip laminated body by one Embodiment of this invention. It is sectional drawing which shows the next step of FIG. 1A of the manufacturing method of the multichip laminated body by one Embodiment of this invention. It is sectional drawing which shows the next step of FIG. 1B of the manufacturing method of the multichip laminated body by one Embodiment of this invention. It is sectional drawing which shows the next step of FIG. 1C of the manufacturing method of the multichip laminated body by one Embodiment of this invention. It is sectional drawing which shows the next step of FIG. 1D of the manufacturing method of the multichip laminated body by one Embodiment of this invention. It is sectional drawing which shows the next step of FIG. 1E of the manufacturing method of the multichip laminated body by one Embodiment of this invention. It is sectional drawing which shows the next step of FIG. 1F of the manufacturing method of the multichip laminated body by one Embodiment of this invention. It is sectional drawing which shows the next step of FIG. 1G of the manufacturing method of the multichip laminated body by one Embodiment of this invention. It is sectional drawing which shows the next step of FIG. 1H of the manufacturing method of the multichip laminated body by one Embodiment of this invention. It is a front view which shows the wafer test tray used in the manufacturing method of the multichip laminated body by one Embodiment of this invention. It is sectional drawing which shows the wafer test tray used in the manufacturing method of the multichip laminated body by one Embodiment of this invention. It is a front view which shows the wafer test tray used in the manufacturing method of the multichip laminated body by one Embodiment of this invention, and is different from FIG. 2A and FIG. 2B. It is sectional drawing which shows the wafer test tray used in the manufacturing method of the multichip laminated body by one Embodiment of this invention, and is different from FIG. 2A and FIG. 2B. It is a front view which shows the wafer test tray which mounts a tape carrier in the manufacturing method of the multichip laminated body by one Embodiment of this invention. It is a three-dimensional view showing a wafer inspection apparatus used in a method for manufacturing a multichip laminate according to an embodiment of the present invention.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, in the drawings, it is a schematic diagram showing the basic configuration and implementation method of the present invention, showing only the elements and configuration according to the present invention, and describing the number, outer shape, and dimensions of the members actually implemented at a certain ratio. Rather, they are simplified or exaggerated for convenience and clarity of explanation. On the other hand, the number, outer shape, and dimensions actually used may be complicated by the arrangement of members according to various designs.

(One embodiment)
The manufacturing method as a multichip laminated body by one Embodiment of this invention is demonstrated based on FIG. 1A-FIG.
As shown in FIG. 1A, in the step of providing the substrate-free chip stack 100 as the “first step”, the wafer is divided to form a plurality of chips 110, and a plurality of test electrodes 130 are formed on the surface of each chip 110. And a plurality of external electrodes 131 are formed. During and after the wafer is divided, the group of chips 110 is attached onto the wafer dicing tape 210. The wafer dicing tape 210 is affixed to a wafer support ring (not shown), and a chip 110 group is formed by making a cut along the wafer dicing line using the wafer dicing blade 220 when dividing the wafer.

  After wafer level inspection, good chips 110 are classified and collected, and a plurality of chips 110 are stacked on a chip carrier 230 to form a substrate-free chip stack 100 as shown in FIG. 1B. At this time, a chip stacking gap 120 is formed between adjacent chips 110. A plurality of exposed pad-shaped test electrodes 130 are formed on the surface of the uppermost chip, and columnar external electrodes 131 made of copper are provided. The interval between the test electrode 130 groups is larger than the interval between the external electrode 131 groups. In this embodiment, the test electrode group 130 is provided at intervals of about 60 μm to about 100 μm. The external electrode 131 group is provided at an interval of about 30 μm to 60 μm.

  As shown in FIG. 1B, each chip 110 is provided with a plurality of silicon through holes 111. The silicon through hole 111 is connected to the external electrode 131 in the vertical direction and is electrically connected to the group of external electrodes 131. Further, the silicon through hole 111 is electrically connected to the test electrode 130 group via a redistribution layer (not shown). A plurality of interconnecting electrodes 140 are provided in the chip stacking gap 120 of the substrate-free chip stack 100. The interconnecting electrode 140 group is constituted by the external electrode 131 on the chip surface formed before the chip 110 is stacked, and is electrically connected to the silicon through hole 111 group.

  Next, as shown in FIG. 1C, as a “second step”, the non-substrate chip stack 100 is fixed on the adhesive tape 252. At this time, the substrate-free chip stack 100 is fixed so that the test electrode group 130 is on the opposite side of the adhesive tape 252. The adhesive tape 252 can fix the substrate-free chip stack 100 by adhesiveness, and is installed in the opening 251 of the tape carrier 250 (see FIG. 1F). The tape carrier 250 is an elongated metal housing, and the step of installing the adhesive tape 252 on the tape carrier 250 is performed before or during the formation of the filling sealing body. In the present embodiment, the adhesive tape 252 is installed on the tape carrier 250 after dispensing during the filling sealing body formation process and before heat curing. Thereby, the tape carrier 250 is used as a mounting jig for transporting the substrate-free chip stack 100 to the heating furnace.

  Next, as shown in FIG. 1C, as a “third step”, the filling sealing body 150 is formed on the adhesive tape 252 using the application needle 240. At this time, by applying an appropriate temperature and time, the filled sealing body 150 is sufficiently filled in the chip stacking gap 120 group by capillary action. Fill seal 150 seals interconnected electrode 140 group as shown in FIG. 1D. The filled sealing body 150 filled is cured by heating.

  Further, as shown in FIGS. 1D and 1E, the step of forming the filling sealing body 150 includes an overflow resin removing step. In the overflow resin removing step, the filling sealing body 150 of the resin overflow portion 151 protruding from the non-substrate chip laminated body 100 is removed. Thereby, the non-substrate chip laminated body 100 is brought close to a cubic shape. The overflow resin removal step is performed before the molding of the filling sealing body 150, and as shown in FIG. 1E, the filling sealing body 150 is removed so as to cover the plurality of side surfaces 112 of the chip 110 group after the overflow resin removal step. To do. This effectively protects the group of chips 110 in the substrate-free chip stack 100.

  Next, as shown in FIG. 1G, the tape carrier 250 is fixed in the wafer test tray 260 as the “fourth step”.

  Next, as shown in FIG. 1H, as a “fifth step”, the non-substrate chip stack 100 is mounted in the wafer inspection apparatus 270 while being bonded to the adhesive tape 252. The wafer test tray 260 is larger than the tape carrier 250 as shown in FIG. 4, and the wafer test tray 260 and the tape carrier 250 are different in shape. Here, the wafer test tray 260 is for mounting the tape carrier 250, and constitutes a module conversion jig. The wafer test tray 260 has a disk shape, which is the same as the shape of a well-known wafer support ring. However, the wafer test tray 260 is not formed with a central opening of a known wafer support ring, and is not provided with a dicing tape for bonding the wafers. Further, by making the tape carrier 250 have an elongated shape, strip-like transportation can be performed as in the substrate strip method.

  The wafer test tray 260 includes a base 261 made of copper, iron, or an alloy thereof. Specifically, as shown in FIGS. 2A and 2B, the wafer test tray 260 has a plurality of fixing portions 262, and the fixing portions 262 are installed on the base 261 to fix the tape carrier 250 at a predetermined position. To do. As shown in FIG. 4, the fixing portion 262 group fixes a plurality of corner portions of the tape carrier 250 that fixes the non-substrate chip stack 100 attached to the adhesive tape 252. As a result, the non-substrate chip stack 100 is mounted in the wafer inspection apparatus 270 while being bonded to the adhesive tape 252.

  3A and 3B show different shapes of the wafer test tray 260 as a variation of the present embodiment. The base 261 of the wafer test tray 260 shown in FIG. 3A has a fixed surface 263 and an opening 264 formed in the fixed surface 263, and the shape of the opening 264 is the same shape as the periphery of the tape carrier 250. When the tape carrier 250 is mounted on the fixing surface 263, the bottom of the tape carrier 250 is fixed in the wafer test tray 260 by being partially fitted in the opening 264.

  In the wafer inspection apparatus 270, as shown in FIG. 1H, the test electrode 130 group is searched using a plurality of probes 271 of the wafer inspection apparatus 270, and the continuity inspection of the substrate-free chip stack 100 is performed. Here, the probe 271 group is attached to the probe card 275. As shown in FIG. 5, the wafer inspection apparatus 270 has a load area 272, a transfer area 273, and a test area 274. A well-known wafer position fixing ring is loaded or unloaded in the load area 272, and is transferred to the test area 274 after passing the alignment inspection in the transfer area 273. In the test area 274, a probe card 275 equipped with a group of probes 271 is provided to search the wafer level of the electrodes on the chip surface. The wafer test tray 260 has the same dimensions as the wafer support ring, and is mounted directly in the load area 272. In the test area 274, the test electrode 130 group of the substrate-free chip stack 100 is searched with the probe 271 group.

  After the inspection is completed, the tape carrier 250 is removed from the wafer test tray 260 as shown in FIG. 1I. Thereby, the wafer test tray 260 is repeatedly used. Thereafter, for the non-substrate chip laminated body 100, manufacturing processes such as marking and packaging are performed.

(effect)
(A) In the inspection of the non-substrate chip stack 100, it is possible to eliminate the need for reattaching the non-substrate chip stack 100 and removing the tape carrier 250 by peeling the adhesive tape 252. Further, the substrate-free chip stack 100 can perform a continuity test without being mounted on a transfer substrate having a fan-out circuit and a fan-in terminal that are conventionally used. That is, whether or not the interconnecting electrode 140 is bonded can be determined. Thereby, the frequency | count of use of an adhesive tape can be decreased. Therefore, the inspection cost of the non-substrate chip stacked body 100 can be reduced, and the inspection efficiency of the non-substrate chip stacked body 100 can be improved.

  (B) In the method for manufacturing the substrate-free chip stack 100 according to this embodiment, the substrate-free chip stack 100 can be directly classified in the wafer inspection apparatus 270. Thereby, the quality of the non-substrate chip laminated body 100 can be determined before being placed on the substrate, and the non-standard non-substrate chip laminated body 100 can be removed. Therefore, it is possible to prevent the use of the non-standard substrate-free chip stack 100.

  (C) Moreover, in the manufacturing method of the substrate-free chip laminated body 100 of the present embodiment, the continuity inspection can be performed using a conventional wafer inspection apparatus, and the demand for fine pitch search can be satisfied.

(Other examples)
(A) In the above-described embodiment, a plurality of external electrodes are provided on the surface of the uppermost chip. However, the electrode provided on the surface of the uppermost chip is not limited to this. The external electrode may be omitted, or the test electrode may be an external electrode.

  (A) In the above-described embodiment, the test electrode has a pad shape. However, the shape of the test electrode is not limited to this. It may be a bump shape.

  (C) In the above embodiment, the external electrode has a columnar shape made of copper. However, the shape and material of the external electrode are not limited to this. Solder balls or metal bumps may be used.

  (D) In the above-described embodiment, the interconnection electrode is constituted by the external electrode on the chip surface formed before lamination. However, the parts constituting the interconnection electrode are not limited to this. A conductive element may be used, or a combination of a metal column and a solder material may be used.

  (E) In the above-described embodiment, the overflow resin removing step is performed before the cured molding of the filled sealing body. However, the timing at which the overflow resin removing step is performed is not limited to this. You may implement after hardening molding of a filling sealing body. At this time, the resin overflow portion may be removed using a laser dividing tool.

  Although the present invention has been described based on the preferred embodiments thereof, the protection scope of the present invention is limited by the scope of the claims, and on the basis of this protection scope, any changes or modifications that come within the spirit and scope of the present invention. The modifications belong to the protection scope of the present invention.

100 Non-substrate chip stack (multi-chip stack),
110 chips,
111 Silicon through hole,
112 sides,
120 chip stacking gap,
130 test electrodes,
140 interconnecting electrodes,
150 filled sealing body,
151 Resin overflow site,
210 wafer dicing tape,
220 wafer dicing blade,
230 chip carrier,
240 application needle,
250 tape carrier,
251 opening,
252 adhesive tape,
253 corner,
260 wafer test tray,
261 base,
262 fixing part,
263 fixed surface,
264 opening,
270 wafer inspection equipment,
271 probe,
272 Road area,
273 transport area,
274 test area,
275 Probe card.

Claims (10)

A first step of providing a substrate-free chip stack having a plurality of test electrodes on a surface of a chip group consisting of a plurality of chips to be stacked and having a chip stacking gap formed between adjacent chips;
A second step of fixing an adhesive tape to a surface opposite to the surface on which the test electrode of the substrate-free chip stack is formed;
A third step of forming a filling sealing body so as to fill the chip stacking gap on the adhesive tape;
A fourth step of fixing a tape carrier forming an opening for supporting the adhesive tape to a wafer test tray;
The substrate-free chip stack is mounted in a wafer inspection apparatus while being bonded to the adhesive tape, and the test electrode group is searched using a plurality of probes of the wafer inspection apparatus to inspect the substrate-free chip stack. The fifth step;
The manufacturing method of the multichip laminated body characterized by the above-mentioned.   The method of manufacturing a multichip laminate according to claim 1, further comprising a step of detaching the tape carrier from the wafer test tray.   2. The method of manufacturing a multi-chip laminate according to claim 1, wherein the wafer test tray is larger than the tape carrier, and the wafer test tray and the tape carrier are different in shape.   The method for manufacturing a multichip laminate according to claim 1, wherein the wafer test tray includes a base made of copper, iron, or an alloy thereof.   5. The multi-chip laminate manufacturing method according to claim 4, wherein the wafer test tray has a plurality of fixing portions provided on the base, and the fixing portion group fixes the tape carrier at a predetermined position. Method.   6. The method of manufacturing a multichip laminate according to claim 5, wherein the fixing part group fixes a plurality of corners of the tape carrier.   The base of the wafer test tray has a fixed surface and an opening formed in the fixed surface, and the shape of the opening is the same shape as the periphery of the tape carrier. A manufacturing method of a multichip laminate.   2. The multichip laminate according to claim 1, wherein the third step includes an overflow resin removing step of removing a filling sealing body of a resin overflow portion where the resin overflows from the substrate-free chip laminate. Manufacturing method.   9. The method of manufacturing a multi-chip laminate according to claim 8, wherein after the overflow resin removing step, the filling sealing body covers a plurality of side surfaces of the chip group.   A plurality of silicon through holes are installed in the chip, and a plurality of interconnect electrodes are installed in the chip stack gap group of the substrate-free chip stack, and the interconnect electrode group is electrically connected to the silicon through hole group. The method for producing a multichip laminate according to claim 1, wherein the multichip laminate is electrically connected.

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