JP2013074038A - Method of manufacturing photoelectric conversion device and photoelectric conversion device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a photoelectric conversion device capable of improving power generation characteristics of a solar cell having a hetero junction cell composed of a p-type crystal Ge (substrate), an i-type amorphous silicon layer, and an n-type amorphous silicon layer.SOLUTION: A method of manufacturing a photoelectric conversion device includes a hetero junction cell 1 in which a p-type crystal Ge is used as a substrate 11 and an i-type amorphous silicon layer 12 and an n-type amorphous silicon layer 13 are laminated on the substrate 11 in this order. This method includes a PHexposure processing step in which the substrate 11 of the p-type crystal Ge having a Ge (111) face on the surface is used and after heating the substrate 11 from which an oxide film 5 formed on the surface is removed to a predetermined temperature, the substrate 11 is exposed to the PHgas by being disposed in a vacuum chamber.

Description

  The present invention relates to a method for manufacturing a photoelectric conversion device and a photoelectric conversion device, and particularly to a method for manufacturing a solar cell having a heterogeneous junction with a crystalline power generation layer and a solar cell.

  A solar cell is known as a photoelectric conversion device that converts sunlight energy into electrical energy. Patent Document 1 discloses a heterojunction photoelectric conversion device in which an amorphous silicon layer is stacked on a single crystal substrate. In Patent Document 1, in order to increase the short-circuit current due to the optical confinement effect, the crystal substrate sliced along the (100) plane is anisotropically etched and oriented to the (111) plane in order to provide pyramidal irregularities on the substrate surface. A substrate in which a V-shaped concave portion formed on the four walls is formed on the entire surface is used. The substrate is pretreated to remove impurities attached to the surface. Since an oxide film is formed on the substrate surface by the pretreatment, an amorphous silicon layer is laminated on the substrate after the oxide film is removed.

  In recent years, with the aim of improving the conversion efficiency of solar cells, research on solar cells with heterojunction structures using narrow gap materials such as germanium (Ge) or silicon (Si) -Ge-tin (Sn) alloys Development is underway. Ge has a band gap of 0.66 eV, which is smaller than the band gap (1.1 eV) of crystalline Si conventionally used in the photoelectric conversion layer. By using such a narrow gap material, it is possible to increase the absorption of light on the longer wavelength side, which could not be used until now, and to further improve the conversion efficiency of the solar cell.

  As one of solar cells having a heterojunction structure using a narrow gap material, a p-type crystal Ge is used as a substrate, and an i-type amorphous silicon layer and an n-type amorphous silicon layer are sequentially formed on the substrate. There is a solar battery using a stacked heterojunction cell as a photoelectric conversion layer.

Japanese Patent No. 3271990 (page 5, right column, line 37 to page 6, left column, line 14 and page 6, left column, line 45 to page 6, right column, line 30)

  When p-type crystal Ge is used as a substrate, the substrate is first cleaned with an organic solvent and a cleaning agent. Since an oxide film (GeOx) is formed on the cleaned substrate surface, the i-type amorphous silicon layer and the n-type amorphous silicon layer are sequentially formed after the substrate is heated to remove the oxide film. Laminate. However, a solar cell having a heterojunction cell manufactured in this manner has a problem that desired power generation characteristics cannot be obtained.

  Further, when a crystal substrate is used, the surface characteristics vary depending on the surface orientation of the substrate surface. Therefore, it is expected that there is an appropriate photoelectric conversion device structure and manufacturing method according to the plane orientation corresponding to the type of crystal, but the optimization method has not been clarified.

  The present invention has been made in view of such circumstances, and a solar battery having a heterojunction cell composed of p-type crystal Ge (substrate) / i-type amorphous silicon layer / n-type amorphous silicon layer It aims at providing the manufacturing method of the photoelectric conversion apparatus which can improve the electric power generation characteristic of this.

In order to solve the above problems, the present invention provides a heterojunction cell in which a p-type crystal Ge is used as a substrate and an i-type amorphous silicon layer and an n-type amorphous silicon layer are sequentially stacked on the substrate. A method of manufacturing a photoelectric conversion device provided with a substrate of p-type crystal Ge having a Ge (111) surface on the surface, after the substrate from which the oxide film formed on the surface has been removed is set to a predetermined temperature Provided is a method for manufacturing a photoelectric conversion device including a PH ₃ exposure treatment step that is arranged in a vacuum chamber and exposed to PH ₃ gas.

When the substrate of p-type crystal Ge is heated, oxygen (O) is sublimated and the oxide film on the substrate surface is removed. As a result of earnest research, the present inventors have obtained the following findings. That is, the substrate surface from which the oxide film has been removed is covered with dangling bonds (dangling bonds), and exhibits a strong p-type due to the presence of a stability order in the valence band. Even if an amorphous silicon layer is formed on a strong p-type substrate, power generation characteristics cannot be obtained.
According to the present invention, when the substrate from which the oxide film has been removed is subjected to PH ₃ exposure treatment, PH ₃ gas is adsorbed (or bonded) to the substrate surface, and the Fermi level on the substrate surface can be returned to the vicinity of the intrinsic. By laminating the i-type amorphous silicon layer and the n-type amorphous silicon layer on such a substrate, the power generation characteristics of the photoelectric conversion device can be significantly improved.

  Here, a p-type crystal Ge substrate having a Ge (111) plane is used. The density of dangling bonds existing on the substrate surface is lower in the Ge (111) plane than in the Ge (100) plane. As a result, the interface defect density between the substrate and the i-type amorphous silicon layer can be kept low, so that the recombination speed at the interface is reduced and the open circuit voltage can be improved. Therefore, when a Ge (111) substrate is used, a photoelectric conversion device with higher conversion efficiency than that when a Ge (100) substrate is used can be obtained.

In the PH ₃ exposure treatment step, it is preferable that the predetermined temperature of the substrate is a normal temperature. By setting the substrate temperature at the time of PH ₃ exposure to room temperature, the conversion efficiency when the photoelectric conversion device is obtained can be improved. The normal temperature includes a temperature range of several degrees Celsius to 50 degrees Celsius.

  In one embodiment of the present invention, a p-type crystal Ge substrate having the Ge (111) plane may be formed from a p-type crystal Ge (100) substrate by anisotropic etching.

The p-type crystal Ge (100) substrate is a p-type crystal substrate sliced along the Ge (100) plane, and is relatively easy to obtain in the market because of the use of the crystal Ge substrate. . Therefore, if the Ge (111) surface can be obtained from the Ge (100) substrate, the material cost can be reduced.
Further, when the Ge (100) substrate is processed by anisotropic etching, the Ge (111) surface is exposed as a surface inclined with respect to the horizontal plane, and the substrate surface is textured. Thereby, light reflection can be reduced and the optical path length can be increased, and an improvement in short-circuit current density can be expected.

  In one embodiment of the present invention, a p-type crystal Ge substrate having the Ge (111) surface may be manufactured so that the Ge (100) surface remains at a predetermined ratio.

By leaving the Ge (100) surface having a predetermined area, a photoelectric conversion device having both the characteristics of the Ge (100) surface and the characteristics of the Ge (111) surface can be obtained. That is, the short wavelength sensitivity can be compensated by leaving the Ge (100) plane, and the open voltage can be compensated by providing the Ge (111) plane. This is an important factor for improving the performance of solar cells.
In addition, when a photoelectric conversion device is formed by laminating an i-type amorphous silicon layer and an n-type amorphous silicon layer on a p-type crystal Ge substrate, a Ge (100) plane which is a horizontal plane is left. As a result, the i-type amorphous silicon layer is easily deposited thereon. Therefore, the i-type amorphous silicon layer can be deposited thickly on the Ge (100) surface with many unbonded hands without any special operation. It has been reported that an amorphous silicon film has a passivation effect, and the thicker the effect, the higher the effect (see NE Posthuma et al./Solar Energy Materials & Solar Cells 88 (2005) 37-45). ). On the other hand, since an amorphous silicon film can be selectively deposited on the inclined Ge (111) surface, the optical absorption including the short wavelength of the amorphous silicon film is suppressed to reduce the short wavelength. The effect of improving sensitivity can be expected.
In addition, by leaving the Ge (100) plane, the acute-angled portion of the textured uneven portion is eliminated, so that it is difficult to form a part of the amorphous silicon film in the deep portion of the concave portion, and the convex portion is amorphous. This is effective in eliminating a bonding defect such as a leak path to the transparent electrode layer side through the porous silicon film.
Further, by leaving a planar portion on the substrate surface, the contact area between the substrate and the i-type amorphous silicon layer increases. For this reason, when manufacturing a multi-junction cell with a mechanical stack structure in which the substrate side cell and the upper side cell are separately manufactured and then stacked, the adhesion strength between the substrate and the upper cell can be improved, and light scattering and light confinement capability Can also be secured. When bonding the substrate and the i-type amorphous silicon layer with a conductive adhesive, the reflection / scattering effect can be further adjusted by selecting the size of the flat surface remaining in the recess and the refractive index of the adhesive to be filled. Can be expected to be possible.

In one embodiment of the present invention, a Ge (111) surface and a Ge (100) surface exist on the surface of the substrate, and an area ratio of the Ge (111) surface to the Ge (100) surface is Ge (111). ) / Ge (100) ≧ 0.6, the predetermined temperature in the PH ₃ exposure treatment step is set to room temperature, and Ge (111) / Ge (100) <0.6 in the PH ₃ exposure treatment step. The predetermined temperature is preferably 150 ° C. or higher.
It has been found that the optimum PH ₃ exposure treatment temperature differs between the Ge (100) surface and the Ge (111) surface. Therefore, when the Ge (100) plane and the Ge (111) plane coexist, by setting the substrate temperature during PH ₃ exposure according to the area ratio of the Ge (100) plane and the Ge (111) plane, Conversion efficiency can be further improved.

According to the present invention, in exposing the p-type crystal Ge from which the oxide film has been removed to PH ₃ , a Ge (111) surface is provided, and the substrate temperature at the time of PH ₃ exposure is set to room temperature (several to 50 ° C.). By setting it to include, the Fermi level of the surface of the p-type crystal Ge can be returned to the vicinity of the intrinsic.
Further, there is a Ge (111) plane on the inclined surface on the substrate and a Ge (100) plane on the horizontal surface, and depending on the area ratio between the Ge (111) plane and the Ge (100) plane, when PH _{3 is} exposed. By setting the substrate temperature, the short wavelength sensitivity and the open circuit voltage can be improved.
The power generation characteristics of the photoelectric conversion device can be improved by stacking an i-type amorphous silicon layer and an n-type amorphous silicon layer on such a p-type crystal Ge.

It is the schematic which shows an example of a structure of the photoelectric conversion apparatus which concerns on 1st Embodiment. It is a flowchart explaining the procedure of the washing | cleaning process of a board | substrate. It is a figure explaining the manufacturing method of the solar cell after board | substrate washing | cleaning. It is a graph which compares the IV characteristic by the surface orientation of a board | substrate. It is a figure explaining the unbonded number of hands in the outermost surface of a Ge (111) surface and a Ge (100) surface. It is a graph which compares the external quantum efficiency by the surface orientation of a board | substrate. It is a schematic diagram of a semiconductor band diagram composed of an n-type amorphous silicon layer / i-type amorphous silicon layer / p-type single crystal Ge layer. It is a figure which shows the electric power generation characteristic of a solar cell. PH ₃ is a graph showing the relationship between the characteristic improvement degree of exposure processing time of the substrate heater temperature and the band compensation. PH ₃ is a graph showing the relationship between the recombination promotion by performance degradation due to exposure process when the substrate heater temperature and PH _3. PH ₃ is a graph showing the relationship between the exposure process when the substrate heater temperature and the conversion efficiency. It is a figure explaining the etching rate in anisotropic etching. It is a top view which shows an example of a photomask. It is a fragmentary sectional view of the board | substrate which carried out anisotropic etching. It is a fragmentary sectional view of the board | substrate which carried out anisotropic etching. It is a fragmentary sectional view of the board | substrate which carried out anisotropic etching. It is a fragmentary sectional view of the board | substrate which carried out anisotropic etching. (Mechanical stack structure) It is a partial top view of the board | substrate which carried out anisotropic etching. It is a graph which shows the relationship between the length of the side of a plane part, and a plane rate. It is a partial top view of the board | substrate which carried out anisotropic etching. It is a graph which shows the relationship between the length of the side of a plane part, and a plane rate. It is a graph which shows the area ratio and conversion efficiency of Ge (111) surface in the Ge substrate surface. It is a figure explaining the etching rate selection ratio of the Ge board | substrate which the etching process on the etching conditions 1 was complete | finished.

Hereinafter, an embodiment of a method for producing a photoelectric conversion device according to the present invention will be described with reference to the drawings.
<First Embodiment>
FIG. 1 is a schematic diagram illustrating an example of a configuration of a photoelectric conversion apparatus according to the present embodiment. The photoelectric conversion device 100 is a solar cell having a heterojunction structure, and includes a heterojunction cell 1, a transparent electrode layer 2, a grid electrode 3, and a back electrode layer 4.

The heterojunction cell 1 includes a p-type single crystal Ge (substrate 11), an i-type amorphous silicon layer 12, and an n-type amorphous silicon layer 13.
The substrate 11 is made of Ga-doped p-type single crystal Ge (100) (c-Ge) grown by the Czochralski (CZ) method. c-Ge is a crystal substrate having a (111) plane on the surface. In this embodiment, c-Ge is a Ge (111) substrate whose upper surface is all along the Ge (111) plane. The thickness of c-Ge is 1.5 μm or more and 500 μm or less, preferably 50 μm or more and 200 μm or less. The i-type amorphous silicon layer 12 is mainly made of amorphous silicon and has a thickness of 5 nm to 80 nm. The n-type amorphous silicon layer 13 is mainly P-doped silicon containing a phosphorus component: P in amorphous silicon, and has a thickness of 4 nm to 10 nm.
The substrate 11 is not limited to p-type single crystal Ge, and polycrystalline Ge can be used in the same manner by optimizing the surface treatment.

The transparent electrode layer 2 is a film composed mainly of a metal oxide such as indium tin oxide (ITO), tin oxide (SnO ₂ ), or zinc oxide (ZnO). The thickness of the transparent electrode layer 2 is set to 50 nm or more and 150 nm or less from the current collecting resistance and the light reflection characteristics.
Although the grid electrode 3 is a film mainly made of Ag, a highly conductive material such as Al can be used by optimizing the film forming method. It is preferable to install so that the grid area is narrowed and the occupied area of the substrate surface is reduced so as not to prevent light incidence while suppressing the current collecting resistance.
The back electrode layer 4 is a film made of Al and has a thickness of 50 nm to 500 nm. A film made of Ag can be used for improving the reflectance, and a film made of Cu can be used for reducing the cost.
Since Ag and Cu easily react with atmospheric components (oxygen, water vapor, sulfur, etc.), the surface of Ag or Cu may be further coated with Ti or Ni, and a method for sealing the entire photoelectric conversion device is devised. You may do it.

  A method for manufacturing the photoelectric conversion device according to this embodiment will be described. The solar cell manufacturing method according to the present embodiment includes a substrate cleaning step, an oxide film removing step, a heterojunction cell manufacturing step, an electrode forming step, and an annealing treatment step. FIG. 2 is a flowchart for explaining the procedure of the substrate cleaning process. FIG. 3 is a diagram illustrating a method for manufacturing a solar cell after substrate cleaning.

(1) Substrate cleaning process: FIG.
First, the substrate 11 is sequentially cleaned with an organic solvent such as acetone and a cleaning agent such as semi-clean. Next, after removing the oxide film formed on the surface of the substrate 11 using hydrogen fluoride (HF), the substrate 11 is rinsed with pure water. Next, after forming the oxide film 5 on the surface of the substrate 11 using hydrogen peroxide (H ₂ O ₂ ), the substrate 11 is rinsed with pure water.

(2) Oxide film removal step: FIGS. 3 (a) and 3 (b)
After carrying the substrate 11 into the vacuum chamber, the oxide film 5 formed on the surface of the substrate 11 is removed. Conditions for removing the oxide film are appropriately set according to the type of heat source to be used, the size of the substrate 11, and the like. For example, the inside of the vacuum chamber is evacuated to about 10 ⁻⁷ Torr (13.3 μPa) or less, and the substrate 11 is heated for about 20 minutes using a heat source such as an infrared heater. The heat source temperature should be raised to about 450 ° C. As a result, the oxide film (GeOx) formed on the surface of the substrate 11 can be sublimated to provide a clean surface on the substrate 11.
As a result of raising the temperature using an infrared heater and measuring the actual substrate temperature with a radiation thermometer, the actual substrate temperature was about 600 ° C.

(3) Heterojunction cell fabrication process: FIG. 3 (c)
The heterojunction cell manufacturing process includes a PH ₃ exposure treatment process, an i-layer film forming process, and an n-layer film forming process.
(PH ₃ exposure treatment process)
The substrate 11 from which the oxide film has been removed is set to a predetermined temperature. The predetermined temperature in this embodiment is normal temperature. The normal temperature includes several to 50 ° C.
Next, the substrate 11 is placed in another vacuum chamber, preferably in an n-type amorphous silicon layer deposition chamber (n-layer deposition chamber) of a plasma CVD apparatus. A PH ₃ gas diluted with H ₂ gas is introduced into the vacuum chamber.

The conditions for PH ₃ exposure (PH ₃ introduction amount, substrate temperature, exposure time, pressure, etc.) are appropriately set. For example, 0.6 volume% PH ₃ gas diluted with H ₂ gas is introduced at 0.3 sccm / cm ² and 0.1 Torr (13.3 Pa). At this time, the substrate 11 is preferably not heated. Non-heating means that the substrate is not actively heated using a heat source. For example, in the case of using a type of substrate heater that is heated in contact with the substrate, the heater is not heated by separating the heater from the substrate. At this time, the substrate heater temperature is preferably a temperature in the vicinity of a predetermined temperature of the substrate, but the substrate heater separated from the substrate may not be in a state of not releasing heat.
An extremely small amount of PH ₃ gas may be introduced.

(I-layer deposition process and n-layer deposition process)
An i-type amorphous silicon layer 12 and an n-type amorphous silicon layer 13 are sequentially formed on the substrate 11 using a plasma CVD apparatus. The i-type amorphous silicon layer 12 is formed in an i-type amorphous silicon layer deposition chamber (i-layer deposition chamber). Source gas: SiH ₄ gas and H ₂ gas, reduced pressure atmosphere: 1 Pa to 1000 Pa, Substrate temperature: Film is formed at about 150 ° C.
The n-type amorphous silicon layer 13 is formed in an n-type amorphous silicon layer deposition chamber (n-layer deposition chamber). Source gas: SiH ₄ gas, H ₂ gas and PH ₃ gas, reduced pressure atmosphere: 1 Pa The film is formed at 1000 Pa or less and the substrate temperature: about 150 ° C.

(4) Electrode forming step: FIG. 3 (d) to FIG. 3 (g)
The transparent electrode layer 2 is formed on the n-type amorphous silicon layer 13 by high frequency (RF) sputtering. The sputtering conditions, target: ITO sintered body, the atmosphere gas: Ar, ultimate ^pressure: 10 -4 ^{Pa to 10} -5 Pa, RF ^power: are ^{2W / cm 2 ~3W / cm 2} .
Next, element isolation is performed by reactive ion etching (RIE). Target transparent electrode layer 2 SnO ₂ and doped with F, ZnO doped with Ga or _Al, more atmospheric _gas: Ar + O 2: it may be 0.5 to 10 vol%.

A pattern mask plate is installed on the transparent electrode layer 2, and the grid electrode 3 is formed by a direct current (DC) sputtering method. The sputtering conditions, targets: Ag, Atmosphere gas: Ar, ultimate ^pressure: 10 -4 ^{Pa to 10} -5 Pa, RF ^power: are ^{2W / cm 2 ~3W / cm 2} .

  The back electrode layer 4 is formed on the back surface of the substrate 11 (the surface opposite to the side on which the amorphous silicon layer is formed) by resistance heating vapor deposition. Al is heated and evaporated by passing a current of 30 A through the tungsten filament.

(5) Annealing process: FIG. 3 (g)
The solar cell manufactured in the above process is heated in a vacuum and annealed. The annealing treatment is preferably performed at a substrate temperature of about 150 ° C. for 8 hours so as not to adversely affect the hydrogen terminating the Si in the amorphous silicon layer.

(Examination of substrate surface orientation)
Using the substrates having different plane orientations (p-type single crystal Ge), solar cells having the following configurations were produced according to the first embodiment.
Grid electrode: Ag film, average film thickness 200 nm
Transparent electrode layer: ITO film, average film thickness 70 nm
n-type amorphous silicon layer: average film thickness 8 nm
i-type amorphous silicon layer: average film thickness 40 nm
Back electrode layer: Al film, average film thickness 200 nm

＊ＥＰＤ：エッチピット密度（Ｅｔｃｈ Ｐｉｔ Ｄｅｎｓｉｔｙ） Table 1 shows the characteristics of the substrate used.

* EPD: Etch Pit Density

In this test, the resistivities of the substrates used were made approximately equal. PH ₃ exposure treatment conditions were: PH ₃ flow rate (H ₂ 0.6% dilution): 40 sccm, pressure: 0.1 Torr (13.3 Pa), time: 5 minutes, substrate temperature 150 ° C. (heater temperature: 200 ° C.) did.

About the solar cell produced above, the short circuit current and the open circuit voltage were measured. The results are shown in FIG. In the figure, the horizontal axis is the open circuit voltage, and the vertical axis is the short circuit current. According to FIG. 4, Ge (1
11) The substrate (substrate No. 1) had higher open-circuit voltage and better characteristics than the Ge (100) substrate (substrates No. 2 and No. 3).

  An electronic state different from that of the bulk is formed on the outermost surface of the semiconductor, and atoms in the first layer on the surface have dangling bonds (dangling bonds). This presence greatly characterizes the physical properties of the outermost surface. FIG. 5 shows the number of dangling bonds on the outermost surfaces of the Ge (111) plane and the Ge (100) plane. When comparing the density of dangling bonds existing on the outermost surface of the substrate, the Ge (111) plane has a lower density than the Ge (100) plane. If the number of dangling bonds present on the outermost surface is low, the interface defect density can be kept low. Therefore, in the Ge (111) substrate, it is presumed that the recombination speed at the interface is lowered and the open circuit voltage is improved.

  About the solar cell produced above, the external quantum efficiency was measured according to JIS C 8915. The results are shown in FIG. In the figure, the horizontal axis represents wavelength, and the vertical axis represents external quantum efficiency (EQE). According to FIG. 6, the Ge (111) substrate has a characteristic that the short wavelength sensitivity of about 300 nm to about 500 nm is lower than the Ge (100) substrate, but the long wavelength sensitivity of about 600 nm to 1200 nm is high. found.

FIG. 7 shows a band diagram of a semiconductor composed of an n-type amorphous silicon layer / i-type amorphous silicon layer / p-type single crystal Ge layer. FIG. 7A shows a case where the p-type single crystal Ge layer is a G (100) substrate, and FIG. 7B shows a case where the p-type single crystal Ge layer is a Ge (111) substrate.
When a Ge (100) substrate is used, p-type conversion becomes remarkable because the number of dangling bonds on the surface of the Ge (100) substrate is large. As shown in FIG. 7A, when p-type conversion is significant, the electric field strength (tilt) in the i-type amorphous silicon layer (a-Si (i)) changes abruptly. The greater the slope, the higher the ability to separate excited electron-hole pairs. Here, since the light on the short wavelength side is mainly absorbed by the amorphous silicon layer, the external quantum efficiency on the short wavelength side is increased when the Ge (100) substrate is used in the result of FIG. Presumed to be.
When a Ge (111) substrate is used, since the number of dangling bonds on the surface of the Ge (111) substrate is small, p-type conversion is relaxed, and the electric field strength applied to a-Si (i) is reduced. This increases the loss of light guided to the p-type single crystal Ge layer by optical absorption in the a-Si (i) forming the heterojunction, which is shorter than that using the Ge (100) substrate. It is presumed that the external quantum efficiency of was low.

  On the other hand, since light on the long wavelength side is hardly absorbed by a-Si, it is mainly absorbed by the p-type single crystal Ge layer. At that time, it is necessary to transport electrons from the p-type single crystal Ge layer to the a-Si (n) side. In the Ge (111) substrate, electrons are accelerated by the depletion layer, so that the amount of current that can be extracted increases. Thereby, in the result of FIG. 6, it is presumed that the external quantum efficiency on the long wavelength side was increased although the Ge (111) substrate was used.

＊非加熱とは、ヒータを基板から離し、積極的に加熱していない状態を指す。上記試験におけるヒータ温度は２００℃のままであるが、基板温度は５０℃程度になっており常温範囲であった。常温とは、数℃〜５０℃の温度範囲を含むものである。 (Substrate temperature dependence during PH ₃ exposure)
Using substrates with different plane orientations (Ge (100) substrate and Ge (111) substrate), the optimum substrate temperature during PH ₃ exposure was investigated. Table 2 shows the conditions at the time of PH ₃ exposure. For comparison, a sample not subjected to PH ₃ exposure treatment was also prepared.

* Non-heating refers to the state where the heater is not actively heated while being separated from the substrate. The heater temperature in the above test remained at 200 ° C., but the substrate temperature was about 50 ° C. and was in the normal temperature range. The normal temperature includes a temperature range of several to 50 ° C.

Except for the above conditions, a solar cell having the following configuration was fabricated according to the first embodiment.
Grid electrode: Ag film, average film thickness 200 nm
Transparent electrode layer: ITO film, average film thickness 70 nm
n-type amorphous silicon layer: average film thickness 8 nm
i-type amorphous silicon layer: average film thickness 40 nm
Back electrode layer: Al film, average film thickness 200 nm

Table 3 shows the characteristics of the substrate used.

About the solar cell produced above, an open circuit voltage (Voc), a short circuit current (Jsc), a form factor (FF), and a conversion efficiency (Eff.) Were measured. The measurement results are shown in (a) to (d) of FIG.
According to FIG 8, compared to that of untreated did not exposed to PH _3, PH ₃ which exposed the process, the open-circuit voltage, fill factor, and conversion efficiency was improved.

When a Ge (100) substrate was used, the substrate temperature when exposed to PH ₃ was better, and the conversion efficiency of the solar cell heated at a substrate heater temperature of 300 ° C. (substrate temperature of 220 ° C.) was the highest. . According to the above results, when a Ge (100) substrate is used, PH ₃ exposure treatment at a high temperature is suitable, and when the substrate temperature is about 150 ° C., the temperature under the film forming conditions of the n-layer film forming chamber remains as it is. Can be used. Therefore, when a Ge (100) substrate is used, the predetermined temperature in the PH ₃ exposure treatment step is preferably 150 ° C. or higher.

When the Ge (111) substrate was used, the conversion efficiency of the solar cell exposed to PH ₃ with the substrate not heated (the substrate temperature was about 50 ° C. in the normal temperature range) was the highest. The conversion efficiency of the solar cell in which the substrate was heated to 150 ° C. at a substrate heater temperature of 200 ° C. showed a tendency to be lower than the conversion efficiency of the non-heated solar cell.

Here, it will be considered that the conversion efficiency of a solar cell in which a Ge (111) substrate is used and the substrate is heated at 150 ° C. (substrate heater temperature 200 ° C.) and subjected to PH ₃ exposure treatment tends to decrease. The PH ₃ exposure treatment (1) supplies electrons as an n-type dopant and corrects the p-type conversion due to dangling bonds on the surface of the Ge substrate (band correction), and (2) a Ge substrate and an amorphous material as impurities. It is considered that there is a function of promoting recombination at the interface with the porous silicon layer.

FIG. 9 shows the relationship between the substrate heater temperature during the PH ₃ exposure treatment and the degree of improvement in characteristics by band correction. FIG. 10 shows the relationship between the substrate heater temperature during PH ₃ exposure treatment and the performance degradation due to recombination promotion by PH ₃ . FIG. 11 shows the relationship between the substrate heater temperature and the conversion efficiency during the PH ₃ exposure treatment.
When the substrate temperature at the time of the PH ₃ exposure treatment is increased, the reactivity between the PH ₃ and the Ge substrate increases, the correction of p-type in (1) is promoted, and the recombination in (2) is also promoted. The If it is considered that the performance improvement is realized by this balance, at the substrate 150 ° C. (substrate heater temperature 200 ° C.), the effect of the performance deterioration due to the recombination promotion of the above (2) is more effective than the p-type correction effect of the above (1). It is considered that the characteristics are degraded due to the large value.

However, according to FIG. 8, even if the characteristics are deteriorated under some conditions as described above, the solar cells using the Ge (111) substrate are both Ge substrates when the substrate heater temperature at the time of PH ₃ exposure is the same. The open circuit voltage, form factor, and conversion efficiency were higher than those of the solar cell using the (100) substrate. Specifically, when the substrate is heated at 220 ° C. (substrate heater temperature 300 ° C.), the conversion efficiency of the solar cell using the Ge (111) substrate is 1 of the conversion efficiency of the solar cell using the Ge (100) substrate. .28 times. In addition, the highest conversion efficiency of the solar cell using the Ge (111) substrate was 1.43 times the highest conversion efficiency of the solar cell using the Ge (100) substrate.

From the above, when producing a solar cell with a heterojunction structure, it is preferable that the surface orientation of the substrate surface is a Ge (111) plane rather than a Ge (100) plane. Further, when a Ge (111) substrate is used, it is preferable to perform the PH ₃ exposure treatment without actively heating the substrate (without heating).

As shown in FIG. 5, considering that the density of dangling bonds existing on the surface of the Ge (111) surface is lower than that of the Ge (100) surface, it is necessary to correct the Fermi level with a dopant in the Ge (111) substrate. Less is. Therefore, it is considered that the efficiency is maximized by the PH ₃ exposure treatment with non-heating (room temperature including a temperature range of several to 50 ° C.) with low reactivity. Therefore, when a Ge (100) substrate with many unbonded hands is used, it is preferable to perform the PH ₃ exposure treatment at a high temperature. However, when a Ge (111) substrate with few unbonded hands is used, the PH ₃ exposure treatment is performed at a low temperature. Good to do.

Moreover, since PH ₃ is originally an impurity for the Ge substrate and the amorphous silicon layer, when it is exposed to PH ₃ at a high temperature, it tends to increase interface defects. On the other hand, in the Ge (111) substrate, it is considered that the effect of impurities is suppressed and the interface defects are reduced by performing the PH ₃ exposure treatment without heating (at room temperature) compared to the case of treatment at a high temperature.

  When a Ge (111) substrate is used, the interface Fermi level treatment can be performed without heating, so that a temperature raising facility is unnecessary and a performance management item of temperature management for substrate heating is not required. Therefore, it can be set as the solar cell of the heterojunction structure excellent in productivity and stability.

Second Embodiment
In this embodiment, a Ge substrate having a Ge (111) surface is produced from a p-type single crystal Ge (100) substrate (hereinafter referred to as a Ge (100) substrate) by anisotropic etching. Specifically, the surface of the Ge (100) substrate is covered with a mask having a predetermined opening, and is patterned by etching with an etchant. The surface of the Ge (100) substrate is etched by the etchant in the depth direction and the plane direction of the Ge (100) substrate. FIG. 12 is a diagram for explaining the etching rate. The etching rate differs depending on the crystal plane orientation of the Ge substrate, and the Ge (111) plane (arrow E direction) is slower than the Ge (100) plane (arrow D direction). When the surface of the Ge (100) substrate is processed by anisotropic etching, the Ge (111) surface is exposed as a surface inclined by 54.7 ° C. with respect to the substrate surface (Ge (100) surface) of the Ge (100) substrate. To do. Thereby, the surface of the Ge substrate having the Ge (111) surface has a texture shape. In anisotropic etching, it is possible to form a desired texture shape by adjusting the type of mask 14 and etchant used, and the etching time. As anisotropic etching, G.I. Chianetta et al. J Low Temp Phys 151 (2008) 387, S.J. Kagawa et al. When anisotropic etching described in JJAP 21 (1982) 1616-1618 is used, a Ge (111) surface can be exposed from a Ge (100) substrate to form a textured shape. By making the substrate surface a textured shape, an increase in optical scattering can be obtained, so that the power generation characteristics of the solar cell can be improved.

  In the present embodiment, the mask 14 is patterned using photolithography using UV. The patterning method is not particularly limited as long as it has a function as a mask such as electron beam exposure, imprint, and fine particle coating, and can obtain a fine pattern.

The etchant is appropriately selected according to a desired texture shape to be formed, accuracy, and etching rate.
The etchant is prepared, for example, by mixing at a ratio of phosphoric acid: hydrogen peroxide: ethanol = 1: 1: 1. Since the etchant mixed at the above ratio has a low etching rate selection ratio, it is easy to manage the remaining time of the plane. When the above etchant is used, a mask other than a resist is used. As a result, etching defects caused by ethanol eroding the resist are hardly caused, and etching reproducibility can be improved.
The etchant is prepared, for example, by mixing at a ratio of phosphoric acid: hydrogen peroxide water: ion exchange water = 4: 1: 5. Since the etchant mixed in the above ratio does not use an organic solvent, there is no fear of damaging the resist even if a photoresist is used as a mask. Although the etching rate is faster than that using ethanol, the Ge (100) surface can be left by strictly controlling the etching time.

  FIG. 13 shows an example of a photomask. The photomask 14 includes a plurality of openings 15 that are periodically arranged at intervals. The area, shape, accuracy, and etching rate of the opening are appropriately set according to the desired texture shape to be formed and the type of etchant to be used. The area of the opening is appropriately set according to the etching rate selection ratio. When an etchant of phosphoric acid: hydrogen peroxide water: ion exchange water = 4: 1: 5 is used, the length of one side of the opening is preferably about 1/10 or less of the period (P) of the opening. Thereby, the area of the plane remaining on the substrate can be reduced. Here, the plane is a substrate surface before processing or a surface substantially parallel to the substrate surface, that is, a Ge (100) surface.

  The period (P) of the opening is set to a distance within about 0.71 times the thickness of the substrate, assuming that etching can be allowed to a depth of ½ of the thickness of the substrate as will be described later. The period (P) of the opening is desirably 1 μm to 5 μm. When the period (P) of the opening is 5 μm or more, the effect of scattering incident light in the solar cell is reduced. However, even if the period (P) of the opening is further increased from 5 μm, the ratio at which the light reflected by the surface re-enters the solar cell does not change as long as the uneven shape is similar. Therefore, even if the period (P) of the opening is further increased from 5 μm, the reflectance of the solar cell surface seen from the incident side is hardly changed.

  When the period of the opening is increased, the accuracy required for photolithography is reduced, and the manufacturing can be simplified. However, if the period is increased too much, the etching depth in the thickness direction of the Ge (100) substrate increases. This causes problems such as a thin portion in the Ge (100) substrate and penetration of the Ge (100) substrate.

  In order to reduce the light absorption loss due to the reduction in the plate thickness, etching to a depth of about ½ of the plate thickness of the substrate can be allowed. FIG. 14 shows a cross-sectional view of the substrate 11 when etching is performed to a depth of ½ of the plate thickness. In the figure, it is assumed that the area of the plane portion becomes zero as much as possible by etching, and that the inclination angle of the Ge (111) plane with respect to the Ge (100) plane of the substrate 11 can be etched at a theoretical value of 54.7 °. It is a model. According to FIG. 14, the opening period can be increased to about 0.71 times the plate thickness, and this can be set as the upper limit of the opening period (P).

For example, when a general Ge (100) substrate having a plate thickness of 100 μm is used, the period of the opening can be increased to 71 μm. By using the mask having the above-described period, it becomes possible to simplify the manufacturing.
For example, when a thin Ge (100) substrate having a plate thickness of 10 μm is used, the period of the opening can be increased to 7 μm. In that case, since the upper limit value of the period becomes small, it is possible to obtain an effect of scattering incident light in the solar cell.

The surface of the Ge substrate provided with the Ge (111) plane is preferably processed into a shape in which a plane remains as little as possible. By reducing the number of planes, the reflectance is reduced.
On the other hand, when etching is performed so that the flat surface does not remain as much as possible, the convex portion 16 or the concave portion 17 has an acute angle as shown in FIG. When the amorphous silicon i layer 12 is formed on the acute angle part, it becomes difficult to form a part of the amorphous silicon film in the deep part of the concave part, and the transparent part passes through the amorphous silicon film in the convex part. Bonding defects such as a leak path with the layer side occur. Therefore, at the time of etching, as shown in FIG. 16, it is preferable to leave the planes in the convex portions 18 and the concave portions 19 to such an extent that no poor bonding occurs. In order to eliminate the bonding failure, it is preferable that the length of one side of each plane of the convex portion 18 and the concave portion 19 is about the thickness of the amorphous silicon layer, that is, 10 nm or more. The length of one side of the concave plane may be different from the length of the short side of the convex plane.

As a solar cell according to another manufacturing method of the present embodiment, a multi-junction cell may be manufactured as a mechanical stack structure in which the substrate 11 and the upper cell 20 are separately manufactured and then overlapped via the conductive adhesive 6. . At this time, if the length of the short side of the projection plane is increased so that the area of the plane of the projection 18 (Ge (100) plane) is increased, the contact between the substrate 11 and the upper cell 20 as shown in FIG. Since the area increases, the adhesive strength with the upper cell 20 can be improved. With this structure, the adhesion strength between the substrate 11 and the upper cell 20 can be improved, and light scattering / light confinement capability can be secured.
Further, when the substrate 11 and the amorphous silicon i layer are bonded with the conductive adhesive 6, the size of the plane left in the concave portion of the substrate 11 and the refractive index of the conductive adhesive 6 to be filled are selected. Thus, the reflection / scattering effect can be further adjusted, and the performance of the solar cell can be improved.

FIG. 18 shows a top view of a Ge substrate etched so that one side (l) of the plane of the recess 19 is the same as the short side (s) of the plane of the projection. FIG. 19 shows the relationship between the plane length and the side length (one side (1) of the concave plane + the short side (s) of the convex plane) when etching is performed under the conditions shown in FIG. In the figure, the horizontal axis represents the length of the side of the plane portion (% relative to the period of the opening), and the vertical axis represents the ratio of the plane when viewed from directly above.
In FIG. 20, the short side (s) of the plane on the convex portion is etched so as to be fixed to 1% of the period of the opening (for example, if the period of the opening is 1 μm, the short side (s) is 10 nm). A top view of a Ge substrate is shown. FIG. 21 shows the relationship between the plane length and the side length (one side (1) of the concave plane + the short side (s) of the convex plane) when etching is performed under the conditions shown in FIG. In the figure, the horizontal axis represents the length of the side of the plane portion (% relative to the period of the opening), and the vertical axis represents the ratio of the plane when viewed from directly above.
According to FIG. 19 and FIG. 21, when the flatness of 10% or less is realized, the length of the side of the plane needs to be 5% or less and 28% or less, respectively. In this way, the flatness can be controlled by adjusting the planar sizes of the concave and convex portions, and the uneven shape of the substrate 11 can be easily designed and manufactured. When the side lengths of the plane are 5% and 28%, Ge (111) / Ge (100) is 0.94 and 0.96, respectively.

  Further, it is possible to adjust the planar size of the convex portion by adjusting the interval (period) of the openings and the etching time.

Using the Ge substrate having the Ge (111) surface produced above, a solar cell is produced in the same manner as in the first embodiment. However, the substrate temperature (substrate heater temperature) during the PH ₃ exposure process in the heterojunction cell manufacturing process is the area ratio of Ge (111) to Ge (100), that is, Ge (111) / Ge (100) (etching). The rate selection ratio is set as appropriate.
FIG. 22 shows the relationship between the area ratio of the Ge (111) plane on the surface of the Ge substrate and the conversion efficiency. In the figure, the horizontal axis represents the ratio of the Ge (111) plane, and the vertical axis represents the conversion efficiency. According to the figure, assuming that the area ratio of Ge (111) / Ge (100) corresponds to the conversion efficiency, the substrate temperature is 220 ° C. (heater temperature: 300 when G (111) / Ge (100) <0.6. (° C.) and PH ₃ exposure treatment may be performed. That is, it is preferable to match the conditions suitable for exposing the Ge (100) surface to PH ₃ . When G (111) / Ge (100) ≧ 0.6, the predetermined temperature is normal temperature (including a temperature range of several degrees C. to 50 ° C.), and the PH ₃ exposure treatment may be performed without heating the substrate. By doing so, the conversion efficiency of a solar cell can be improved more.

According to the second embodiment, a Ge substrate having a Ge (111) surface was produced from a Ge (100) substrate having a thickness of 175 μm. The etching conditions for this test are shown below.
(Etching condition 1)
Etchant; phosphoric acid: hydrogen peroxide water: ion-exchanged water = 4: 1: 5
(Reagent concentration: phosphoric acid 98%, hydrogen peroxide solution 30%)
Etchant temperature: 25 ° C (room temperature)
Patterning technique: photolithography (light source uses UV from mercury lamp. Mask and sample are in close contact for exposure)
Mask used: Photomask with an opening of 2 μm □ and an opening cycle of 20 μm Etching time: 15 min
Depth direction etching rate: about 0.44 μm / min (direction of arrow D in FIG. 12)
Lateral etching rate: about 0.56 μm / min (direction of arrow F in FIG. 12, different from Ge (111) etching rate)

(Etching condition 2)
Etchant; phosphoric acid: hydrogen peroxide solution: ethanol = 1: 1: 1
(Reagent concentration: phosphoric acid 98%, hydrogen peroxide 30%, ethanol 99.5%)
Etchant temperature: 25 ° C (room temperature)
Patterning method: photolithography (light source uses UV of mercury lamp. Mask and sample are in close contact with each other for exposure)
Mask used: Photomask with 2 μm square opening and 20 μm opening period Etching time: 20 min
Depth direction etching rate: about 0.21 μm / min
Lateral etching rate: about 0.275 μm / min

  Under the etching conditions in the above test, the opening of the mask was 2 μm □. In order to reduce the reflectance of the incident light on the surface of the solar cell, it is better to have a shape with as few planes (horizontal planes) as possible and a large number of slope portions. However, since the etch rate selection ratio (Ge (100) / Ge (111)) is low in the etchant used in the etching conditions of the above test, a plane remains in the recess corresponding to the opening regardless of the etching time. Further, even if the etching time is increased, the area is almost the same or slightly widened. Therefore, under the etching conditions of the above test, an opening as small as possible was selected within a range that can be realized by photolithography of UV exposure and contact exposure.

  In order to increase light absorption, not only the light reflected from the surface is re-entered into the solar cell, but also has the function of providing irregularities of the same order as the wavelength of the light to be absorbed and scattering the incident light within the solar cell. It is also important that Therefore, the period of the opening is considered to be too large at 20 μm. However, under the etching conditions in the above test, the etching rate selectivity of the etchant used is low, and the opening of the photomask is as wide as 2 μm □. For this reason, if the openings are arranged with a very small period, the proportion of the remaining concave portions corresponding to the openings becomes high. Therefore, openings were arranged with a relatively large period of 20 μm to reduce the ratio of the plane (horizontal plane).

  Depending on the etching time, the residual amount of the Ge (100) plane can be adjusted.

By etching under the etching condition 1, a Ge substrate having a Ge (111) surface with few planes can be manufactured.

By etching under the etching condition 2, a plane (Ge (100) plane) can be left.
FIG. 23 shows the shape when the area ratio of Ge (111) / Ge (100), which is the boundary of the optimum conditions for the PH ₃ exposure treatment, is 0.6 when etching is performed using the etchant under the etching condition 1. FIG.

DESCRIPTION OF SYMBOLS 1 Heterojunction cell 2 Transparent electrode layer 3 Grid electrode 4 Back surface electrode layer 5 Oxide film 6 Conductive adhesive agent 11 Substrate (p-type single crystal Ge)
12 i-type amorphous silicon layer 13 n-type amorphous silicon layer 14 mask (photomask)
15 Opening 16 Convex part 17 Concave part 18 Convex part (plane)
19 Recess (plane)
20 Upper cell 100 Photoelectric conversion device

Claims (6)

A method of manufacturing a photoelectric conversion device including a heterojunction cell in which a p-type crystal Ge is used as a substrate and an i-type amorphous silicon layer and an n-type amorphous silicon layer are sequentially stacked on the substrate,
Using a substrate of p-type crystal Ge having a Ge (111) surface on its surface,
A method for manufacturing a photoelectric conversion device, comprising: a PH ₃ exposure treatment step in which the substrate from which the oxide film formed on the surface is removed is brought to a predetermined temperature and then placed in a vacuum chamber and exposed to PH ₃ gas. The method for manufacturing a photoelectric conversion device according to claim 1, wherein in the PH ₃ exposure treatment step, the predetermined temperature of the substrate is set to room temperature.   The manufacturing method of the photoelectric conversion apparatus of Claim 1 or Claim 2 which produces the board | substrate of the p-type crystal | crystallization Ge provided with the said Ge (111) surface from the p-type crystal | crystallization Ge (100) board | substrate by anisotropic etching.   4. The method of manufacturing a photoelectric conversion device according to claim 3, wherein a substrate of p-type crystal Ge provided with the Ge (111) surface so that the Ge (100) surface remains at a predetermined ratio. Ge (111) plane and Ge (100) plane exist on the surface on the substrate,
The area ratio between the Ge (111) plane and the Ge (100) plane is:
When Ge (111) / Ge (100) ≧ 0.6, the predetermined temperature in the PH ₃ exposure treatment step is set to room temperature,
5. The method of manufacturing a photoelectric conversion device according to claim 1, wherein, when Ge (111) / Ge (100) <0.6, the predetermined temperature in the PH ₃ exposure treatment step is set to 150 ° C. or higher. A photoelectric conversion device manufactured by the method according to claim 1.

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