JP2013065849A - Semiconductor element, wafer, method of manufacturing semiconductor element, and method of manufacturing wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor element having high efficiency, a wafer, a method of manufacturing the semiconductor element, and a method of manufacturing the wafer.SOLUTION: The semiconductor element includes an n-type first layer, a p-type second layer, a light-emitting part, a first stack, and a second stack. The light-emitting part is provided between the first layer and the second layer. The first stack is provided between the first layer and the light-emitting part, and includes third layers of AlGaInN and fourth layers of GaInN that are alternately stacked. The second stack is provided between the first layer and the first stack, and includes a plurality of fifth layers and sixth layers of GaInN that are alternately stacked. The first stack has recesses provided on a surface of the first stack on the light-emitting part side. In at least parts of the recesses, a part of the light-emitting part is embedded. The side surface of each recess surrounds dislocation penetrating through the first stack. The In composition ratio around the dislocation is lower than that of the other portion.

Description

  Embodiments described herein relate generally to a semiconductor device, a wafer, a method for manufacturing a semiconductor device, and a method for manufacturing a wafer.

  Nitride semiconductors are used in various semiconductor elements such as semiconductor light emitting elements and HEMT (High Electron Mobility Transistor) elements. In such a nitride semiconductor, device characteristics are restricted by high-density threading dislocations due to lattice mismatch with the GaN crystal.

  For example, a semiconductor light-emitting device using a nitride semiconductor is expected as a phosphor excitation light source such as a white LED, but has low efficiency.

  Various proposals have been made to improve the efficiency of semiconductor light emitting devices such as LEDs using nitride semiconductors.

JP 2010-205988 A

  Embodiments of the present invention provide a highly efficient semiconductor device, wafer, semiconductor device manufacturing method, and wafer manufacturing method.

  According to an embodiment of the present invention, an n-type first layer including a nitride semiconductor, a p-type second layer including a nitride semiconductor, a light emitting unit, a first stacked body, a second stacked body, A semiconductor device is provided. The light emitting unit is provided between the first layer and the second layer. The light emitting unit includes a barrier layer and a well layer. The first stacked body is provided between the first layer and the light emitting unit. The first stacked body includes a plurality of third layers including AlGaInN and a plurality of fourth layers including GaInN stacked alternately with the plurality of third layers. The second stacked body is provided between the first layer and the first stacked body. The second stacked body includes a plurality of fifth layers including a nitride semiconductor having a composition different from the composition of the third layer, and a plurality of sixth layers including GaInN stacked alternately with the plurality of fifth layers. And including. The first stacked body has a recess provided on a surface of the first stacked body on the light emitting unit side. A part of the light emitting part is embedded in at least a part of the recess. A part of the second layer is disposed on the part of the light emitting part embedded in the at least part of the recess. A dislocation penetrating the first laminate is formed, and a side surface of the recess surrounds the dislocation. The In composition ratio in the vicinity of the dislocation in the first stacked body is lower than the In composition ratio in a portion of the first stacked body away from the dislocation.

1 is a schematic cross-sectional view showing a semiconductor element according to a first embodiment. FIG. 2A to FIG. 2D are schematic cross-sectional views showing a part of the semiconductor element according to the first embodiment. 1 is a schematic cross-sectional view showing a semiconductor element according to a first embodiment. It is a typical sectional view showing another semiconductor device concerning a 1st embodiment. It is a typical sectional view showing another semiconductor device concerning a 1st embodiment. It is a typical sectional view showing another semiconductor device concerning a 1st embodiment. It is typical sectional drawing which shows the wafer which concerns on 2nd Embodiment. It is a flowchart figure which shows the manufacturing method of the semiconductor element which concerns on 3rd Embodiment. It is typical sectional drawing which shows the semiconductor element which concerns on 4th Embodiment. It is a graph which shows the characteristic of the semiconductor element which concerns on 4th Embodiment. It is typical sectional drawing which shows the wafer which concerns on 5th Embodiment. It is a flowchart figure which shows the manufacturing method of the semiconductor element which concerns on 6th Embodiment.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between the parts, and the like are not necessarily the same as actual ones. Further, even when the same part is represented, the dimensions and ratios may be represented differently depending on the drawings.
Note that, in the present specification and each drawing, the same elements as those described above with reference to the previous drawings are denoted by the same reference numerals, and detailed description thereof is omitted as appropriate.

(First embodiment)
The present embodiment relates to a semiconductor element. The semiconductor element according to the embodiment includes a semiconductor device such as a semiconductor light emitting element, a semiconductor light receiving element, and an electronic device. The semiconductor light emitting element includes, for example, a light emitting diode (LED) and a laser diode (LD). The semiconductor light receiving element includes a photodiode (PD) and the like. The electronic device includes, for example, a high electron mobility transistor (HEMT), a heterojunction bipolar transistor (HBT), a field transistor (FET), a Schottky barrier diode (SBD), and the like.
Hereinafter, an example in which the embodiment is applied to a semiconductor light emitting element will be described.

FIG. 1 is a schematic cross-sectional view illustrating the configuration of the semiconductor element according to the first embodiment.
As shown in FIG. 1, the semiconductor element 10 according to this embodiment includes a first layer 130, a second layer 150, a light emitting unit 140 (functional unit), and a first stacked body 210.

  The first layer 130 includes a nitride semiconductor and is n-type. The second layer 150 includes a nitride semiconductor and is p-type.

  In this example, the first layer 130 includes an n-type confinement layer 131 and an n-type contact layer 132. The n-type confinement layer 131 is disposed between the n-type contact layer 132 and the light emitting unit 140. The n-type confinement layer 131 includes, for example, at least one of n-type GaN and n-type AlGaN.

  In this example, the second layer 150 includes a p-type confinement layer 151 and a p-type contact layer 152. The p-type confinement layer 151 is disposed between the n-type contact layer 152 and the light emitting unit 140. The p-type confinement layer 151 includes, for example, p-type AlGaN.

  The light emitting unit 140 is provided between the first layer 130 and the second layer 150. The light emitting unit 140 includes a barrier layer (described later) and a well layer (described later). For example, a plurality of barrier layers are provided. The well layer is provided between the plurality of barrier layers.

  The first stacked body 210 is provided between the first layer 130 and the light emitting unit 140. The first stacked body 210 includes a plurality of third layers 203 and a plurality of fourth layers 204. The plurality of fourth layers 204 are alternately stacked with the plurality of third layers 203. The third layer 203 includes, for example, AlGaInN. The multiple fourth layers 204 include, for example, GaInN. Each thickness of the fourth layer 204 may be smaller than the thickness of a well layer (described later) of the light emitting unit 140.

  Here, the direction from the first layer 130 toward the second layer 150 is defined as the Z-axis direction. For example, the first layer 130, the first stacked body 210, the light emitting unit 140, and the second layer 150 are stacked in this order along the Z-axis direction.

  In the present specification, the state of being stacked includes not only the state of being directly stacked but also the state of being stacked with another element inserted therebetween.

  A first stacked body 210 is provided on the first layer 130, a light emitting unit 140 is provided on the first stacked body 210, and a second layer 150 is provided on the light emitting unit 140.

  In the specification of the present application, the state provided above includes the state in which another element is inserted therebetween and the state in which the other element is disposed in addition to the state in which the element is disposed above in contact.

  In this example, the semiconductor element 10 further includes a second stacked body 220. The second stacked body 220 is provided between the first layer 130 and the first stacked body 210. The second stacked body 220 includes a plurality of fifth layers 205 and a plurality of sixth layers 206. The plurality of sixth layers 206 are alternately stacked with the plurality of fifth layers 205. The plurality of fifth layers 205 have a composition different from the composition of the third layer 203. As the fifth layer 205, for example, GaN is used. The sixth layer 206 includes GaInN. The thickness of the sixth layer 206 may be smaller than the thickness of a well layer (described later) of the light emitting unit 140.

  For example, in the semiconductor element 10, for example, the first buffer layer 121 of AlN is provided on the main surface of the substrate 110. The main surface of the substrate 110 is, for example, a sapphire c-plane. A non-doped GaN second buffer layer 122 is provided on the substrate 110. Specifically, the first buffer layer 121 includes a high-carbon concentration first AlN buffer layer 121a formed on the substrate 110 and a high-purity second AlN buffer layer 121b formed on the first AlN buffer layer 121a. And including. The carbon concentration in the first AlN buffer layer 121a is higher than the carbon concentration in the second AlN buffer layer 121b.

  On the second buffer layer 122, for example, an Si-doped n-type GaN n-type contact layer 132, an Si-doped n-type confinement layer 131, a light emitting unit 140, and an Mg-doped p-type AlGaN p-type confinement layer. 151 and an Mg-doped p-type GaN p-type contact layer 152 are stacked.

  Further, a p-side electrode 160 of Ni, for example, is provided on the p-type contact layer 152. On the n-type contact layer 132, for example, an n-side electrode 170 of an Al / Au laminated film is provided.

  By applying a voltage to the p-side electrode 160 and the n-side electrode 170, a current is supplied to the light emitting unit 140, and light (emitted light) is emitted from the light emitting unit 140.

FIG. 2A to FIG. 2D are schematic cross-sectional views illustrating the configuration of a part of the semiconductor element according to the first embodiment.
FIG. 2A illustrates the configuration of the light emitting unit 140 in the semiconductor element 10, semiconductor elements 11, 12, 13, and 14, which will be described later, and wafers 60 and 64. FIG. 2B illustrates the configuration of the light emitting unit 140 in the semiconductor elements 10a, 11a, 12a, 13a and 14a, and the wafers 60a and 64a. FIG. 2C illustrates the configuration of the light emitting unit 140 in the semiconductor elements 10b, 11b, 12b, 13b, and 14b, which will be described later, and the wafers 60b and 64b. FIG. 2D illustrates a configuration of the light emitting unit 140 in the semiconductor elements 11c, 12c, 13c, and 14c, which will be described later, and the wafers 60c and 64c.

  As shown in FIG. 2A, in the semiconductor element 10, the light emitting unit 140 includes a plurality of barrier layers 41 (for example, the first barrier layer BL1 and the second barrier layer BL2) and the well layer 42. Including. The well layer 42 is provided between the plurality of barrier layers 41.

  For example, the light emitting unit 140 may have a single quantum well (SQW) structure. At this time, the light emitting unit 140 includes two barrier layers 41 and a well layer 42 provided between the barrier layers 41. For example, the light emitting unit 140 may have a multi quantum well (MQW) structure. At this time, the light emitting unit 140 includes three or more barrier layers 41 and a well layer 42 provided between the barrier layers 41.

  In the example shown in FIG. 2A, the light emitting unit 140 includes (n + 1) barrier layers 41 and n well layers 42 (n is an integer of 1 or more). The (i + 1) -th barrier layer BL (i + 1) is disposed between the i-th barrier layer BLi and the second layer 150 (i is an integer not less than 1 and not more than (n−1)). The (i + 1) th well layer WL (i + 1) is disposed between the i-th well layer WLi and the second layer 150. The first barrier layer BL1 is provided between the first layer 130 and the first well layer WL1 (that is, between the first stacked body 210 and the first well layer WL1). The nth well layer WLn is provided between the nth barrier layer BLn and the (n + 1) th barrier layer BL (n + 1). The (n + 1) th barrier layer BL (n + 1) is provided between the nth well layer WLn and the second layer 150.

  As shown in FIG. 2B, in the semiconductor element 10 a according to this embodiment, one well layer 42 is provided in the light emitting unit 140. As shown in FIG. 2C, in the semiconductor element 10 b according to the present embodiment, the two well layers 42 are provided in the light emitting unit 140. As illustrated in FIG. 2D, in the semiconductor element 10 c according to the present embodiment, the three well layers 42 are provided in the light emitting unit 140. Four or more well layers 42 may be provided in the light emitting unit 140.

  Here, the barrier layer 41 closest to the second layer 150 among the plurality of barrier layers 41 is referred to as a p-side barrier layer BLp. In the case where a plurality of well layers 42 are provided, the barrier layer 41 provided between the plurality of well layers 42 is referred to as an inter-well barrier layer BLI.

  Among the plurality of barrier layers 41, the barrier layer 41 closest to the first layer 130 is the first barrier layer BL1. A part of the first stacked body 210 may also serve as this layer. In other words, the layer closest to the light emitting unit 140 among the plurality of third layers 203 of the first stacked body 210 may be the first barrier layer BL1.

The first barrier layer BL1 includes, for example, Al _x1 Ga _1-x1-y1 In _y1 N (0 ≦ x <1, 0 ≦ _y1, 0 <x1 + y1 ≦ 1). For example, Si-doped n-type AlGaInN is used for the first barrier layer BL1.

The second barrier layer BL2 (and the m-th barrier layer BLm: m is an integer of 2 or more) includes Al _x2 Ga _1-x2-y2 In _y2 N (0 ≦ x2, y2 <1, 0 <x2 + y2 ≦ 1). . X2 may be the same as or different from x1. Moreover, y2 may be the same as y1, and may differ. It is particularly preferable that x2 <x1. It is particularly preferable that y1 <y2.

The well layer 42 includes Al _x0 Ga _1-x0-y0 In _y0 N (0 ≦ x0, 0 <y0, x0 + y0 <1, y1 <y0, y2 <y0). The well layer 42 includes Ga _1-y0 In _y0 N (0 <y0 ≦ 1, y1 <y0, y2 <y0). Thus, the well layer 42 can contain at least one of GaInN and AlGaInN.
The well layer 42 has a thickness (length along the Z-axis direction) of, for example, 2 nanometers (nm) or more and 9 nm or less.

  The band gap energy of the well layer 42 is smaller than the band gap energy of the barrier layer 41. The band gap energy of the well layer 42 is smaller than the band gap energy in the first stacked body 210 and the band gap energy in the second stacked body 220. Thereby, the light emitted from the well layer 42 is suppressed from being absorbed by other semiconductor layers included in the semiconductor element 10. Thereby, light is extracted outside with high efficiency.

  In the first stacked body 210, the fourth layer 204 may be thinner than the well layer 42. The third layer 203 may be thinner than the thickness of the second barrier layer BL2 (and the mth barrier layer BLm: m is an integer of 2 or more).

  The lower limit of the thickness of the fourth layer 204 is determined by a thickness greater than the fourth layer 204 continuously showing physical properties as a layer. The upper limit of the thickness of the fourth layer 204 is determined by the condition that a difference is provided between the energy at the absorption edge in the fourth layer 204 and the energy at the absorption edge in the well layer 42.

  That is, the thickness of the fourth layer 204 is set to, for example, three atomic layers or more, and the thickness at which the energy at the absorption edge in the fourth layer 204 is sufficiently larger than the absorption edge of the well layer 42. Specifically, the wavelength corresponding to the energy at the absorption edge of the fourth layer 204 is set to a shorter wavelength side than the wavelength at which the intensity of the emission spectrum of the well layer 42 is not more than half of the peak value. The thickness of the well layer 42 is, for example, not less than the thickness of the four atomic layer.

  For example, when the same composition as the well layer 42 is applied to the fourth layer 204, the fourth layer 204 can be grown under the same conditions as the well layer 42, and the process can be easily performed. In addition, preparation under the same growth conditions as the well layer 42 can be performed for a sufficient time through the growth of the fourth layer 204 before the growth of the well layer 42, and the controllability of the well layer 42 can be improved. In this case, by making the thickness of the fourth layer 204 thinner than that of the well layer 42, the band gap energy can be made larger than that of the well layer 42, and the occurrence of absorption loss in the fourth layer 204 can be easily suppressed. .

  On the other hand, for example, if GaInN having a lower In composition ratio and a larger band gap energy than the well layer 42 is used for the fourth layer 204, the absorption of light emitted from the well layer 42 in the fourth layer 204 can be further reduced. . In this case, since the absorption is small, the fourth layer 204 can be made thicker, and the number of pairs of the third layer 203 and the fourth layer 204 can be increased.

The thickness of the third layer 203 is, for example, not less than 3 nm and not more than 6 nm. The lower limit is the minimum thickness that exhibits properties similar to a continuous layer. The upper limit is the thickness at which the effect of overlapping wave functions penetrating from both sides remains and the resistivity decreases.
For example, the third layer 203 has an Al composition (Al composition ratio is about 10% or less) comparable to that of the barrier layer 41 (for example, the first barrier layer BL1). As a result, the resistance due to the barrier against electrons between the GaN layer and the GaN layer can be reduced, and high-quality crystal growth can be obtained.

The third layer 203 is doped with Si. The concentration of Si in the third layer 203 is, for example, 1 × 10 ¹⁷ cm ⁻³ or more and 2 × 10 ¹⁹ cm ⁻³ or less. If it is less than 1 × 10 ¹⁷ cm ⁻³ , for example, the electrical resistance becomes high. When it exceeds 2 × 10 ¹⁹ cm ⁻³ , for example, the crystallinity decreases.

  For example, when the same composition as that of the barrier layer 41 (for example, the first barrier layer BL1) is applied to the third layer 203, the third layer 203 can be grown under the same conditions as the barrier layer 41, and the process can be easily performed. In addition, before the growth of the barrier layer 41, the preparation under the same growth conditions as the barrier layer 41 can be performed for a sufficient time through the growth of the third layer 203, and the barrier layer 41 (for example, the first barrier layer BL1) can be prepared. Controllability can be improved.

  For example, the barrier layer 41 has a function of confining carriers in the well layer 42. Conversely, the third layer 203 is expected to have an effect of flowing current with low resistance. Therefore, by reducing the resistance component by making the thickness of the third layer 203 smaller than that of the barrier layer 41, the resistance of the element is effectively reduced without impairing the carrier confinement effect in the well layer 42. can do.

  In the second stacked body 220, the sixth layer 206 may be thinner than the well layer 42. The fifth layer 205 may be thinner than the thickness of the second barrier layer BL2 (and the mth barrier layer BLm: m is an integer of 2 or more).

  The thickness of the sixth layer 206 is, for example, not less than the thickness of the three atomic layers. The thickness of the sixth layer 206 is set to a thickness at which the energy at the absorption edge in the sixth layer 206 is sufficiently larger than the absorption edge of the well layer 42. Specifically, the sixth layer 206 is set so that the wavelength corresponding to the energy at the absorption edge of the sixth layer 206 is shorter than the wavelength that is half or less of the peak value of the emission spectrum intensity of the well layer 42. A thickness of 206 is set. The relationship between the thickness of the sixth layer 206 and the thickness of the well layer 42 can be considered similarly to the relationship between the thickness of the fourth layer 204 and the thickness of the well layer 42. Therefore, like the fourth layer 204, the thickness of the sixth layer 206 may be made thinner than that of the well layer. The thickness of the sixth layer 206 is, for example, 1 nm.

  The thickness of the fifth layer 205 is, for example, not less than 3 nm and not more than 6 nm. The lower limit is the minimum thickness that exhibits properties similar to a continuous layer. The upper limit is the thickness at which the effect of overlapping wave functions penetrating from both sides remains and the resistivity decreases. The thickness of the fifth layer 205 is, for example, 2.5 nm.

For example, Si is added to the fifth layer 205. The concentration of Si in the fifth layer 205 is, for example, 10 × 10 ¹⁷ cm ⁻³ or more and 2 × 10 ¹⁹ cm ⁻³ or less. If it is less than 10 × 10 ¹⁷ cm ⁻³ , for example, the electrical resistance becomes high. When it exceeds 2 × 10 ¹⁹ cm ⁻³ , for example, the crystallinity decreases. The Si concentration in the fifth layer 205 is, for example, 1.2 × 10 ¹⁸ cm ⁻³ .

  The relationship between the thickness of the fifth layer 205 and the thickness of the barrier layer 41 is considered the same as the relationship between the thickness of the third layer 203 and the thickness of the barrier layer 41. For this reason, like the third layer 203, the thickness of the fifth layer 205 may be made thinner than that of the barrier layer 41. The thickness of the fifth layer 205 is, for example, 2.5 nm.

  The number of fifth layers 205 may be one more than the number of sixth layers 206, and the number of fifth layers 205 may be one less than the number of sixth layers 206.

  In the case where the second stacked body 220 is grown at a low temperature in accordance with the sixth layer 206, the first growth layer performed at a lower temperature can be the sixth layer 206. When the number of the sixth layers 206 is increased, growth can be started with a flatter layer, and particularly high-quality crystal growth is possible.

  In the embodiment, the number of pairs of the third layer 203 and the fourth layer 204 in the first stacked body 210 may be the same as the number of pairs of the fifth layer 205 and the sixth layer 206 in the second stacked body 220, It may be different.

  The emission-equivalent wavelength of the first laminate 210 is preferably 370 nm or more and 380 nm or less. The inventor of the present application experimentally confirmed by PL measurement that the emission efficiency of the light emitting unit 140 is high when the emission equivalent wavelength of the first laminate 210 is 370 nm to 380 nm, particularly 370 nm to 375 nm. did. Based on this experimental result, it is considered that it is desirable for improving the device characteristics that the emission equivalent wavelength of the first stacked body 210 is a wavelength range of 370 nm or more and 380 nm or less. Here, the emission equivalent wavelength will be described. The inventor of this application has confirmed that light emission from the first stacked body 210 may be confirmed when PL measurement is performed on a wafer used in the semiconductor element of the present embodiment. The peak wavelength of this emission spectrum was taken as the emission equivalent wavelength of this semiconductor element.

  Hereinafter, specific examples of the configuration of the various layers described above will be shown. However, the present embodiment is not limited to this, and various modifications can be made.

The thickness of the first buffer layer 121 is, for example, about 2 micrometers (μm). The thickness of the first AlN buffer layer 121a is, for example, not less than 3 nm and not more than 20 nm. The thickness of the second AlN buffer layer 121b is, for example, about 2 μm.
Further, the thickness of the second buffer layer 122 is, for example, 2 μm.

The Si concentration in the n-type contact layer 132 is, for example, 5 × 10 ¹⁸ cm ⁻³ or more and 2 × 10 ¹⁹ cm ⁻³ or less. Further, the thickness of the n-type contact layer 132 is, for example, about 6 μm.

For the n-type confinement layer 131, for example, Si-doped n-type GaN is used. The Si concentration in the n-type confinement layer is, for example, about 2 × 10 ¹⁸ cm ⁻³ . The thickness of the n-type confinement layer 131 is, for example, about 0.5 μm.

For the p-type confinement layer 151, for example, Mg-doped p-type Al _0.15 Ga _0.85 N is used. The thickness of the p-type confinement layer 151 is, for example, about 24 nm. The Mg concentration on the light emitting unit 140 side of the p-type confinement layer 151 is, for example, about 3 × 10 ¹⁹ cm ⁻³ . The Mg concentration on the side of the p-type confinement layer 151 opposite to the light emitting portion 140 (in this specific example, the side of the p-side electrode 160) is, for example, 1 × 10 ¹⁹ cm ⁻³ .

The Mg concentration on the p-type confinement layer 151 side of the p-type contact layer 152 is, for example, about 1 × 10 ¹⁹ cm ⁻³ . The Mg concentration on the side of the p-type contact layer 152 opposite to the n-type confinement layer 151 (the side of the p-side electrode 160 in this specific example) is, for example, 2 × 10 ¹⁹ cm ⁻³ or more and 20 × 10 ¹⁹ cm ⁻³ or less. It is said.

  As already described, for example, GaInN is used for the well layer 42. The thickness of the well layer 42 is, for example, not less than 2 nm and not more than 9 nm. In particular, good light emission can be obtained when the thickness is 2.6 nm or more and 7 nm or less.

  The light (emitted light) emitted from the light emitting unit 140 is, for example, near ultraviolet light. The peak wavelength of the emitted light is, for example, not less than 380 nm and not more than 400 nm. However, the embodiment is not limited to this, and the wavelength of the emitted light is arbitrary. The peak wavelength of the emitted light may be longer than 400 nm and not longer than 500 nm, for example.

  When the peak wavelength of the emission wavelength in the light emitting unit 140 is 380 nm or more, in addition to the absorption of GaN having an absorption edge of 365 nm, the influence of absorption by the first stacked body 210 can be reduced. Since it is considered desirable for improving the device characteristics that the emission equivalent wavelength of the first laminate 210 is in the wavelength range of 370 nm or more and 380 nm or less, the characteristics can be improved if the emission wavelength of the light emitting unit 140 is longer than 380 nm.

  When the peak wavelength of the emission wavelength in the light emitting unit 140 is 400 nm or less, the thickness of the well layer 42 is set to 4.5 nm or more and 9 nm or less. Thereby, for example, good light emission can be obtained. When the peak wavelength of the emission wavelength in the light emitting unit 140 is 395 nm or less, the thickness of the well layer 42 is set to 4.5 nm or more and 7 nm or less. Thereby, favorable light emission was obtained, and the controllability of the emission wavelength and intensity was further improved.

  When the peak wavelength of the emission wavelength in the light emitting part 140 is 420 nm or more and 450 nm or less, high luminous efficiency can be obtained by setting the thickness of the well layer 42 to 3 nm or more and 4.5 nm or less. In the case where the peak wavelength is 420 nm or more and 450 nm or less, the controllability of the emission intensity is improved when the thickness of the well layer 42 is set to 3.5 nm or more and 4 nm or less.

  In the single quantum well structure in which the peak wavelength of the emission wavelength in the light emitting part 140 is 430 nm or more and 470 nm or less, high luminous efficiency can be obtained when the thickness of the well layer 42 is 3 nm or more and 3.5 nm or less. In the multiple quantum well structure having a peak wavelength of the emission wavelength of 430 nm or more and 470 nm or less, high emission efficiency could be obtained when the thickness of the well layer 42 was 2.6 nm or more and 3 nm or less.

  The peak wavelength of the emitted light in the light emitting section 140 can be set to, for example, 470 nm or more, and light emission can be obtained from the well layer 42 having a thickness of 2 nm to 3.5 nm.

  In the present embodiment, since a high-quality base crystal is obtained, the configuration of the present embodiment has a longer wavelength (for example, 500 nm band, 600 nm band, 700 nm band, and shorter than 0.75 eV which is an absorption edge of InN). The present invention is applicable to an element having an active layer having an arbitrary wavelength. In the embodiment, the light emitting unit 140 includes various types such as a DH (Double Hetero) structure, a piecewise quantum well structure, and a quantum dot structure in addition to a single quantum well structure and a multiple quantum well structure. Can have a configuration.

For example, Ga _0.85 In _0.15 N is used for the well layer 42. At this time, the thickness of the well layer 42 is, for example, about 3.3 nm. The peak wavelength of light emitted from the light emitting unit 140 (well layer 42) is 400 nm or more and 450 nm or less. When the number of well layers 42 is two, particularly high efficiency is obtained. The number of well layers 42 may be three.

For example, Si-doped n-type Al _0.065 Ga _0.93 In _0.005 N is used for the first barrier layer BL1. The Si concentration in the first barrier layer BL1 is, for example, 0.3 × 10 ¹⁹ cm ⁻³ or more and 2 × 10 ¹⁹ cm ⁻³ or less. The thickness of the first barrier layer BL1 is, for example, not less than about 10 nm and not more than 25 nm.

  For example, GaInN is used for the second barrier layer BL2 (and the m-th barrier layer BLm: m is an integer of 2 or more). The thickness of the second barrier layer BL2 (and the mth barrier layer BLm: m is an integer of 2 or more) is, for example, about 6 nm.

  Alternatively, for example, GaN is used for the second barrier layer BL2 (and the mth barrier layer BLm: m is an integer of 2 or more).

  When a plurality of well layers 42 are provided, for example, GaInN is used for the inter-well barrier layer BLI. The band gap energy of the inter-well barrier layer BLI is preferably set to be equal to or lower than the band gap energy of the first barrier layer BL1 and equal to or lower than the band gap energy of the p-side barrier layer BLp.

For example, Ga _0.93 In _0.07 N is used for the second barrier layer BL2 (and the m-th barrier layer BLm: m is an integer of 2 or more). The thickness of the second barrier layer BL2 (and the mth barrier layer BLm: m is an integer of 2 or more) is, for example, more than 2 nm and less than 9 nm. The thickness of the second barrier layer BL2 (and the mth barrier layer BLm: m is an integer of 2 or more) is particularly preferably more than 2 nm and less than 5 nm.

  The Al composition in the first barrier layer BL1 and the i-th barrier layer BLi (1 <i ≦ n) is 6% in order to form a deep potential for generating ultraviolet light having an emission wavelength of 380 nm to 400 nm with high efficiency. It may be set as described above.

  The thickness of the barrier layer 41 is set to 2 nm or more. When the thickness of the barrier layer 41 (p-side barrier layer BLp) closest to the p-type AlGaN second layer 150 is less than 2 nm, the n-th well is used in the process of increasing the growth temperature to grow the p-type AlGaN layer. This is because the well layer 42 including the layer WLn causes thermal degradation. In order to control the characteristics of the well layer 42 including the influence of impurity diffusion, the thickness of the p-side barrier layer BLp is set to 4.5 nm or more. In particular, when the thickness of the p-side barrier layer BLp is larger than the thickness of the well layer 42, the effect of reducing the influence of strain between the p-type AlGaN layer and the well layer 42 is great.

  Note that if the p-side barrier layer BLp is excessively thick, the element resistance becomes high. On the other hand, if the barrier layer 41 other than the first barrier layer BL1 is excessively thick, the element resistance is increased, and carriers overflowing the well layer 42 are accumulated to cause absorption. Conversely, if the barrier layer 41 other than the p-side barrier layer BLp is too thin, the confinement of carriers in the well layer 42 is weakened and the light emission efficiency is lowered. In order to reduce this influence, it is desirable to make the barrier layers 41 other than the first barrier layer BL1 thinner than the first barrier layer BL1. In particular, in a semiconductor device in which the thickness of the p-side barrier layer BLp is 4 nm or more and 9 nm or less, the device can be operated with a voltage increase within 10% of the operating voltage expected from the emission wavelength. In the device in which the thickness of the barrier layer 41 other than the first barrier layer BL1 and the p-side barrier layer BLp is 4 nm or more and 15 nm or less, high-efficiency light emission characteristics are obtained.

  The thickness of the first barrier layer BL1 can be set to a value in the range of, for example, not less than 4.5 nm and not more than 30 nm. When the thickness of the first barrier layer BL1 is 4.5 nm or more, the original physical properties of the material are exhibited, and the effect of suppressing the overflow of holes can be obtained. In addition, when the thickness of the first barrier layer BL1 is 30 nm or less, high-quality crystal growth can be performed relatively easily.

  The first to n-th barrier layers BL1 to BLn are preferably thicker than the well layer 42. By setting the thickness of the first barrier layer BL1 to be larger than the thickness of the well layer 42, the control of the carrier supply to the well layer 42 becomes effective. In particular, the thickness of the first to n-th barrier layers BL1 to BLn is preferably at least twice the thickness of the well layer 42. By setting the thicknesses of the first to nth barrier layers BL1 to BLn to be twice or more the thickness of the well layer 42, the first to (n-1) th barrier layers BL1 to BL (n-1) are set. Carrier supply is possible on both sides, and the accuracy of carrier supply to the well layer 42 is improved.

  For the n-th well layer WLn, the thickness of the p-side barrier layer BLp is thin except for the above-described conditions in order to efficiently inject holes from the second layer 150 of p-type AlGaN. It is desirable. For this reason, the thickness of the p-side barrier layer BLp may be thinner than the third layer 203 of the first stacked body 210 and the fourth layer 204 of the second stacked body 220.

  For example, the first barrier layer BL1 suppresses holes injected into each well layer 42 of the light emitting unit 140 from flowing out to the first layer 130 side. In particular, the thickness of the first barrier layer BL1 is made sufficiently thick in order to have a potential block effect on carriers including the case where there is a crystal defect or the like. A sufficient effect can be obtained when the thickness of the first barrier layer BL1 is about 15 nm or more and 20 nm or less. When the thickness of the first barrier layer BL1 is less than 13 nm, there is a case where the rate of generation of elements having a large efficiency drop increases when the current injection density is increased. When the thickness of the first barrier layer BL1 is thicker than 22 nm, there is a case where the ratio of occurrence of elements with high resistance increases.

  The third layer 203 of the first stacked body 210 and the fifth layer 205 of the second stacked body 220 are on the opposite side of the light emitting unit 140 with respect to the first barrier layer BL1. Therefore, compared with the first barrier layer BL1, the role of the third layer 203 and the fifth layer 205 to suppress the phenomenon of holes leaking from the light emitting unit 140 is small. On the other hand, since a plurality of the third layers 203 and the fifth layers 205 are provided, they easily work as current resistance. For this reason, in order to reduce the driving voltage of the element, the third layer 203 and the fifth layer 205 are preferably as thin as possible. For this reason, it is desirable that the thickness of the third layer 203 and the fifth layer 205 is smaller than the thickness of the first barrier layer BL1.

  Since the thickness of the third layer 203 and the fifth layer 205 is desired to be thin in order to lower the electrical resistance, the band gap of the first barrier layer BL1 is made larger than these layers, and the first barrier layer The electric resistance of BL1 is increased. The relationship between the thickness of the first barrier layer BL1, the thickness of the third layer 203, and the thickness of the fifth layer 205 is an effective thickness relationship based on electrical resistance. For example, at least the effective thickness of the first barrier layer BL1 is set to be greater than or equal to the effective thickness of the third layer 204 and the effective thickness of the fifth layer 205. Thereby, the characteristic of an element improves.

  Note that by adding Si to the first barrier layer BL1 at a high concentration, the influence of the piezoelectric field applied to the well layer 42 can be reduced, and highly efficient light emission can be obtained.

  Regarding the relationship between the well layer 42 of the light emitting unit 140, the GaInN layer of the fourth layer 204 of the first stacked body 210, and the GaInN layer of the sixth layer 206 of the second stacked body 220, also depends on the thickness of the well layer 42. It is desirable that the GaInN layer be thin. As a result, the optical band gap energy of the well layer 42 becomes smaller than the optical band gap energy of GaInN of the fourth layer 204 and GaInN of the sixth layer 206. Thereby, the light emission of the well layer 42 is suppressed from being absorbed by at least one of GaInN of the fourth layer 204 and GaInN of the sixth layer 206. The relationship among the thicknesses of the well layer 42, the GaInN of the fourth layer 204, and the GaInN of the sixth layer 206 can be defined by the effective thicknesses based on the respective optical band gap energies. It is desirable that the effective thickness of GaInN in the fourth layer 204 and the effective thickness of GaInN in the sixth layer 206 be smaller than the effective thickness of the well layer 42.

  In a thin film structure, if the band gap energy is changed greatly only by changing the composition, and a crystal having a smaller band gap energy than that of the thicker layer is produced, the difference in the In composition ratio of GaInN increases. Because of the large difference in material properties, high-quality crystal growth is difficult. For this reason, even in real space, it is more desirable that the GaInN thickness of the fourth layer 204 and the GaInN thickness of the sixth layer 206 are smaller than the thickness of the well layer 42.

  When the Al composition ratio in the first barrier layer BL1 and the i-th barrier layer BLi (1 <i ≦ (n + 1)) exceeds 10%, the crystal quality deteriorates. Further, for example, crystal quality can be improved by doping a small amount of In into the first barrier layer BL1 and the i-th barrier layer BLi. Improvement in crystal quality is observed when the In composition ratio in the first barrier layer BL1 and the i-th barrier layer BLi is 0.3% or more. However, when the In composition ratio exceeds 1.0%, the crystal quality deteriorates and the light emission efficiency decreases. However, when the first barrier layer BL1 and the i-th barrier layer BLi are thin, the In composition ratio can be increased to 2%.

As the fifth layer 205 of the second stacked body 220, for example, a GaN layer having a thickness of 2.5 nm is used. For the sixth layer 206, for example, a Ga _0.93 In _0.07 N layer of 1 nm is used. The number of layers (number of pairs) of the fifth layer 205 and the sixth layer 206 is 16, for example. At this time, for example, the number of the fifth layers 205 may be 17, and the number of the sixth layers 206 may be 16.

For the third layer 203 of the first stacked body 210, for example, an Al _0.07 Ga _0.93 In _0.01 N layer having a thickness of 2 nm is used. For the fourth layer 204, for example, a 1 nm Ga _0.93 In _0.07 N layer is used. The number of stacked layers (number of pairs) of the third layer 203 and the fourth layer 204 is, for example, 30.

  Further, as will be described later, an intermediate layer may be provided between the first stacked body 210 and the second stacked body 220.

FIG. 3 is a schematic cross-sectional view illustrating the configuration of the semiconductor element according to the first embodiment. As shown in FIG. 3, in the semiconductor element 10 according to the present embodiment, the first stacked body 210 has a recess 210 d. The recess 210d is provided on the surface 210a of the first laminate 210 on the light emitting unit 140 side. The recess 210d retreats along the direction from the second layer 150 toward the first layer 130 (−Z axis direction). A part of the light emitting unit 140 is embedded in at least a part of the recess 210d.
Thereby, a highly efficient semiconductor element is provided.

  Furthermore, a part of the second layer 150 is disposed on a part of the light emitting unit 140 embedded in at least a part of the recess 210d. Furthermore, a part of the second layer 150 may be embedded in at least a part of the recess 210d (residual space).

  Further, for example, the recess 210d does not penetrate the first stacked body 210 along the Z-axis direction. That is, the tip 210e of the recess 210d is located in the first stacked body 210. The tip 210e of the recess 210d is located between the surface 210b on the first layer 130 side of the first stacked body 210 and the surface 210a on the light emitting section 140 side of the first stacked body 210.

  In addition, as illustrated in FIG. 3, dislocations 510 penetrating the first layer 130, the first stacked body 210, the light emitting unit 140, and the second layer 150 are formed. The side surface 210s of the recess 210d surrounds the dislocation 510.

  The side surface 210s of the recess 210d is, for example, substantially symmetric with respect to the extension axis of the dislocation 510 (for example, circular symmetry, three-fold symmetry, six-fold symmetry, etc. are included). The dislocation 510 is, for example, substantially parallel to the Z-axis direction. “Substantially symmetric” includes structures that are not perfect symmetry but are imperfect and generally highly interesting.

  By having such a configuration, high efficiency can be obtained in the semiconductor element 10.

  The inventor of the present application has constructed a configuration of a semiconductor element that can emit light with high efficiency based on the experimental results and considerations described below.

  In a semiconductor element using a nitride semiconductor, there is a configuration in which a stacked body in which a plurality of GaInN layers are stacked is provided between a light emitting unit 140 including a well layer 42 using a GaInN layer and a sapphire substrate. The inventor of the present application forms a stacked body (corresponding to the second stacked body 220) by alternately stacking a plurality of GaN layers and a plurality of GaInN layers, and a light emitting unit 140 having a GaInN well layer 42 thereon. An experiment was conducted to form a semiconductor element. Then, the relationship between the number of stacked layers in the stacked body and the planar flatness of the semiconductor element was examined. As a result, the surface flatness is improved by providing a laminated body in which the GaN layer and the GaInN layer are alternately and repeatedly laminated. However, if the number of laminated layers is increased, the surface flatness may be impaired. I found.

  Furthermore, when a laminated body (corresponding to the first laminated body 210) in which a plurality of AlGaInN layers and a plurality of GaInN layers are alternately laminated is inserted between the second laminated body 210 and the light emitting portion 140, high surface flatness is obtained. It has been found that the number of GaInN layers to be maintained may increase.

  The thickness of the GaInN layer of the well layer 42 is several nm. If the surface flatness is improved, it is considered that the GaInN layer of the light emitting unit 140 is less affected by unevenness, and the light emission efficiency can be improved.

  When forming the 1st laminated body 210 (lamination of an AlGaInN layer and a GaInN layer) on the 2nd laminated body 220 (lamination of a GaN layer and a GaInN layer), the number of layers of an AlGaInN layer and a GaInN layer was changed. The dependency of the flatness of the crystal surface on the number of layers shows the same tendency as the dependency of the flatness on the number of layers when only the second stacked body 220 is provided. However, when the AlGaInN layer and the GaInN layer are combined, the flatness of the crystal surface is improved as compared with the case where the structure combining the AlGaInN layer and the GaInN layer is not introduced even in a larger number of layers. There was no rapid deterioration of flatness like the laminated structure with the GaN layer. Further, in the case of providing the first first stacked body 210 on the second stacked body 220, the range of the number of layers that improves the flatness is the number of layers that improves the flatness when only the second stacked body 220 is provided. It was wider than the range. That is, it can be seen that the combination of the AlGaInN layer and the GaInN layer is particularly effective in improving flatness.

  That is, when the first stacked body 210 in which the AlGaInN layer and the GaInN layer are stacked a plurality of times and the second stacked body 220 in which the GaN layer and the GaInN layer are stacked a plurality of times are combined, the number of layers can be increased. The flatness of the crystal surface can be improved.

  For example, when the thickness of the AlGaInN layer is 2.5 nm and the thickness of the GaInN layer is 1 nm, the flatness is improved when the number of AlGaInN layers and GaInN layers is 3 or more and 25 or less, respectively. That is, when the total thickness of the GaInN layer is 3 nm or more and 25 nm or less, the flatness is improved and the light emission efficiency can be improved.

  When the first stacked body 210 and the second stacked body 220 are combined, the range of the total thickness of the GaInN layer that can improve the flatness of the crystal surface is widened, and the flatness may be improved at 3 nm or more and 50 nm or less.

  The inventor of the present application has found that in the first laminate 210, the stacking speed around the dislocation 510 (threading dislocation) is reduced, and a concave structure (concave 210d) is formed. When this recess 210d is filled with, for example, AlGaN (for example, the first barrier layer BL1), the AlGaN layer and a region where the AlGaIn layer and the GaInN layer that are thinner than those formed on the flat portion are dislocated. A recess 210d around 510 is embedded.

  If the effective band gap energy in the region where the AlGaInN layer and the GaInN layer that are thinner than those formed on the flat portion is larger than the band gap energy of GaInN in the well layer 42, the injected current becomes GaInN. It is possible to suppress waste around the dislocation 510 without effectively contributing to light emission in the well layer 42.

  Further, when the light emitting unit 140 includes a plurality of well layers 42 and the inter-well barrier layer BLI exists, the effective area of the region in which the AlGaInN layer and the GaInN layer that are thinner than those formed on the flat portion are stacked. The above effect is considered to be greater when the effective band gap energy is larger than the band gap energy of the inter-well barrier layer BLI.

  For example, it is preferable that the tip 210e of the recess 210d generated around the threading dislocation is formed in the first stacked body 210, and a region where the AlGaInN layer and the GaInN layer are mixed is formed around the threading dislocation. . The band gap energy in the region in which the AlGaInN layer and the GaInN layer that are thinner than when formed on the flat portion is larger than the band gap energy in which the GaN layer and the GaInN layer are laminated. By forming such a region having a large band gap energy, for example, the above-described effect can be obtained efficiently.

  This will be described in more detail below. When GaN, InN, AlN, and these mixed crystals are formed on the concave surface and become thinner than on the flat part, the thin film is easily separated from the crystal in the order of In, Ga, and Al, which are weakly bonded to N. It is thought that the contribution to conversion is large. For this reason, it is considered that the slope of embedding the recess 210d tends to increase the composition of Al and decrease the composition of In. In GaInN, it is considered that the band gap energy tends to increase from the viewpoint of composition and also from the viewpoint of thickness when the quantum effect is considered. AlGaInN is considered to show a tendency to increase the band gap energy in terms of composition. In this case, in the laminated structure of AlGaInN and GaInN, the band gap energy is particularly large, and when a thinned laminated structure is formed around the dislocation, the effect of suppressing the flow of current to the dislocation is large, and the light emitting device It is thought that the contribution to high (light) output is large.

  Thus, according to the semiconductor element 10 according to the present embodiment, a highly efficient semiconductor element is provided.

  In addition, it was found that by providing the first stacked body 210 between the second stacked body 220 and the light emitting unit 140, the characteristics of the semiconductor element, particularly the characteristics of electrical bonding can be improved.

  In the second stacked body 220, a GaN layer and a GaInN layer are provided. The second stacked body 220 has, for example, a superlattice structure. Since the lattice mismatch between the GaN layer and the GaInN layer is large and the growth rate around the dislocation 510 is slow, a dent is formed around the dislocation 510. At the center of the recess, for example, a dislocation 510 exists. At this time, strain is applied by the superlattice structure being laminated, and the dislocation 510 is gradually bent, and the dislocation 510 is generally along the vertical direction (Z-axis direction) with respect to the layer.

This inventor observed this state by cross-sectional TEM.
FIG. 3 is drawn based on this cross-sectional TEM image.
The opening of the dent depends on the orientation of the dislocation 510. In the portion where the dislocation 510 is oblique, the opening of the recess is wide. As the dislocation 510 becomes vertical (parallel to the Z-axis direction), the opening of the recess becomes smaller. The slope (side surface) of the dent is formed with an energy stable surface. Along with this, it is considered that the growth rate decreases, the In incorporation efficiency decreases, and the symmetry of the side surface of the dent improves. That is, In is difficult to be captured in a portion where the opening of the recess is narrow.

  For this reason, the In average composition ratio in the first portion (the portion on the first layer 130 side) of the second stacked body 220 is high. Then, it is considered that the second stacked body 220 grows, the opening becomes narrower, the In average composition ratio gradually decreases, and a constant In average composition ratio is obtained when the shape of the recess 210d is stabilized.

  Such a crystal can be formed by adjusting the superlattice structure of GaN and GaInN. Mainly the thickness and period are adjusted. For example, the thickness of the GaN layer is 2.5 nm, for example. The thickness of the GnInN layer is 1 nm, for example, and the In composition ratio is about 0.5%. The period (number of GaN layers and number of GaInN layers) is 16.

  The dent generated in the second stacked body 220 is transferred to the first stacked body 210 (AlGaInN layer and GaInN layer) and the light emitting unit 140 while the dislocation 510 is maintained in the vertical direction and the shape is maintained. It extends toward the surface while maintaining a substantially vertical direction. The shape of the recess (recessed portion 210d) is a substantially rotationally symmetric structure opened on the surface side (the side from the first layer 130 toward the second layer 150). For example, a cone, a hexagonal pyramid, and a triangular pyramid. The rotational symmetry axis is a direction along the approximate dislocation 510.

  A part of the light emitting unit 140 is embedded in the recess 210 d formed in the first stacked body 210. For example, from the cross-sectional TEM image, it is observed that the well layer 42 (InGaN layer) and the barrier layer 41 (AlGaInN layer) are laminated symmetrically with respect to the dislocation 510 passing through the central axis of the recess 210d.

  The thickness of the first stacked body 210 is thicker than the depth of the recess 210 d formed in the first stacked body 210. If the recess 210d penetrates the first stacked body 210, for example, it may cause carrier leakage. In order to suppress this, the configuration (mainly thickness and period) of the first stacked body 210 is appropriately set. For example, the thickness of the AlGaInN layer is 2 nm, for example. The thickness of the GaInN layer is 1 nm, for example. The period (the number of AlGaInN layers and the number of GaInN layers) is, for example, 30.

  When the direction of the dislocation 510 penetrating the light emitting portion 140 becomes vertical, the ratio of the area of the portion disturbed by the dislocation 510 to the area of the light emitting portion 140 decreases. Thereby, luminous efficiency improves. Further, since the dislocations 510 are vertical, it becomes difficult for current to flow, and current leakage is suppressed. Furthermore, since the In composition ratio around the dislocation 510 decreases, the band gap energy around the dislocation 510 increases, the lateral current toward the dislocation 510 is suppressed, and the leakage current decreases. In addition, since the relative area ratio of the region where the crystal around the dislocation 510 is disturbed is small, the quality of the second layer 150 grown on the light emitting unit 140 is improved. Moreover, the yield in manufacturing is improved.

  When forming a laminate, if the growth rate is slow, the efficiency of incorporation of Al (strongly bound to nitrogen) into the crystal surface is improved, and In (weakly bound to nitrogen) and Ga (bound to nitrogen) It is higher than the efficiency of incorporation into the medium surface). Therefore, by using the first stacked body 210 using the AlGaIn layer and the GaInN layer, a region with a high Al composition is easily formed around the dislocation 510. Thereby, the inflow of current to the dislocation 510 is suppressed, and the leakage current is suppressed.

  In a layer having a high Al composition ratio, the direction of dislocations 510 is likely to change from vertical. It is considered that the shape of the recess 210d is stabilized by supplying In, which has a weak bond with nitrogen and facilitates the movement of atoms on the crystal surface, during the formation of the AlGaInN layer.

  In addition, by repeatedly forming the thin AlGaInN layer and the thin GaInN layer, it is easy to take a high thermodynamically stable state before the shape of the recess 210d changes greatly during the formation of the AlGaInN layer. A GaInN layer is formed. Thereby, it is thought that the shape of the recess 210d is stable.

  Thus, by providing the first stacked body 210 in which a plurality of AlGaN layers and a plurality of GaInN layers are alternately stacked, the dislocation 510 is formed vertically in the light emitting unit 140. This improves efficiency.

  The inventors of the present application have also found that the flatness of the crystal surface is improved by the configuration of the semiconductor element 10 according to the present embodiment. By combining the second stacked body 220 and the first stacked body 210, a crystal with high surface flatness can be formed. Therefore, in this configuration, by increasing the number of GaInN layers, the recesses 210d can be efficiently formed in the first stacked body 210, and the flat well layer 42 can be formed.

  As described above, the stacking speed around the threading dislocation (dislocation 510) is reduced in the first stacked body 210 to form the recess 210d. In the recess 210d, a part of the light emitting unit 140 and the second layer 150 are formed. Part is embedded. As a result, a region having a large band gap energy in which the AlGaInN layer and the GaInN layer that are thinner than the flat portion are stacked is formed around the dislocation 510. As a result, current leakage to the vicinity of the dislocation is suppressed, and a decrease in the efficiency of the semiconductor element is suppressed. Thereby, highly efficient light emission is obtained.

  In the present embodiment, when a plurality of well layers 42 are provided, if the band gap energy of the barrier layer 41 between the well layers 42 is smaller than the band gap energy of the first barrier layer BL1 (for example, AlGaInN), more uniform carriers. An injection is obtained.

  In the present embodiment, the band gap energy of the well layer 42 is set to other layers (for example, the first barrier layer BL1, the layer containing GaN, the layer containing AlGaN, the first stacked body 210, and the second stacked body 210). ) Less than the band gap energy. For this reason, the light emission of the well layer 42 is suppressed from being absorbed by other layers. Furthermore, since the unevenness of the well layer 42 is small, the fluctuation of the absorption edge energy of the well layer 42 is small. For this reason, the effect that light emission in a certain region of the well layer 42 is absorbed at a place where another absorption edge energy of the well layer 42 is small is small. Further, when the number of well layers 42 is small (for example, 1, 2, 3, etc.), there are differences in carrier distribution among a plurality of well layers 42 (for example, four layers or more, etc.), and the light emission state is different. Even in this case, light is suppressed from being absorbed by other layers. Due to these effects, the emitted light is efficiently extracted outside.

  In the semiconductor element 10 according to the present embodiment, for example, the number of well layers 42 is set to 1 or more and 3 or less. As a result, carrier nonuniformity does not occur as in the case where a large number of well layers 42 are provided. In addition, since the number of well layers 42 is small, a uniform well layer 42 can be formed under the best manufacturing conditions. As a result, the light emission efficiency in the well layer 42 can be increased. Further, since the absorption in the well layers generated in the many well layers 42 is small, the light extraction efficiency can be improved.

  For example, when there is one well layer 42, electrons and holes are injected into the same well layer 42, and the light emission efficiency is increased. In addition, since there is no other well layer, there is no problem that the injected carrier density is distributed between the well layers, and light emission is absorbed by the well layer having a low injected carrier density, resulting in a decrease in luminous efficiency as a whole.

  When two well layers 42 are provided, a well layer 42 on the injection region side with high injection efficiency and a well layer 42 with high storage efficiency on the pn junction side are provided. For this reason, unlike the case where a large number (for example, four or more) of well layers 42 are provided, the well layers 42 having low light emission efficiency and large effects as absorbers are hardly generated.

  When the number of well layers 42 is three, the simplest structure that is symmetric with respect to electron injection and hole injection is generated as a structure having a plurality of well layers 42. For this reason, for example, a well layer 42 that is likely to be generated when a large number of well layers 42 of eight or more layers are provided has a low light emission efficiency and has a large effect as an absorber.

  In the semiconductor element 11 according to the present embodiment, when the number of the well layers 42 is a large number of 4 or more, even if the current injection density per area is increased, the carrier injection density per state density is difficult to increase, and a large current flows. Thus, a high-power semiconductor device can be easily realized.

  In a semiconductor element that emits light in blue (emission peak wavelength is 450 nm or more and 480 nm or less, for example), the In composition ratio in the well layer 42 is high. For this reason, when the well layer 42 having a thickness of 4.5 nm or more is formed, the strain based on the lattice irregularity between the GaN layer and the well layer 42 is too large, the crystal quality is lowered, and the emission intensity is lowered. On the other hand, when the thickness of the well layer 42 is small, the confinement of carriers in the well layer 42 is weak, and it is difficult to obtain high light emission efficiency with the SQW structure. Therefore, as a result, the MQW structure is adopted.

  In the present embodiment, when a plurality of well layers 42 are provided, the band gap energy of the inter-well barrier layer BLI may be set smaller than the band gap energy of AlGaInN of the first barrier layer BL1. Thereby, holes are uniformly injected into the well layer 42, and higher luminous efficiency can be obtained. Further, when such a first barrier layer BL1 is used, the first barrier layer BL1 has at least one of an Al composition ratio higher than that of the inter-well barrier layer BLI and a lower In composition ratio. For this reason, the lattice constant of the first barrier layer BL1 is smaller than the lattice constant of the inter-well barrier layer BLI. Thereby, the distortion of the light emitting unit 140 having a high In composition ratio and a large lattice strain is relaxed by the first barrier layer BL1 adjacent thereto. For this reason, even when a high In composition ratio is used, a good crystal can be obtained.

  In addition, when the band gap energy in the p-side barrier layer BLp is higher than the band gap energy of the inter-well barrier layer BLI, high-energy holes can be injected into the light emitting unit 140. In addition, the nonuniformity of the hole concentration distribution among the plurality of well layers 42 can be suppressed. Thereby, luminous efficiency can be further improved.

  Thus, according to the semiconductor element 10 according to the present embodiment, a highly efficient semiconductor element can be obtained.

In the present embodiment, by setting the thickness of the well layer 42 to 2 nm or more and 9 nm or less, high light emission efficiency and good spectral characteristics can be obtained.
For example, when Ga _0.93 In _0.07 N is used as the well layer 42, high light emission efficiency is obtained when the thickness of the well layer 42 is 4.5 nm or more and 9 nm or less.
According to the inventor's study, when the thickness of the well layer 42 is less than 4.5 nm, the emission intensity is remarkably low. When the thickness is greater than 9 nm, the emission spectrum is broadened and the emission intensity is remarkable. Will happen.

  When the thickness of the well layer 42 is smaller than 2 nm, the carrier spreads from the well layer 42 to the barrier layer (for example, at least one of the first barrier layer BL1, the inter-well barrier layer BLI, and the p-side barrier layer BLp). It is considered that the efficiency has been reduced. When the thickness of the well layer 42 exceeds 9 nm, the lattice irregularity between the GaN layer (for example, the second buffer layer 122, the n-type contact layer 132, the n-type confinement layer 131, etc.) and the well layer 42 increases. It is presumed that the strain applied to the crystal becomes excessive and the quality of the crystal decreases.

  In particular, when the number of the well layers 42 is increased when the thickness of the well layers 42 is 3 nm or more and 4.5 nm or less, the emission intensity can be made equal to or more than that in the case of the single well layer 42 configuration. . On the other hand, if the thickness is 7 nm or more, the limitation on the emission wavelength increases, and it is difficult to produce the well layer 42 having a wavelength longer than 450 nm. If the thickness of the well layer 42 is 7 nm or less, spectrum broadening does not substantially occur. For this reason, even when there are fluctuations in the shape and composition of the crystal, it is presumed that the crystallinity is not lowered due to strain in almost the entire region (for example, the entire region of the well layer 42).

  The light (emitted light) emitted from the light emitting unit 140 is not limited to this wavelength, and can be set to various values as in the above description regarding the embodiment. The light emitting unit 140 can have various configurations as described above with respect to the embodiment.

  If the number of wells is reduced in the semiconductor element 10 according to the present embodiment, the problem of carrier non-uniformity and reabsorption in the many well layers 42 as described above can be solved. Furthermore, when the configuration of the semiconductor element 10 according to the present embodiment was further examined, it was found that in addition to the above effects, there was further an effect of improving the light emission efficiency in terms of crystal quality. That is, in this embodiment, when the number of well layers 42 is small, each layer can be optimized so that the crystal quality of the well layers 42 is the highest. Conversely, in a structure in which a large number of well layers 42 are stacked, a large number of well-strained well layers 42 are stacked to grow a crystal. Therefore, strain accumulation occurs with the growth, and all the well layers 42 are grown under the same growth conditions. Crystal growth is difficult, and the crystal characteristics of each well layer 42 are different.

Hereinafter, an example of a method for manufacturing the semiconductor element 10 according to the present embodiment will be described.
For example, an AlN layer to be the first buffer layer 121 is formed with a thickness of about 2 μm on the substrate 110 having a surface of sapphire c-plane by using a metal organic chemical vapor deposition method. Specifically, the first AlN buffer layer 121a having a high carbon concentration (with a carbon concentration of, for example, 3 × 10 ¹⁸ cm ⁻³ or more and 5 × 10 ²⁰ cm ⁻³ or less) is formed with a thickness of 3 nm to 20 nm. A high-purity second AlN buffer layer 121b (carbon concentration of 1 × 10 ¹⁶ cm ⁻³ or more and 3 × 10 ¹⁸ cm ⁻³ or less) is formed thereon with a thickness of 2 μm. Thereafter, a non-doped GaN layer to be the second buffer layer 122 (lattice relaxation layer) is formed thereon with a thickness of 2 μm.

Thereafter, a Si-doped n-type GaN layer having an Si concentration of 5 × 10 ¹⁸ cm ⁻³ or more and 2 × 10 ¹⁹ cm ⁻³ or less to be the n-type contact layer 132 is formed with a thickness of 6 μm. Further, an Si-doped n-type GaN layer having a Si concentration of 2 × 10 ¹⁸ cm ⁻³ to be the n-type confinement layer 131 is formed with a thickness of 0.5 μm. The Si concentration in the n-type contact layer 132 is more preferably set to 1 × 10 ¹⁹ cm ⁻³ or more and 2 × 10 ¹⁹ cm ⁻³ or less.

  A second stacked body 220 is formed thereon. For example, 2.5 nm GaN layers and 1 nm GaInN layers are alternately stacked. The thickness of the GaN layer is equal to or greater than the thickness of the GaInN layer. The thickness of the GaN layer is preferably 7 nm or less. In particular, it is preferably 3 nm or less. The GaInN layer is thinner than the well layer 42. For example, Si is added to the GaN layer. The number of GaN layers and the number of GaInN layers in the second stacked body 220 are 12 or more and 20 or less. If it is less than 12, for example, the effect of improving the flatness of the surface is small. When it exceeds 30, dislocations are easily introduced into the crystal.

  A first stacked body 210 is formed on the second stacked body 220. For example, GaInN layers and AlGaInN layers are alternately stacked. The thickness of the GaInN layer is smaller than the thickness of the well layer 42. The thickness of the AlGaInN layer is 7 nm or less. In particular, it is preferably 3 nm or less. The number of AlGaInN layers and the number of GaInN layers in the first stacked body 210 are 16 or more and 40 or less. The total thickness of the plurality of GaInN layers is preferably thicker than 22.5 nm and thinner than 40 nm. The total thickness of the first stacked body 210 is more preferably thicker than 70 nm and thinner than 120 nm.

Furthermore, a Si-doped n-type Al _0.065 having a Si concentration of 13.5 nm and a thickness of 0.5 × 10 ¹⁹ cm ⁻³ or more and 2 × 10 ¹⁹ cm ⁻³ or less serving as the first barrier layer BL1 is formed _thereon. A Ga _0.93 In _0.005 N layer is formed. Further, a Ga _0.85 In _0.15 N layer having a thickness of 3.5 nm to be the first well layer 42 is formed thereon. On top of this, a Ga _0.99 In _0.01 N layer having a thickness of 3 nm is formed as an inter-well barrier layer BLI. A Ga _0.85 In _0.15 N layer having a thickness of 3.5 nm to be the second well layer 42 is formed thereon. Further, a GaN layer having a thickness of 6 nm is formed thereon as a barrier layer 41 (p-side barrier layer BLp). As a result, the light emitting section 140 having the two well layers 42 is formed.

Furthermore, an Mg-doped p-type Al _0.15 Ga _0.85 N layer (the Mg concentration on the light emitting part 140 side is 1.8 × 10 ¹⁹ cm ⁻³⁾ , which becomes the p-type confinement layer 151, The Mg concentration on the side opposite to 140 is 1 × 10 ¹⁹ cm ⁻³ ) with a thickness of 24 nm. Furthermore, on this, an Mg-doped p-type GaN layer to be the p-type contact layer 152 (the Mg concentration on the p-type confinement layer 151 side is 1 × 10 ¹⁹ cm ⁻³ , the side opposite to the p-type confinement layer 151) Mg concentration of 5 × 10 ¹⁹ cm ⁻³ or more and 9 × 10 ¹⁹ cm ⁻³ or less). The Al composition ratio in the p-type confinement layer 151 is, for example, not less than 0.13 and not more than 0.28. In particular, when it is 0.13 or more and 0.16 or less, good quality crystals are easily obtained. Further, since AlGaN having an excessively large band gap energy is not used, the element resistance can be lowered.

An electrode is provided on the semiconductor layer stack including the semiconductor layer, for example, by the method exemplified below.
That is, in the partial region of the semiconductor layer stack, the second layer 150 and the light emitting unit 140 are removed by dry etching using a mask until the n-type contact layer 132 is exposed on the surface. Then, a SiO ₂ layer is formed to a thickness of 400 nm on the entire semiconductor layer stack including the surface where the first layer 130 is exposed, using a thermal CVD (Chemical Vapor Deposition) apparatus. This SiO ₂ layer is omitted in FIG.

Then, in order to form the p-side electrode 160, a patterned resist for resist-off is formed on the semiconductor layer stack. Then, the SiO ₂ layer on the p-type contact layer 152 is removed by ammonium fluoride treatment. Then, in the region from which the SiO ₂ layer has been removed, for example, using a vacuum vapor deposition apparatus, a reflective conductive Ag serving as the p-side electrode 160 is formed with a thickness of 200 nm, and the nitrogen atmosphere at 350 ° C. is applied for 1 minute. Sinter processing is performed.

Then, in order to form the n-side electrode 170, a patterned resist for registry shift-off is formed on the semiconductor layer stack. The SiO ₂ layer on the exposed n-type contact layer 132 is removed by ammonium fluoride treatment. In the region where the SiO ₂ layer is removed, for example, a laminated film of Ti layer / Pt layer / Au layer is formed with a thickness of 500 nm, and the n-side electrode 170 is formed.

For the n-side electrode 170, for example, a highly reflective silver alloy (for example, containing about 1% Pd) can be used. In this case, in order to improve the ohmic contact, for example, the n-type contact layer 132 has a two-layer structure. Specifically, a high concentration layer having an Si concentration of 1.5 × 10 ¹⁹ cm ⁻³ or more and 3 × 10 ¹⁹ cm ⁻³ or less is grown as an electrode forming portion with a thickness of about 0.3 μm. Thereby, the reliability fall by precipitation of Si can be suppressed.

  Next, the back surface of the substrate 110 (the surface opposite to the first buffer layer 121) is polished, and the substrate 110 and the semiconductor layer stack are cut by cleaving or a diamond blade. Thereby, an individual LED element, that is, the semiconductor element 10 according to the present embodiment is manufactured. The width of the semiconductor element 10 is 400 μm, for example, and the thickness is 100 μm, for example.

  The peak wavelength of light emission in the semiconductor element 10 thus fabricated is 440 nm or more and 450 nm or less. The present embodiment is not limited to this, and light emission with a peak wavelength of 380 nm or more and 780 nm or less can be obtained by controlling at least one of the In composition ratio and the Al composition ratio of the well layer 42. In particular, good light emission can be obtained in the region of 380 nm to 560 nm. In the region of 385 nm or more and 460 nm or less, the degree of freedom in the configuration of various layers included in the semiconductor element 10 is increased. Thereby, a particularly efficient semiconductor element can be easily obtained.

  As a method for forming a semiconductor layer included in the semiconductor element 10 according to the present embodiment, for example, a metal organic chemical vapor deposition method, a molecular beam epitaxial growth method, or the like can be used. However, in the embodiment, the method for forming the semiconductor layer is arbitrary.

  For the substrate 110, for example, sapphire, SiC, GaN, GaAs, Si, or the like is used. However, in the embodiment, the substrate 110 is optional. The substrate 110 may be removed after the growth of the semiconductor layer.

  In the semiconductor element 10 according to the present embodiment, in order to obtain high-efficiency light emission by taking advantage of low-defect crystals, a configuration for improving the efficiency of the light-emitting unit 140 itself and an overflow of electrons from the light-emitting unit 140 are provided. A configuration that facilitates the use of a thick p-type confinement layer 151 having a high Al composition for suppression is applied.

Hereinafter, examples of each layer included in the semiconductor element 10 according to the present embodiment will be described.
The first AlN buffer layer 121a having a high carbon concentration serves to alleviate the difference in crystal type from the substrate 110, and particularly reduces screw dislocations. Further, the surface is planarized at the atomic level by the high purity second AlN buffer layer 121b. Therefore, crystal defects in the non-doped GaN buffer layer (second buffer layer 122) grown thereon are reduced. Therefore, the thickness of the high purity second AlN buffer layer 121b is preferably thicker than 1 μm. In order to prevent warping due to distortion, the thickness of the high purity second AlN buffer layer 121b is preferably 4 μm or less.

Note that AlN can be used for the first buffer layer 121 as described above, but the present embodiment is not limited to this. For example, Al _α2 Ga _1-α2 N (0.8 ≦ α2 ≦ 1). ) Can also be used. In this case, the warpage of the wafer can be compensated by adjusting the Al composition.

  The second buffer layer 122 (lattice relaxation layer) plays a role of defect reduction and strain relaxation by three-dimensional island growth on the first buffer layer 121. In order to planarize the growth surface, the average thickness of the second buffer layer 122 (lattice relaxation layer) is preferably 0.6 μm or more. From the viewpoint of reproducibility and warpage reduction, the thickness of the second buffer layer 122 (lattice relaxation layer) is preferably 0.8 μm or more and 2 μm or less.

  By employing these buffer layers, the dislocation density can be reduced to 1/10 or less as compared with a conventional low temperature growth buffer layer. As a result, crystal growth at a high growth temperature and a high V group / III raw material ratio, which is normally difficult to employ due to abnormal growth, becomes possible. As a result, the occurrence of point defects is suppressed, and high-concentration doping can be performed on the AlGaN layer having a high Al composition and the barrier layer 41 (such as the first barrier layer BL1).

  When Si is used as the substrate, the first AlN buffer layer 121a serves to alleviate the difference in crystal type from the substrate 110, and in particular, reduces screw dislocations. The high-purity second AlN buffer layer 121b is provided as necessary, and may be omitted in some cases. Crystal defects of the non-doped GaN buffer layer (second buffer layer 122) grown thereon are reduced. The thickness of the first AlN buffer layer 121a is preferably 6 nm or more, and particularly preferably 1 μm or more. In the thickness of 6 nm or more, the effect of protecting the substrate surface can be obtained. When the thickness is 1 μm or more, the effect of suppressing dislocation is increased. In order to prevent warping due to distortion, the thickness of the high purity second AlN buffer layer 121b is preferably 4 μm or less.

Even when Si is used as the substrate, AlN can be used for the first buffer layer 121 as described above. However, the present embodiment is not limited to this, and for example, Al _α2 Ga _1-α2 N (0.8 ≦ α2 ≦ 1) can be used. In this case, the warpage of the wafer can be compensated by adjusting the Al composition.

As already described, the first barrier layer BL1 is made of, for example, Si-doped quaternary mixed crystal AlGaInN (Al composition is 6% or more and 10% or less, and In composition ratio is 0.3% or more and 1.0% or less. )including. The other barrier layer 41 (inter-well barrier layer BLI and p-side barrier layer BLp) is, for example, a quaternary mixed crystal AlGaInN (Al composition of 6% to 10%, In composition ratio of 0.3% to 1.0%). %), And doping of Si is optional. The well layer 42 includes, for example, In _0.05 Ga _0.95 N (In composition ratio can be appropriately changed between 4% and 10%).

  In order to generate ultraviolet light with an emission wavelength of 380 nm to 400 nm with high efficiency, the Al composition in the first barrier layer BL1 is set to 6% or more in order to form a deep potential.

  The composition of the first barrier layer BL1 can be changed as appropriate. For example, AlGaInN having an Al composition ratio lower than 6% can be used for the first barrier layer BL1. GaInN having a lower In composition ratio than the well layer 42 can be used for the first barrier layer BL1.

  The composition of the barrier layer 41 other than the first barrier layer BL1 is also possible as appropriate. These barrier layers 41 can be made of AlGaInN or GaN having an Al composition ratio lower than 6%, as in the first barrier layer BL1. For these barrier layers 41, GaInN having a lower In composition ratio than the well layer 42 can be used.

  It is more desirable to use a crystal having a lower Al composition ratio or a higher In composition ratio than the first barrier layer BL1 for the barrier layers 41 other than the first barrier layer BL1. Unlike the first barrier layer BL1, the barrier layers 41 other than the first barrier layer BL1 are formed on the GaInN well layer 42. Therefore, the barrier layers 41 are made of a material having physical properties closer to those of the GaInN well layer 42. By using it, it is possible to grow a good quality crystal at a lower temperature. Thereby, deterioration of the GaInN layer mainly due to the influence of heat can be suppressed during crystal growth. Furthermore, since the difference in the band gap energy between the barrier layer 41 and the well layer 42 becomes small, the uniformity of carrier distribution can be increased, and the carrier utilization efficiency can be improved. Further, the barrier layer 41 and the well layer 42 Thus, the influence of the difference in band gap energy on the electrical resistance can be reduced, and the operating voltage of the semiconductor element can be reduced.

  The In composition ratio of the well layer 42 may be lower or higher than the above. For example, when the In composition of the well layer 42 is low, light emission at a wavelength closer to 365 nm is possible. For example, when light is emitted in a wavelength band of 430 nm or more and 400 nm or less, good light emission can be obtained when the In composition ratio of the well layer 42 is 0.2 or more and 0.3 or less. For example, when emitting light in the wavelength band of 440 nm or more and 460 nm, the In composition ratio of the well layer 42 may be 0.3 or more and 0.4 or less. For example, when emitting light in the wavelength band of 460 nm or more and 500 nm or less, the In composition ratio of the well layer 42 may be 0.3 or more and 0.5 or less. Furthermore, in order to obtain light emission at a longer wavelength, the In composition ratio of the well layer 42 may be appropriately increased within a range of 1 or less.

  The thickness of the p-side barrier layer BLp is set to 2 nm or more, for example. By making the thickness of the p-side barrier layer BLp 2 nm or more, for example, the phenomenon that the well layer 42 deteriorates while the growth temperature is raised to grow the second layer 150 after the growth of the p-side barrier layer BLp is suppressed. Is done. For example, if the thickness of the p-side barrier layer BLp is less than 3 nm, for example, the emission wavelength of the well layer 42 may change due to the influence of the p-type AlGaN layer. When the thickness of the p-side barrier layer BLp is set to 4.5 nm or more, the effect of controlling the characteristic change of the well layer 42 including the influence of impurity diffusion is great. When the thickness of the p-side barrier layer BLp is larger than the thickness of the well layer 42, the effect of reducing the influence of strain between the AlGaN layer and the well layer 42 is great. If the p-side barrier layer BLp is excessively thick, the device resistance may increase. On the other hand, when the p-side barrier layer BLp is excessively thick, for example, carriers overflowing the well layer 42 are accumulated and cause absorption. In order to reduce this influence, it is preferable to make the p-side barrier layer BLp thinner than the first barrier layer BL1. In a semiconductor device in which the thickness of the p-side barrier layer BLp was 9 nm or less, the device could be operated with a voltage increase within 10% of the operating voltage expected from the emission wavelength.

  The thickness of the first barrier layer BL1 is set to a value in the range of, for example, not less than 4.5 nm and not more than 30 nm. When the thickness of the first barrier layer BL1 is 4.5 nm or more, the original physical properties of the material are exhibited, and the effect of suppressing the overflow of holes can be obtained. In addition, when the thickness of the first barrier layer BL1 is 30 nm or less, high-quality crystal growth can be performed relatively easily. The first barrier layer BL1 is preferably thicker than the well layer 42. By setting the thickness of the first barrier layer BL1 to be larger than the thickness of the well layer 42, the control of the carrier supply to the well layer 42 becomes effective. In particular, the thickness of the first barrier layer BL1 is preferably at least twice the thickness of the well layer 42. By setting the thickness of the first barrier layer BL1 to at least twice the thickness of the well layer 42, carriers can be supplied to both sides of the first barrier layer BL1, and the accuracy of carrier supply to the well layer 42 is improved. To do. As described above, by adding Si to the first barrier layer BL1 at a high concentration, it is possible to reduce the influence of the piezoelectric field applied to the well layer 42 and obtain highly efficient light emission.

  When the Al composition ratio in the barrier layer 41 exceeds 10%, the crystal quality deteriorates. Further, by doping the barrier layer 41 with a small amount of In, for example, the crystal quality is improved. When the In composition ratio in the barrier layer 41 is 0.3% or more, the effect of improving the crystal quality is observed. If the In composition ratio exceeds 1.0%, the crystal quality deteriorates and the luminous efficiency decreases. However, when the thickness is small, the In composition ratio can be increased to 2%.

  For example, in this embodiment, when the thickness of the first barrier layer BL1 is 15 nm or more, the In composition ratio is limited to about 1%. However, when the first barrier layer BL1 is thinned to 7 nm, the In composition ratio is reduced. Even if 2%, the crystal does not deteriorate and strong light emission is obtained.

  An example of the growth technique of the first barrier layer BL1 will be described. It is difficult to grow a quaternary mixed crystal AlGaInN layer with good crystal quality, and when Si is doped at a high concentration, the crystal is likely to deteriorate. The inventors of the present application have succeeded in increasing the In composition ratio of the barrier layer BL1 made of AlGaInN without degrading the crystal quality by optimizing the configuration and growth conditions of the LED element.

  For example, as described above, in this embodiment, when the thickness of the first barrier layer BL1 exceeds 15 nm, the In composition ratio is limited to about 1%. However, when the first barrier layer BL1 is thinned to 7 nm, the In composition is reduced. Even if the ratio is 2%, the crystals are not deteriorated and strong light emission is obtained.

  When the In composition ratio can be increased, the steepness of the interface with the GaInN well layer 42 is improved, and the crystallinity of the well layer 42 is improved. As a result, Si is highly concentrated in the first barrier layer BL1 of AlGaInN. It becomes possible to dope.

  Further, by making the first barrier layer BL1 having a high Si concentration thinner, Si can be further doped with a higher concentration.

  The Al composition ratio of the first barrier layer BL1 can be set higher than the Al composition ratio of the p-side barrier layer BLp. As a result, the band gap energy of the first barrier layer BL1 is increased, the confinement effect for holes is increased, current leakage is reduced when the injection current is increased, and the light output can be increased. Since the p-type confinement layer 151 (p-type AlGaN layer) serves as a barrier against electrons, the Al composition ratio of the p-side barrier layer BLp is set sufficiently lower than that of the p-type confinement layer 151.

  For example, the Al composition ratio of the first barrier layer BL1 can be 8% or more, and the Al composition ratio of the p-side barrier layer BLp can be 0%. In this case, the first barrier layer BL1 may be grown at a high temperature, and the well layer 42 and the p-side barrier layer BLp may be grown at a temperature lower than that temperature.

  GaN or GaInN may be used for the inter-well barrier layer BLI. For example, the first barrier layer BL1 having a high Al composition ratio is grown at a high temperature. The well layer 42 and the inter-well barrier layer BLI are grown at a low temperature. The p-side barrier layer BLp having a low Al composition ratio is grown at a low temperature. Thereby, for example, the well layer 42 having a high In composition ratio can be grown with good characteristics. Note that the p-side barrier layer BLp may be grown by increasing the temperature after growing to a thickness that protects the surface of the well layer 42.

  For example, the first barrier layer BL1 may have a two-layer structure, and an AlGaN layer having a high Al composition ratio and an AlGaInN layer having a low Al composition ratio may be combined. For example, hole overflow can be suppressed by this AlGaN layer, and the characteristics of the crystal surface can be improved by the AlGaInN layer. As a result, the well layer 42 can be formed on the crystal surface with improved characteristics. In this case, the AlGaN layer and a part of the AlGaInN layer may be grown at a high temperature, and the rest of the AlGaInN layer may be grown at the same temperature as the well layer 42. By using such a method, a high-quality AlGaN crystal can be grown at a high temperature, and the well layer 42 can be grown at a temperature suitable for the well layer 42.

  Such a temperature change requires a lot of time and lowers the process efficiency. However, in a configuration in which the number of well layers 42 in the light emitting unit 140 is small (for example, a configuration having three or less well layers 42), the process efficiency is low. Reduction can be suppressed.

  For example, when the number of the well layers 42 is 3 (for example, the semiconductor element 10c), for example, the In composition ratio and the Ga composition ratio in the well layer 42 are, for example, 0.12 and 0.88, respectively. . Thereby, for example, blue light having a peak wavelength in a wavelength region of about 400 nm is emitted from the light emitting unit 140. Also in this semiconductor element, the band gap energy of the cladding layer is higher than the band gap energy of the well layer 42.

  FIG. 4 is a schematic cross-sectional view illustrating the configuration of another semiconductor element according to the first embodiment. As shown in FIG. 4, in the semiconductor element 11 (and the semiconductor elements 11 a to 11 c) according to the present embodiment, an intermediate layer 181 is provided between the first stacked body 210 and the second stacked body 220. .

  In the semiconductor element 11, for example, a GaN layer having a thickness of 2.5, which becomes the intermediate layer 181, is formed on the second stacked body 220 at 800 ° C. to 900 ° C. by metal organic chemical vapor deposition or MOCVD. It is formed. Then, the first stacked body 210 is formed on the intermediate layer 181.

  For the intermediate layer 181, at least one of GaN, GaInN, AlGaN, AlGaIn, and AlN can be used. The thickness of the intermediate layer 181 is desirably thinner than the thickness of the light emitting unit 140 (the entire thickness of the light emitting unit 140). When the intermediate layer 181 is thinner than the light emitting unit 140, the distortion effect of the first stacked body 210 can be transmitted not only to the light emitting unit 140 but also to the second stacked body 220, and the distortion effect of the second stacked body 220 can be transmitted. It receives strongly in the 1st laminated body 210, and interaction occurs effectively. The intermediate layer 181 is provided as necessary, and may be omitted in some cases.

  FIG. 5 is a schematic cross-sectional view illustrating the configuration of another semiconductor element according to the first embodiment. As shown in FIG. 5, in another semiconductor element 12 (and semiconductor elements 12 a to 12 c) according to this embodiment, a first metal layer 455 is provided between the conductive substrate 460 and the p-side electrode 160. A second metal layer 465 is provided between the conductive substrate 460 and the first metal layer 455.

  In the semiconductor element 12 (12a to 12c), a low impurity concentration semiconductor layer 135 is provided. An n-type contact layer 132 is disposed between the low impurity concentration semiconductor layer 135 and the second stacked body 220 (between the low impurity concentration semiconductor layer 135 and the light emitting portion 140), and the n-type contact layer 132 and the second stacked body. The n-type confinement layer 131 is disposed between the n-type confinement layer 131 and 220.

  The impurity concentration in the low impurity concentration semiconductor layer 135 is lower than the impurity concentration in the n-type contact layer 132. For the low impurity concentration semiconductor layer 135, for example, a non-doped GaN layer is used. As the low impurity concentration semiconductor layer 135, the second buffer layer 122 (lattice relaxation layer) already described can be employed.

  An opening 138 is provided in the low impurity concentration semiconductor layer 135. The opening 138 exposes a part of the n-type contact layer 132. The opening 138 is connected to the n-type contact layer 132 from the main surface 135 a of the low impurity concentration semiconductor layer 135 on the side opposite to the n-type contact layer 132. That is, the bottom of the opening 138 is connected to the n-type contact layer 132.

  An n-side electrode 170 is provided so as to cover the n-type contact layer 132 exposed in the opening 138 and a part of the low impurity concentration semiconductor layer 135.

  A rough surface portion 137 having unevenness 137p is provided on the main surface 135a of the portion of the low impurity concentration semiconductor layer 135 that is not covered with the n-side electrode 170.

  The semiconductor element 12 (12a to 12c) is manufactured by the following method, for example. For example, on the substrate 110 made of sapphire, the first buffer layer 121, the second buffer layer 122 (which becomes the low impurity concentration semiconductor layer 135), the n-type contact layer 132, the n-type confinement layer 131, the second stacked body 220. The first stacked body 210, the light emitting unit 140, the p-type confinement layer 151, and the p-type contact layer 152 are formed to form the crystal stacked body 180.

  A p-side electrode 160 is formed on the p-type contact layer 152 of the crystal stack 180. Then, the crystal stack 180 and the conductive substrate 460 are bonded, and the substrate 110 and the first buffer layer 121 are removed. Further, the n-side electrode 170 is formed on the exposed crystal layer (n-type contact layer 132). A rough surface portion 137 (that is, unevenness 137p) is formed in the low impurity concentration semiconductor layer 135. Thereby, the semiconductor element 12 is obtained.

  Also in this case, the recess 210d is provided on the surface 210a on the light emitting unit 140 side of the first stacked body 210, and a part of the light emitting unit 140 is embedded in at least a part of the recess 210d. Thereby, a highly efficient semiconductor element is provided. For example, a part of the second layer 150 is disposed on the part of the light emitting unit 140 embedded in at least a part of the recess 210d. Furthermore, a part of the second layer 150 may be embedded in at least a part of the recess 210d (residual space).

  In the semiconductor element 12, the size of the unevenness 137p is set to be larger than the wavelength of the emitted light emitted from the light emitting unit 140, for example. Specifically, the size of the unevenness 137p is set to be larger than the wavelength of the emitted light emitted from the light emitting unit 140 in the low impurity concentration semiconductor layer 135, for example. Thereby, in the rough surface portion 137 provided with the unevenness 137p, the light path is changed, the light extraction efficiency is improved, and a further highly efficient semiconductor element is obtained.

  FIG. 6 is a schematic cross-sectional view illustrating the configuration of another semiconductor element according to the first embodiment. As shown in FIG. 6, in another semiconductor element 13 (and semiconductor elements 13 a to 13 c) according to the present embodiment, the first stacked body 210 and the second stacked body in the semiconductor element 12 (and semiconductor elements 13 a to 13 c). An intermediate layer 181 is provided between the stacked body 220. This configuration also provides a highly efficient semiconductor element.

(Second Embodiment)
FIG. 7 is a schematic cross-sectional view illustrating the configuration of the wafer according to the second embodiment.
As shown in FIG. 7, the wafer 60 (wafers 60 a to 60 c) according to the present embodiment includes a substrate 110, a first layer 130, a first stacked body 210, a light emitting unit 140, a second layer, including.

  The first layer 130 is provided on the substrate 110. The first layer 130 includes a nitride semiconductor and is n-type. The first stacked body 210 is provided on the first layer 130. The first stacked body 210 includes a plurality of third layers 203 including AlGaInN, and a plurality of fourth layers including GaInN stacked alternately with the plurality of third layers 204.

  The light emitting unit 140 is provided on the first stacked body 210. The light emitting unit 140 includes a plurality of barrier layers 41 and a well layer 42 provided between the plurality of barrier layers 41. The second layer 150 is provided on the light emitting unit 140. The second layer 150 includes a nitride semiconductor and is p-type.

The first stacked body 210 has a recess 210d provided on the surface 210a of the first stacked body 210 on the light emitting unit 140 side. A part of the light emitting unit 140 is embedded in at least a part of the recess 210d (see FIG. 3). For example, a part of the second layer 150 is disposed on the part of the light emitting unit 140 embedded in at least a part of the recess 210d. Furthermore, a part of the second layer 150 may be embedded in at least a part of the recess 210d (residual space).
Thereby, a highly efficient wafer can be provided.

  As described with reference to FIG. 3, also in the wafer 60 (60 a to 60 c), the recess 210 d does not penetrate the first stacked body 210. Dislocations 510 penetrating the first layer 130, the first stacked body 210, the light emitting unit 140, and the second layer 150 are formed. The side surface 210s of the recess 210d surrounds the dislocation 510.

  As illustrated in FIG. 7, the wafer 60 (60 a to 60 c) further includes a second stacked body 220. The second stacked body 220 is provided between the first layer 130 and the first stacked body 210. The second stacked body 220 includes a plurality of fifth layers 205 and a plurality of sixth layers 206. The plurality of fifth layers 205 have a composition different from the composition of the third layer 203 and include a nitride semiconductor. The plurality of sixth layers 206 are alternately stacked with the plurality of fifth layers 205. Each of the sixth layers 206 is thinner than the well layer 42 and contains GaInN. The fifth layer 205 includes, for example, GaN, and each of the plurality of fifth layers 205 is thinner than each of the plurality of barrier layers 41.

  Each thickness of the fourth layer 204 of the first stacked body 210 is smaller than the thickness of the well layer 42. Also in this case, the wafer 60 (60a to 60c) can further include an intermediate layer 181. The intermediate layer 181 is provided between the first stacked body 210 and the second stacked body 220. The intermediate layer 181 is thinner than the light emitting unit 140.

  In the wafer 60 (60a to 60c), the well layer 42 includes, for example, at least one of GaInN and AlGaInN. Of the plurality of barrier layers 41, the first barrier layer BL1 closest to the first stacked body 210 includes AlGaInN.

  The wafer 60 (60a to 60c) includes a first buffer layer 121 provided between the substrate 110 and the first layer 130, and a second buffer provided between the first buffer layer 121 and the first layer 130. Layer 122. The first buffer layer 121 includes a first AlN buffer layer 121a provided between the substrate 110 and the second buffer layer 122, and a second AlN buffer provided between the first AlN buffer layer 121b and the second buffer layer 122. Layer 121b.

(Third embodiment)
FIG. 8 is a flowchart illustrating the method for manufacturing the semiconductor element according to the third embodiment.
As shown in FIG. 8, in the method for manufacturing a wafer according to the present embodiment, an n-type first layer 130 containing a nitride semiconductor is formed on a substrate 110 (step S <b> 102). If necessary, a buffer layer (for example, the first buffer layer 121 and the second buffer layer 122 described above) is formed before step S102 (step S101).

  Then, a plurality of third layers 203 containing AlGaInN and a plurality of fourth layers 204 containing GaInN are alternately stacked on the first layer 130 to form the first stacked body 210 (step S104). . If necessary, before step S104, a fifth layer 205 including a nitride semiconductor having a composition different from the composition of the third layer 203 on the first layer 130, and the thickness of each well layer 42 A second stacked body 220 is formed by alternately stacking a plurality of sixth layers 206 containing GaInN thinner than the thickness (step S103).

  Then, the light emitting unit 140 including the plurality of barrier layers 41 and the well layer 42 provided between the plurality of barrier layers 41 is formed on the first stacked body 210 (step S105). Further, the p-type second layer 150 including a nitride semiconductor is formed on the light emitting unit 140 (step S106). Furthermore, if necessary, after the formation of the second layer 150, the upper surface of the second layer 150 is bonded to a bonding substrate (for example, a conductive substrate), and then the substrate 110 is removed (step S107).

The first stacked body 210 has a recess 210d provided on the light emitting section 140 side surface of the first stacked body 210, and the light emitting section 140 is formed on at least a part of the recessed section 210d. Including embedding part of. The formation of the second layer 150 includes embedding a part of the second layer 150 in at least a part of the remaining space of the recess 210d.
Thereby, a highly efficient semiconductor element can be manufactured.

  Moreover, a highly efficient wafer can be manufactured by implementing said step S101-S106.

(Fourth embodiment)
The semiconductor element according to the present embodiment includes a semiconductor device such as a semiconductor light emitting element, a semiconductor light receiving element, and an electronic device. Hereinafter, an example in which the embodiment is applied to a semiconductor light emitting element will be described.

FIG. 9 is a schematic cross-sectional view illustrating the configuration of the semiconductor element according to the fourth embodiment.
As illustrated in FIG. 9, the semiconductor element 14 according to the present embodiment includes a first layer 130, a second layer 150, a light emitting unit 140 (functional unit), a first stacked body 210, and a second stacked body. 220. The configurations (including materials) described in regard to the first to third embodiments may be applied to the first layer 130, the second layer 150, the light emitting unit 140, the first stacked body 210, and the second stacked body 220. Since it can, explanation is omitted. In this example, an intermediate layer 181 is provided between the first stacked body 210 and the second stacked body 220.

FIG. 10 is a graph illustrating characteristics of the semiconductor element according to the fourth embodiment.
FIG. 10 illustrates characteristics relating to the concentration of In in the semiconductor element 14. This figure shows an example of the SIMS analysis result of the semiconductor element 14. The horizontal axis of FIG. 10 is the position Dz (nm) in the depth direction. The vertical axis represents the secondary ion intensity I (In) for In (Counts / s: count / second).

  As shown in FIG. 10, the concentration of In in the second stacked body 220 is not constant. The average In composition in the portion of the second stacked body 220 on the first layer 130 side is higher than that of the portion of the second stacked body 220 on the first stacked body 210 side. The average In composition ratio in the second stacked body 220 gradually decreases as it approaches the first stacked body 210 from the first layer 130. Here, the average In composition ratio is an average In composition ratio in the fifth layer 205 and the sixth layer 206.

  As described above, the second stacked body 220 includes the first portion 220 a close to the first layer 130 and the second portion 220 b positioned between the first portion 220 a and the light emitting unit 140. The average In concentration (average In composition ratio) in the first portion 220a is higher than the average In concentration in the second portion 220b.

  On the other hand, the In average composition ratio in the first stacked body 210 is substantially constant. Thus, the amount of change along the Z-axis direction of the In average composition ratio in the first stacked body 210 is smaller than the amount of change along the Z-axis direction of the In average composition ratio in the second stacked body 220.

  The reason why the distribution of the In composition ratio as described above is formed in the second stacked body 220 is considered to be due to the influence of the dislocations 510.

  In the second stacked body 220, a GaN layer and a GaInN layer are provided. The second stacked body 220 has, for example, a superlattice structure. Since the lattice mismatch between the GaN layer and the GaInN layer is large and the growth rate around the dislocation 510 is slow, a dent is formed around the dislocation 510. At the center of the recess, for example, a dislocation 510 exists. At this time, strain is applied by the superlattice structure being laminated, and the dislocation 510 is gradually bent, and the dislocation 510 is generally along the vertical direction (Z-axis direction) with respect to the layer.

  In the semiconductor element 14, the same recess illustrated in the schematic diagram illustrated in FIG. 3 is formed. The opening of the dent depends on the orientation of the dislocation 510. In the portion where the dislocation 510 is oblique, the opening of the recess is wide. As the dislocation 510 becomes vertical (parallel to the Z-axis direction), the opening of the recess becomes smaller. The slope (side surface) of the dent is formed with an energy stable surface. Along with this, it is considered that the growth rate decreases, the In incorporation efficiency decreases, and the symmetry of the side surface of the dent improves. That is, In is easy to be taken in a portion where the recessed opening is wide.

  For this reason, the In average composition ratio in the 1st part 220a (part by the side of the 1st layer 130) of the 2nd laminated body 220 is high. Then, it is considered that the second stacked body 220 grows, the opening becomes narrower, the In average composition ratio gradually decreases, and a constant In average composition ratio is obtained when the shape of the recess 210d is stabilized.

  As shown in FIG. 9, in the semiconductor element 14, the first metal layer 455 is provided between the conductive substrate 460 and the p-side electrode 160, and between the conductive substrate 460 and the first metal layer 455. A second metal layer 465 is provided. An intermediate layer 181 is provided between the first stacked body 210 and the second stacked body 220.

  In the semiconductor element 14, a low impurity concentration semiconductor layer 135 is provided. An n-type contact layer 132 is disposed between the low impurity concentration semiconductor layer 135 and the second stacked body 220, and an n-type confinement layer 131 is disposed between the n-type contact layer 132 and the second stacked body 220. .

  The impurity concentration in the low impurity concentration semiconductor layer 135 is lower than the impurity concentration in the n-type contact layer 132. As the low impurity concentration semiconductor layer 135, a non-doped GaN layer is used. The already described second buffer layer 122 (lattice relaxation layer) is employed for the low impurity concentration semiconductor layer 135.

  An opening 138 is provided in the low impurity concentration semiconductor layer 135. The opening 138 exposes a part of the n-type contact layer 132. The opening 138 is connected to the n-type contact layer 132 from the main surface 135 a of the low impurity concentration semiconductor layer 135 on the side opposite to the n-type contact layer 132. That is, the bottom of the opening 138 is connected to the n-type contact layer 132.

  An n-side electrode 170 is provided so as to cover the n-type contact layer 132 exposed in the opening 138 and a part of the low impurity concentration semiconductor layer 135.

  A rough surface portion 137 having unevenness 137p is provided on the main surface 135a of the portion of the low impurity concentration semiconductor layer 135 that is not covered with the n-side electrode 170.

The inventor of the present application produced the semiconductor element 14 according to the present embodiment and evaluated its characteristics. The semiconductor element 14 was produced as follows.
On the sapphire substrate (not shown), an AlN layer having a thickness of 2 μm and serving as the first buffer layer 121 was formed at about 1300 ° C. by MOCVD. A 2 μm-thick GaN layer to be the second buffer 122 was formed thereon at about 1200 ° C. by MOCVD.

On top of that, the thickness is 4 μm and the Si concentration is 0.1. A GaN layer (n-type contact layer 132) of ² × 10 ¹⁹ cm ^{−3 to} 1.5 × 10 ¹⁹ cm ⁻³ was formed at 1050 ° C. to 1200 ° C. by MOCVD. Further, an n-GaN layer (n-type confinement layer 131) having a thickness of 0.5 μm and a Si concentration of 2 × 10 ¹⁷ cm ^{−3 to} 5 × 10 ¹⁸ cm ⁻³ is formed at 1050 ° C. to 1200 ° by MOCVD. Formed at ° C.

On top of this, a GaN layer (fifth layer 205) having a thickness of 2.5 nm and 8 × 10 ¹⁸ cm ⁻³ added Si, and a Ga _0.93 In _0.07 N first layer having a thickness of 1 nm. Six layers 206 and 12 to 20 layers were alternately formed at 800 ° C. to 900 ° C. by MOCVD. Thereby, the second stacked body 220 is formed.

  A GaN layer (intermediate layer 181) having a thickness of 2.5 was formed thereon at 800 ° C. to 900 ° C. by MOCVD.

An Al _0.7 Ga _0.925 In _0.005 N layer (third layer 203) having a thickness of 2 nm and doped with 8 × 10 ¹⁸ cm ⁻³ of Si, and a Ga layer _having a thickness of 1 nm are formed thereon. _0.93 In _0.07 N layers (fourth layer 204) and 26 to 34 layers were alternately formed at 800 to 900 ° C. by MOCVD. Thereby, the 1st laminated body 210 is formed.

On top of this, an Al _0.07 Ga _0.925 In _0.005 N layer (first barrier) _having a thickness of 13.5 nm and added with Si of 4 × 10 ¹⁸ cm ^{−3 to} 16 × 10 ¹⁸ cm ^−3. Layer BL1: barrier layer 41) was formed at about 800 ° C. to 900 ° C. by MOCVD. A Ga _0.93 In _0.07 N layer (well layer 42) having a thickness of 7 nm was formed thereon at about 800 to 900 ° C. by MOCVD. On this, an Al _0.07 Ga _0.925 In _0.005 N layer (second barrier layer BL2: barrier layer 41) having a thickness of 4 nm to 12 nm was formed at about 800 to 900 ° C. by MOCVD.

On this, an Mg-added p-Al _0.2 Ga _0.8 N layer (p-type confinement layer 151) having a thickness of 24 nm was formed at about 950 ° C. to 1100 ° C. by MOCVD.

  A p-GaN layer (p-type contact layer 15250) having a thickness of 0.3 μm was formed thereon at 950 ° C. to 1100 ° C. by MOCVD. A p-side electrode 160 was formed thereon. Further, a first metal layer 455 was formed thereon.

  A conductive substrate 460 having a second metal layer 465 was prepared, and the first metal layer 455 and the second metal layer 465 were bonded (bonded). Thereafter, the sapphire substrate was removed by a laser lift-off method, and an uneven structure was formed by etching on the exposed surface of the n-GaN layer (low impurity concentration semiconductor layer 135). In addition, the n-side electrode 170 having a predetermined shape was formed by vapor deposition and patterning using lithography. The pattern when the n-side electrode 170 is viewed along the Z-axis has a cross shape. The cross shape includes a peripheral portion along the peripheral edge of the n-type contact layer 132, a first extending portion extending along the Y-axis through the central portion of the n-type contact layer 132 in the X-axis, and the n-type contact layer 132. And a second extending portion extending along the X axis through the central portion of the Y axis.

  Thereafter, the semiconductor element 14 is obtained by dividing the processed body into individual elements. The length along the X axis of the semiconductor element 14 is about 1 mm (millimeter), and the length along the Y axis is about 1 mm.

  In the semiconductor element 14, the intermediate layer 181 can be omitted. For the intermediate layer 181, at least one of GaN, GaInN, AlGaN, AlGaIn, and AlN can be used. The thickness of the intermediate layer 181 is desirably thinner than the thickness of the light emitting unit 140. When the intermediate layer 181 is thinner than the light emitting unit 140, the distortion effect of the first stacked body 210 can be transmitted not only to the light emitting unit 140 but also to the second stacked body 220, and the distortion effect of the second stacked body 220 can be transmitted. It receives strongly in the 1st laminated body 210, and interaction occurs effectively.

  In the semiconductor element 14 according to the present embodiment, the light emission efficiency was substantially constant up to a drive current of 350 mA, and an output of 0.6 W was obtained at the drive current.

  In a semiconductor element having the same configuration as that of the present embodiment, the average In composition in the second stacked body 220 is continuously reduced to form a constant composition region, or the average In composition is also in the first stacked body 210. When the ratio was not constant, the luminous efficiency was lowered when the injection current density was increased, and the light output at a driving current of 350 mA was 0.55 W or less.

  In the present embodiment, the crystal having the In composition distribution described above (second stacked body 220) can be manufactured by adjusting the superlattice structure of GaN and GaInN. Mainly the thickness and period are adjusted. For example, the thickness of the GaN layer is 2.5 nm, for example. The thickness of the GnInN layer is 1 nm, for example, and the In composition ratio is about 0.5%. The period (the number of GaN layers and the number of GaInN layers) is, for example, 12 to 27. For example, the period is more preferably 16-20.

  The second stacked body 220 having the average In composition profile as described above is grown, and the first stacked body 210 having the average In composition profile as described above is grown thereon, whereby a highly efficient semiconductor issue element can be formed. This is presumed to be due to the following mechanism.

  A dent is generated around the dislocation 510, the dislocation 510 is oriented in a substantially vertical direction, and the shape is maintained, and the first stacked body 210 (AlGaInN layer and GaInN layer) and the light emitting unit 140 are taken over, It is thought that it extends toward the surface while maintaining a substantially vertical direction. The shape of the recess (recessed portion 210d) is open on the surface side (the side from the first layer 130 toward the second layer 150) and is approximately axisymmetric (cone, triangular pyramid, hexagonal pyramid, etc.) with respect to the dislocation. It is estimated that

  A part of the light emitting unit 140 is embedded in the recess 210 d formed in the first stacked body 210. For example, it can be observed from the cross-sectional TEM image that the well layer 42 (InGaN layer) and the barrier layer 41 (AlGaInN layer) are stacked symmetrically with respect to the dislocation 510 passing through the central axis of the recess 210d.

  The thickness of the first stacked body 210 is thicker than the depth of the recess 210 d formed in the first stacked body 210. If the recess 210d penetrates the first stacked body 210, for example, it may cause carrier leakage. In order to suppress this, the configuration (mainly thickness and period) of the first stacked body 210 is appropriately set. For example, the thickness of the AlGaInN layer is 2 nm, for example. The thickness of the GaInN layer is 1 nm, for example. The period (the number of AlGaInN layers and the number of GaInN layers) is, for example, 30.

  When the direction of the dislocation 510 penetrating the light emitting portion 140 becomes vertical, the ratio of the area of the portion disturbed by the dislocation 510 to the area of the light emitting portion 140 decreases. Thereby, luminous efficiency improves. Further, since the dislocations 510 are vertical, it becomes difficult for current to flow, and current leakage is suppressed. Furthermore, since the In composition ratio around the dislocation 510 decreases, the band gap energy around the dislocation 510 increases, the lateral current toward the dislocation 510 is suppressed, and the leakage current decreases. In addition, since the relative area ratio of the region where the crystal around the dislocation 510 is disturbed is small, the quality of the second layer 150 grown on the light emitting unit 140 is improved. Moreover, the yield in manufacturing is improved.

  When forming a laminate, if the growth rate is slow, the efficiency of incorporation of Al (strongly bound to nitrogen) into the crystal surface is improved, and In (weakly bound to nitrogen) and Ga (bound to nitrogen) It is higher than the efficiency of incorporation into the medium surface). Therefore, by using the first stacked body 210 using the AlGaIn layer and the GaInN layer, a region with a high Al composition is easily formed around the dislocation 510. Thereby, the inflow of current to the dislocation 510 is suppressed, and the leakage current is suppressed.

  In a layer having a high Al composition ratio, the direction of dislocations 510 is likely to change from vertical. It is considered that the shape of the recess 210d is stabilized by supplying In, which has a weak bond with nitrogen and facilitates the movement of atoms on the crystal surface, during the formation of the AlGaInN layer.

  In addition, by repeatedly forming the thin AlGaInN layer and the thin GaInN layer, it is easy to take a high thermodynamically stable state before the shape of the recess 210d changes greatly during the formation of the AlGaInN layer. A GaInN layer is formed. Thereby, it is thought that the shape of the recess 210d is stable.

  Thus, by providing the first stacked body 210 in which a plurality of AlGaN layers and a plurality of GaInN layers are alternately stacked, the dislocation 510 is formed vertically in the light emitting unit 140. This improves efficiency.

  In the semiconductor element 14 (and 14a to 14c) according to the present embodiment, the light emitting unit 140 can have various configurations, compositions, and light emission wavelengths described with respect to the other embodiments.

(Fifth embodiment)
FIG. 11 is a schematic cross-sectional view illustrating the configuration of a wafer according to the fifth embodiment.
As illustrated in FIG. 11, the wafer 64 (and 64a to 64c) according to the present embodiment includes the first layer 130, the second layer 150, the light emitting unit 140, the first stacked body 210, and the second stacked layer. And body 220. The first layer 130 includes a nitride semiconductor and is n-type. The first layer 150 includes a nitride semiconductor and is p-type. The light emitting unit 140 is provided between the first layer 130 and the second layer 150. The light emitting unit 140 includes a barrier layer 41 and a well layer 42. For example, a plurality of barrier layers 41 are provided, and the well layer 42 is provided between the plurality of barrier layers 41.

  The first stacked body 210 is provided between the first layer 130 and the light emitting unit 140. The first stacked body 210 includes a plurality of third layers 203 including AlGaInN and a plurality of fourth layers 204 including GaInN stacked alternately with the plurality of third layers.

  The second stacked body 220 is provided between the first layer 130 and the first stacked body 210. The second stacked body 220 includes a plurality of fifth layers 205 including a nitride semiconductor having a composition different from the composition of the third layer 203 and a plurality of sixth layers including GaInN stacked alternately with the plurality of fifth layers 205. Layer 206.

As illustrated in FIG. 10, the second stacked body 220 includes a first portion 220 a close to the first layer 130 and a second portion 220 b positioned between the first portion 220 a and the light emitting unit 140. The In average composition ratio in the first portion 220a is higher than the In average composition ratio in the second portion 220b.
Thereby, a highly efficient wafer can be provided.

(Sixth embodiment)
FIG. 12 is a flowchart illustrating the method for manufacturing the semiconductor element according to the sixth embodiment.
As shown in FIG. 12, the method for manufacturing a semiconductor device according to the present embodiment determines crystal growth conditions (Step S <b> 210), and uses the determined crystal growth conditions, the second stacked body 220 and the first stacked body. 210, the light emitting unit 140, and the second layer 150 are formed (step S220).

  For example, on the n-type first layer 130 containing a nitride semiconductor, a plurality of fifth layers 205 containing a nitride semiconductor and a plurality of sixth layers 206 containing GaInN are alternately stacked to form a second layer. A stacked body 220 is formed, and a plurality of third layers 203 having a composition different from that of the fifth layer 205 and including AlGaInN, and a plurality of fourth layers 204 including GaInN are formed on the second stacked body 220. The first stacked body 210 is formed by alternately stacking (step S211).

Then, the composition analysis of In in the second stacked body 220 is performed (step S212).
The second stacked body 220 includes a first portion 220a that is closer to the first layer 130 and a second portion 220b that is farther from the first layer 130 than the first portion 220a. Based on the result of the composition analysis, it is determined whether the In composition profile of the second stacked body 220 is a condition in which the In average composition ratio in the first portion 220a is higher than the In average composition ratio in the second portion 220b (step) S213). If the result of this determination is NO, the conditions (conditions including at least one of crystal growth conditions and wafer structures) are changed (step S214). Then, the process returns to step S211. Repeat until the result of the determination is YES.

  On the other hand, if the result of composition analysis indicates YES (when the In composition profile of the second stacked body 220 is such that the In average composition ratio in the first portion 220a is higher than the In average composition ratio in the second portion 220b). ), Crystal growth conditions are determined (step S210). As described above, the In average composition ratio in the first portion 220a of the second stacked body 220 near the first layer 130 is farther from the first layer 130 than the first portion 220a of the second stacked body 220. The crystal growth conditions that are higher than the In average composition ratio in the two portions 220b are determined.

Then, the second stacked body 220 and the first stacked body 210 are formed using the determined crystal growth conditions, and the light emitting unit 140 including the barrier layer 41 and the well layer 42 is formed on the first stacked body 210. The p-type second layer 150 including a nitride semiconductor is formed on the light emitting unit 140 (step S220). Thereby, a semiconductor element is formed.
According to this manufacturing method, a highly efficient method for manufacturing a semiconductor device can be provided.

  For example, an n-type first layer 130 including a nitride semiconductor is formed on the substrate 110, the second stacked body 220 is formed on the first layer 130, and the first stacked on the second stacked body 220. A stacked body 210 is formed.

  Then, the light emitting unit 140 including the barrier layer 41 and the well layer 42 is formed on the first stacked body 210. A p-type second layer 150 including a nitride semiconductor is formed on the light emitting unit 140.

  Next, for example, the In composition profile of the first stacked body 210 and the In composition profile of the second stacked body 220 are measured by SIMS.

  The second stacked body 220 includes a region where the average In composition ratio is high on the first layer 130 side and decreases on the functional region side (light emitting unit 140 side), and a region where the average In composition is substantially constant. When a predetermined average In composition profile having a substantially constant average In composition is obtained in the laminate 210, the crystal growth conditions and the wafer structure are determined. If the target profile has not been obtained, the crystal growth conditions are corrected, and the processes after step S211 are performed again. Crystal growth is performed using the crystal growth conditions and wafer structure determined by obtaining a predetermined average In composition profile. Thereby, a wafer capable of producing a high-power semiconductor element can be produced. Furthermore, an elementization process is performed using this wafer, and a semiconductor element is produced. Thereby, a highly efficient semiconductor element can be manufactured.

  The high efficiency of the semiconductor device according to the embodiment described above is because, for example, the periphery of the dislocation is buried by a laminated structure of AlGInN and GaInN having a larger band gap than the flat portion, and an active region and current are injected therein. This is considered to be because the region is effectively separated from the dislocation periphery.

  In one embodiment, for example, a first stacked body 210 in which a plurality of layers containing AlGaInN and a plurality of layers containing GaInN are alternately stacked is formed on a GaN layer. On top of that, a functional region (functional part) is formed, and a structure in which current injection or current drawing occurs in the functional region is provided. A recess is formed on the surface of the first laminate 210. For example, a structure is provided in which the thickness of the functional region or the peripheral portion of the recess is reduced at the recess.

  For example, the semiconductor element according to the embodiment includes a first layer including a nitride semiconductor, a first stacked body provided on the first layer, a plurality of third layers including AlGaInN, and the plurality of layers. A first stacked body including a plurality of fourth layers alternately stacked with the third layer and including GaInN, and a functional unit including a nitride semiconductor provided on the first stacked body. The first laminated body has a concave portion provided on the surface of the first laminated body on the functional unit side, and a part of the light emitting unit is embedded in at least a part of the concave portion.

  In one embodiment, for example, a second stacked body in which a plurality of layers having a composition different from that of AlGaInN and including a nitride semiconductor and a plurality of layers including GaInN are alternately stacked on a GaN layer. 220 is formed. A first stacked body 210 in which a plurality of layers containing AlGaInN and a plurality of layers containing GaInN are alternately stacked is formed thereon. On top of that, a functional region (functional part) is formed. A structure is provided in which current injection or current drawing occurs in the functional region. The second stacked body 220 has a region where the average In composition ratio is high on the GaN layer side and decreases on the functional region side, and a region where the average In composition is substantially constant. A substantially constant structure is provided.

  For example, the semiconductor element according to the embodiment includes a first layer including a nitride semiconductor, a first stacked body provided on the first layer, a plurality of third layers including AlGaInN, and the plurality of layers. And a second stacked body provided between the first layer and the first stacked body, the first stacked body including a plurality of fourth layers including GaInN alternately stacked with the third layer. A second layer including a plurality of fifth layers including a nitride semiconductor having a composition different from the composition of the third layer, and a plurality of sixth layers including GaInN stacked alternately with the plurality of fifth layers. And a functional unit that is provided on the first stacked body and includes a nitride semiconductor. The second stacked body includes a first portion close to the first layer, and a second portion located between the first portion and the functional portion, and an In average composition ratio in the first portion. Is higher than the In average composition ratio in the second portion.

  The embodiment can be applied to all semiconductor devices and wafers having such a configuration.

  For example, various optical semiconductor elements such as a semiconductor laser element and a light receiving element, current or voltage control semiconductor elements such as a diode, a transistor, an electric field transistor, and a thyristor, and combinations thereof are examples to which the embodiment can be applied.

  According to the embodiment, a highly efficient semiconductor device, a wafer, a semiconductor device manufacturing method, and a wafer manufacturing method can be provided.

In this specification, “nitride semiconductor” refers to B _x In _y Al _z Ga _1-xyz N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z ≦ 1) It is assumed that the semiconductors having all the compositions in which the composition ratios x, y, and z are changed within the respective ranges in the following chemical formula are included. Furthermore, in the above chemical formula, those further containing a group V element other than N (nitrogen), those further containing various elements added for controlling various physical properties such as conductivity type, and unintentionally Those further including various elements included are also included in the “nitride semiconductor”.

  In the present specification, “vertical” and “parallel” include not only strictly vertical and strictly parallel, but also include, for example, variations in the manufacturing process, and may be substantially vertical and substantially parallel. is good.

  The embodiments of the present invention have been described above with reference to specific examples. However, embodiments of the present invention are not limited to these specific examples. For example, the specific configuration of each element such as a semiconductor layer, a light emitting portion, a well layer, a barrier layer, a stacked body, an electrode, a substrate, a buffer layer, and a concave portion included in the semiconductor element is appropriately selected by those skilled in the art from a known range. The present invention is included in the scope of the present invention as long as the present invention can be carried out in the same manner and the same effects can be obtained.

  Moreover, what combined any two or more elements of each specific example in the technically possible range is also included in the scope of the present invention as long as the gist of the present invention is included.

  In addition, based on the semiconductor element, wafer, semiconductor element manufacturing method, and wafer manufacturing method described above as embodiments of the present invention, all semiconductor elements, wafers, and semiconductors that can be implemented with appropriate design modifications by those skilled in the art An element manufacturing method and a wafer manufacturing method also belong to the scope of the present invention as long as they include the gist of the present invention.

  In addition, in the category of the idea of the present invention, those skilled in the art can conceive of various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the present invention. .

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  10, 10a to 10c, 11, 11a to 11c, 12, 12a to 12c, 13, 13a to 13c, 14, 14a to 14c ... semiconductor element, 41 ... barrier layer, 42 ... well layer, 60, 60a-60c, 64 64a to 64c ... wafer 110 ... substrate 121 ... first buffer layer 121a ... first AlN buffer layer 121b ... second AlN buffer layer 122 ... second buffer layer 130 ... first layer 131 ... n-type confinement Layer, 132 ... n-type contact layer, 135 ... low impurity concentration semiconductor layer, 135a ... main surface, 137 ... rough surface portion, 137p ... unevenness, 138 ... opening, 140 ... light emitting portion, 150 ... second layer, 151 ... p Type confinement layer, 152 ... p-type contact layer, 160 ... p-side electrode, 170 ... n-side electrode, 180 ... crystal laminate, 181 Intermediate layer 203-206 3rd layer-6th layer 210 ... 1st laminated body 210a ... surface 210b ... surface 210d ... recessed part 210e ... tip, 210s ... side surface 220 ... 2nd laminated body 220a ... first part, 220b ... second part, 455 ... first metal layer, 460 ... conductive substrate, 465 ... second metal layer, 510 ... dislocation, BL ... barrier layer, BL1 ... first barrier layer, BL2 ... first 2 barrier layers, BLI ... well barrier layer, BLi ... barrier layer, BLp ... p-side barrier layer, Dz ... position, WL ... well layer, WL1 ... first well layer, WLi ... well layer

The inventor of the present application has found that in the first laminate 210, the stacking speed around the dislocation 510 (threading dislocation) is reduced, and a concave structure (concave 210d) is formed. When the recess 210d is filled with, for example, AlGaN (for example, the first barrier layer BL1), the AlGaN layer and a region in which an AlGaIn N layer and a GaInN layer thinner than those formed on the flat portion are stacked. A recess 210d around the dislocation 510 is embedded.

When forming a laminate, if the growth rate is slow, the efficiency of incorporation of Al (strongly bound to nitrogen) into the crystal surface is improved, and In (weakly bound to nitrogen) and Ga (bound to nitrogen) It is higher than the efficiency of incorporation into the medium surface). Therefore, by using the first stacked body 210 using the AlGaIn N layer and the GaInN layer, a region with a high Al composition is easily formed around the dislocation 510. Thereby, the inflow of current to the dislocation 510 is suppressed, and the leakage current is suppressed.

The intermediate layer 181 may be used GaN, GaInN, AlGaN, the small of AlGaIn N and AlN. The thickness of the intermediate layer 181 is desirably thinner than the thickness of the light emitting unit 140 (the entire thickness of the light emitting unit 140). When the intermediate layer 181 is thinner than the light emitting unit 140, the distortion effect of the first stacked body 210 can be transmitted not only to the light emitting unit 140 but also to the second stacked body 220, and the distortion effect of the second stacked body 220 can be transmitted. It receives strongly in the 1st laminated body 210, and interaction occurs effectively. The intermediate layer 181 is provided as necessary, and may be omitted in some cases.

In the semiconductor element 14, the intermediate layer 181 can be omitted. The intermediate layer 181 may be used GaN, GaInN, AlGaN, at least one of AlGaIn N and AlN. The thickness of the intermediate layer 181 is desirably thinner than the thickness of the light emitting unit 140. When the intermediate layer 181 is thinner than the light emitting unit 140, the distortion effect of the first stacked body 210 can be transmitted not only to the light emitting unit 140 but also to the second stacked body 220, and the distortion effect of the second stacked body 220 can be transmitted. It receives strongly in the 1st laminated body 210, and interaction occurs effectively.

When forming a laminate, if the growth rate is slow, the efficiency of incorporation of Al (strongly bound to nitrogen) into the crystal surface is improved, and In (weakly bound to nitrogen) and Ga (bound to nitrogen) It is higher than the efficiency of incorporation into the medium surface). Therefore, by using the first stacked body 210 using the AlGaIn N layer and the GaInN layer, a region with a high Al composition is easily formed around the dislocation 510. Thereby, the inflow of current to the dislocation 510 is suppressed, and the leakage current is suppressed.

Claims (16)

An n-type first layer comprising a nitride semiconductor;
A p-type second layer comprising a nitride semiconductor;
A light emitting unit provided between the first layer and the second layer, the light emitting unit including a barrier layer and a well layer;
A first laminated body provided between the first layer and the light emitting unit,
A plurality of third layers comprising AlGaInN;
A plurality of fourth layers alternately stacked with the plurality of third layers and containing GaInN;
A first laminate including:
A second laminated body provided between the first layer and the first laminated body,
A plurality of fifth layers including a nitride semiconductor having a composition different from the composition of the third layer;
A plurality of sixth layers including GaInN stacked alternately with the plurality of fifth layers;
A second laminate including:
With
The first stacked body has a recess provided on a surface on the light emitting unit side of the first stacked body, and a part of the light emitting unit is embedded in at least a part of the recess. A part of the layer is disposed on the part of the light emitting part embedded in the at least part of the recess;
A dislocation penetrating the first laminate is formed, and a side surface of the recess surrounds the dislocation;
A semiconductor element in which a composition ratio of In in the vicinity of the dislocation in the first stacked body is lower than a composition ratio of In in a portion away from the dislocation in the first stacked body. The second stacked body includes a first portion close to the first layer, and a second portion located between the first portion and the light emitting unit,
The semiconductor element according to claim 1, wherein an In average composition ratio in the first portion is higher than an In average composition ratio in the second portion. The In average composition ratio in the first portion decreases from the first layer side toward the second layer side,
The semiconductor element according to claim 2, wherein a change amount of the In average composition ratio in the second portion is smaller than a change amount of the In average composition ratio in the first portion.   The amount of change in the In average composition ratio in the first stacked body along the direction from the first layer toward the second layer is greater than the amount of change in the In average composition ratio in the second stacked body along the direction. The semiconductor element according to claim 2 or 3, which is smaller.   5. The plurality of fifth layers include GaN, and each of the plurality of fifth layers has a thickness smaller than each of the plurality of barrier layers. Semiconductor element.   The semiconductor element according to claim 1, further comprising an intermediate layer that is provided between the first stacked body and the second stacked body and is thinner than the thickness of the light emitting unit.   The semiconductor element according to claim 1, wherein the part of the second layer is further embedded in the at least part of the recess.   The thickness of each said 4th layer is a semiconductor element as described in any one of Claims 1-7 thinner than the thickness of the said well layer.   The semiconductor element according to claim 1, wherein the recess does not penetrate the first stacked body.   The semiconductor element according to claim 1, wherein the dislocation further penetrates the first layer, the light emitting unit, and the second layer.   The semiconductor element according to claim 1, wherein the well layer includes at least one of GaInN and AlGaInN.   The semiconductor element according to claim 1, wherein the first barrier layer closest to the first stacked body among the plurality of barrier layers includes AlGaInN. A substrate,
An n-type first layer provided on the substrate and including a nitride semiconductor;
A first laminated body provided on the first layer,
A plurality of third layers comprising AlGaInN;
A plurality of fourth layers alternately stacked with the plurality of third layers and containing GaInN;
A first laminate including:
A light emitting unit provided on the first stacked body, the light emitting unit including a plurality of barrier layers and a well layer provided between the plurality of barrier layers;
A p-type second layer provided on the light emitting portion and including a nitride semiconductor;
A second laminated body provided between the first layer and the first laminated body,
A plurality of fifth layers including a nitride semiconductor having a composition different from the composition of the third layer;
A plurality of sixth layers including GaInN stacked alternately with the plurality of fifth layers;
A second laminate including:
With
The first laminate has a recess provided on the light emitting portion side surface of the first laminate, and a part of the light emitting portion is embedded in at least a part of the recess,
A part of the second layer is disposed on the part of the light emitting part embedded in the at least part of the recess;
A dislocation penetrating the first laminate is formed, and a side surface of the recess surrounds the dislocation;
The wafer having a lower In composition ratio in the vicinity of the dislocation in the first stacked body than an In composition ratio in a portion of the first stacked body away from the dislocation. Forming an n-type first layer including a nitride semiconductor on a substrate;
A plurality of fifth layers including a nitride semiconductor and a plurality of sixth layers including GaInN alternately stacked with the plurality of fifth layers are alternately stacked on the first layer. Form the body,
A plurality of third layers including AlGaInN having a composition different from the composition of the fifth layer and a plurality of fourth layers including GaInN are alternately stacked on the second stacked body. Form the body,
Forming a light emitting unit including a plurality of barrier layers and a well layer provided between the plurality of barrier layers on the first stacked body;
Forming a p-type second layer including a nitride semiconductor on the light emitting portion;
The first laminate has a recess provided on the light emitting portion side surface of the first laminate,
The formation of the light emitting part includes embedding a part of the light emitting part in at least a part of the recess,
Forming the second layer includes embedding part of the second layer in at least part of the remaining space of the recess;
A dislocation penetrating the first laminate is formed, and a side surface of the recess surrounds the dislocation;
A method of manufacturing a semiconductor device, wherein an In composition ratio in the vicinity of the dislocation in the first stacked body is lower than an In composition ratio in a portion away from the dislocation in the first stacked body.   15. The method of manufacturing a semiconductor element according to claim 14, further comprising removing the substrate after bonding the upper surface of the second layer to a bonding substrate after forming the second layer. Forming an n-type first layer including a nitride semiconductor on a substrate;
A plurality of fifth layers including a nitride semiconductor and a plurality of sixth layers including GaInN alternately stacked with the plurality of fifth layers are alternately stacked on the first layer. Form the body,
A plurality of third layers including AlGaInN having a composition different from the composition of the fifth layer and a plurality of fourth layers including GaInN are alternately stacked on the second stacked body. Form the body,
Forming a light emitting unit including a plurality of barrier layers and a well layer provided between the plurality of barrier layers on the first stacked body;
Forming a p-type second layer including a nitride semiconductor on the light emitting portion;
The first laminate has a recess provided on the light emitting portion side surface of the first laminate,
The formation of the light emitting part includes embedding a part of the light emitting part in at least a part of the recess,
Forming the second layer includes embedding part of the second layer in at least part of the remaining space of the recess;
A dislocation penetrating the first laminate is formed, and a side surface of the recess surrounds the dislocation;
A method for manufacturing a wafer, wherein an In composition ratio in the vicinity of the dislocation in the first stacked body is lower than an In composition ratio in a portion of the first stacked body away from the dislocation.

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