JP2013065766A - Switching element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique that can reduce a gate threshold voltage without causing the trade-off relationship between the gate threshold voltage and a dielectric strength voltage.SOLUTION: A switching element includes a semiconductor substrate in which a trench is formed on its top surface, an insulating film covering the inner surface of the trench, and a gate electrode disposed in the trench. On the side surfaces of the gate electrode facing the semiconductor substrate, recesses extending in the depth direction of the semiconductor substrate are formed. A first region that is in contact with the insulating film in the recesses and has a first conductivity type, a second region that is in contact with the insulating film in the recesses, is in contact with the first region in the recesses from below, and has a second conductivity type, and a third region that is in contact with the insulating film in the recesses, is in contact with the second region in the recesses from below, is isolated from the first region by the second region, and has the first conductivity type are formed in the semiconductor substrate.

Description

  The present invention relates to an insulated gate switching element such as an IGBT or an FET.

  Insulated gate switching elements such as IGBTs and FETs are known. For example, Patent Document 1 discloses a MISFET which is a kind of an insulated gate switching element. An insulated gate switching element has a gate electrode facing the semiconductor layer via an insulating film. By applying a predetermined voltage to the gate electrode, a channel is formed in the semiconductor layer near the gate electrode, and the insulated gate switching element is turned on.

JP 2006-295071 A

  It is preferable that the minimum gate threshold voltage required to turn on the insulated gate switching element is low. If the insulating film in the trench is made thin, a high electric field is likely to be generated in the semiconductor layer when a gate voltage is applied, so that the gate threshold voltage is lowered. However, when the insulating film in the trench is thinned, there arises a problem that the withstand voltage of the switching element is lowered. Therefore, the present specification provides a technique capable of reducing the gate threshold voltage without causing such a trade-off relationship between the gate threshold voltage and the withstand voltage.

  A switching element disclosed in this specification includes a semiconductor substrate having a trench formed on an upper surface, an insulating film covering an inner surface of the trench, and a gate electrode disposed in the trench. A recess extending in the depth direction of the semiconductor substrate is formed on a side surface of the gate electrode facing the semiconductor substrate. A first region, a second region, and a third region are formed in the semiconductor substrate. The first region is in contact with the insulating film in the recess and has the first conductivity type. The second region is in contact with the insulating film in the recess, is in contact with the first region in the recess from below, and has the second conductivity type. The third region is in contact with the insulating film in the recess, is in contact with the second region in the recess from below, is separated from the first region by the second region, and has the first conductivity type. .

  The first conductivity type is one of the p-type and the n-type, and the second conductivity type is a conductivity type opposite to the first conductivity type. That is, when the first conductivity type is p-type, the second conductivity type is n-type, and when the first conductivity type is n-type, the second conductivity type is p-type.

  In this switching element, the second region is in contact with the insulating film and in contact with the first region and the third region in the recess. When a gate voltage is applied, a channel is formed in the second region in the recess. As a result, carriers can move between the first region and the third region. FIG. 6 is an example of the switching element disclosed in the present specification, and the charge in the second region 44 near the insulating film 22 in the recess 28 and the charge in the gate electrode 24 when a gate voltage is applied to the gate electrode 24. The distribution of is shown. In FIG. 6, the second region 44 is shown as a p-type as an example. In FIG. 6, the state where the electron density is low in the gate electrode 24 is schematically shown as a positive charge. As shown in FIG. 6, when a gate voltage is applied, positive charges are collected in the gate electrode 24 near the insulating film 22, and negative charges are collected in the second region 44 near the insulating film 22. A channel is formed by the negative charges collected in the second region 44. As shown in the drawing, negative charges gather at a high density in the second region 44 in the recess 28. That is, in the second region 44 in the recess 28, negative charges are likely to collect and a channel is likely to be formed. Therefore, this switching element has a low gate threshold voltage. That is, according to the configuration in which the channel is formed in the second region in the recess, the gate threshold voltage can be lowered without reducing the thickness of the insulating film. Therefore, according to this configuration, the gate threshold voltage can be lowered without causing a trade-off relationship between the gate threshold voltage and the withstand voltage. In FIG. 6, the cross section of the recess 28 has an arc shape, but this is merely an example, and the cross section of the recess may be an elliptical arc shape or a rectangle. Further, in FIG. 6, the second region 44 is p-type, but the second region 44 may be n-type.

  In the switching element described above, when the semiconductor substrate is viewed in plan view from the upper surface side, one of the side surfaces of the gate electrode on both sides of the recess extends linearly, and the other second portion is It is preferable to extend linearly along the extension line of the first part.

  In the switching element described above, it is preferable that the width of the gate electrode in the portion where the recess is formed is narrower than the width of the gate electrode in the portion where the recess is not formed.

  Further, the switching element described above has a plurality of channel structures constituted by the first region, the second region, and the third region formed in the recess, and the inside of the recess of at least one channel structure. It is preferable that the curvature of the side surface of the gate electrode is smaller than the curvature of the side surface of the gate electrode in the recess of at least one channel structure present at a position farther from the center of the semiconductor substrate than the channel structure.

  In this switching element, the curvature of the side surface of the gate electrode is large in at least one recess located far from the center of the semiconductor substrate. When the curvature of the side surface of the gate electrode of the recess is large, a channel is more easily formed in the second region in the recess. Therefore, in this switching element, current flows more easily through the channel structure at a position far from the center of the semiconductor substrate than at the channel structure at a position near the center of the semiconductor substrate. In this way, by making the current at a position near the center of the semiconductor substrate relatively low, the temperature distribution in the semiconductor substrate can be made uniform. As a result, local degradation of the semiconductor substrate in the vicinity of the center of the semiconductor substrate can be suppressed.

  Further, in an assembly in which two switching elements are mounted on a substrate, the temperature of the semiconductor substrate of each switching element is likely to rise at a position close to the center of the region where the two switching elements are mounted. Accordingly, the present specification provides the following assembly.

  This assembly is an assembly in which a first switching element having the above-described switching element configuration and a second switching element having the above-described switching element configuration are mounted on a substrate. In the first switching element, a plurality of channel structures constituted by the first region, the second region, and the third region formed in the recess are formed. The gate electrode in the recess of the at least one channel structure in which the curvature of the side surface of the gate electrode in the recess of the at least one channel structure of the first switching element is located farther from the second switching element than the channel structure Smaller than the curvature of the side. In the second switching element, a plurality of channel structures constituted by the first region, the second region, and the third region formed in the recess are formed. The gate electrode in the recess of the at least one channel structure in which the curvature of the side surface of the gate electrode in the recess of the at least one channel structure of the second switching element is located farther from the first switching element than the channel structure Smaller than the curvature of the side.

  According to such a configuration, since it becomes difficult for a current to flow through the channel structure near the center of the region where the first switching element and the second switching element are mounted, the temperature in the region is made uniform. Can do. Thereby, local degradation of each semiconductor substrate can be suppressed at a position close to the center of the region.

FIG. 3 is a diagram illustrating an arrangement of a gate electrode 24, a gate insulating film 22, an emitter region 40, and a body contact region 42 when the top surface of the semiconductor device 10 according to the first embodiment is viewed in plan. FIG. 2 is a longitudinal sectional view of the semiconductor device 10 taken along a line II-II in FIG. 1 (a line not passing through a recess 28). FIG. 3 is a longitudinal sectional view of the semiconductor device 10 taken along line III-III in FIG. 1 (a line passing through a recess 28). The perspective view which expanded the area | region of the recessed part 28 vicinity. 1 is an overall view of the upper surface of a semiconductor substrate 12. FIG. The expanded sectional view of the recessed part 28 in the center part 12a (sectional view in the depth of the body area | region 44). The expanded sectional view of the recessed part 28 in the outer peripheral part 12b (sectional drawing in the depth of the body area | region 44). The graph which shows the relationship between the gate voltage Vg and the collector-emitter current Ice when a predetermined voltage is applied between the collector and the emitter. FIG. 6 is a top view of the assembly according to the second embodiment. The figure which shows arrangement | positioning of the gate electrode 24, the gate insulating film 22, the emitter area | region 40, and the body contact area | region 42 when the upper surface of the semiconductor device of a modification is planarly viewed.

  As shown in FIGS. 1 to 3, the semiconductor device 10 according to the embodiment includes a semiconductor substrate 12, electrodes formed on the upper surface and the lower surface of the semiconductor substrate 12, an insulating film, and the like.

  A plurality of trenches 20 are formed on the upper surface of the semiconductor substrate 12. The inner surface of the trench 20 is covered with a gate insulating film 22. A gate electrode 24 is disposed inside the trench 20. The gate electrode 24 is insulated from the semiconductor substrate 12 by the gate insulating film 22. The upper surface of the gate electrode 24 is covered with an interlayer insulating film 30. An emitter electrode 32 is formed on the upper surface of the semiconductor substrate 12. The emitter electrode 32 is insulated from the gate electrode 24 by the interlayer insulating film 30. A collector electrode 34 is formed on the lower surface of the semiconductor substrate 12.

  As shown in FIG. 1, when the upper surface of the semiconductor substrate 12 is viewed in plan, each trench 20 extends long in one direction. In the following, in FIG. 1, the direction in which each trench 20 extends long is referred to as the Y direction, and the direction orthogonal to the Y direction is referred to as the X direction. Each trench 20 has a portion in which the width (width in the X direction) is partially narrowed, whereby a recess 28 is formed on the side surface of the gate electrode 24. As shown in FIG. 4, the recess 28 extends from the upper end to the lower end of the gate electrode 24 along the depth direction of the semiconductor substrate 12. Side surfaces of the gate electrode 24 other than the recesses 28 are formed in a planar shape. That is, as shown in FIG. 1, when the semiconductor substrate 12 is viewed from the upper surface side, the first portion 29 a that is one of the side surfaces of the gate electrode 24 on both sides of the recess 28 extends in a straight line. The second portion 29b extends linearly along the extension line of the first portion 29a. The side surface of the gate electrode 24 in the recess 28 has a cross-sectional shape of an arc or an elliptical arc when cut along a plane parallel to the upper surface of the semiconductor substrate 12. The gate electrode 24 has a pair of recesses 28 formed on the side surfaces on both sides thereof. The pair of recesses 28 are formed at regular intervals along the Y direction. The width of the portion of the gate electrode 24 where the recess 28 is formed (the width in the X direction) is narrower than the width of the gate electrode 24 where the recess 28 is not formed. The gate insulating film 22 is thin and is formed along the recess 28. Therefore, the side surface 22 a (the boundary surface with the semiconductor layer) of the gate insulating film 22 also extends along the recess 28.

  As shown in FIGS. 2 to 4, an emitter region 40, a body contact region 42, a body region 44, a drift region 46, and a collector region 48 are formed in the semiconductor substrate 12.

  The emitter region 40 is an n-type region. The emitter region 40 is formed in a depth range exposed on the upper surface of the semiconductor substrate 12. The emitter region 40 is ohmically connected to the emitter electrode 32. The emitter region 40 is in contact with the gate insulating film 22. A part of the emitter region 40 is formed in the recess 28 and is in contact with the gate insulating film 22 in the recess 28.

  The body contact region 42 is a p-type region. The body contact region 42 is formed in a depth range exposed on the upper surface of the semiconductor substrate 12 and is adjacent to the emitter region 40. The body contact region 42 is ohmically connected to the emitter electrode 32. The body contact region 42 is in contact with the gate insulating film 22 outside the recess 28.

  The body region 44 is a p-type region having a p-type impurity concentration lower than that of the body contact region 42. The body region 44 is formed below the emitter region 40 and the body contact region 42 and is in contact with these regions from below. The body region 44 is in contact with the gate insulating film 22. A part of the body region 44 is formed in the recess 28. The body region 44 in the recess 28 is in contact with the gate insulating film 22 in the recess 28. The body region 44 in the recess 28 is in contact with the emitter region 40 in the recess 28 from below.

  The drift region 46 is an n-type region having an n-type impurity concentration lower than that of the emitter region 40. The drift region 46 is formed below the body region 44 and is in contact with the body region 44 from below. The drift region 46 is separated from the emitter region 40 by the body region 44. The drift region 46 is in contact with the gate insulating film 22 near the lower end of the trench 20. A part of the drift region 46 is formed in the recess 28. The drift region 46 in the recess 28 is in contact with the gate insulating film 22 in the recess 28. The drift region 46 of the recess 28 is in contact with the body region 44 in the recess 28 from below.

  The collector region 48 is a p-type region. The collector region 48 is formed below the drift region 46 and is in contact with the drift region 46 from below. Collector region 48 is separated from body region 44 by drift region 46. The collector region 48 is exposed on the lower surface of the semiconductor substrate 12. The collector region 48 is ohmically connected to the collector electrode 34.

  The emitter electrode 32, the emitter region 40, the body contact region 42, the body region 44, the drift region 46, the collector region 48, the gate electrode 24, and the gate insulating film 22 form an IGBT.

  The above-described IGBT is formed over substantially the entire area of the central portion 12a and the outer peripheral portion 12b of the semiconductor substrate 12 shown in FIG. However, the cross-sectional shape of the side surface of the gate electrode 24 in the recess 28 when cut along a plane parallel to the upper surface of the semiconductor substrate 12 (hereinafter simply referred to as the cross-sectional shape of the recess 28) is the center portion 12a and the outer peripheral portion 12b. Different. FIG. 6 shows a cross-sectional shape of the concave portion 28 formed in the central portion 12a, and FIG. 7 shows a cross-sectional shape of the concave portion 28 formed in the outer peripheral portion 12b. As shown in FIGS. 6 and 7, the curvature of the cross-sectional shape of the concave portion 28 of the central portion 12a (that is, the cross-sectional shape of the side surface of the gate electrode 24 in the concave portion 28 when cut along a plane parallel to the upper surface of the semiconductor substrate 12). (Curvature) is smaller than the curvature of the cross-sectional shape of the concave portion 28 of the outer peripheral portion 12b (that is, the curve is gentle).

  Next, the operation of the IGBT will be described. When a positive voltage is applied to the gate electrode 24, electrons are collected in the body region 44 in a range in contact with the gate insulating film 22. As a result, a channel is formed in the body region 44 along the gate insulating film 22. In this state, when a positive voltage is applied between the emitter electrode 32 and the collector electrode 34, the IGBT is turned on. That is, electrons flow from the emitter electrode 32 to the collector electrode 34 through the emitter region 40, the channel, the drift region 46, and the collector region 48. At the same time, holes flow from the collector electrode 34 through the collector region 48 to the drift region 46. As a result, the electrical resistance of the drift region 46 decreases, and electrons flow in the IGBT with low loss. Further, the holes flowing into the drift region 46 flow to the emitter electrode 32 through the body region 44 and the body contact region 42.

  Next, the gate threshold voltage of the IGBT will be described. As described above, in the semiconductor device 10, the body region 44 is in contact with the insulating film 22 in the recess 28. Accordingly, a channel is formed in the body region 44 in the recess 28. FIG. 6 schematically shows the charge distribution in the vicinity of the recess 28 when a predetermined gate voltage is applied. In FIG. 6, for the sake of explanation, the state in which the number of electrons in the gate electrode 24 is reduced is represented as the accumulation of positive charges in the gate electrode 24. As shown in FIG. 6, when a gate voltage is applied, positive charges are collected in the gate electrode 24 in the range in contact with the gate insulating film 22, and negative charges are collected in the body region 44 in the range in contact with the gate insulating film 22. A channel is formed in the body region 44 by these negative charges. As shown in the drawing, the density of negative charges is higher in the recess 28 than in the outer side of the recess 28. This is because the region 52 in which negative charges are collected along the insulating film 22 in the recess 28 in the body region 44 rather than the region 50 in which positive charges are collected along the insulating film 22 in the recess 28 in the gate electrode 24. This is because of the narrowness. Thus, since negative charges are likely to collect in the recess 28, a channel is easily formed in the recess 28. That is, this IGBT has a low gate threshold voltage. Further, as shown in FIG. 7, negative charges are more likely to collect in the concave portion 28 having a larger curvature. Therefore, the IGBT in which the concave portion 28 having a large curvature shown in FIG. 7 is formed has a lower gate threshold voltage than the IGBT having the concave portion 28 shown in FIG.

Gate threshold voltages V _gth0 , V _gth1 , and V _{gth2 in} FIG. 8 indicate gate voltages when a minute current I ₀ starts to flow through each IGBT. As shown in FIG. 8, than the gate threshold voltage _{V Gth0} of IGBT not recess 28 is formed, the gate threshold voltage _V Gth1 of an IGBT recess 28 is _formed, towards the _{V Gth2} is low. Moreover, than the gate threshold voltage _{V Gth1} of IGBT small curvature of the recess 28, towards the gate threshold voltage _{V Gth2} of IGBT large curvature of the recess 28 is low.

As described above, the curvature of the recess 28 is smaller in the central portion 12 a of the semiconductor substrate 12 than in the outer peripheral portion 12 b of the semiconductor substrate 12. For this reason, the gate threshold voltage of the IGBT formed in the central portion 12a is higher than that of the IGBT formed in the outer peripheral portion 12b. For this reason, when the same gate voltage (voltage higher than the gate threshold voltage) is applied to all the gate electrodes 24, the current density becomes higher at the outer peripheral portion 12b than at the central portion 12a. For example, when applied to all the gate electrode 24 a voltage _{V g0} in FIG. 8, IGBT in the central portion 12a (i.e., IGBT small curvature of the cross-sectional shape of the recess 28) while flowing a current _{I 1} to the outer peripheral A current I ₂ larger than the current I ₁ flows through the IGBT of the portion 12b (that is, an IGBT having a large curvature of the cross-sectional shape of the recess 28). As a result, the current density is higher at the outer peripheral portion 12b than at the central portion 12a. Thereby, the lifetime of the semiconductor device 10 is improved. That is, generally, the lifetime of a semiconductor device is determined by the maximum temperature in the semiconductor substrate. This is because the place where the maximum temperature is applied receives the greatest stress due to thermal expansion and contraction and is most easily damaged. When a current is uniformly applied to the entire semiconductor substrate, the central portion of the semiconductor substrate becomes the highest temperature. On the other hand, as described above, when the current density is made higher at the outer peripheral portion 12b than at the central portion 12a, the temperature distribution in the semiconductor substrate 12 becomes uniform, and the maximum temperature in the semiconductor substrate 12 becomes lower. Therefore, the semiconductor device 10 has a long life.

  As described above, the semiconductor device 10 has the gate threshold voltage lower than that of the conventional IGBT because the recess 28 is formed in the gate electrode 24. That is, according to this configuration, the gate threshold voltage can be lowered as compared with the conventional case without reducing the thickness of the insulating film. Further, since the temperature distribution in the semiconductor substrate 12 is made uniform by the difference in curvature of the recess 28, the life of the semiconductor device 10 is long.

  As Example 2, an assembly having two semiconductor devices will be described. An assembly 100 shown in FIG. 9 is obtained by mounting two semiconductor devices 120 and 130 on a substrate 110. IGBTs are formed on the semiconductor substrates of the semiconductor devices 120 and 130. Each IGBT has the same structure as that described with reference to FIGS. However, the recess in the region 120a (region close to the semiconductor device 130) of the semiconductor device 120 is a recess having a small curvature as shown in FIG. 6, and the recess in the region 120b (region far from the semiconductor device 130) is illustrated in FIG. 7 is a recess having a large curvature. Further, the recess in the region 130a (region close to the semiconductor device 120) of the semiconductor device 130 is a recess having a small curvature as shown in FIG. 6, and the recess in the region 130b (region far from the semiconductor device 120) is illustrated in FIG. 7 is a recess having a large curvature. Accordingly, the IGBTs in the regions 120a and 130a have a higher gate threshold voltage than the IGBTs in the regions 120b and 130b. Therefore, when the IGBTs of the semiconductor devices 120 and 130 are turned on with a constant gate voltage, the current density is higher in the regions 120b and 130b than in the regions 120a and 130a. In the regions 120a and 130a close to adjacent semiconductor devices, heat generated in the regions is difficult to escape. Therefore, by reducing the current density in the regions 120a and 130a in this manner, the temperature distribution in the semiconductor device 120 and the semiconductor device 130 can be made uniform. As a result, the lifetime of the semiconductor devices 120 and 130 can be extended. In addition, according to such a configuration, since the temperature rise in the regions 120a and 130a is suppressed, the semiconductor devices 120 and 130 can be mounted closer to each other. Thereby, the assembly 100 can be miniaturized.

  The first and second embodiments have been described above. In the first and second embodiments described above, the semiconductor device in which the IGBT is formed has been described. However, the technique disclosed in this specification is applied to a switching element such as an FET (switching element having an insulated gate electrode). Also good. When applied to an FET, the FET may be a p-channel type or an n-channel type.

  In the first and second embodiments, the example in which the gate threshold voltage is lowered as compared with the conventional case by the concave portion of the gate electrode has been described. However, other characteristics may be improved due to the advantages obtained by the recesses in the gate electrode. For example, when the concave portion is provided and the thickness of the gate insulating film is increased, the effect of decreasing the gate threshold voltage due to the concave portion is canceled by the effect of increasing the gate threshold voltage by increasing the thickness of the insulating film. On the other hand, by increasing the thickness of the gate insulating film, the switching loss and the withstand voltage of the IGBT are improved. That is, according to this configuration, an IGBT having a gate threshold voltage equivalent to that of the prior art and a switching loss and withstand voltage higher than those of the prior art can be obtained. Further, for example, when the recess is provided and the impurity concentration in the body region is increased, the effect of lowering the gate threshold voltage due to the recess is canceled by the effect of increasing the gate threshold voltage by increasing the impurity concentration in the body region. On the other hand, by increasing the impurity concentration in the body region, the RBSOA tolerance and the avalanche tolerance of the IGBT can be improved. That is, according to this configuration, an IGBT having a gate threshold voltage equivalent to that of the prior art and an RBSOA tolerance and an avalanche tolerance higher than those of the conventional one can be obtained.

  In the embodiment described above, the direction in which the gate electrode 24 extends and the direction in which the emitter region 40 extends intersect on the upper surface of the semiconductor substrate as shown in FIG. 1, but as shown in FIG. The gate electrode 24 and the emitter region 40 may extend in parallel on the upper surface. Even with such a structure, the advantage of the recess 28 can be obtained.

  In addition, in the semiconductor devices of Examples 1 and 2 described above, two types of concave portions having different curvatures are formed. However, in order to make the temperature distribution more uniform, three or more types of concave portions having different curvatures are formed. It may be. Further, when the temperature distribution does not matter so much, the curvature of each recess may be the same.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology illustrated in the present specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.

10: Semiconductor device 12: Semiconductor substrate 12a: Central portion 12b: Peripheral portion 20: Trench 22: Insulating film 24: Gate electrode 28: Recess 30: Interlayer insulating film 32: Emitter electrode 34: Collector electrode 40: Emitter region 42: Body Contact region 44: Body region 46: Drift region 48: Collector region 100: Assembly 110: Substrate 120: Semiconductor device 130: Semiconductor device

Claims (5)

A switching element,
A semiconductor substrate having a trench formed on the upper surface;
An insulating film covering the inner surface of the trench;
A gate electrode disposed in the trench;
Have
On the side surface of the gate electrode facing the semiconductor substrate, a recess extending in the depth direction of the semiconductor substrate is formed,
In the semiconductor substrate,
A first region in contact with the insulating film in the recess and having a first conductivity type;
A second region having a second conductivity type, in contact with the insulating film in the recess, in contact with the first region in the recess from below;
A third region having a first conductivity type, in contact with the insulating film in the recess, in contact with the second region in the recess from below, and separated from the first region by the second region;
A switching element in which is formed.   When the semiconductor substrate is viewed from the upper surface side, the first portion which is one of the side surfaces of the gate electrode on both sides of the concave portion extends linearly, and the second portion which is the other is an extension line of the first portion. The switching element according to claim 1, which extends linearly along the line.   The switching element according to claim 1 or 2, wherein the width of the gate electrode in the portion where the recess is formed is narrower than the width of the gate electrode in the portion where the recess is not formed. It has a plurality of channel structures constituted by the first region, the second region, and the third region formed in the recess,
The curvature of the side surface of the gate electrode in the recess of the at least one channel structure is smaller than the curvature of the side surface of the gate electrode in the recess of the at least one channel structure existing at a position farther from the center of the semiconductor substrate than the channel structure. The switching element as described in any one of Claims 1-3. It is an assembly in which the first switching element according to any one of claims 1 to 3 and the second switching element according to any one of claims 1 to 3 are mounted on a substrate,
In the first switching element, a plurality of channel structures constituted by the first region, the second region, and the third region formed in the recess are formed,
The gate electrode in the recess of the at least one channel structure in which the curvature of the side surface of the gate electrode in the recess of the at least one channel structure of the first switching element is located farther from the second switching element than the channel structure Smaller than the curvature of the side of
In the second switching element, a plurality of channel structures formed by the first region, the second region, and the third region formed in the recess are formed,
The gate electrode in the recess of the at least one channel structure in which the curvature of the side surface of the gate electrode in the recess of the at least one channel structure of the second switching element is located farther from the first switching element than the channel structure Smaller than the curvature of the side,
assembly.

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