JP2013065621A - Wiring board for light emitting device, light emitting device, and manufacturing method of wiring board for light emitting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board for a light emitting device which suppresses the oxidization of a wiring pattern.SOLUTION: A wiring board 1 has: a substrate 10; a wiring pattern 20 formed on a first main surface R1 of the substrate 10; a plating layer 30 formed so as to cover a surface 20A of the wiring pattern 20; and an insulation layer 40 which covers the wiring pattern 20, where the plating layer 30 is formed, and is formed on the first main surface R1. An opening 40X, which exposes a part of the wiring pattern 20 where the plating layer 30 is formed as a mounting region CA of a light emitting element, is formed at the insulation layer 40. The plating layer 30 has a three layer structure formed by sequentially laminating a first plating layer 31 which is formed on the surface 20A of the wiring pattern 20 and made of Ni or Ni alloy; a second plating layer 32 made of Pd or Pd alloy, and a third plating layer 33 made of Au or Au alloy.

Description

  The present invention relates to a wiring substrate for a light emitting device, a light emitting device, and a method for manufacturing the wiring substrate for a light emitting device.

  Conventionally, light emitting devices having a light emitting element mounted on a substrate have been proposed in various shapes. As a light emitting device of this type, for example, a structure in which a wiring pattern is formed on a resin substrate and a light emitting element such as a light emitting diode (LED) is mounted on the wiring pattern is known (for example, a patent References 1 and 2).

Japanese Patent Laid-Open No. 2003-092010 Japanese Patent Laid-Open No. 2003-092011

  By the way, in the light-emitting device, when the light-emitting diode is energized during actual use, the light-emitting diode generates heat and the temperature rises. In addition, copper (Cu) that is liable to be oxidized or corroded is used as a material for the wiring pattern. For this reason, there is a possibility that the wiring pattern (copper) is oxidized due to a temperature rise during actual use as described above, and copper oxide is formed on the surface of the wiring pattern. When such copper oxide is formed, there arises a problem that the resistance of the wiring increases and the light emission efficiency of the light emitting diode decreases.

  According to one aspect of the present invention, a substrate, a wiring pattern formed on the first main surface of the substrate, a plating layer formed to cover the surface of the wiring pattern, and the plating layer are formed. And an insulating layer formed on the first main surface. The insulating layer includes a part of the wiring pattern on which the plating layer is formed as a mounting region of a light emitting element. An exposed opening is formed, and the plating layer has an outermost plating layer made of a noble metal or a noble metal alloy in the outermost layer.

  According to one aspect of the present invention, there is an effect that oxidation of a wiring pattern can be suppressed.

(A) is a schematic top view which shows the wiring board of 1st Embodiment, (b) is AA schematic sectional drawing of the wiring board shown to (a), (c) is a wiring board shown to (b). The expanded sectional view which expanded a part of. The schematic plan view which shows a wiring pattern. (A) is a schematic plan view which shows the light-emitting device of 1st Embodiment, (b) is BB schematic sectional drawing of the light-emitting device shown to (a). In addition, in (a), illustration of sealing resin is abbreviate | omitted. (A)-(c) is a schematic sectional drawing which shows the state in the manufacturing process of the wiring board of 1st Embodiment, (d) is an expanded sectional view which expanded the principal part of (c). The schematic plan view which shows the state in the manufacture process of the wiring board of 1st Embodiment. (A), (c) is a schematic sectional drawing which shows the state in the manufacturing process of the wiring board of 1st Embodiment, (b) is an expanded sectional view which expanded the principal part of (a). (A), (c) is a schematic sectional drawing which shows the state in the manufacturing process of the wiring board of 1st Embodiment, (b) is an expanded sectional view which expanded the principal part of (a). The schematic plan view which shows the state in the manufacture process of the wiring board of 1st Embodiment. (A), (b) is a schematic sectional drawing which shows the state in the manufacture process of the light-emitting device of 1st Embodiment. A table showing the relationship between surface roughness and adhesion. The expanded sectional view which shows the wiring board of a modification. The schematic sectional drawing which shows the light-emitting device of a modification. (A) is a schematic sectional drawing which shows the wiring board of 2nd Embodiment, (b) is an expanded sectional view which expanded a part of wiring board shown to (a). (A)-(c) is a schematic sectional drawing which shows the state in the manufacturing process of the wiring board of 2nd Embodiment, (d) is an expanded sectional view which expanded the principal part of (c). (A)-(c) is a schematic sectional drawing which shows the state in the manufacture process of the wiring board of 2nd Embodiment. The expanded sectional view which shows the wiring board of a modification. The expanded sectional view which shows the wiring board of a modification. (A), (b) is a schematic sectional drawing which shows the light-emitting device of a modification. The expanded sectional view which shows the wiring board of a modification. The schematic plan view which shows the wiring pattern of a modification.

  Hereinafter, each embodiment will be described with reference to the accompanying drawings. In the accompanying drawings, in order to make the features easy to understand, the portions that become the features may be shown in an enlarged manner for the sake of convenience, and the dimensional ratios and the like of the respective components are not always the same as the actual ones. In the cross-sectional view, hatching of some resin layers is omitted for easy understanding of the cross-sectional structure of each member. In the enlarged cross-sectional view, hatching of the plating layer is omitted for easy understanding of the cross-sectional structure of each member.

(First embodiment)
Hereinafter, a first embodiment will be described with reference to FIGS.
(Wiring board structure)
As shown in FIG. 1B, the wiring substrate 1 applied to the light emitting device includes a substrate 10, a wiring pattern 20 formed on the substrate 10, a plating layer 30 formed on the wiring pattern 20, And an insulating layer 40 covering a part of the plating layer 30.

  The substrate 10 is a substantially rectangular thin plate, for example. As a material of the substrate 10, for example, an insulating resin such as a polyimide resin or an epoxy resin, or a resin material in which a filler such as silica or alumina is mixed in an epoxy resin can be used. The thickness of the board | substrate 10 can be about 25-200 micrometers, for example.

  The wiring pattern 20 is formed on the first main surface R1 (the upper surface in FIG. 1B) of the substrate 10. As shown in FIG. 2, the wiring pattern 20 is formed so as to entirely cover the first main surface R1 of the substrate 10, and has a plurality of substantially rectangular wirings D1 that are electrically separated from each other. doing. Specifically, the wiring pattern 20 is formed in a substantially comb-like shape as a whole, and the comb-like pattern is formed into a plurality of wirings by groove-like openings 20X extending in the vertical direction in the drawing. It is separated into D1. In other words, the plurality of wirings D <b> 1 are arranged on the substrate 10 in a substantially comb shape.

  As shown in FIG.1 (c), the surface 20A (upper surface and side surface) of the wiring pattern 20 is roughened, and the fine uneven | corrugated shape is formed. The roughness of the surface 20A of the roughened wiring pattern 20 is set to be, for example, 50 to 500 nm as a surface roughness Ra value. Here, the surface roughness Ra value is a kind of numerical value representing the surface roughness, and is called arithmetic average roughness. Specifically, the absolute value of the height changing in the measurement region is expressed as an average line. Measured from the surface and arithmetically averaged.

In addition, as a material of the wiring pattern 20, metals, such as copper and a copper alloy, can be used, for example. The thickness of the wiring pattern 20 can be set to 15 to 150 μm, for example.
As shown in FIG. 1B, the plating layer 30 is formed so as to cover the surface 20 </ b> A (roughened surface) of the wiring pattern 20. The plating layer 30 is formed along the surface 20A of the wiring pattern 20, and the surface 30A is roughened. The roughness of the surface 30A of the roughened plating layer 30 is set to be 50 to 500 nm, for example, in terms of the surface roughness Ra value.

  As shown in FIG. 1C, the plating layer 30 includes a first plating layer 31 for base formed on the surface 20 </ b> A of the wiring pattern 20, a second plating layer 32, and a third plating layer 33. It has a three-layer structure laminated in order. Here, in the present embodiment, the first plating layer 31 is a nickel (Ni) plating layer, the second plating layer 32 is a palladium (Pd) plating layer, and the third plating layer 33 is a gold (Au) plating layer. In addition, these 1st-3rd plating layers 31-33 can be formed by the electroplating method, for example.

  In the first plating layer 31 for the first layer, Cu contained in the lower wiring pattern 20 diffuses into the upper second plating layer 32 (Pd layer) and the third plating layer 33 (Au layer). It has the function to prevent. The first plating layer 31 has a material composition and thickness in consideration of the diffusion preventing effect, the corrosion resistance effect for preventing the wiring pattern 20 from being corroded, and the adhesion with the second plating layer 32 made of Pd. Is set. As the material of the first plating layer 31, for example, Ni or Ni alloy can be used. Moreover, the thickness of the 1st plating layer 31 has the preferable range of 0.05 micrometer or more and 5.00 micrometers or less, and the range of 0.1 micrometer or more and 2.00 micrometers or less from the viewpoint of the said characteristic and manufacturing cost.

  The second plating layer 32 of the second layer plays a role of preventing mutual diffusion between Ni contained in the first plating layer 31 and Au contained in the third plating layer 33 due to heat, for example. As a material of the second plating layer 32 for realizing such a function, for example, Pd or a Pd alloy can be used. The thickness of the second plating layer 32 is preferably in the range of 0.001 μm or more and 0.5 μm or less in order to suppress the mutual diffusion while reducing the thickness as much as possible from the viewpoint of manufacturing cost. A range of 0.03 μm or less is more preferable.

  The third plating layer 33 of the third layer plays a role of improving contact property (wire bonding property and solderability) while preventing oxidation of the plating layer 30 and the wiring pattern 20 during heating, for example. The material of the third plating layer 33 for realizing such a function is preferably a metal that is harder to oxidize than the wiring pattern 20 (copper) and has a low hardness, such as Au or silver (Ag). A noble metal or a noble metal alloy containing at least one of these metals can be used. The thickness of the third plating layer 33 is preferably 0.001 μm or more and 0.5 μm or less in order to improve wire bonding properties while reducing the thickness as much as possible from the viewpoint of manufacturing cost. A range of 0.01 μm or less is more preferable.

  The surfaces 31A to 33A (upper surface and side surfaces) of the first to third plating layers 31 to 33 are roughened in the same manner as the surface 20A of the wiring pattern 20, and a fine uneven shape is formed. The roughness of the surfaces 31A to 33A of the roughened first to third plating layers 31 to 33 is set to, for example, 50 to 500 nm in terms of the surface roughness Ra value. Thereby, when the surface 33A of the third plating layer 33 is a smooth surface, the adhesion between the plating layer 30 (particularly, the third plating layer 33) and the insulating layer 40 formed on the third plating layer 33 is improved. Can be increased.

  As shown in FIG. 1B, the insulating layer 40 is formed on the first main surface R <b> 1 side of the substrate 10 so as to cover a part of the plating layer 30. Specifically, as shown in FIG. 1A, the insulating layer 40 covers the plating layer 30 and the substrate 10 other than the mounting area CA where the light emitting element is mounted and the terminal area where the electrode terminal 50 is formed. Is formed. In other words, in the insulating layer 40, the plating layer 30 formed in the mounting area CA and the opening 40X for exposing the substrate 10 are formed, and the plating layer 30 formed in the terminal area is used as the electrode terminal 50. An opening 40Y for exposure is formed. The planar shapes of the openings 40X and 40Y are formed in a circular shape, for example. The openings 40X are formed in a matrix (4 × 4 in FIG. 1A) on the substrate 10. For this reason, the mounting areas CA defined by the openings 40X are similarly arranged on the substrate 10 in a matrix (4 × 4 in FIG. 1A). In the mounting area CA, the two plating layers 30 separated by the opening 20X are exposed from the opening 40X. Here, the opening 20X is formed in a groove shape between two adjacent plating layers 30 (wiring patterns 20). The plating layer 30 exposed from the opening 40X functions as a pad. The electrode terminal 50 defined by the opening 40Y is supplied with power from an external power source via a power supply cable (not shown) and the like, and the wiring pattern 20 is electrically connected thereto.

  The insulating layer 40 has a high reflectance. Specifically, the insulating layer 40 has a reflectance of 50% or more (preferably 80% or more) when the wavelength is between 450 nm and 700 nm. Such an insulating layer 40 is also called a white resist layer. As a material of the insulating layer 40, for example, a white insulating resin can be used. As the white insulating resin, for example, a resin material in which a filler such as white titanium oxide is mixed in an epoxy resin or an organopolysiloxane resin, or a resin material containing a white pigment such as TiO 2 or BaSO 4 can be used. By covering the outermost surface of the substrate 10 with such an insulating layer 40 (white resist layer), in addition to protecting the wiring pattern 20, the reflectance of light from the light emitting element mounted on the substrate 10 is increased, and the light emitting element Can be reduced.

  In addition, a plurality of groove portions 60 are formed in the wiring board 1. As shown in FIG. 1B, the groove 60 penetrates the insulating layer 40, the plating layer 30 (first to third plating layers 31 to 33), and the wiring pattern 20 from the upper surface of the insulating layer 40. It is formed up to the middle of the thickness of the substrate 10. The groove 60 is formed in order to remove the power supply line 22 for plating power supply (see FIG. 5) used in the manufacturing process of the wiring board 1.

(Structure of light emitting device)
Next, the structure of the light emitting device 2 will be described.
As shown in FIG. 3B, the light-emitting device 2 includes the wiring board 1, a plurality (16 in FIG. 3A) of light-emitting elements 70 mounted on the wiring board 1, the light-emitting elements 70, and the like. And a sealing resin 75 for sealing.

  As shown in FIG. 3A, each light emitting element 70 is mounted in each mounting area CA of the wiring board 1. Specifically, each light emitting element 70 is mounted on one plating layer 30 (wiring pattern 20) formed in each mounting area CA. More specifically, as shown in FIG. 3B, each light emitting element 70 is bonded to the one plating layer 30 via an adhesive 71. In addition, in each light emitting element 70, one electrode (not shown) is electrically connected to one plating layer 30 in the mounting area CA via the bonding wire 72, and the other electrode (not shown) is the bonding wire 72. Is electrically connected to the other plating layer 30 in the mounting area CA. Thereby, each electrode of each light emitting element 70 is electrically connected to the wiring pattern 20 via the bonding wire 72 and the plating layer 30. With such connection, in the light emitting device 2 of the present embodiment, as shown in FIG. 3A, 16 light emitting elements 70 are connected in series between the positive electrode terminal 50 and the negative electrode terminal 50. Will be connected to. The light emitting elements 70 are supplied with power from an external power source (not shown) via the electrode terminals 50 and the wiring pattern 20 to emit light. In FIG. 1 to FIG. 3, “+” and “−” symbols are shown in the electrode terminal 50 portion in order to show an example of electrical connection.

  As the light emitting element 70, for example, a light emitting diode (LED) or a surface emitting semiconductor laser (VCSEL) can be used. As the bonding wire 72, for example, an Au wire, an aluminum (Al) wire, a Cu wire, or the like can be used.

  As shown in FIG. 3B, the sealing resin 75 is provided on the upper surface of the wiring substrate 1 so as to seal the light emitting element 70, the bonding wire 72, and the like. As a material of the sealing resin 75, for example, a resin material in which a phosphor is contained in a silicone resin can be used. By forming such a phosphor-containing resin material on the light emitting element 70, it is possible to use a mixed color of light emission of the light emitting element 70 and light emission of the phosphor, and various emission colors of the light emitting device 2 can be used. Can be controlled.

(Function)
A plating layer 30 is formed so as to cover the entire surface 20A of the wiring pattern 20, and a third plating layer 33 made of highly stable Au or Au alloy is formed on the outermost layer (outermost layer) of the plating layer 30. I made it. Thereby, the oxidation and discoloration of the surface 30A of the plating layer 30, the second plating layer 32, the first plating layer 31, and the wiring pattern 20 can be suitably suppressed.

(Method for manufacturing a wiring board)
Next, the manufacturing method of the said wiring board 1 is demonstrated according to FIGS. 4A and 4B are schematic cross-sectional views showing the state of the manufacturing process of the wiring board at the position AA in FIG. 1, and FIG. 4C is the wiring shown in FIG. It is CC schematic sectional drawing of a board | substrate. 6 and 7 are schematic cross-sectional views showing the state of the manufacturing process of the wiring board at the position AA in FIG.

  First, in order to manufacture the wiring substrate 1, as shown in FIG. 4A, a single-sided copper-clad substrate in which a copper foil 20B is deposited on one side of a substrate 10A is prepared. The substrate 10 </ b> A is a substrate that is finally cut at the cutting position B <b> 1 to become the substrate 10 shown in FIG. 1, and has an outer shape that is slightly larger than the substrate 10.

  Next, in the step shown in FIG. 4B, a resist layer 77 having openings 77X at predetermined positions is formed on the upper surface of the copper foil 20B. The resist layer 77 is formed so as to cover the required wiring pattern 20 and the copper foil 20B corresponding to the first and second feeding lines 21 and 22 for plating feeding (see FIG. 4C). As a material of the resist layer 77, a photosensitive dry film resist or a liquid photoresist (for example, a dry film resist or a liquid resist such as a novolac resin or an acrylic resin) can be used. For example, when a photosensitive dry film resist is used, a dry film is laminated on the upper surface of the copper foil 20B by thermocompression bonding, and the dry film is patterned by exposure and development to form the resist layer 77. Even when a liquid photoresist is used, the resist layer 77 can be formed through a similar process.

  4C, the copper foil 20B is etched using the resist layer 77 as an etching mask, and the copper foil 20B is patterned into a predetermined shape. Thereby, the required wiring pattern 20 and the first and second power supply lines 21 and 22 are formed on the first main surface R1 (upper surface) of the substrate 10A. Specifically, as shown in FIG. 5, a wiring pattern 20 having a large number of wirings D1, a first feeding line 21 formed on the outer periphery of the substrate 10A, the first feeding line 21 and the wiring pattern 20 Are electrically connected to each other, or the second power supply line 22 is formed to electrically connect each wiring D1. As a result, all the wirings D1 are electrically connected via the first and second power supply lines 21 and 22. In the following description, the wiring pattern 20 and the first and second feed lines 21 and 22 are collectively referred to as a wiring layer 23. Note that, after the patterning of the copper foil 20B is completed, the resist layer 77 shown in FIG. 4B is removed by, for example, an alkaline stripping solution.

  Next, in the step shown in FIG. 4D, the wiring pattern 20 is roughened. This roughening process is performed so that the roughness of the surface 20A (upper surface and side surface) of the wiring pattern 20 is 50 to 500 nm in terms of the surface roughness Ra. By such roughening treatment, fine irregularities are formed on the surface 20A of the wiring pattern 20, and the surface 20A is roughened. As the roughening treatment, for example, etching, oxidation, plating, blasting, or the like can be performed. In this roughening process, the first and second power supply lines 21 and 22 made of copper are also roughened in the same manner as the wiring pattern 20.

  Next, in the process shown in FIG. 6A, the surface 20A of the wiring pattern 20 is subjected to an electrolytic plating method using the wiring layer 23 as a plating power feeding layer, and the plating layer having a three-layer structure is formed on the surface 20A of the wiring pattern 20. 30 is formed. Specifically, as shown in FIG. 6B, Ni having a thickness of 0.05 to 5.00 μm (preferably 0.1 to 2.00 μm) is obtained by applying Ni plating to the surface 20A of the wiring pattern 20. A layer (first plating layer 31) is formed. At this time, since the first plating layer 31 is formed in a shape along the surface 20A of the wiring pattern 20, the surface 31A of the first plating layer 31 is also roughened similarly to the wiring pattern 20. Subsequently, Pd plating is performed on the first plating layer 31 to form a Pd layer (second plating layer 32) having a thickness of 0.001 to 0.5 μm (preferably 0.005 to 0.03 μm). At this time, since the second plating layer 32 is formed in a shape along the surface 31A of the first plating layer 31, the surface 32A of the second plating layer 32 is also roughened in the same manner as the first plating layer 31. The Then, Au plating is performed on the second plating layer 32 to form an Au layer (third plating layer 33) having a thickness of 0.001 to 0.5 μm (preferably 0.001 to 0.01 μm). At this time, since the third plating layer 33 is formed in a shape along the surface 32A of the second plating layer 32, the surface 33A of the third plating layer 33 is also roughened similarly to the second plating layer 32. The Therefore, the roughness of the surface 33 </ b> A of the third plating layer 33 is 50 to 500 nm in terms of the surface roughness Ra, similarly to the wiring pattern 20.

  In the present embodiment, the plating layer 30 is also formed on the first and second power supply lines 21 and 22 as in the case of the wiring pattern 20, but on the first and second power supply lines 21 and 22. The formation of the plating layer 30 may be omitted.

  Next, in the step shown in FIG. 6C, the insulating layer 40 having openings 40 </ b> X and 40 </ b> Y respectively corresponding to the mounting area CA and the electrode terminal 50 is formed on the substrate 10 and the plating layer 30. For example, after forming a resist layer to be the insulating layer 40 so as to cover the first main surface R1, the wiring pattern 20 and the power supply lines 21 and 22 of the substrate 10A, the resist layer is exposed and developed by a photolithography method, and the openings are formed. By forming 40X and 40Y, the insulating layer 40 can be formed. The insulating layer 40 can also be formed by, for example, a resin paste screen printing method. At this time, since the surface 33A (see FIG. 6B) of the third plating layer 33 which is the outermost layer of the plating layer 30 is roughened, the surface 33A of the third plating layer 33 and the insulating layer 40 Good adhesion can be obtained.

  In addition, by forming the insulating layer 40, it is possible to form a mounting area CA where the plating layer 30 formed on the wiring pattern 20 is exposed from the opening 40X. For this reason, after forming the insulating layer 40, it is not necessary to perform electrolytic plating or the like in order to improve the contact property. Thereby, deterioration of the plating solution used when forming the plating layer 30 can be suppressed. More specifically, after the insulating layer 40 is formed, when the plating method (electrolytic plating method or electroless plating method) is applied to the wiring pattern 20 exposed from the opening 40X, the plating used at that time is used. There is a problem that the resin material or the like contained in the insulating layer 40 is eluted with respect to the solution, causing deterioration of the plating solution and thereby shortening the life of the solution. On the other hand, according to the manufacturing method of the present embodiment, since the insulating layer 40 is not formed when the electrolytic plating method is performed, it is possible to prevent the above-described problem from occurring. That is, according to the manufacturing method of this embodiment, since deterioration of the plating solution can be suppressed, shortening of the life of the plating solution can be suppressed.

  Next, in the step shown in FIG. 7A, the groove 60 is formed so as to remove the second power supply line 22 shown in FIG. Specifically, as shown in FIG. 7B, the groove 60 includes the insulating layer 40 and the plating layer 30 facing the second power supply line 22 and the second power supply line 22 (see FIG. 6C). It penetrates in the thickness direction, and is formed so that the bottom surface of the groove part 60 is located in the middle of the thickness direction of the substrate 10A. As shown in FIG. 8, since this groove part 60 is formed in all the places (20 places in FIG. 8) in which the 2nd electric power feeding line 22 was formed, in this process, 20 groove parts 60 are formed. Thereby, all the 2nd electric power feeding lines 22 and the plating layer 30 formed on these 2nd electric power feeding lines 22 are removed, and board | substrate 10A is exposed in the area | region in which the groove part 60 was formed. By forming the groove 60, the first power supply line 21 and the wiring pattern 20 formed on the outer peripheral edge of the substrate 10A are separated, and the wirings D1 are separated. That is, the wirings D1 are electrically separated by the formation of the groove 60 (removal of the second power supply line 22). The groove 60 can be formed by, for example, router processing, laser processing, or die processing using a fine die.

  Subsequently, in the step shown in FIG. 7C, the insulating layer 40 and the substrate 10 at a portion corresponding to the cutting position B1 are cut by a dicing blade or the like. Thereby, the 1st electric power feeding line 21 is removed and the wiring board 1 shown in FIG. 1 is manufactured.

Next, a method for manufacturing the light emitting device 2 will be described with reference to FIG. FIG. 9 is a schematic cross-sectional view showing the state of the manufacturing process of the light emitting device at the position of line BB in FIG.
9A, the light emitting element 70 is mounted on the wiring pattern 20 (plating layer 30) formed in each mounting area CA of the wiring board 1 with an adhesive 71 interposed therebetween. Then, the electrode of the light emitting element 70 and the plating layer 30 are connected by the bonding wire 72, and the light emitting element 70 and the wiring pattern 20 are electrically connected. Specifically, one electrode of the light emitting element 70 is electrically connected to one plating layer 30 in the mounting area CA by the bonding wire 72, and the other electrode of the light emitting element 70 is connected to the other electrode in the mounting area CA. The plating layer 30 and the bonding wire 72 are electrically connected.

  Next, in a step shown in FIG. 9B, a sealing resin 75 for sealing the plurality of light emitting elements 70 and the bonding wires 72 mounted on the wiring board 1 is formed. For example, when a thermosetting resin is used as the sealing resin 75, the structure shown in FIG. 9A is accommodated in a mold, and pressure (for example, 5 to 10 MPa) is applied to the mold. Introduce fluidized resin. Thereafter, the sealing resin 75 is formed by heating and curing the resin at about 180 ° C., for example. At this time, as shown in FIG. 9B, the sealing resin 75 is also filled in the groove portion 60 of the wiring substrate 1. The sealing resin 75 can also be formed by potting liquid resin.

The light emitting device 2 shown in FIG. 3 is manufactured by the above manufacturing process.
(Evaluation of plating layer adhesion)
Next, the results of evaluating the relationship between the surface roughness of the surface 30A of the plating layer 30 and the adhesion of the insulating layer 40 to the plating layer 30 will be described with reference to FIG.

  First, five types of samples for evaluation were created. Specifically, in the samples of Examples 1 and 2 and Comparative Examples 1 and 2, the surface roughness is composed of a Ni plating layer, a Pd plating layer, and an Au plating layer on a copper plate having a surface roughness Ra value of 75 nm. A plating layer was formed. At this time, the surface roughness Ra value of the outermost layer of the plating layer, that is, the surface of the Au plating layer was adjusted to a different value for each sample by appropriately adjusting the Ni plating conditions. Specifically, as shown in FIG. 10, the surface roughness Ra value of the surface of the outermost layer in Example 1, Example 2, Comparative Example 1 and Comparative Example 2 was adjusted to 65 nm, 368 nm, 20 nm and 511 nm, respectively. doing. On the other hand, in the sample of Comparative Example 3, a copper plate having a surface roughness Ra value of 75 nm was prepared.

  And after screen-printing a white resist material on the outermost layer (Au plating layer in Examples 1 and 2 and Comparative Examples 1 and 2, and a copper plate in Comparative Example 3) of each sample, the white resist material is 150 minutes in an oven for 150 minutes. Heat-curing was performed by heating at 0 ° C. to form an insulating layer having a thickness of 30 μm. As the white resist material, an insulating material containing an organopolysiloxane resin, a silica filler, a titanium oxide filler, and a curing agent was used.

(Adhesion evaluation method)
About all the samples, the grid | lattice-like cut | notch was put in the insulating layer at intervals of 1 mm using the cutter, and the grid of 100 squares was created. Then, the adhesive tape was affixed on the grid of the insulating layer, and the adhesive tape was peeled off vigorously. At this time, the number of cells remaining without peeling was counted. And the adhesiveness of the insulating layer with respect to the plating layer was evaluated from the number of cells remaining without peeling. The result is shown in FIG. Here, if 10 or more squares out of 100 squares remain, it can be said that the insulating layer of the wiring board has adhesiveness that does not impede practically. On the other hand, if about 75 squares out of 100 remain, it can be said that it has sufficient adhesion as an insulating layer of the wiring board. In other words, even if the adhesion is further improved, it is not practical in view of the roughening processing time and processing time.

  As is apparent from the results of Examples 1 and 2 and Comparative Examples 1 and 2 shown in FIG. 10, the higher the surface roughness Ra value of the surface of the Au plating layer, the larger the number of cells remaining without peeling. That is, the adhesion with the insulating layer 40 is increased. Specifically, when the surface roughness Ra value of the Au plating layer is 20 nm as in Comparative Example 1, the number of cells remaining without peeling is 0, and the adhesion to the insulating layer is insufficient. It was. On the other hand, when the surface roughness Ra value of the Au plating layer is 65 nm as in the case of Example 1, 15 masses remain without being peeled off, and an adhesive having no practical problem as an insulating layer of the wiring board is obtained. Can do. Thus, by making the surface roughness Ra value of the Au plating layer 50 nm or more, the adhesion between the plating layer and the insulating layer is improved. Further, when the surface roughness Ra value of the Au plating layer is set to 368 nm as in Example 2, 48 masses remain without being peeled off and are equivalent to the case where an insulating layer is directly formed on the copper plate (see Comparative Example 3). Can be obtained. However, when the surface roughness Ra of the Au plating layer is 511 nm as in Comparative Example 2, 81 cells remain without peeling. Thus, when the surface roughness Ra value of the Au plating layer is 500 nm or more, it can be seen that the roughening treatment is excessive.

  In view of the above, from the viewpoint of adhesion to the insulating layer, roughening process, and processing time, the roughness of the outermost surface of the plating layer is preferably 50 nm or more and 500 nm or less in terms of the surface roughness Ra value.

As described above, according to this embodiment, the following effects can be obtained.
(1) A plating layer 30 is formed so as to cover the entire surface 20A of the wiring pattern 20, and a third plating layer 33 made of highly stable Au or Au alloy is formed on the outermost layer (outermost layer) of the plating layer 30. It was made to form. Thereby, the oxidation and discoloration of the surface 30A of the plating layer 30, the second plating layer 32, the first plating layer 31, and the wiring pattern 20 can be suitably suppressed. Therefore, oxidation and discoloration of the plating layer 30 and the wiring pattern 20 due to heat generated when the light emitting device 2 is used can be suppressed, and an increase in wiring resistance can be suppressed. As a result, it can suppress suitably that the luminous efficiency of the light emitting element 70 falls.

  (2) Further, after forming the plating layer 30 so as to cover the entire surface 20A of the wiring pattern 20, the insulating layer 40 covering a part of the plating layer 30 is formed. In this case, since the insulating layer 40 is not formed when the plating layer 30 is formed by the electrolytic plating method, it is possible to prevent the plating solution from being deteriorated due to the presence of the insulating layer 40. be able to. As a result, the life of the plating solution can be extended, and the plating solution can be used continuously. As a result, it can contribute to cost reduction.

  (3) By the way, in the wiring board 1 of this embodiment, the ratio of the area of the wiring pattern 20 to the area on the first main surface R1 of the board 10 is very large (for example, 70 to 80% or more is the wiring pattern 20). Area). For this reason, from the viewpoint of preventing peeling of the insulating layer 40 from the wiring substrate 1, it is important to improve the adhesion between the plating layer 30 formed on the wiring pattern 20 and the insulating layer 40. In this regard, in the wiring board 1 of the present embodiment, the surface 30A of the plating layer 30 (the surface 33A of the third plating layer 33) is roughened. Thereby, since the contact area of the plating layer 30 and the insulating layer 40 increases, the adhesiveness of the plating layer 30 and the insulating layer 40 can be improved. Therefore, it can suppress suitably that the insulating layer 40 peels from the wiring board 1. FIG.

  (4) Furthermore, the roughness of the surface 30A of the plating layer 30 (the surface 33A of the third plating layer 33) was set to 50 to 500 nm in terms of the surface roughness Ra value. Thereby, since favorable adhesiveness can be acquired between the plating layer 30 and the insulating layer 40, it can suppress more suitably that the insulating layer 40 peels from the wiring board 1. FIG.

  (5) The plating layer 30 includes a first plating layer 31 (Ni layer), a second plating layer 32 (Pd layer), and a third plating layer 33 (Au layer) formed on the surface 20A of the wiring pattern 20. A plating layer having a three-layer structure in which was sequentially laminated. By forming the third plating layer 33 made of Au as the outermost layer of the plating layer 30, as described above, it is possible to suppress the oxidation of the wiring pattern 20 and the plating layer 30, thereby obtaining good wire bonding properties. be able to. Further, since the second plating layer 32 made of Pd having a high barrier property is interposed between the first plating layer 31 made of Ni and the third plating layer 33 made of Au, Au and Ni caused by heat or the like Mutual diffusion can be suppressed.

  (6) The first to third plating layers 31 to 33 are formed by an electrolytic plating method. Thereby, manufacturing cost can be reduced rather than the case where the plating layer 30 is formed by the electroless plating method.

In addition, the said 1st Embodiment can also be implemented in the following aspects which changed this suitably.
As shown in FIG. 11, the groove 60 formed to remove the second power supply line 22 has the insulating layer 40, the plating layer 30, the second power supply line 22 (wiring pattern 20), and the substrate 10 in the thickness direction. You may form so that it may penetrate. That is, it is only necessary to form a groove so as to penetrate the insulating layer 40, the plating layer 30, and the second power supply line 22 in the thickness direction so that at least the second power supply line 22 is removed.

  As shown in FIG. 12, a metal layer 80 may be formed on the second main surface R2 (the lower surface in FIG. 12) of the substrate 10. For example, a metal plate formed in a flat plate shape can be used for the metal layer 80. As a material of the metal layer 80, for example, a metal having excellent thermal conductivity such as copper, aluminum, or iron can be used. The thickness of the metal layer 80 can be about 0.1 to 0.4 mm, for example. The metal layer 80 functions as a support plate for the wiring board 1 and also functions as a heat dissipation plate that dissipates heat generated when the light emitting element 70 emits light. Here, the light emission efficiency of the light emitting element 70 (light emitting diode) tends to decrease as the temperature rises. For this reason, by efficiently dissipating the heat generated from the light emitting element 70 by the metal layer 80, it is possible to suitably suppress a decrease in the light emission efficiency of the light emitting element 70.

(Second Embodiment)
Hereinafter, the second embodiment will be described with reference to FIGS. The wiring board 3 of this embodiment is different from the first embodiment in that the wiring pattern and the structure of the plating layer, and the metal layer 80 is formed on the second main surface R2 of the substrate 10. Hereinafter, the difference from the first embodiment will be mainly described. The same members as those shown in FIGS. 1 to 12 are denoted by the same reference numerals, and detailed description of these elements is omitted.

  As shown in FIG. 13A, a metal layer 80 is formed on the second main surface R2 of the substrate 10 (the lower surface in FIG. 13A). For example, a metal plate formed in a flat plate shape can be used for the metal layer 80. As a material of the metal layer 80, for example, a metal having excellent thermal conductivity such as copper, aluminum, or iron can be used. The thickness of the metal layer 80 can be about 0.1 to 0.4 mm, for example.

  As shown in FIG. 13 (b), the wiring pattern 25 formed on the first main surface R1 (upper surface in FIG. 13 (b)) of the substrate 10 has a smooth surface with less unevenness on the surface 25A (upper surface and side surfaces). Is formed. Since the planar shape of the wiring pattern 25 is the same as that of the wiring pattern 20 of the first embodiment, the illustration thereof is omitted.

  A three-layer structure in which a first plating layer (rough surface plating layer) 36 having a roughened surface, a second plating layer 37, and a third plating layer 38 are sequentially laminated on the surface 25A of the wiring pattern 25. The plating layer 35 is formed. Here, in the present embodiment, the first plating layer 36 is a nickel (Ni) plating layer, the second plating layer 37 is a palladium (Pd) plating layer, and the third plating layer 38 is a gold (Au) plating layer. In addition, these 1st-3rd plating layers 36-38 can be formed by the electroplating method, for example.

  The surface (roughened surface) 36A of the first plating layer 36 is formed in a fine uneven shape. The roughness of the roughened surface 36A is set to be, for example, a surface roughness Ra value of 50 nm or more. Specifically, the roughness of the roughened surface 36A is determined by adjusting the surface roughness Ra value by adjusting the composition, current density, etc. of the plating solution used when the first plating layer 36 is formed by the electrolytic plating method. Is set to 50 to 500 nm. The first plating layer 36 takes into consideration the characteristics such as the diffusion preventing effect of Cu contained in the wiring pattern 25, the corrosion resistance effect preventing corrosion of the wiring pattern 25, and the adhesion to the second plating layer 37 made of Pd. Thus, the material composition and thickness are set. As a material of the first plating layer 36, for example, Ni or Ni alloy can be used. Moreover, the thickness of the 1st plating layer 36 has the preferable range of 0.05 micrometer or more and 5.00 micrometers or less, and the range of 0.1 micrometer or more and 2.00 micrometers or less is more preferable from a viewpoint of the said characteristic and manufacturing cost.

  The second plating layer 37 serves to prevent mutual diffusion between Ni contained in the first plating layer 36 and Au contained in the third plating layer 38 due to heat, for example. As a material of the second plating layer 37 for realizing such a function, for example, Pd or a Pd alloy can be used. The thickness of the second plating layer 37 is preferably in the range of 0.001 μm or more and 0.5 μm or less in order to suppress the mutual diffusion while reducing the thickness as much as possible from the viewpoint of manufacturing cost. A range of 0.03 μm or less is more preferable. The surface 37A (upper surface and side surface) of the second plating layer 37 is roughened in the same manner as the first plating layer 36, and a fine uneven shape is formed. The roughness of the surface 37A of the roughened second plating layer 37 is set, for example, to be 50 to 500 nm as a surface roughness Ra value.

  The third plating layer 38 plays a role of improving contact properties (wire bonding property and soldering property) while preventing oxidation of the plating layer 35 and the wiring pattern 25 during heating, for example. The material of the third plating layer 38 for realizing such a function is preferably a metal that is harder to oxidize than the wiring pattern 25 (copper) and has a low hardness, such as a noble metal such as Au or Ag, or the like. A noble metal alloy containing at least one of these metals can be used. The thickness of the third plating layer 38 is preferably in the range of 0.001 μm or more and 0.5 μm or less in order to improve the contact property while reducing the thickness as much as possible from the viewpoint of manufacturing cost. A range of 01 μm or less is more preferable. The surface 38A (upper surface and side surface) of the third plating layer 38 is roughened in the same manner as the second plating layer 37, and a fine uneven shape is formed. The roughness of the surface 38A of the roughened third plating layer 38 is set to be, for example, 50 to 500 nm in terms of the surface roughness Ra value. Thereby, the adhesiveness of the 3rd plating layer 38 and the insulating layer 40 formed on the 3rd plating layer 38 can be increased rather than the case where the surface 38A of the 3rd plating layer 38 is a smooth surface. .

  Further, a groove 61 is formed in the wiring board 3. The groove 61 is formed from the upper surface of the insulating layer 40 to the middle of the thickness of the metal layer 80 through the insulating layer 40, the plating layer 35, the wiring pattern 25 and the substrate 10. The groove 61 is formed in order to remove the power feeding line 22 for plating power feeding (see FIG. 14B) used in the manufacturing process of the wiring board 3.

(Method for manufacturing a wiring board)
Next, a method for manufacturing the wiring board 3 will be described.
First, in order to manufacture the wiring substrate 3, as shown in FIG. 14A, a structure is prepared in which a single-sided copper-clad substrate with a copper foil 25B attached to one side of the substrate 10A is bonded to the metal layer 80A. To do. Here, the substrate 10A is the substrate 10 shown in FIG. 13 by being finally cut at the cutting position B1. Further, the metal layer 80A is finally cut at the cutting position B1 to become the metal layer 80 shown in FIG.

  Next, in the step shown in FIG. 14B, similarly to the steps shown in FIG. 4B and FIG. 4C, the first main surface R1 (the upper surface in FIG. 14B) of the substrate 10A is formed. The formed copper foil 25B is patterned into a predetermined shape. Thereby, the required wiring pattern 25 and the first and second power supply lines 21 and 22 are formed on the first main surface R1 of the substrate 10A. In the following description, the wiring pattern 25 and the first and second power supply lines 21 and 22 are collectively referred to as a wiring layer 26.

  14C, the surface 25A of the wiring pattern 25 is subjected to electrolytic plating using the wiring layer 26 as a plating power supply layer, and the surface 25A (upper surface and side surfaces) of the wiring pattern 25 is subjected to 3 A plating layer 35 having a layer structure is formed.

  Specifically, as shown in FIG. 14D, first, a first plating layer (rough surface plating layer) 36 whose surface is a roughened surface 36A is formed on the surface 25A of the wiring pattern 25. Here, the surface roughness of the roughened surface 36A is preferably in the range of 50 to 500 nm in terms of the surface roughness Ra value. However, in order to set such roughness, it is necessary to appropriately adjust the composition and current density of the plating solution to be used as described above. Below, an example of the plating conditions at the time of forming the rough surface plating layer 36 comprised from Ni is demonstrated. Specifically, the composition and plating conditions of the plating bath when using a nickel chloride plating bath as the plating solution are as follows.

Nickel chloride plating bath:
Nickel chloride 75g / L
Sodium thiocyanate 15g / L
Ammonium chloride 30g / L
Boric acid 30g / L
pH: about 4.5 to 5.5
Bath temperature: Room temperature (about 25 ° C)
Processing time: about 1-30 minutes Cathode current density: about 1-3 A / dm ²
Thus, the surface 36A of the first plating layer 36 is roughened by appropriately adjusting the composition and current density of the plating solution used in advance, and the roughness of the roughened surface 36A is set to a desired surface roughness. Can be set in degrees. In addition, the composition and plating conditions of the plating solution described above are examples, and the composition and conditions are not particularly limited as long as the roughened surface 36A of the first plating layer 36 is adjusted to have a desired roughness. .

  Next, Pd plating is performed on the first plating layer 36 to form a Pd layer (second plating layer 37) having a thickness of 0.001 to 0.5 μm (preferably 0.005 to 0.03 μm). At this time, since the second plated layer 37 is formed in a shape along the roughened surface 36A of the first plated layer 36, the surface 37A of the second plated layer 37 is also roughened like the first plated layer 36. It becomes. Hereinafter, an example of the composition of the plating bath and the plating conditions when forming the second plating layer 37 made of Pd will be described.

Pd plating bath:
Dinitrotetraamminepalladium 10g / L
Ammonium citrate 150 g / L
Stress relaxation agent Crystal modifier pH: about 7.5 to 8.5
Bath temperature: about 50 ° C
Processing time: about 2 to 10 seconds Cathode current density about 1 to 3 A / dm ²
Subsequently, Au plating is performed on the second plating layer 37 to form an Au layer (third plating layer 38) having a thickness of 0.001 to 0.5 μm (preferably 0.001 to 0.01 μm). At this time, since the third plating layer 38 is formed in a shape along the surface 37A of the second plating layer 37, similarly to the second plating layer 37, the surface 38A of the third plating layer 38 is also roughened. The Therefore, the roughness of the surface 38A of the third plating layer 38 is 50 to 500 nm in terms of the surface roughness Ra, similarly to the roughened surface 36A of the first plating layer 36. Hereinafter, an example of the composition of the plating bath and the plating conditions when forming the third plating layer 38 made of Au will be described.

Au plating bath:
Potassium cyanide potassium 10g / L
Potassium citrate 100g / L
Substitution inhibitor Brightening agent pH: about 5.5 to 6.5
Bath temperature: about 50 ° C
Treatment time: about 2-20 seconds Cathode current density: about 0.5-1 A / dm ²
15A, the insulating layer 40 having openings 40X and 40Y corresponding to the mounting area CA and the electrode terminals 50 is formed on the substrate 10A and the plating layer 35. At this time, since the surface 38A of the third plating layer 38 which is the outermost layer of the plating layer 35 is roughened, good adhesion between the third plating layer 38 and the insulating layer 40 can be obtained. .

  Next, in the step shown in FIG. 15B, the groove 61 is formed so as to remove the second power supply line 22 shown in FIG. Specifically, the groove 61 penetrates the insulating layer 40 and the plating layer 35 facing the second power supply line 22, the second power supply line 22, and the substrate 10A in the thickness direction, and the bottom surface of the groove 61 is the metal layer 80A. It is formed so as to be located in the middle of the thickness direction. Thereby, the 2nd electric supply line 22 is removed. The groove 61 can be formed by, for example, router processing, laser processing, or mold processing using a fine mold.

  Subsequently, in the step shown in FIG. 15C, the insulating layer 40, the substrate 10A, and the metal layer 80A at a portion corresponding to the cutting position B1 are cut by a dicing blade or the like. Thereby, the 1st electric power feeding line 21 is removed and the wiring board 3 shown in FIG. 13 is manufactured.

According to the embodiment described above, the following effects are obtained in addition to the effects (1) to (6) of the first embodiment.
(7) The metal layer 80 is formed on the second main surface R2 of the substrate 10. By efficiently dissipating the heat generated from the light emitting element 70 by the metal layer 80, a decrease in the light emission efficiency of the light emitting element 70 can be suitably suppressed.

In addition, the said 2nd Embodiment can also be implemented in the following aspects which changed this suitably.
As shown in FIG. 16, instead of the groove 61 formed to remove the second power supply line 22, the insulating layer 40, the plating layer 35, the second power supply line 22 (wiring pattern 25), the substrate 10 and the metal A groove 61A that penetrates the layer 80 in the thickness direction may be formed.

  As shown in FIG. 17, the side surfaces of the wiring pattern 25 and the plating layer 35 exposed by the formation of the groove portion 61A, that is, the side surfaces of the wiring pattern 25 and the plating layer 35 that also become the side surfaces of the groove portion 61A are removed. You may do it. Specifically, a part of the side surfaces of the wiring pattern 25 and the plating layer 35 may be removed so that the side surfaces thereof are in a position retracted into the substrate 10 from the side surface of the groove 61A. Thereby, even when the thickness of the substrate 10 is thin, the distance between the wiring pattern 25 and the plating layer 35 and the metal layer 80 is widened, so that they are preferably electrically connected (short-circuited). Can be suppressed.

  The wiring pattern 25 and the plating layer 35 as described above can be removed by etching, for example. As the etching, for example, partial etching by masking using rubber or the like can be used. According to this partial etching, etching can be performed only on the periphery of the groove 61A, and therefore selective to a desired portion (here, the wiring pattern 25 and the plating layer 35 exposed by the formation of the groove 61A). Etching can be performed.

Although the case where the groove portion 61A is formed has been described here, the same processing may be performed when the groove portions 60 and 61 are formed.
-You may abbreviate | omit the metal layer 80 in the said 2nd Embodiment.

(Other variations)
In addition, each said embodiment can also be implemented in the following aspects which changed this suitably.
In each of the above embodiments, the light emitting element 70 is wire-bonded and mounted on the plating layers 30 and 35 formed so as to cover the wiring patterns 20 and 25 formed on the substrate 10. For example, as shown in FIGS. 18A and 18B, the light emitting element 90 may be flip-chip mounted on the plating layers 30 and 35. In this case, the light emitting element 90 is mounted on the plating layers 30 and 35 formed on both sides of the openings 20X and 25X so as to straddle the openings 20X and 25X formed in the mounting area CA. Specifically, one bump 91 formed on the circuit formation surface (the lower surface in FIG. 18) of the light emitting element 90 is flip-chip connected to one plating layer 30, 35 in the mounting area CA, and the other bump 91 is The other plating layers 30 and 35 in the mounting area CA are flip-chip connected.

  As shown in FIG. 19, a recess 10X may be formed in the mounting area CA of the substrate 10, and the light emitting element 90 may be mounted in the recess 10X. In this case, the wiring pattern 20 is formed in the recess 10X, the plating layer 30 is formed so as to cover the surface 20A of the wiring pattern 20, and the insulating layer 40 is formed so as to cover the plating layer 30 other than the mounting area CA. To do. And the light emitting element 90 is mounted on the plating layer 30 formed in the bottom face of the recessed part 10X. In FIG. 19, the light emitting element 90 is flip-chip mounted. However, the light emitting element may be mounted by wire bonding.

  In each of the above-described embodiments, the outermost plating layers 33 and 38 of the plating layers 30 and 35 are arranged such that part of the surfaces 32A and 37A of the lower plating layers 32 and 37 are exposed. It may be formed in a distributed manner on the surfaces 32A, 37A of 37.

  In the above embodiments, the layer configuration of the plating layers 30 and 35 may be changed as appropriate. For example, a fourth plating layer made of Ag or an Ag alloy may be formed between the second plating layers 32 and 37 and the third plating layers 33 and 38. Further, the first plating layers 31 and 36 made of Ni or Ni alloy and the third plating layers 33 and 38 made of Au or Au alloy may be formed on the wiring patterns 20 and 25. That is, the second plating layers 32 and 37 may be omitted.

  Moreover, on the wiring patterns 20 and 25, the 1st plating layers 31 and 36 which consist of Ni or Ni alloy, the 2nd plating layers 32 and 37 which consist of Pd or Pd alloy, and the 4th plating layer which consists of Ag or Ag alloy And may be formed. That is, a fourth plating layer may be formed instead of the third plating layers 33 and 38. Further, the first plating layers 31 and 36 made of Ni or Ni alloy and the fourth plating layer made of Ag or Ag alloy may be formed on the wiring patterns 20 and 25. Alternatively, only one fourth plating layer made of Ag or an Ag alloy may be formed on the wiring patterns 20 and 25. As described above, when the outermost layer of the plating layers 30 and 35 is a fourth plating layer made of Ag or an Ag alloy, Ag has a higher light reflectance than Au, so that the luminous efficiency as a light emitting device is improved. Can be improved.

  In each of the above embodiments, the plating layers 30 and 35 are formed by the electrolytic plating method. However, the present invention is not limited to this. For example, the plating layers 30 and 35 may be formed by the electroless plating method. In this case, since it is not necessary to form the power supply lines 21 and 22, the grooves 60 and 61 can be omitted.

The planar shape of the opening 40X in each of the above embodiments is not limited to a circular shape, and may be a polygonal shape such as a rectangular shape, a pentagon, or a hexagon.
In each of the above embodiments, an example is shown in which one wiring substrate 1 or 3 is formed on the substrate 10A. However, a member to be a plurality of wiring substrates 1 and 3 is formed on the substrate 10A, and the members are separated into pieces. The process may be changed to obtain a plurality of wiring boards 1 and 3.

  -The number and arrangement of the light emitting elements 70 and 90 in each of the above embodiments are not particularly limited. Further, the shape of the wiring patterns 20 and 25 in each of the above embodiments is not particularly limited. For example, the wiring pattern may be changed as shown in FIG. That is, a plurality of strip-shaped wiring patterns 24 may be arranged adjacent to each other in parallel. In this case, a groove-like opening 24 </ b> X exposing the lower substrate 10 is formed between the adjacent wiring patterns 24. The plurality of wiring patterns 24 are electrically separated from each other by the opening 24X. The electrode terminals 50 are respectively formed on the wiring patterns 24 formed on the outside. When a light emitting element is mounted on a wiring board having such wiring patterns 24 and electrode terminals 50, a plurality of light emitting elements are connected in parallel and in series.

1,3 Wiring board (light emitting device wiring board)
2 Light emitting device 10 Substrate 20, 24, 25 Wiring pattern 21, 22 Feed line 23, 26 Wiring layer 30, 35 Plating layer 31, 36 First plating layer 32, 37 Second plating layer 33, 38 Third plating layer (most Outer plating layer)
40 Insulating layer 60, 61, 61A Groove 70, 90 Light emitting element 75 Sealing resin 80 Metal layer

Claims (12)

A substrate,
A wiring pattern formed on the first main surface of the substrate;
A plating layer formed to cover the surface of the wiring pattern;
Covering the wiring pattern in which the plating layer is formed, and having an insulating layer formed on the first main surface,
In the insulating layer, an opening that exposes a part of the wiring pattern in which the plating layer is formed as a mounting region of the light emitting element is formed,
The said plating layer has the outermost plating layer which consists of a noble metal or a noble metal alloy in an outermost layer, The wiring board for light-emitting devices characterized by the above-mentioned.   The wiring board for a light-emitting device according to claim 1, wherein a surface of the plating layer is roughened.   The wiring board for a light-emitting device according to claim 2, wherein the surface roughness Ra of the plating layer is 50 to 500 nm in terms of surface roughness Ra.   The surface of the wiring pattern is roughened, and the surface of the plating layer is roughened by providing the plating layer along the surface of the roughened wiring pattern. Item 4. A wiring board for a light-emitting device according to Item 2 or 3.   The plating layer is formed by sequentially laminating a first plating layer made of Ni or Ni alloy formed on the surface of the wiring pattern, a second plating layer made of Pd or Pd alloy, and the outermost plating layer. The wiring substrate for a light-emitting device according to claim 1, wherein the wiring substrate is a light-emitting device.   The plating layer is formed on a surface of the wiring pattern, the first plating layer made of Ni or Ni alloy having a roughened surface, the second plating layer made of Pd or Pd alloy, and the outermost plating layer. The wiring board for a light emitting device according to claim 2 or 3, wherein and are laminated in order.   The wiring board for a light-emitting device according to claim 1, wherein a groove that penetrates at least the insulating layer, the plating layer, and the wiring pattern in the thickness direction is formed.   The wiring board for a light-emitting device according to claim 1, wherein a metal layer is formed on a second main surface opposite to the first main surface of the substrate. . A substrate,
A wiring pattern formed on the first main surface of the substrate;
A plating layer formed to cover the surface of the wiring pattern;
An insulating layer that covers the wiring pattern in which the plating layer is formed, is formed on the first main surface, and is formed with an opening that exposes a part of the wiring pattern in which the plating layer is formed;
A light emitting device mounted on the plating layer exposed from the opening;
A sealing resin formed to seal the light emitting element,
The said plating layer has the outermost plating layer which consists of a noble metal or a noble metal alloy in an outermost layer, The light-emitting device characterized by the above-mentioned. Forming a wiring layer including a power supply line for electrolytic plating and a wiring pattern on the first main surface of the substrate;
A step of forming a plating layer on the entire surface of the wiring pattern by an electrolytic plating method using the wiring layer as a power feeding layer;
Forming an insulating layer covering the wiring pattern on which the plating layer is formed on the first main surface;
Forming an opening in the insulating layer that exposes a part of the wiring pattern in which the plating layer is formed as a mounting region of a light emitting element;
A method of manufacturing a wiring board for a light emitting device, comprising:   The method for manufacturing a wiring board for a light-emitting device according to claim 10, further comprising a step of forming a groove portion that penetrates the insulating layer, the plating layer, and the power supply line.   The method for manufacturing a wiring substrate for a light emitting device according to claim 11, further comprising a step of removing a part of the plating layer and the wiring pattern which are side surfaces of the groove.