JP2013061703A - Substrate mounted circuit including slave substrate connector - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a substrate mounted circuit including a slave substrate connector which can prevent erroneous detection due to an external factor such as static electricity, and also accurately determine whether the slave substrate is being inserted or extracted, at low costs without requiring complicated operations of a user.SOLUTION: When an insertion/extraction detection circuit, which detects whether a slave substrate is inserted in a slave substrate connector on the basis of the voltage of electrode terminals of the slave substrate connector, detects that the slave substrate has changed its state from a state inserted to the slave substrate connector to a state not inserted to the slave substrate connector, a substrate mounted circuit first transmits a read-out instruction to read out fixed data stored in a register mounted on the slave substrate via the slave substrate connector. At this time, if the fixed data cannot be read out from the register, the substrate mounted circuit determines that the slave substrate is extracted from the slave substrate connector, and if the fixed data can be read out from the register, the substrate mounted circuit determines that the slave substrate is inserted in the slave substrate connector.

Description

  The present invention relates to a board mounted circuit having a sub board connector into which a sub board is inserted.

  A computer board (hereinafter referred to as a parent board) equipped with a CPU (Central Processing Unit) is provided with a slot for connecting a subsidiary board such as various auxiliary boards or wireless cards to the CPU bus later. Exists. Also, as such a parent substrate, a so-called hot-wire insertion / removal substrate is known in which a child substrate can be inserted / removed while being energized.

  By the way, when a child board is inserted into and removed from the energized parent board, the noise generated due to the contact between the electrodes at the time of insertion / removal is superimposed on the CPU bus, resulting in a malfunction in the operation of the parent board and the child board. There was a risk of occurrence.

  Therefore, when the child board is removed from the parent board, the CPU is interrupted by operating a switch provided on the parent board side, and the CPU bus is forcibly set to a high impedance state by this interrupt processing. There has been proposed a substrate active insertion / extraction system that eliminates the influence of noise generated during extraction (see, for example, Patent Document 1). In such a board active insertion / removal method, when inserting a child board into the parent board, the CPU bus is forcibly connected by connecting a power connector to the parent board for forcibly setting the CPU bus to a high impedance state. The high impedance state is set to eliminate the influence of noise that occurs during insertion.

  However, such a substrate hot insertion / removal method has a problem in that a switch and wiring for interrupting the removal work must be provided to the CPU, which increases the manufacturing cost on the parent substrate side. In addition, when this function is added to a parent board that does not have the above-described board active insertion / removal function, a hardware change occurs, so that a quick addition cannot be performed. In addition, every time the user performs a removal operation for removing the child board from the parent board, the user must manually perform a switch operation for interrupting the CPU.

  Furthermore, in such a board | substrate active insertion / extraction system, it is made to detect by the voltage level of the electrode provided in the parent board | substrate side whether the above-mentioned power supply connector is connected to the parent board | substrate. Therefore, an external factor that an overcurrent due to static electricity or the like flows into this electrode causes the voltage level to fluctuate greatly, resulting in a problem that the insertion and removal states of the power connector cannot be detected correctly. If an electrostatic protection circuit is provided on the parent substrate side in order to eliminate such a problem, the manufacturing cost on the parent substrate side increases.

JP 05-127777 A

The present invention does not require a troublesome operation from the user side, and at a low cost, while preventing erroneous detection due to external factors such as static electricity, the child board is in any of the inserted and removed states. An object of the present invention is to provide a board-mounted circuit including a sub board connector capable of accurately determining whether or not.

  A board mounting circuit including a sub board connector according to the present invention is a board mounting circuit including a sub board connector, and a sub board is inserted into the sub board connector based on a voltage of an electrode terminal of the sub board connector. An insertion / extraction detection circuit that generates a detection signal indicating whether or not the control board is included, and a control section that determines whether or not the sub board has been removed from the sub board connector based on the detection signal, the control section Is a register stored in advance in a register mounted on the child board when the detection signal indicates that the child board has transitioned from the inserted state to the not inserted state in the child board connector. Register read command sending means for sending a read command to be read through the slave board connector, and reading the fixed data from the register in spite of sending the read command. If it is not possible to determine that the sub board has been removed from the sub board connector, if the fixed data can be read, the sub board is inserted into the sub board connector. Insertion / extraction determination means for determining.

  In the present invention, the child board is inserted by the insertion / extraction detection circuit that detects whether or not the child board is inserted into the child board connector based on the voltage of the electrode terminal of the child board connector provided on the parent board side. When it is detected that the state has changed to the uninserted state, the following insertion / extraction determination is performed. That is, when a read command for reading fixed data stored in advance in a register mounted on the slave board is sent through the slave board connector, if the fixed data cannot be read, the slave board It is determined that the slave board has been removed from the connector. On the other hand, when the fixed data can be read, it is determined that the slave board is inserted into the slave board connector.

  According to such insertion / removal determination, it is possible to determine whether or not the child board is inserted into the parent board without providing a switch and wiring for interrupting the insertion / removal operation for the CPU on the parent board side. It becomes. Furthermore, since the result of access to the register mounted on the child board side along with the detection result of the insertion / extraction detection circuit is used as a condition for determining whether or not the child board is inserted into the parent board, the protection circuit Therefore, it is possible to eliminate the influence of erroneous detection caused by application of an overcurrent due to static electricity or the like to the insertion / extraction detection electrode terminal of the sub board connector.

  Therefore, according to the present invention, it is possible to accurately determine whether the daughter board is in the inserted or removed state without requiring a troublesome operation from the user and at a low cost. .

It is a block diagram which shows schematic structure of the main board | substrate containing the board | substrate mounting circuit provided with the sub board | substrate connector which concerns on this invention, and the sub board | substrate inserted in a sub board | substrate connector. It is a block diagram which shows the whole structure of the program memorize | stored in ROM13 shown by FIG. It is a flowchart which shows the flow of the insertion / extraction process in the insertion / extraction processing program 132 shown by FIG. It is a flowchart which shows the flow of the insertion / extraction process in the insertion / extraction processing program 132 shown by FIG. It is a block diagram which shows another example of schematic structure of a parent board | substrate and a child board | substrate. It is a block diagram which shows the whole structure of the program memorize | stored in ROM13 shown by FIG. It is a flowchart which shows the flow of the insertion / extraction process in the insertion / extraction processing program 132 shown by FIG. It is a flowchart which shows the flow of the insertion / extraction process in the insertion / extraction processing program 132 shown by FIG. It is a figure which shows an example of the log information recorded on RAM15.

  The board mounting circuit provided with the sub board connector according to the present invention detects whether or not the sub board (2) is inserted into the sub board connector based on the voltage of the electrode terminal of the sub board connector (11). When it is detected by the circuit (12) that the slave board has transitioned from the state inserted in the slave board connector to the non-inserted state (S1 to S5), first, the register (22) mounted on the slave board A read command for reading out the fixed data stored in () is sent through the sub-board connector (S12). At this time, if the fixed data cannot be read from the register, it is determined that the sub board is removed from the sub board connector (S103). If the fixed data can be read, the sub board is connected to the sub board connector. Is determined to have been inserted (S105).

  FIG. 1 is a block diagram schematically showing a mother board as a board-mounted circuit provided with a child board connector according to the present invention and a child board inserted into the child board connector of the mother board.

FIG. 1 shows a state in which the sub board 2 is inserted into the sub board connector 11 provided on the main board 1. The sub board 2 is provided with a radio transmission / reception unit 21, a register 22, and a data bus 200. The wireless transmission / reception unit 21 performs a wireless communication operation according to a wireless communication control command supplied from the parent substrate 1 side via the data bus 200. At this time, the wireless transmission / reception unit 21 wirelessly transmits data supplied from the parent substrate 1 side via the data bus 200 and transmits the wirelessly received data to the parent substrate 1 side via the data bus 200.
The register 22 stores various control data necessary for executing the wireless communication operation by the wireless transmission / reception unit 21. For example, the register 22 stores in advance fixed data such as a device ID and a vendor code for identifying the child board 2. Further, in the register 22, various parameter information necessary for controlling the wireless transmission / reception unit 21 from the parent board 1 side, and status data indicating the state of the wireless communication operation by the child board 2 at the present time (for example, at the present time) Communication buffer size information indicating the buffer size of the wireless communication) is sequentially updated and stored.

  The main board 1 includes a sub board connector 11 for connecting the sub board 2 to the main board 1, an insertion / removal detection circuit 12, a ROM (Read Only Memory) 13, a CPU (Central Processing Unit) 14, and a RAM (Random Access Memory). ) 15 is provided. The RAM 15 stores an access prohibition flag (described later) indicating whether or not access to the register 22 of the slave board 2 is prohibited. As an initial value of the access prohibition flag, the RAM 15 stores a logical level 0 value indicating access permission. Further, the master board 1 is provided with a data bus 100 for the CPU 14 to access the slave board connector 11, the ROM 13 and the RAM 15.

  The sub board connector 11 is provided with a plurality of electrode terminals (not shown) connected to the plurality of bit lines in the data bus 100. When the sub board 2 is inserted into the sub board connector 11, the electrode terminals connected to the bit lines of the data bus 200 of the sub board 2 come into contact with the electrode terminals of the sub board connector 11. Thereby, the data bus 100 of the parent substrate 1 and the data bus 200 of the child substrate 2 are electrically connected. Further, the child board connector 11 is maintained at a high voltage (for example, 3.3 volts) when the child board 2 is not inserted. On the other hand, when the child board 2 is inserted, An electrode terminal (not shown) for detection of insertion / removal that is brought into a low voltage (for example, 0 volt) state by contacting an electrode terminal connected to a ground line (not shown) is provided.

  The insertion / removal detection circuit 12 detects whether or not the child board 2 is inserted based on the voltage of the insertion / removal detection electrode terminal of the child board connector 11. At this time, when the voltage at the electrode terminal for insertion / removal detection is a high voltage (for example, 3.3 volts), the insertion / removal detection circuit 12 inserts / removes logic level 1 indicating that the child board 2 is not inserted. A detection signal IT is supplied to the CPU 14. On the other hand, when the voltage at the insertion / extraction detection electrode terminal is a low voltage (for example, 0 volts), a logic level 0 insertion / removal detection signal IT indicating that the daughter board 2 is in the insertion state is supplied to the CPU 14.

  As shown in FIG. 2, the ROM 13 includes a main program 130 that controls the main operation of the parent board 1, a wireless communication program 131 for performing wireless communication control for the wireless transmission / reception unit 21 mounted on the child board 2, and Is stored in advance. Further, the ROM 13 stores an insertion / extraction processing program 132 for determining whether the sub-board 2 is in the inserted state or the non-inserted state, and protecting the operation of the board corresponding to the state.

  The insertion / extraction processing program 132 includes a slave board register read / write API (Application Program Interface) 31, an interrupt handler 32, an insertion / extraction state read command API (Application Program Interface) 33, and a hot-line insertion / extraction task 34. The slave board register read / write API 31 reads and writes various data (described later) via the data buses 100 and 200 with respect to the register 22 of the slave board 2 inserted into the slave board connector 11. The interrupt handler 32 operates with priority over the wireless communication program 131, and is activated when the child board 2 is inserted or removed to occupy the CPU. The insertion / extraction state read command API 33 is used when acquiring information indicating whether or not the child board 2 is inserted into the child board connector 11. The hot-swap task 34 is a non-resident task activated by the interrupt handler 32, and when other processing occurs during the task processing, the CPU 14 is surrendered and enters a standby state.

  Here, when the daughter board 2 is removed from the daughter board connector 11 of the parent board 1 that is energized, the voltage of the insertion / extraction detection electrode terminal of the daughter board connector 11 changes from a low voltage state to a high voltage state. As a result, the insertion / extraction detection circuit 12 supplies the CPU 14 with an insertion / extraction detection signal IT that transitions from the logic level 0 to 1. In response to the insertion / extraction detection signal IT, the CPU 14 suspends the execution of the wireless communication program 131 and activates the interrupt handler 32, and proceeds to the execution of the insertion / extraction processing program 132.

  3 and 4 are flowcharts showing an insertion / extraction processing flow in the insertion / extraction processing program 132.

  First, the CPU 14 activates the interrupt handler 32 and rewrites the content of the access prohibition flag stored in the RAM 15 to a logic level 1 indicating that access to the register 22 of the child board 2 is prohibited (step S1). . While the access prohibition flag is at logic level 1, access to the register 22 by execution of the wireless communication program 131 is prohibited. As a result, inconveniences caused when communication control is performed on the child board 2 in parallel with the execution of the insertion / extraction processing program 132 are avoided.

  Next, the CPU 14 ends the interrupt handler 32 and activates the hot-swap task 34. When an interrupt request is generated by the wireless communication program 131 during execution of steps S2 to S19 by the hot-swap task 34 described below, the CPU 14 temporarily interrupts the processing by the hot-swap task 34. The wireless communication program 131 is preferentially executed.

  With the activation of the hot-swap task 34, the CPU 14 first starts a time counting operation using a built-in timer (not shown) (step S2), and whether the measured time has passed a chattering wait period TCH (for example, 200 msec). The determination of whether or not is repeated until it is determined that it has passed (step S3). That is, it waits for the amount of time that will be spent from the removal of the sub board 2 from the sub board connector 11 until the chattering ends, that is, the chattering wait period TCH. If it is determined in step S3 that the chattering wait period TCH has elapsed, the CPU 14 takes in the insertion / extraction detection signal IT again (step S4), and the insertion / extraction detection signal IT is at a logic level 1 indicating that the sub-board 2 is not inserted. It is determined whether or not there is (step S5).

  Here, it is detected by the insertion / extraction detection circuit 12 that the child board 2 has been removed from the child board connector 11, and the child board 2 is moved to the child board in step S5 even though the chattering weight period TCH has elapsed. If it is determined that the connector 11 is in the inserted state, it is considered that the voltage at the insertion / extraction detection electrode terminal of the sub board connector 11 is in an unstable state due to some external factor.

  Therefore, when it is determined in step S5 that the insertion / extraction detection signal IT is not at the logic level 1, that is, when it is determined that the child board 2 is inserted into the child board connector 11, the following step S6 is performed. ˜S9 is executed. That is, the CPU 14 restarts the time counting operation by the built-in timer (step S6) until it is determined that the time measured by the built-in timer has passed the chattering wait period TCH. Repeatedly (step S7). When it is determined in step S7 that the chattering wait period TCH has elapsed, the CPU 14 takes in the insertion / extraction detection signal IT again (step S8), and the insertion / extraction detection signal IT indicates a logical level indicating that the child board 2 is not inserted. It is determined whether or not 1 (step S9). That is, initially, it is detected that the child board 2 has been removed from the child board connector 11 based on the insertion / removal detection signal IT, but the child board 2 is inserted in the insertion / removal process executed accordingly. If it is determined (S5) that there is an error, there may be a temporary error in the insertion / removal detection result due to the application of an overcurrent due to static electricity or the like to the insertion / removal detection electrode terminal of the child board connector 11. . Therefore, if it is determined that the child board 2 is inserted (S5), whether the child board 2 is not inserted again after the chattering weight period TCH (after execution of S7) continues. It is determined whether or not (S9).

  Here, if it is determined in step S9 that the insertion / extraction detection signal IT is not at the logic level 1, that is, if it is determined that the child board 2 is inserted into the child board connector 11, the CPU 14 Then, the access prohibition flag stored in the RAM 15 is rewritten to a logical level 0 indicating that access to the register 22 of the child board 2 is permitted (step S10). After execution of step S10, the CPU 14 ends the insertion / extraction processing program 132 and restarts execution of the suspended wireless communication program 131.

  That is, if it is determined that the child board 2 is still inserted into the child board connector 11 even after the time twice as long as the chattering weight period TCH has passed (S2 to S9), the child board 2 is originally a child board. It is determined that the connector is not removed from the board connector 11, and the communication operation is resumed. In short, in the transition from the logic level 0 to 1 of the insertion / extraction detection signal IT that became the trigger for executing the insertion / extraction processing program 132, an overcurrent due to static electricity or the like was applied to the insertion / extraction detection electrode terminal of the child board connector 11. It is only a temporary thing caused by this, and it is judged that the child board 2 is actually inserted into the child board connector 11, and the wireless communication operation by the child board 2 is resumed.

  On the other hand, when it is determined in step S9 that the insertion / extraction detection signal IT is at logic level 1, that is, when it is determined that the child board 2 is not inserted into the child board connector 11, the insertion / removal operation of the child board 2 is performed. Since an overcurrent due to static electricity or the like is applied to the insertion / extraction detection electrode terminal of the sub board connector 11, an erroneous determination may be temporarily made in step S5.

  If it is determined in step S9 or S5 that the insertion / extraction detection signal IT is at logic level 1, that is, if it is determined that the child board 2 is not inserted into the child board connector 11, the CPU 14 reads the child board register read / write. By starting the API 31, a read command for reading fixed data stored in advance in the register 22 of the child board 2 is sent to the child board 2 (step S12). The fixed data read from the register 22 in step S12 is fixed information whose contents are unchanged, such as a device ID or a vendor code. Next, the CPU 14 determines whether or not the above-described fixed data has been read from the register 22 (step S13).

  If it is determined in step S13 that the fixed data could not be read, the CPU 14 changes the content of the program counter (not shown) so that the main program 130 is executed after the insertion / extraction processing program 132 is executed. As a result, the wireless communication program 131 suspended as described above is terminated (step S14). That is, if the fixed data cannot be read correctly, the CPU 14 determines that the child board 2 has been removed from the child board connector 11, and completes the wireless communication program 131 suspended as described above. It ends it.

  On the other hand, if it is determined in step S13 that the fixed data has been read correctly, the CPU 14 determines that the child board 2 is inserted into the child board connector 11, and determines the following steps S15 and S16. As a result of execution, the cause that the insertion / extraction detection circuit 12 has detected the removal of the sub board 2 is determined. That is, first, the CPU 14 activates the slave board register read / write API 31 to read out status data indicating the setting state of the wireless communication operation from among various data stored in the register 22 of the slave board 2 (step) S15). The status data is a predetermined initial value immediately after the start of the wireless communication program 131, but is changed to an operation value corresponding to the state of the wireless communication operation while the wireless communication program 131 is being executed. For example, the status data includes communication buffer size information indicating the current communication buffer size. The initial value of the communication buffer size is 1024 Kbytes, but is changed to 2048 Kbytes, which is an operation value, after the wireless communication program 131 is started.

  Next, the CPU 14 determines whether or not the status data read from the register 22 of the slave board 2 remains the initial value (step S16). For example, in step S16, the CPU 14 determines whether or not the communication buffer size as status data is the initial value of 1024 Kbytes.

  If it is determined in step S16 that the status data read from the register 22 is other than the initial value, that is, indicates an operational value, the CPU 14 proceeds to the execution of step S10 described above. That is, at this time, the CPU 14 initially detected that the insertion / extraction detection circuit 12 detected the removal of the daughter board 2 because an overcurrent due to static electricity or the like was applied to the insertion / extraction detection electrode terminal of the daughter board connector 11. to decide. At this time, finally, it is determined that the sub board 2 is inserted into the sub board connector 11, and the CPU 14 restarts the wireless communication operation by the sub board 2 (S10).

  On the other hand, if it is determined in step S16 that the status data read from the register 22 indicates the initial value, the value of the program counter at the current stage in the suspended wireless communication program 131 is returned to the initial address ( Step S17). Next, the CPU 14 rewrites the content of the access prohibition flag stored in the RAM 15 to a logic level 0 indicating that access to the register 22 of the child board 2 is permitted (step S18). Next, the CPU 14 starts executing the wireless communication program 131 (step S19). That is, when the status data read from the register 22 indicates an initial value, the insertion / extraction detection circuit 12 detects the removal of the child board 2 because the child board 2 is actually removed from the child board connector 11. Immediately thereafter, it is determined that the slave board 2 has been inserted into the slave board connector 11, and the wireless communication program 131 is restarted (S17 to S19).

  After executing step S10, 14 or S19, the CPU 14 ends the execution of the insertion / extraction processing program 132. At this time, after execution of step S10 or S19, the CPU 14 restarts the interrupted wireless communication program 131. Thereby, for example, when an overcurrent due to static electricity or the like is applied to the insertion / extraction detection electrode terminal of the sub board connector 11, the insertion / extraction detection circuit 12 temporarily detects that the sub board 2 is in an extraction state. Even then, it is finally determined that the child board 2 is inserted into the child board connector 11, and the wireless communication operation by the child board 2 is resumed.

  On the other hand, after execution of step S14, the CPU 14 proceeds to execution of the main program 130. That is, at this time, since it is determined that the sub board 2 is not inserted into the sub board connector 11, the interrupted wireless communication program 131 is not resumed, and is terminated.

  As described above, in the insertion / extraction process as shown in FIGS. 3 and 4, when the insertion / extraction detection circuit 12 detects the removal of the sub board 2, first, access to the register 22 of the sub board 2 is prohibited to prevent malfunction ( From S1), after waiting for the chattering weight period TCH (S3), it is determined whether or not the sub board 2 is inserted in the sub board connector 11 (S5). If it is determined in this determination (S5) that the sub-board 2 is inserted into the sub-board connector 11, after waiting again for the chattering weight period TCH (S7), the sub-board 2 is connected to the sub-board connector. 11 is determined (S9). That is, after chattering that occurs when inserting / removing the sub board 2 ends, it is determined whether or not the sub board 2 is in the insertion state based on the insertion / extraction detection result (IT) obtained by the insertion / extraction detection circuit 12 (S5). ). As a result, the insertion determination that eliminates the influence of chattering is performed. Even if it is determined in this insertion determination (S5) that the sub board 2 is inserted into the sub board connector 11, an overcurrent due to static electricity or the like has been applied to the insertion / extraction detection electrode terminal of the sub board connector 11. Due to this, there is a possibility that an erroneous determination that the child board 2 is temporarily inserted into the child board connector 11 is made. Therefore, in order to determine whether or not such a temporary failure has occurred, after waiting again for the chattering waiting period TCH (S7), the insertion determination (S9) is performed again. That is, when it is determined in the second insertion determination (S9) that the child board 2 is not inserted, an overcurrent due to static electricity or the like is detected for insertion / removal detection of the child board connector 11 in the first insertion determination (S5). It is determined that an erroneous determination caused by being applied to the electrode terminal has been made.

  Here, when it is determined in the above-described re-insertion determination (S9) that the child board 2 is inserted, the CPU 14 permits access to the register 22 of the child board 2 (S10), and the wireless communication program 131 is executed. Let it resume. In other words, although the removal of the child board 2 is detected by the insertion / removal detection circuit 12, it is determined that the child board 2 is inserted into the child board connector 11 after waiting for the next two chattering wait periods TCH (S9). ), The final determination is made that the sub-board 2 is in a state of being inserted into the sub-board connector 11. In short, the detection result by the first insertion / extraction detection circuit 12 (the child board 2 is not inserted) is a temporary result due to an overcurrent due to static electricity or the like being applied to the insertion / extraction detection electrode terminal of the child board connector 11. Yes, it is determined that the sub-board 2 is still inserted in the sub-board connector 11, and the wireless communication program 131 is restarted.

  When it is determined in the first or second insertion determination (S5, S6) that the child board 2 is not inserted, the fixed data stored in advance in the register 22 of the child board 2 should be read out. A read command is sent (S12), and it is determined whether the fixed data has actually been read (S13). If it is determined in this determination (S13) that the reading of the fixed data stored in the register 22 has not been correctly performed, it is determined that the child board 2 has been removed from the child board connector 11, and the suspended wireless communication is determined. The communication program 131 is terminated.

  If it is determined in the determination (S13) that the fixed data stored in the register 22 has been correctly read out, it is determined that the child board 2 is inserted into the child board connector 11. At this time, the status data is read from the register 22 (S15), and it is determined whether or not the content is an initial value (S16). If it is determined in this determination (S16) that the content of the status data is an initial value, the wireless communication program 131 is restarted (S17 to S19). That is, when it is determined in the determination (S5, S9) that the child board 2 is not inserted, but it is determined in the determination (S16) that the status data read from the register 22 indicates the initial value. That is, it is determined that the daughter board 2 has been temporarily removed but has been immediately inserted, and the wireless communication operation by the daughter board 2 is resumed.

  If the status data read from the register 22 in the determination (S16) indicates contents other than the initial value, that is, an operation value, access to the register 22 is permitted (S10), and the wireless communication program 131 is executed. Let it resume. That is, at this time, the determination result that the child board 2 is not inserted in the determination (S5) is due to an overcurrent due to static electricity or the like being applied to the insertion / extraction detection electrode terminal of the child board connector 11. This is a temporary erroneous determination, and it is determined that the child board 2 is inserted into the child board connector 11 in the first place, and the wireless communication operation by the child board 2 is restored.

  Therefore, according to the insertion / removal process shown in FIGS. 3 and 4, whether or not the child board 2 has been removed from the parent board 1 without providing a switch for interrupting the CPU for insertion / removal work on the parent board side. Can be determined. Therefore, a troublesome switch operation manually performed by the user before the insertion / extraction operation becomes unnecessary, and the manufacturing cost on the parent substrate side can be suppressed.

  Furthermore, even if an overcurrent due to static electricity or the like is applied to the insertion / extraction detection electrode terminal of the sub board connector 11 as an external factor, it is possible to correctly determine whether or not the sub board is inserted by eliminating the influence. It becomes possible.

  In the embodiment as described above, log information indicating a determination result for each processing stage of the insertion / extraction process may be recorded, and a display for notifying the log information may be performed on the parent substrate 1 side.

  FIG. 6 is a diagram showing a schematic configuration of the parent substrate 1 made in view of this point.

  In addition, in the mother board 1 shown in FIG. 6, other configurations are the same except that a log information notification unit 16 for notifying the execution date and time of the insertion / extraction processing and the processing result or determination result at each stage is added. Is the same as shown in The log information notification unit 16 includes a display or a plurality of point light sources that visually indicate the execution date and time of the insertion / extraction process and the processing results or determination results at each stage, or these information by voice. It may be provided with a speaker for notification. In addition, the ROM 13 mounted on the parent board 1 shown in FIG. 6 stores a log API (Application Program Interface) 35 added to the module shown in FIG. The log API is used in the step of recording log information as follows.

  5 is supplied from the insertion / removal detection circuit 12 to the insertion / extraction detection signal IT that transitions from the logic level 0 to 1, the CPU 14 temporarily interrupts the execution of the wireless communication program 131, and the insertion / extraction processing program Shift to execution of 132.

  7 and 8 are flowcharts showing another example of the insertion / extraction processing flow in the insertion / extraction processing program 132.

  The insertion / extraction process flow shown in FIGS. 7 and 8 is obtained by inserting steps S101 to S111 executed by the log API into steps S1 to S19 shown in FIGS. 3 and 4. The procedure is the same as that shown in FIGS.

  Therefore, hereinafter, only the operations of steps S101 to S111 executed by the log API 35 will be extracted from FIGS. 7 and 8 and described.

  After execution of step S1 shown in FIG. 7, the CPU 14 stores date / time information indicating the current date / time in the address X0 of the RAM 15 as shown in FIG. 9 (step S101). After execution of step S101, the CPU 14 proceeds to execution of step S2.

  Further, when it is determined in step S3 shown in FIG. 7 that the chattering weight period TCH has elapsed, the CPU 14 shows, for example, chattering weight completion information indicating that the first chattering weight of 200 msec has been completed in FIG. As shown, it is stored in the address X1 of the RAM 15 (step S102). After execution of step S102, the CPU 14 proceeds to execution of step S4.

  On the other hand, if it is determined in step S13 shown in FIG. 8 that the fixed data cannot be correctly read from the register 22 of the child board 2, the CPU 14 determines that the child board 2 has been removed, and notifies the fact. The child board removal confirmation information shown is stored in the address X2 of the RAM 15 as shown in FIG. 9 (step S103). After execution of step S103, the CPU 14 proceeds to execution of step S14.

  Further, after the execution of this step S14, the CPU 14 shows the communication program stop completion information indicating the stop of the execution of the wireless communication program 131 and the communication stop information indicating that the communication operation is stopped, as shown in FIG. And X4 (step S104).

  On the other hand, when it is determined in step S13 shown in FIG. 8 that the fixed data can be correctly read from the register 22 of the child board 2, the CPU 14 is in a state where the child board 2 is inserted into the child board connector 11. Then, the sub board insertion confirmation information indicating that is stored in the address X5 of the RAM 15 as shown in FIG. 9 (step S105).

  On the other hand, when it is determined in step S16 shown in FIG. 8 that the status data read from the register 22 indicates the initial value, the CPU 14 temporarily removes the child board 2 and enters the insertion state again. The child board instantaneous disconnection confirmation information indicating this is stored in the address X6 of the RAM 15 as shown in FIG. 9 (step S106). After execution of step S106, the CPU 14 proceeds to execution of step S17.

  Further, after the execution of step S17, the CPU 14 stores communication program stop completion information indicating stop of execution of the wireless communication program 131 in the address X7 of the RAM 15 as shown in FIG. 9 (step S107). After execution of step S107, the CPU 14 proceeds to execution of step S18.

  In addition, after the execution of step S18, the CPU 14 completes communication program start completion information indicating that the execution of the wireless communication program 131 has been resumed, and a communication reusable state indicating that wireless communication has been restored to a usable state. The restoration information is stored in the addresses X8 and X9 of the RAM 15 as shown in FIG. 9 (step S108).

  The CPU 14 determines that the insertion / extraction detection signal IT is not at the logic level 1 in step S9, that is, if it is determined that the child board 2 is inserted into the child board connector 11, or the register 22 in step S16. When it is determined that the status data read from the above indicates other than the initial value, the following step S109 is executed. That is, the CPU 14 stores the overcurrent application confirmation information indicating that the overcurrent is applied in the address XA of the RAM 15 as shown in FIG. 9 (step S109). After execution of step S109, the CPU 14 proceeds to execution of step S10.

  Further, after the execution of step S10, the CPU 14 stores communication state recovery information indicating that the communication operation by the child board 2 has been recovered in the address XB of the RAM 15 as shown in FIG. 9 (step S110).

  After executing step S104, S108, or S110, the CPU 14 causes the log information notification unit 16 to notify various log information stored in each of the addresses X0 to XB of the RAM 15 as shown in FIG. 9 (step S111). By executing step S111, the log information notification unit 16 notifies (displays or sounds) various log information as shown in FIG. According to the notification of the log information, an operator who performs the insertion / removal operation of the child board 2 can check the insertion / removal state of the child board 2 at the current time.

  In short, the present invention provides a child board that is inserted into the child board by the insertion / extraction detection circuit (12) that detects whether or not the child board (2) is inserted into the child board connector based on the voltage of the electrode terminal of the child board connector (11). When it is detected that the state of being inserted into the board connector has changed to the non-inserted state, the following sub-board insertion / removal determination process is performed.

  That is, first, the register read command sending means (CPU 14, S12) sends a read command for reading fixed data stored in advance in the register (22) mounted on the slave board via the slave board connector. At this time, the insertion / removal determination means (CPU 14, S13, S103, S105) detects the fixed data from the sub board connector when the fixed data cannot be read out from the register in spite of the above read command being sent. It is determined that it has been removed. On the other hand, when the fixed data can be read, it is determined that the slave board is inserted into the slave board connector.

  According to such insertion / removal determination, it is possible to determine whether or not the child board is inserted into the parent board without providing a switch and wiring for interrupting the insertion / removal operation for the CPU on the parent board side. It becomes. Furthermore, since the result of access to the register mounted on the child board side along with the detection result of the insertion / extraction detection circuit is used as a condition for determining whether or not the child board is inserted into the parent board, the protection circuit Therefore, it is possible to eliminate the influence of erroneous detection caused by application of an overcurrent due to static electricity or the like to the insertion / extraction detection electrode terminal of the sub board connector.

  Therefore, according to the present invention, it is possible to accurately determine whether the daughter board is in the inserted or removed state without requiring a troublesome operation from the user and at a low cost. .

  In the above-described embodiment, the operation of the so-called wireless card having a wireless communication function is described as an example of the slave board 2, but the function of the slave board 2 is not limited to the wireless communication function. For example, the slave board 2 may be a wired LAN (Local Area Network) card or a storage card. In short, what is necessary is that the sub-board 2 is mounted with a register that is used to perform the main operation and is accessible from the main board 1 side.

  The child board connector 11 for connecting the child board 2 to the mother board 1 is not limited as long as data communication can be performed between the mother board 1 and the child board 2. For example, PCI (Peripheral Component Interconnect) Corresponding connectors are also applicable.

1 Parent board
2 Sub board 11 Sub board connector 12 Insertion / extraction detection circuit 13 ROM
14 CPU
22 registers

Claims (5)

A board-mounted circuit with a sub board connector,
An insertion / extraction detection circuit that generates a detection signal indicating whether or not a child board is inserted into the child board connector based on a voltage of an electrode terminal of the child board connector, and the child board is connected to the child based on the detection signal A control unit for determining whether or not the board connector has been removed,
The control unit is pre-stored in a register mounted on the child board when the detection signal indicates that the child board has been inserted into the child board connector and has transitioned from the inserted state to the non-inserted state. A register read command sending means for sending a read command to read out a registered register via the slave board connector;
When the fixed data cannot be read from the register in spite of sending the read command, it is determined that the child board has been removed from the child board connector, while the fixed data is read. A board mounting circuit comprising: an insertion / removal determination unit that determines that the sub board is inserted into the sub board connector, if possible. The insertion / extraction determination means, when the fixed data can be read from the register, stores a read instruction to read status data indicating the current operation state of the child board stored in the register. Means for delivery via a connector;
When the content of the status data indicates an initial value, it is determined that the child board has transitioned to the inserted state after being temporarily removed from the child board connector, while the content of the status data is the initial value. 2. The circuit board-mounted circuit according to claim 1, further comprising means for temporarily determining that the insertion / extraction detection circuit has made a false detection by applying an overcurrent from outside.   3. The circuit board according to claim 1, further comprising means for notifying a determination result by the insertion / extraction determination means.   The register read command sending means is supplied with the detection signal indicating that the child board has transitioned from the state inserted into the child board connector to the non-inserted state from the insertion / removal detection circuit, and then in a chattering waiting period. When the detection signal indicates a transition from the state in which the child board is inserted into the child board connector to the non-inserted state after the elapse of time, a read command to read out the fixed data is transmitted via the child board connector. The board-mounted circuit according to claim 1, wherein the circuit is mounted on the board.   5. The circuit board mounted circuit according to claim 1, wherein the fixed data indicates an identification ID of the sub board or a manufacturer of the sub board. 6.

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