JP2013048367A - Signal conversion circuit, and amplification circuit, transmission device and communication device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a signal conversion circuit that suppresses the generation of unwanted pulses, and an amplification circuit, transmission device and communication device therewith.SOLUTION: The signal conversion circuit includes: a transistor 7 for receiving a first signal S1 and a second signal S2 at a source terminal and a gate terminal, respectively; a first circuit 5 for receiving the first signal S1 and the second signal S2, and outputting a third signal S3 having information on a phase difference between the first signal S1 and the second signal S2; a second circuit 6 for receiving the first signal S1 and the third signal S3, and outputting a fourth signal S4 having a phase shifted from the phase of the first signal S1 in accordance with the phase difference between the first signal S1 and the second signal S2; and a transistor 9 with a source terminal connected to a drain terminal of the transistor 7 for receiving the fourth signal S4 at a gate terminal, and outputting a fifth signal S5 having a duty ratio variable in accordance with the phase difference between the first signal S1 and the second signal S2 from a drain terminal.

Description

  The present invention relates to a signal conversion circuit in which generation of unnecessary pulses is suppressed, an amplifier circuit using the same, a transmission device, and a communication device.

  Conventionally, a signal conversion circuit that outputs a pulse signal having a duty ratio corresponding to a phase difference between two input signals is known (see, for example, Patent Document 1).

JP 2009-182906 A

  However, in the conventional signal conversion circuit described above, unnecessary pulses may occur when the phase difference between two input signals is large.

  The present invention has been devised in view of such problems in the prior art, and an object of the present invention is to provide a signal conversion circuit in which generation of unnecessary pulses is suppressed, an amplifier circuit using the same, a transmission device, and communication. To provide an apparatus.

  The first signal conversion circuit of the present invention includes a first transistor in which a first signal is input to a source terminal and a second signal or a signal in phase with the second signal is input to a gate terminal; One signal or a signal having a predetermined phase difference from the first signal and the second signal or a signal having a predetermined phase difference from the second signal are input, and the first signal and the second signal A first circuit for outputting a third signal having phase difference information, at least one of a signal having a predetermined phase relationship with the first signal and a signal having a predetermined phase relationship with the second signal, A second signal that outputs a fourth signal having a phase obtained by shifting a phase of the first signal or the second signal in accordance with a phase difference between the first signal and the second signal. A circuit and a source terminal of the first transistor; The fourth signal is connected to the drain terminal and the gate signal is input to the gate terminal, and the fifth signal whose duty ratio changes according to the phase difference between the first signal and the second signal is output from the drain terminal. And at least a second transistor.

  According to a second signal conversion circuit of the present invention, in the first signal conversion circuit, the second signal has a phase intermediate between the phase of the first signal and the phase of the second signal. Is output.

  The amplifying circuit of the present invention is the first signal conversion circuit and two constant envelope signals in which a sixth signal is inputted and a phase difference between the first signal converting circuit and the sixth signal is changed in accordance with a change in amplitude of the sixth signal. A third circuit for outputting the first signal and the second signal, a transistor for inputting the fifth signal directly or through another circuit to a gate terminal, and outputting a seventh signal from a drain terminal; And a fourth circuit that mainly receives a signal having a fundamental frequency of the sixth signal and receives the seventh signal.

The transmission device of the present invention includes at least a transmission circuit, the amplification circuit, and an antenna connected to the transmission circuit via the amplification circuit.

  The communication apparatus of the present invention includes at least a transmission circuit, the amplification circuit, an antenna connected to the transmission circuit via the amplification circuit, and a reception circuit connected to the antenna. It is what.

According to the signal conversion circuit of the present invention, a signal conversion circuit in which generation of unnecessary pulses is suppressed can be obtained.
According to the amplifier circuit of the present invention, an amplifier circuit with low power consumption can be obtained.
According to the transmission device of the present invention, a transmission device with low power consumption can be obtained.
According to the communication device of the present invention, a communication device with low power consumption can be obtained.

It is a circuit diagram showing a signal conversion circuit of the 1st example of an embodiment of the invention. FIG. 2 is a circuit diagram illustrating an example of a first circuit in FIG. 1. It is a circuit diagram which shows an example of the 2nd circuit in FIG. (A), (b) is a figure for demonstrating the problem of the conventional signal conversion circuit. (A), (b) is a figure for demonstrating the effect which the signal converter circuit of this invention has. It is a circuit diagram which shows the amplifier circuit of the 2nd example of embodiment of this invention. It is a block diagram which shows the transmission apparatus of the 3rd example of embodiment of this invention. It is a block diagram which shows the communication apparatus of the 4th example of embodiment of this invention.

Hereinafter, a signal conversion circuit of the present invention, an amplifier circuit using the same, a transmission device, and a communication device will be described in detail with reference to the accompanying drawings.
(First example of embodiment)
FIG. 1 is a circuit diagram showing a signal conversion circuit of a first example of an embodiment of the present invention. FIG. 2 is a circuit diagram showing an example of the first circuit in FIG. FIG. 3 is a circuit diagram showing an example of the second circuit in FIG. As shown in FIG. 1, the signal conversion circuit 30 of this example includes terminals 1 to 4, transistors 7 to 10, a first circuit 5, and a second circuit 6.

  The terminal 1 receives a first signal S1 from an external circuit (not shown), and the terminal 2 receives a second signal S2 from an external circuit (not shown). In the signal conversion circuit of this example, the first signal S1 and the second signal S2 are constant envelope signals having the same frequency.

  The transistor 7 has a source terminal connected to the terminal 1 and a gate terminal connected to the terminal 2. The transistor 7 receives the first signal S1 at the source terminal and the second signal S2 at the gate terminal, and has a duty ratio according to the phase difference between the first signal S1 and the second signal S2. A changing signal is output from the drain terminal. The transistor 8 has a source terminal connected to the terminal 2 and a gate terminal connected to the terminal 1. The transistor 8 receives the second signal S2 at the source terminal and the first signal S1 at the gate terminal, and has a duty ratio according to the phase difference between the first signal S1 and the second signal S2. A changing signal is output from the drain terminal.

  In the first circuit 5, the terminal 20 is connected to the terminal 1, the terminal 21 is connected to the terminal 2, and the terminal 22 is connected to the terminal 16 of the second circuit 6. The first circuit 5 receives the first signal S1 at the terminal 20 and the second signal S2 at the terminal 21, and has information on the phase difference between the first signal S1 and the second signal S2. The third signal S3 is output from the terminal 22.

  FIG. 2 shows an example of the circuit configuration of the first circuit 5. The terminal 20 is connected to the gate terminal of the transistor 23, and the terminal 21 is connected to the gate terminal of the transistor 24. Note that a bias circuit (not shown) is provided, and a DC bias voltage is supplied to the gate terminals of the transistors 23 and 24.

  The drain terminal of the transistor 23 is connected to the power supply voltage Vdd. The source terminal of the transistor 23 is connected to the drain terminal of the transistor 24. The source terminal of the transistor 24 is connected to the drain terminal of the transistor 25. The 25 source terminals are connected to the ground potential. The transistor 25 has a drain terminal and a gate terminal connected to each other, and functions as a reference current side transistor of the current mirror circuit.

  Normally, when a positive voltage equal to or higher than the pinch-off voltage is applied to the gate terminal, the n-channel transistor conducts between the drain and source terminals. Therefore, when the first signal S1 and the second signal S2 are positive voltages equal to or higher than the pinch-off voltage, the transistors 23 and 24 are turned on. In this circuit configuration, since the transistor 23 and the transistor 24 form an AND circuit, the power supply voltage is applied to the drain terminal of the transistor 25 only when the first signal S1 and the second signal S2 are both positive voltages equal to or higher than the pinch-off voltage. Vdd is supplied.

  The time when both the transistor 23 and the transistor 24 are in the ON state corresponds to the phase difference between the first signal S1 and the second signal S2. That is, when the phase difference between the two input signals is small, the time for which both are in the ON state is long, and when the phase difference between the two input signals is large, the time for which both are in the ON state is short. Thereby, the increase / decrease in the phase difference between the first signal S1 and the second signal S2 is replaced with the increase / decrease in the supply time of the power supply voltage Vdd to the drain terminal of the transistor 25.

  The transistor 25 can be regarded as a diode equivalently because the gate terminal and the drain terminal are connected. As a result, a voltage corresponding to the current flowing through the drain terminal is obtained at the gate terminal. As described above, since the power supply voltage Vdd is supplied to the drain of the transistor 25 in accordance with the phase difference between the first signal S1 and the second signal S2, the first signal S1 and the signal from the gate terminal of the transistor 25 are supplied. A third signal S3 having a voltage corresponding to the phase difference from the second signal S2 is output.

  That is, the first circuit 5 receives a signal having a predetermined phase difference from the first signal S1 or the first signal S1 and a signal having a predetermined phase difference from the second signal S2 or the second signal S2. A third signal S3 having information on the phase difference between the first signal S1 and the second signal S2 is output. The first circuit 5 only needs to have such a function, and may have another circuit configuration.

  In the second circuit 6, the terminal 14 is connected to the terminal 1, and the terminal 16 is connected to the terminal 22 of the first circuit 5. Then, the first signal S1 is input to the terminal 14 and the third signal S3 is input to the terminal 16, and the phase of the first signal S1 is changed according to the phase difference between the first signal S1 and the second signal S2. The shifted fourth signal S4 is output. More specifically, the second circuit 6 outputs a fourth signal S4 having a phase intermediate between the phase of the first signal S1 and the phase of the second signal S2.

FIG. 3 shows an example of the circuit configuration of the second circuit 6. The terminal 14 is connected to one end of the resistor 11, and the other end of the resistor 11 is connected to the terminal 15. One end of the variable capacitor 12 is connected to the terminal 15, and the other end of the variable capacitor is connected to the ground potential. The terminal 16 is a control terminal for changing the capacitance of the variable capacitor 12. The resistor 11 and the variable capacitor 12 constitute a phase circuit. The phase amount of the phase shift circuit varies depending on the capacitance value of the variable capacitor 12, and the capacitance value of the variable capacitor 12 varies depending on the voltage applied to the terminal 16. The terminal 16 receives the third signal S3 having a voltage corresponding to the phase difference between the first signal S1 and the second signal S2. Therefore, the phase of the first signal S1 input to the terminal 14 is shifted according to the phase difference between the first signal S1 and the second signal S2, and is output from the terminal 15 as the fourth signal S4.

  The second circuit 6 receives the first signal S1, the signal having the predetermined phase relationship with the first signal S1, the signal having the predetermined phase relationship with the second signal S2, and the third signal S3 as inputs. It is only necessary to have a function of outputting the fourth signal S4 having a phase shifted from the first signal S1 or the second signal S2 according to the phase difference between the signal S1 and the second signal S2. A circuit configuration may be used.

  In the transistor 9, the source terminal is connected to the drain terminal of the transistor 7, and the fourth signal S 4 is input to the gate terminal connected to the terminal 15 of the second circuit 6. Then, the fifth signal S5 whose duty ratio changes according to the phase difference between the first signal S1 and the second signal S2 is output from the drain terminal. In the transistor 10, the source terminal is connected to the drain terminal of the transistor 8, and the fourth signal S 4 is input to the gate terminal connected to the terminal 15 of the second circuit 6. Then, the fifth signal S5 whose duty ratio changes according to the phase difference between the first signal S1 and the second signal S2 is output from the drain terminal. The transistors 7 to 10 are n-channel FETs, and a predetermined bias voltage is applied to each gate terminal as necessary.

  FIG. 4 is a diagram for explaining a problem in a conventional signal conversion circuit in which the first circuit 5, the second circuit 6, and the transistors 9 and 10 are removed from the signal conversion circuit 30 of this example shown in FIG. . 4A, 41 indicates the voltage of the first signal S1 input to the terminal 1, 42 indicates the voltage of the second signal S2 input to the terminal 2, and 47 indicates the pinch-off voltage of the transistors 7 and 8. Indicates. FIG. 4B is a diagram showing waveforms of signals output from the drain terminals of the transistors 7 and 8, 43 indicates a desired pulse, and 44 indicates an unnecessary pulse. When the phase difference between the first signal S1 and the second signal S2 is large and the state shown in FIG. 4A is obtained, the signals output from the drain terminals of the transistors 7 and 8 are shown in FIG. The inventors have made it clear that unnecessary pulses such as 44) may occur.

  FIG. 5 is a diagram for explaining the effect of the signal conversion circuit 30 of this example shown in FIG. In FIG. 5A, 41 indicates the voltage of the first signal S1 input to the terminal 1, 42 indicates the voltage of the second signal S2 input to the terminal 2, and 45 indicates the gates of the transistors 9 and 10. The voltage of the fourth signal S4 input to each of the terminals is indicated. 47 indicates the pinch-off voltage of the transistors 7 and 8. FIG. 5B is a diagram illustrating the waveforms of signals output from the drain terminals of the transistors 9 and 10.

  Also in the signal conversion circuit 30 of this example shown in FIG. 1, the waveform of the signal output from the drain terminals of the transistors 7 and 8 is as shown in FIG. 4B, and an unnecessary pulse 44 exists. However, a fourth signal S4 having an intermediate phase between the phase of the first signal S1 and the phase of the second signal S2 as indicated by 45 in FIG. 5A is input to the gate terminals of the transistors 9 and 10. Thus, as shown in FIG. 5B, the fifth signal S5 with reduced unnecessary pulses can be output from the drain terminals of the transistors 9 and 10.

(Second example of embodiment)
FIG. 6 is a circuit diagram showing an amplifier circuit according to a second example of the embodiment of the present invention. As shown in FIG. 6, the amplifier circuit of this example includes a third circuit 31, a fourth circuit 33, and a transistor 63 in addition to the signal conversion circuit 30 of the first example of the embodiment shown in FIG. A low-pass filter circuit 65, a resistor 66, and terminals 34 and 35.

  The third circuit 31 receives the sixth signal S6, and the first signal S1 and the second signal S2 are two constant envelope signals whose phase difference changes according to the change in the amplitude of the sixth signal S6. Is generated. Then, the first signal S1 is output to the terminal 1 of the signal conversion circuit 30, and the second signal S2 is output to the terminal 2 of the signal conversion circuit 30. As such a third circuit 31, a known constant envelope signal generation circuit can be used. Any configuration may be used as long as it is a constant envelope signal generation circuit, and either an analog method or a digital method may be used.

  The signal conversion circuit 30 receives the first signal S1 and the second signal S2, and receives the fifth signal S5 whose duty ratio changes according to the phase difference between the first signal S1 and the second signal S2 at the terminals 3 and 4. Output from. The terminal 4 is connected to the ground potential via the resistor 66 and terminated with a predetermined impedance. The terminal 3 is connected to the gate terminal of the transistor 63, and the fifth signal S5 is output from the terminal 3 to the gate terminal of the transistor 63.

  The gate terminal of the transistor 63 is connected to the terminal 3 of the signal conversion circuit 30, and the fifth signal S5 is input to the gate terminal via a DC cut capacitor (not shown). A predetermined bias voltage is applied to the gate terminal of the transistor 63 from a bias circuit (not shown). The drain terminal of the transistor 63 is connected to the power supply potential Vdd via the low-pass filter circuit 65. The source terminal of the transistor 63 is connected to a reference potential (ground potential). The transistor 63 outputs a seventh signal S7, which is a signal obtained by switching amplification of the fifth signal S5, from the drain terminal to the fourth circuit 33.

  The fourth circuit 33 includes an LC series resonance circuit 26 and a matching circuit 27. The LC series resonance circuit 26 is connected to the drain terminal of the transistor 63, and the LC series resonance circuit 26 and the terminal 35 are connected via a matching circuit 27. The LC series resonance circuit 26 is configured by an inductor and a capacitor connected in series with each other, and the resonance frequency is substantially equal to the fundamental frequency of the sixth signal S6 (same as the fundamental frequency of the seventh signal). It is set to an equal value. The matching circuit 27 includes an inductor and a capacitor, and is a low-pass filter type matching circuit. The fourth circuit 33 having such a configuration receives the seventh signal S7 from the signal conversion circuit 30 and mainly outputs a signal having a fundamental frequency of the sixth signal S6.

  The amplifier circuit 80 of this example having such a configuration can output with linear amplification with high efficiency even when the input sixth signal S6 is a signal having an envelope variation. In addition, since the signal conversion circuit 30 in which generation of unnecessary pulses is suppressed is provided, an amplifier circuit with low power consumption can be obtained.

(Third example of embodiment)
FIG. 7 is a block diagram showing a transmission apparatus according to a third example of the embodiment of the present invention.

  As shown in FIG. 7, the transmission device of this example includes a transmission circuit 81, an amplification circuit 80 shown in FIG. 6, and an antenna 82 connected to the transmission circuit 81 via the amplification circuit 80. . According to the transmission apparatus of this example having such a configuration, the transmission signal output from the transmission circuit 81 can be amplified using the amplification circuit 80 with low power consumption and output to the antenna 82. A transmission device with low power can be obtained.

(Fourth example of embodiment)
FIG. 8 is a block diagram showing a communication apparatus according to a fourth example of the embodiment of the present invention.

  As shown in FIG. 8, the communication device of this example includes a transmission circuit 81, a second amplification circuit 80, an antenna 82 connected to the transmission circuit 81 via the amplification circuit 80, and an antenna 82. And a receiving circuit 83. An antenna sharing circuit 84 is inserted between the antenna 82 and the amplifier circuit 80 and the receiving circuit 83. According to the communication apparatus of this example having such a configuration, the transmission signal output from the transmission circuit 81 can be amplified using the amplifier circuit 80 with low power consumption and output to the antenna 82. A communication device with low power can be obtained.

(Modification)
The present invention is not limited to the embodiments described above, and various modifications and improvements can be made without departing from the spirit of the present invention.

  For example, in the first example of the above-described embodiment, an example in which the signal conversion circuit 30 includes the transistors 8 and 10 as shown in FIG. 1 is shown, but the present invention is not limited to this. For example, the transistors 8 and 10 may be removed from the signal conversion circuit 30 shown in FIG. 1 so that the terminal 2 is directly connected to the terminal 4 and the terminal 4 may be terminated with a characteristic impedance. At this time, the terminal 4 may be connected only to the terminal 2 and the terminal 21 of the first circuit 5, the source terminal of the transistor 7, the terminal 20 of the first circuit 5, and the terminal 14 of the second circuit 6. The first signal S1 is input from the terminal 1, the second signal S2 is input from the terminal 2 to the terminal 21 of the first circuit 5, the gate terminal of the transistor 7, and the terminal 4, and the gate terminal of the transistor 9 The fourth signal S4 may be input to the input.

  In the first example of the above-described embodiment, the example in which the fourth signal S4 has an intermediate phase between the phase of the first signal S1 and the phase of the second signal S2 has been described. However, the present invention is not limited to this. It is not something. Any signal having a voltage smaller than the pinch-off voltage of the transistor 9 when the unnecessary pulse is generated may be used, and can be set according to the voltage of the first signal S1, the pinch-off voltage of the transistor 9, or the like.

  Furthermore, in the first example of the above-described embodiment, the example in which the first signal S1 and the second signal S2 are input to the first circuit 5 is shown, but the present invention is not limited to this. One of the two signals input to the first circuit 5 may be a signal having a predetermined phase relationship with the first signal S1, and a signal having a predetermined phase difference from the first signal S1 (the first signal S1 and the first signal S1). (Including in-phase signals). The other of the two signals input to the first circuit 5 may be a signal having a predetermined phase relationship with the second signal S2, and a signal having a predetermined phase difference from the second signal S2 (the second signal S2 and the second signal S2). (Including in-phase signals).

  Furthermore, in the first example of the above-described embodiment, the example in which the first signal S1 is input to the second circuit 6 is shown, but the present invention is not limited to this. It is sufficient that at least one of a signal having a predetermined phase relationship with the first signal S1 and a signal having a predetermined phase relationship with the second signal S2 is input. For example, the phase of the second signal S2 is shifted by a predetermined value. Such a signal may be input.

7, 8, 9, 10, 23, 24, 25, 63: transistor 5: first circuit 6: second circuit 30: signal conversion circuit 31: third circuit 33: fourth circuit 80: amplification circuit 81: transmission circuit 82: Antenna 83: Receiver circuit

Claims (5)

A first transistor in which a first signal is input to a source terminal and a second signal or a signal in phase with the second signal is input to a gate terminal;
The first signal or the signal having a predetermined phase difference from the first signal and the second signal or the signal having a predetermined phase difference from the second signal are input, and the first signal and the second signal are input. A first circuit for outputting a third signal having information on a phase difference from the signal;
At least one of a signal having a predetermined phase relationship with the first signal and a signal having a predetermined phase relationship with the second signal, and the third signal are input, and the first signal and the second signal are input. A second circuit that outputs a fourth signal having a phase obtained by shifting the phase of the first signal or the second signal in accordance with the phase difference of
The source terminal is connected to the drain terminal of the first transistor and the fourth signal is input to the gate terminal, and the duty ratio changes according to the phase difference between the first signal and the second signal. And a second transistor that outputs a fifth signal from a drain terminal.   2. The signal conversion circuit according to claim 1, wherein the second circuit outputs the fourth signal having a phase intermediate between the phase of the first signal and the phase of the second signal. A signal conversion circuit according to claim 1;
A third circuit that receives the sixth signal and outputs the first signal and the second signal, which are two constant envelope signals whose phase difference changes in accordance with a change in the amplitude of the sixth signal; ,
A transistor in which the fifth signal is input to the gate terminal directly or through another circuit and outputs a seventh signal from the drain terminal;
An amplifier circuit comprising at least a fourth circuit that receives the seventh signal and mainly outputs a signal having a fundamental frequency of the sixth signal.   A transmission apparatus comprising: a transmission circuit; an amplification circuit according to claim 3; and an antenna connected to the transmission circuit via the amplification circuit.   It has at least a transmission circuit, an amplification circuit according to claim 3, an antenna connected to the transmission circuit via the amplification circuit, and a reception circuit connected to the antenna. Communication device.

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