JP2013093810A - Signal conversion circuit and amplifier circuit, transmitter device and communication equipment using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a signal conversion circuit which restrains a reduction in output electric power when an input signal has a large phase difference.SOLUTION: The signal conversion circuit comprises: a first circuit 4 which outputs a first signal S1, a second signal S2, a third signal S3 consisting of the first signal S1 delaying by φ1, and a fourth signal S4 consisting of the second signal S2 delayed by φ2(φ2=φ1+φ3); a transistor 7 which accepts as its input the first signal S1 and the second signal S2 at its source and gate terminals and outputs a fifth signal S5; a transistor 8 which accepts as its input the third signal S3 and the fourth signal S4 at its source and gate terminals and outputs a sixth signal S6; a second circuit 5 which outputs a seventh signal S7 consisting of the sixth signal S6 delayed by φ4(φ4≥0) via a switch circuit 57, and outputs an eighth signal S8 consisting of the fifth signal S5 delayed by φ5(φ5=180°+φ1+φ4); a third circuit 6 which controls the switch circuit 57; and a fourth circuit 9 which adds the seventh signal S7 and the eighth signal S8.

Description

  The present invention relates to a signal conversion circuit in which a decrease in output power when a phase difference between two input signals is large, and an amplifier circuit, a transmission device, and a communication device using the signal conversion circuit.

  Conventionally, a signal conversion circuit that outputs a pulse signal having a duty ratio corresponding to a phase difference between two input signals is known (see, for example, Patent Document 1).

JP 2009-182906 A

  However, in the conventional signal conversion circuit described above, the output power may decrease when the phase difference between the two input signals is large.

  The present invention has been devised in view of such problems in the prior art, and its purpose is to perform signal conversion in which a decrease in output power is suppressed when the phase difference between two input signals is large. An object of the present invention is to provide a circuit and an amplifier circuit, a transmission device, and a communication device using the circuit.

  The signal conversion circuit according to the present invention receives the first signal, the second signal, and the first signal by inputting the first signal and the second signal having the same or delayed phase with respect to the first signal. A third signal having a phase delayed by φ1 (φ1 ≧ 0) and a phase delayed by φ2 (φ2 = φ1 + φ3, φ3 is a predetermined positive value). A first circuit that outputs a fourth signal; and one of the first signal and the second signal is input to a source terminal, and the other of the first signal and the second signal is input to a gate terminal. The first transistor that outputs the fifth signal from the drain terminal, one of the third signal and the fourth signal is input to the source terminal, and the other of the third signal and the fourth signal is the gate terminal 6th input from the drain terminal A second transistor that outputs a signal and a seventh signal having a phase obtained by inputting the fifth signal and the sixth signal and delaying the phase of the sixth signal by φ4 (φ4 ≧ 0) And a second circuit for outputting an eighth signal having a phase delayed by φ5 (φ5 = 180 ° + φ1 + φ4), the first signal, and the second signal, A third circuit that outputs a ninth signal for controlling the switch circuit so that the switch circuit is closed when the phase difference between the first signal and the second signal is greater than a predetermined value, and the inputted seventh and eighth signals And at least a fourth circuit for outputting the tenth signal.

  The amplifier circuit of the present invention outputs the first signal and the second signal, to which the eleventh signal is input and the phase difference between the signal conversion circuit and the eleventh signal changes in accordance with a change in amplitude of the eleventh signal. The fifth circuit, the tenth signal is input to the gate terminal directly or through another circuit, the twelfth signal is input from the drain terminal, the twelfth signal is input, and the eleventh signal is input. And a sixth circuit that outputs a signal having a frequency of the fundamental wave of the signal.

  The transmission device of the present invention includes at least a transmission circuit, the width circuit, and an antenna connected to the transmission circuit via the amplifier circuit.

  The communication apparatus of the present invention includes at least a transmission circuit, the amplification circuit, an antenna connected to the transmission circuit via the amplification circuit, and a reception circuit connected to the antenna. It is what.

According to the signal conversion circuit of the present invention, it is possible to obtain a signal conversion circuit in which a decrease in output power when a phase difference between two input signals is large is suppressed.
According to the amplifier circuit of the present invention, an amplifier circuit in which a decrease in output power when input power is small can be obtained.
According to the transmission device of the present invention, a transmission device with low power consumption can be obtained.
According to the communication device of the present invention, a communication device with low power consumption can be obtained.

It is a circuit diagram showing a signal conversion circuit of the 1st example of an embodiment of the invention. FIG. 7 is a circuit diagram illustrating an example of a seventh circuit 61 in FIG. 1. It is a circuit diagram which shows the conventional signal conversion circuit. It is a graph for demonstrating the problem of the conventional signal converter circuit. (A), (b) is a figure for demonstrating the problem of the conventional signal conversion circuit. (A), (b) is a figure for demonstrating the problem of the conventional signal conversion circuit. (A), (b) is a figure for demonstrating the problem of the conventional signal conversion circuit. It is a circuit diagram which shows the signal conversion circuit of the 2nd example of embodiment of this invention. It is a circuit diagram which shows the amplifier circuit of the 3rd example of embodiment of this invention. It is a block diagram which shows the transmission apparatus of the 4th example of embodiment of this invention. It is a block diagram which shows the communication apparatus of the 5th example of embodiment of this invention. It is a graph which shows the effect of the signal converter circuit of the present invention. It is a graph which shows the effect of the signal converter circuit of the present invention.

  Hereinafter, a signal conversion circuit of the present invention, an amplifier circuit using the same, a transmission device, and a communication device will be described in detail with reference to the accompanying drawings.

(First example of embodiment)
FIG. 1 is a circuit diagram showing a signal conversion circuit of a first example of an embodiment of the present invention. FIG. 2 is a circuit diagram showing an example of the seventh circuit 61 in FIG. As shown in FIG. 1, the signal conversion circuit 30 of this example includes terminals 1 to 3, transistors 7 and 8, a first circuit 4, a second circuit 5, a third circuit 6, and a fourth circuit 9. And have.

  The terminal 1 receives a first signal S1 from an external circuit (not shown), and the terminal 2 receives a second signal S2 from an external circuit (not shown). In the signal conversion circuit of this example, the first signal S1 and the second signal S2 are signals having a constant amplitude and the same frequency. Further, the first signal S1 and the second signal S2 may be sinusoidal or rectangular wave signals, or may be pulse signals. The second signal S2 is a signal having the same phase or a delayed phase with respect to the first signal S1.

The first circuit 4 includes terminals 11 to 16 and a phase shifter 17. The terminal 11 is connected to the terminal 1, and the first signal S1 is input from the terminal 1. The terminal 1 is connected to the terminal 13 and the terminal 15. Therefore, the first signal S1 input to the terminal 11 is output from the terminal 13 as it is. The third signal S3 output from the terminal 15 is also exactly the same signal as the first signal S1. That is, if the delay amount of the phase of the third signal S3 with respect to the phase of the first signal S1 is φ1, φ1 = 0 is set. Note that φ1 is normally set to 0, but may be set to an arbitrary value of 0 or more. In that case, a phase shifter with a phase shift amount φ 1 is inserted between the terminal 11 and the terminal 15.

  The terminal 12 is connected to the terminal 2, and the second signal S2 is input from the terminal 2. Further, the terminal 12 is connected to the terminal 14, and the second signal S <b> 2 input to the terminal 12 is output from the terminal 14 as it is. The terminal 12 is connected to the terminal 16 through the phase shifter 17. When the phase shift amount of the phase shifter 17 is φ2, φ2 = φ1 + φ3 is set. Note that φ3 is a value determined in advance according to the waveforms of the first signal S1 and the second signal S2, and the setting method will be described later. In the signal conversion circuit of this example, φ3 = 1 ° is set and, as described above, φ1 = 0, so that φ2 = φ1 + φ3 = 0 + 1 ° = 1 °. That is, the delay amount φ2 of the phase of the fourth signal S4 output from the terminal 16 with respect to the phase of the second signal S2 is set to φ2 = 1 °.

  Thus, the first circuit 4 receives the first signal S1 and the second signal S2, and the phases of the first signal S1, the second signal S2, and the first signal S1 are φ1 (φ1 ≧ 0). A third signal S3 having a delayed phase and a fourth signal S4 having a phase obtained by delaying the phase of the second signal S2 by φ2 (φ2 = φ1 + φ3, φ3 is a predetermined positive value) are output.

  The transistor 7 has a source terminal connected to the terminal 13 and a gate terminal connected to the terminal 14. The transistor 7 receives the first signal S1 at the source terminal and the second signal S2 at the gate terminal, and has a duty ratio according to the phase difference between the first signal S1 and the second signal S2. A fifth signal S5, which is a changing signal, is output from the drain terminal. That is, in the transistor 7, one of the first signal S1 and the second signal S2 is input to the source terminal, and the other of the first signal S1 and the second signal S2 is input to the gate terminal and the fifth signal is output from the drain terminal. S5 is output.

  The transistor 8 has a source terminal connected to the terminal 16 and a gate terminal connected to the terminal 15. The transistor 8 receives the fourth signal S4 at the source terminal and the third signal S3 at the gate terminal, and has a duty ratio according to the phase difference between the third signal S3 and the fourth signal S4. A sixth signal S6, which is a changing signal, is output from the drain terminal. That is, in the transistor 8, one of the third signal S3 and the fourth signal S4 is input to the source terminal, the other of the third signal S3 and the fourth signal S4 is input to the gate terminal, and the sixth signal is output from the drain terminal. S6 is output. The transistors 7 and 8 are n-channel FETs, and a predetermined bias voltage is applied to each gate terminal as necessary.

  The second circuit 5 includes terminals 51 to 54, a phase shifter 56, and a switch circuit 57. The terminal 53 is connected to the drain terminal of the transistor 8, and the sixth signal S 6 is input from the transistor 8. The terminal 53 is connected to the terminal 54 via the switch circuit 57. When the switch circuit 57 closes (becomes ON), the terminal 53 and the terminal 54 are brought into conduction (short circuit), and the terminal 54 is connected. To output a seventh signal S7. Therefore, if the delay amount of the phase of the seventh signal S7 with respect to the phase of the sixth signal S6 is φ4, φ4 = 0 is set. Note that φ4 is normally set to 0, but may be set to an arbitrary value of 0 or more. In that case, a phase shifter with a phase shift amount φ 4 is inserted between the terminal 53 and the terminal 54.

The terminal 51 is connected to the drain terminal of the transistor 7, and the fifth signal S <b> 5 is input from the transistor 7. Further, the terminal 51 is connected to the terminal 52 via the phase shifter 56. When the phase shift amount of the phase shifter 56 is φ5, φ5 = 180 ° + φ1 + φ4 is set. That is, the delay amount φ5 of the phase of the eighth signal S8 output from the terminal 52 with respect to the phase of the fifth signal S5 is set to φ5 = 180 ° + φ1 + φ4. In the signal conversion circuit of this example, as described above, φ1 = 0 and φ4 = 0 are set, so that φ5 = 180 °.

  Thus, the second circuit 5 receives the fifth signal S5 and the sixth signal S6 and switches the seventh signal S7 having a phase delayed by φ4 (φ4 ≧ 0). In addition to outputting via the circuit 57, an eighth signal S8 having a phase delayed by φ5 (φ5 = 180 ° + φ1 + φ4) is outputted.

  The third circuit 6 includes a seventh circuit 61 and a comparison circuit 62. In the seventh circuit 61, the terminal 20 is connected to the terminal 1, the terminal 21 is connected to the terminal 2, and the terminal 22 is connected to the comparison circuit 62. The seventh circuit 61 receives the first signal S1 at the terminal 20 and the second signal S2 at the terminal 21, and has information on the phase difference between the first signal S1 and the second signal S2. The thirteenth signal S13 is output from the terminal 22 to the comparison circuit 62.

  FIG. 2 shows an example of the circuit configuration of the seventh circuit 61. The terminal 20 is connected to the gate terminal of the transistor 23, and the terminal 21 is connected to the gate terminal of the transistor 24. Note that a bias circuit (not shown) is provided, and a DC bias voltage is supplied to the gate terminals of the transistors 23 and 24.

  The drain terminal of the transistor 23 is connected to the power supply voltage Vdd. The source terminal of the transistor 23 is connected to the drain terminal of the transistor 24. The source terminal of the transistor 24 is connected to the drain terminal of the transistor 25. The 25 source terminals are connected to the ground potential. The transistor 25 has a drain terminal and a gate terminal connected to each other, and functions as a reference current side transistor of the current mirror circuit.

  Normally, when a positive voltage equal to or higher than the pinch-off voltage is applied to the gate terminal, the n-channel transistor conducts between the drain and source terminals. Therefore, when the first signal S1 and the second signal S2 are positive voltages equal to or higher than the pinch-off voltage, the transistors 23 and 24 are turned on. In this circuit configuration, since the transistor 23 and the transistor 24 form an AND circuit, the power supply voltage is applied to the drain terminal of the transistor 25 only when the first signal S1 and the second signal S2 are both positive voltages equal to or higher than the pinch-off voltage. Vdd is supplied.

  The time when both the transistor 23 and the transistor 24 are in the ON state corresponds to the phase difference between the first signal S1 and the second signal S2. That is, when the phase difference between the two input signals is small, the time for which both are in the ON state is long, and when the phase difference between the two input signals is large, the time for which both are in the ON state is short. Thereby, the increase / decrease in the phase difference between the first signal S1 and the second signal S2 is replaced with the increase / decrease in the supply time of the power supply voltage Vdd to the drain terminal of the transistor 25.

  The transistor 25 can be regarded as a diode equivalently because the gate terminal and the drain terminal are connected. As a result, a voltage corresponding to the current flowing through the drain terminal is obtained at the gate terminal. As described above, since the power supply voltage Vdd is supplied to the drain of the transistor 25 in accordance with the phase difference between the first signal S1 and the second signal S2, the first signal S1 and the signal from the gate terminal of the transistor 25 are supplied. A thirteenth signal S13 having a voltage corresponding to the phase difference from the second signal S2 is output. Specifically, a thirteenth signal S13 having a voltage that decreases as the phase difference between the first signal S1 and the second signal S2 increases is output from the terminal 22 to the comparison circuit 62.

  The comparison circuit 62 receives the thirteenth signal S13 from the seventh circuit 61 and the fourteenth signal S14 having a predetermined voltage from an external circuit (not shown). The comparison circuit 62 compares the voltage of the thirteenth signal S13 and the voltage of the fourteenth signal S14 and switches so that the switch circuit 57 is closed when the voltage of the thirteenth signal S13 is smaller than the voltage of the fourteenth signal S14. A ninth signal S9 for controlling the circuit 57 is output. As the comparison circuit 62, various well-known comparison circuits can be used.

  In this way, the third circuit 6 controls the switch circuit 57 so that the switch circuit 57 is closed when the phase difference between the first signal S1 and the second signal S2 is larger than a predetermined value. Is output. The third circuit 6 may have such a function and may have another circuit configuration. For example, the power of the fundamental wave component of the fifth signal S5 output from the drain terminal of the transistor 7 decreases as the phase difference between the first signal S1 and the second signal S2 increases. Therefore, for example, when the voltage V1 obtained by detecting the power of the fundamental wave component of the fifth signal S5 with the power detector is compared with the voltage of the fourteenth signal S14, the voltage V1 is smaller than the voltage of the fourteenth signal S14. The third circuit 6 may output the ninth signal S9 for controlling the switch circuit 57 so that the switch circuit 57 is closed.

  The fourth circuit 9 receives the seventh signal S7 and the eighth signal S8 from the second circuit 5. The fourth circuit 9 adds the input seventh signal S7 and eighth signal S8 and outputs the tenth signal S10 to the terminal 3. As such a fourth circuit 9, for example, a known addition circuit that adds and outputs the voltages of two input signals can be used.

  FIG. 3 is a circuit diagram showing a conventional signal conversion circuit 40 in which the phase shifter 17, the second circuit 5, and the third circuit 6 are removed from the signal conversion circuit 30 of this example shown in FIG. FIG. 4 is a graph for explaining problems in the conventional signal conversion circuit 40 shown in FIG. In the graph shown in FIG. 4, the horizontal axis indicates the phase difference between the first signal S1 and the second signal S2, and the vertical axis indicates the power of the fundamental component of the fifteenth signal S15 that is the output signal from the signal conversion circuit 40. Show. In this conventional signal conversion circuit 40, the first signal S1 is directly input to the source terminal of the transistor 7 and the gate terminal of the transistor 8, and the second signal S2 is input to the gate terminal of the transistor 7 and the source terminal of the transistor 8. It is input as it is. Then, the signals output from the drain terminals of the transistors 7 and 8 are added as they are, and the fifteenth signal S15 is output.

  As apparent from the graph shown in FIG. 4, in the conventional signal conversion circuit 40 shown in FIG. 3, when the phase difference between the first signal S1 and the second signal S2 increases and approaches 180 degrees, the signal conversion circuit 40 suddenly increases. There arises a problem that the output power decreases. Note that the graph shown in FIG. 4 uses a rectangular wave signal (a signal that is not a complete rectangular wave but has a waveform close to it) as the first signal S1 and the second signal S2, and therefore, When the phase difference with the second signal S2 becomes large and approaches 180 °, the output power rapidly decreases. As the waveforms of the first signal S1 and the second signal S2 approach a sine wave from a complete rectangular wave, the phase difference that causes a decrease in output power decreases.

5-7 is a figure for demonstrating the mechanism in which this problem arises. 5-7, (a) is a graph which shows the waveform of 1st signal S1 and 2nd signal S2, (b) is a graph which shows the waveform of 15th signal S15. 41 indicates the voltage of the first signal S1, 42 indicates the voltage of the second signal S2, 43 indicates the voltage of the fifteenth signal S15, and 47 indicates the pinch-off voltage of the transistors 7 and 8. In each graph, the horizontal axis indicates time, and the vertical axis indicates voltage. 5 shows a state when the phase difference between the first signal S1 and the second signal S2 is small, and FIG. 6 shows that the phase difference between the first signal S1 and the second signal S2 becomes large.
FIG. 7 shows a state when approaching 0 °, and FIG. 7 shows a state when the phase difference between the first signal S1 and the second signal S2 exceeds 180 °. 5 to 7 illustrate a case where the first signal S1 and the second signal S2 are sine waves for the sake of clarity.

  When the phase difference between the first signal S1 and the second signal S2 is small, as shown in FIG. 5, the wave height of the fifteenth signal S15 is sufficiently large. However, when the phase difference between the first signal S1 and the second signal S2 increases and approaches 180 °, the wave height of the fifteenth signal S15 decreases as shown in FIG. As a result, as shown in the graph of FIG. 4, when the phase difference between the first signal S1 and the second signal S2 increases and approaches 180 °, the power of the fundamental wave component of the fifteenth signal S15 decreases rapidly. Problems arise. Note that when the phase difference between the first signal S1 and the second signal S2 exceeds 180 °, spurious signals whose phases differ by 180 ° appear as shown in FIG. 7, and the wave height gradually increases. As a result, as shown in the graph of FIG. 4, as the phase difference between the first signal S1 and the second signal S2 increases beyond 180 °, the power of the fundamental wave component of the fifteenth signal S15 increases abruptly. Phenomenon occurs.

  Since the signal conversion circuit 30 of this example shown in FIG. 1 has the first circuit 4, the phase difference between the third signal S 3 and the fourth signal S 4 input to the transistor 8 is given to the transistor 7. The phase difference between the input first signal S1 and second signal S2 can be increased by φ3. Then, in the graph shown in FIG. 4, when the phase difference between the first signal S1 and the second signal S2 when the power of the fundamental wave component of the fifteenth signal S15 starts to decrease is φ6, the value of φ3 is φ3 = 180 ° −φ6 is set to a value satisfying. Thereby, when the wave height of the fifth signal S5 output from the transistor 7 gradually decreases and the power of the fundamental wave component decreases, the sixth signal S6 whose wave height gradually increases can be output from the transistor 8. Then, the second circuit 5 makes the phases of the fifth signal S5 and the sixth signal S6 equal and outputs them as the seventh signal S7 and the eighth signal S8, and adds them by the fourth circuit 9 and outputs them as the tenth signal S10. To do. Thereby, it is possible to reduce the power reduction of the fundamental wave component of the tenth signal S10 when the phase difference between the first signal S1 and the second signal S2 increases and approaches 180 °.

  The phase difference between the first signal S1 and the second signal S2 when the switch circuit 57 of the second circuit 5 is closed is when the power of the fundamental wave component of the fifteenth signal S15 starts to decrease in the graph shown in FIG. Is set equal to φ6 which is the phase difference between the first signal S1 and the second signal S2. Thereby, the seventh signal S7 can be added to the eighth signal S8 only when necessary.

(Second example of embodiment)
FIG. 8 is a circuit diagram showing a signal conversion circuit of a second example of the embodiment of the present invention. Note that in this example, only differences from the signal conversion circuit 30 of the first example of the above-described embodiment will be described, and the same components will be denoted by the same reference numerals and redundant description will be omitted.

  In the signal conversion circuit 50 of this example, as shown in FIG. 8, the terminal 13 of the first circuit 4 is connected to the gate terminal of the transistor 7, and the terminal 14 of the first circuit 4 is connected to the source terminal of the transistor 7. The terminal 15 of the first circuit 4 is connected to the source terminal of the transistor 8, and the terminal 16 of the first circuit 4 is connected to the gate terminal of the transistor 8. The first signal S1 is input to the gate terminal of the transistor 7, the second signal S2 is input to the source terminal of the transistor 7, the third signal S3 is input to the source terminal of the transistor 8, and the fourth signal S4 is the transistor 8 is input to the gate terminal. The signal conversion circuit 50 of this example having such a configuration also functions in the same manner as the signal conversion circuit 30 of the first example of the embodiment shown in FIG.

(Third example of embodiment)
FIG. 9 is a circuit diagram showing an amplifier circuit according to a third example of the embodiment of the present invention. As shown in FIG. 9, the amplifier circuit 80 of this example includes a fifth circuit 31, a sixth circuit 33, and a transistor in addition to the signal conversion circuit 30 of the first example of the embodiment shown in FIG. 63, a low-pass filter circuit 65, and terminals 34 and 35.

  The eleventh signal S11 is input to the terminal 34 from an external circuit (not shown). In the amplification circuit 80 of the present example, the eleventh signal S11 is a signal having an envelope variation. The fifth circuit 31 is connected to the terminal 34, receives the eleventh signal S11, and the first signal S1 and the second signal S2 whose phase difference changes according to the change in the amplitude of the eleventh signal S11. Is generated. In the amplifier circuit 80 of the present example, the first signal S1 and the second signal S2 are rectangular wave constant envelope signals having the same frequency. The phase difference between the first signal S1 and the second signal S2 is set to increase as the amplitude of the eleventh signal S11 decreases. Then, the fifth circuit 31 outputs the first signal S1 to the terminal 1 of the signal conversion circuit 30, and outputs the second signal S2 to the terminal 2 of the signal conversion circuit 30. As such a fifth circuit 31, a known constant envelope signal generation circuit can be used. Any configuration may be used as long as it is a constant envelope signal generation circuit, and either an analog method or a digital method may be used. Also, conversion of a sine wave signal into a rectangular wave signal can be easily performed using a limiter amplifier or the like.

  The signal conversion circuit 30 receives the first signal S1 and the second signal S2 and outputs from the terminal 3 the tenth signal S10 whose duty ratio changes according to the phase difference between the first signal S1 and the second signal S2. To do.

  The gate terminal of the transistor 63 is connected to the terminal 3 of the signal conversion circuit 30, and the tenth signal S10 is input to the gate terminal via a DC cut capacitor (not shown). A predetermined bias voltage is applied to the gate terminal of the transistor 63 from a bias circuit (not shown). The drain terminal of the transistor 63 is connected to the power supply potential Vdd via the low-pass filter circuit 65. The source terminal of the transistor 63 is connected to a reference potential (ground potential). The transistor 63 outputs the twelfth signal S12, which is a signal obtained by switching amplification of the tenth signal S10, from the drain terminal to the sixth circuit 33.

  The sixth circuit 33 includes an LC series resonance circuit 26 and a matching circuit 27. The LC series resonance circuit 26 is connected to the drain terminal of the transistor 63, and the LC series resonance circuit 26 and the terminal 35 are connected via a matching circuit 27. The LC series resonance circuit 26 includes an inductor and a capacitor connected in series with each other, and the resonance frequency thereof is the same as the fundamental wave frequency of the eleventh signal S11 (same as the fundamental wave frequency of the twelfth signal S12). It is set to approximately the same value. The matching circuit 27 includes an inductor and a capacitor, and is a low-pass filter type matching circuit. The sixth circuit 33 having such a configuration receives the twelfth signal S12 from the signal conversion circuit 30 and mainly outputs a signal having a fundamental frequency of the eleventh signal S11.

  The amplifier circuit 80 of this example having such a configuration can output with linear amplification with high efficiency even when the input eleventh signal S11 is a signal having an envelope variation. In addition, since the signal conversion circuit 30 has a reduced output power when the phase difference between the two input signals is large, the output power is reduced when the amplitude of the input eleventh signal S11 is small. Thus, it is possible to obtain a high-efficiency amplifier circuit with reduced noise. Instead of the signal conversion circuit 30 of the first example of the embodiment shown in FIG. 1, the amplifier circuit 80 having the signal conversion circuit 50 of the second example of the embodiment shown in FIG. 8 may be used. Needless to say.

(Fourth example of embodiment)
FIG. 10 is a block diagram showing a transmission apparatus according to a fourth example of the embodiment of the present invention. As shown in FIG. 10, the transmission apparatus of this example includes a transmission circuit 81, an amplification circuit 80 shown in FIG. 9, and an antenna 82 connected to the transmission circuit 81 via the amplification circuit 80. . According to the transmission apparatus of this example having such a configuration, the transmission signal output from the transmission circuit 81 can be amplified using the high-efficiency amplifier circuit 80 and output to the antenna 82. Can be obtained.

(Fifth example of embodiment)
FIG. 11 is a block diagram showing a communication apparatus according to a fifth example of the embodiment of the present invention. As shown in FIG. 11, the communication apparatus of this example includes a transmission circuit 81, a second amplification circuit 80, an antenna 82 connected to the transmission circuit 81 via the amplification circuit 80, and an antenna 82. And a receiving circuit 83. An antenna sharing circuit 84 is inserted between the antenna 82 and the amplifier circuit 80 and the receiving circuit 83. According to the communication apparatus of this example having such a configuration, the transmission signal output from the transmission circuit 81 can be amplified using the high-efficiency amplifier circuit 80 and output to the antenna 82. Can be obtained.

(Modification)
The present invention is not limited to the embodiments described above, and various modifications and improvements can be made without departing from the spirit of the present invention.

  For example, in the signal conversion circuit 30 of the first example of the embodiment described above and the signal conversion circuit 50 of the second example of the embodiment, the delay amount of the phase of the third signal S3 with respect to the phase of the first signal S1 Although the case where φ1 and the delay amount φ4 of the phase of the seventh signal S7 with respect to the phase of the sixth signal S6 are both 0 is shown, the present invention is not limited to this. For example, when φ1 = 10 °, φ3 = 1 °, φ4 = 20 °, φ2 = φ1 + φ3 = 10 ° + 1 ° = 11 °, and φ5 = 180 ° + φ1 + φ4 = 180 ° + 10 ° + 20 ° = 210 ° It becomes. In this case, a phase shifter with a phase shift amount of 10 ° is newly inserted between the terminal 11 and the terminal 15, and a phase shifter with a phase shift amount of 20 ° is newly inserted between the terminal 53 and the terminal 54. The phase shift amount of the phase shifter 17 disposed between the terminal 12 and the terminal 16 is set to 11 °, and the phase shift of the phase shifter 56 disposed between the terminal 51 and the terminal 52 is inserted. The amount may be set to 210 °.

  Next, a specific example of the signal conversion circuit of the present invention will be described. The electrical characteristics of the signal conversion circuit 30 of the first example of the embodiment of the present invention shown in FIG. 1 and the signal conversion circuit 40 of the comparative example shown in FIG. 3 were calculated by simulation. In this simulation, the first signal S1 and the second signal S2 are rectangular wave signals having a frequency of 730 MHz and a power of 0 dBm. The phase shift amount φ2 in the phase shifter 17 was set to φ2 = φ1 + φ3 = 0 + 1 ° = 1 °. The phase shift amount φ5 in the phase shifter 56 was set to φ5 = 180 ° + φ1 + φ4 = 180 ° + 0 + 0 = 180 °. The transistors 7, 8, 23, 24, and 25 are N-channel FETs.

  The result is shown in the graph of FIG. In the graph, the horizontal axis represents the phase difference between the first signal S1 and the second signal S2, and the vertical axis represents the power of the fundamental wave component of the output signal from the signal conversion circuit. Also, the solid line shows the electrical characteristics of the signal conversion circuit 30 of the first example of the embodiment of the present invention shown in FIG. 1, and the broken line shows the electrical characteristics of the signal conversion circuit 40 of the comparative example shown in FIG. Indicates. According to the graph shown in FIG. 12, in the signal conversion circuit 40 of the comparative example, the power of the fundamental wave component of the output signal suddenly increases from the vicinity where the phase difference between the first signal S1 and the second signal S2 exceeds 179 °. On the other hand, in the signal conversion circuit 30 of the first example of the embodiment of the present invention, it can be seen that there is almost no sudden decrease in the power of the fundamental wave component of the output signal. Thereby, the effectiveness of the present invention can be confirmed.

Further, a circuit obtained by adding the fifth circuit 31 shown in FIG. 9 to the signal conversion circuit 30 of the first example of the embodiment of the invention shown in FIG. 1 and the first of the embodiment of the invention are shown. Instead of the signal conversion circuit 30 of the example, a circuit using the signal conversion circuit 40 of the comparative example shown in FIG. 3 was created, and the electrical characteristics were simulated.

  The result is shown in the graph of FIG. In the graph, the horizontal axis represents the power of the eleventh signal S11 that is an input signal, and the vertical axis represents the power of the fundamental wave component of the output signal from the signal conversion circuit. Further, the solid line shows the electrical characteristics when using the signal conversion circuit 30 of the first example of the embodiment of the present invention shown in FIG. 1, and the broken line shows the signal conversion circuit of the comparative example shown in FIG. The electrical characteristics when 40 is used are shown. According to the graph shown in FIG. 13, when the signal conversion circuit 40 of the comparative example is used, the fundamental wave component of the output signal suddenly starts from the vicinity where the power of the eleventh signal S11 as the input signal becomes smaller than −30 dB. As the power decreases, the linearity between the power of the input signal and the power of the output signal decreases. On the other hand, when the signal conversion circuit 30 of the first example of the embodiment of the present invention is used, the power of the input signal and the output signal are not drastically reduced in the fundamental wave component of the output signal. It can be seen that the linearity with respect to the power is improved. This confirmed the effectiveness of the present invention.

7, 8, 23, 24, 25, 63: transistor 4: first circuit 5: second circuit 6: third circuit 9: fourth circuit 30, 40, 50: signal conversion circuit 31: fifth circuit 33: first 6 circuits 80: amplifying circuit 81: transmitting circuit 82: antenna 83: receiving circuit

Claims (4)

A first signal and a second signal having the same or delayed phase with respect to the first signal are input, and the phases of the first signal, the second signal, and the first signal are φ1 (φ1 ≧ A third signal having a phase delayed by 0) and a fourth signal having a phase delayed by φ2 (φ2 = φ1 + φ3, φ3 is a predetermined positive value). One circuit,
One of the first signal and the second signal is input to the source terminal, and the other of the first signal and the second signal is input to the gate terminal to output the fifth signal from the drain terminal. A transistor,
One of the third signal and the fourth signal is input to the source terminal, and the other of the third signal and the fourth signal is input to the gate terminal to output the sixth signal from the drain terminal. A transistor,
The fifth signal and the sixth signal are input, and a seventh signal having a phase delayed by φ4 (φ4 ≧ 0) is output through the switch circuit, and the fifth signal is output. A second circuit for outputting an eighth signal having a phase delayed by φ5 (φ5 = 180 ° + φ1 + φ4);
A third circuit for outputting a ninth signal for controlling the switch circuit so that the switch circuit is closed when a phase difference between the first signal and the second signal is larger than a predetermined value;
A signal conversion circuit comprising at least a fourth circuit that adds the input seventh and eighth signals and outputs a tenth signal. A signal conversion circuit according to claim 1;
A fifth circuit that receives the eleventh signal and outputs the first signal and the second signal whose phase difference changes in accordance with a change in amplitude of the eleventh signal;
A transistor for inputting the tenth signal directly or through another circuit to the gate terminal and outputting a twelfth signal from the drain terminal;
An amplifier circuit comprising at least a sixth circuit that receives the twelfth signal and outputs a signal having a fundamental frequency of the eleventh signal.   A transmission apparatus comprising: a transmission circuit; an amplification circuit according to claim 2; and an antenna connected to the transmission circuit via the amplification circuit.   It has at least a transmission circuit, an amplification circuit according to claim 2, an antenna connected to the transmission circuit via the amplification circuit, and a reception circuit connected to the antenna. Communication device.

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