JP2013041503A - Reset circuit and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reset a reset object satisfactorily.SOLUTION: A reset circuit and an electronic apparatus of the embodiment include an input section and a reset section. The input section receives input of an abnormality detection signal output from an abnormality detection section provided in a reset object having an execution section for executing BIOS. When the input section receives input of the abnormality detection signal, the reset section resets the reset object.

Description

  Embodiments described herein relate generally to a reset circuit and an electronic apparatus.

  2. Description of the Related Art Conventionally, in an electronic device such as a PC equipped with a BIOS, when a power switch is turned on, power supply is started, and startup processing for initializing hardware using the BIOS is executed. For example, if an error occurs for some reason during the activation process, a malfunction such as a process stop or runaway occurs.

  As a countermeasure against such a malfunction phenomenon, some devices avoid the malfunction phenomenon by starting a watchdog timer during a startup process and applying a PCI reset to the electronic device.

  However, the PCI reset is a reset from the BIOS, and if an error occurs due to hardware such as a CPU or a chip set that executes the BIOS, the reset may not be performed.

  The reset circuit and the electronic device of the embodiment include an input unit and a reset unit. An abnormality detection signal output from an abnormality detection unit provided in a reset target unit having an execution unit that executes BIOS is input to the input unit. The reset unit resets the reset target unit when the abnormality detection signal is input to the input unit.

FIG. 1 is a block diagram illustrating a configuration of an electronic device according to the embodiment. FIG. 2 is a flowchart illustrating a flow of reset processing executed by the reset circuit according to the embodiment.

  Hereinafter, an embodiment of an electronic device according to an embodiment will be described in detail with reference to the accompanying drawings.

  As shown in FIG. 1, the electronic device 1 includes a device main body 10 and a reset circuit 20 connected to the device main body 10. The electronic device 1 is, for example, a PC (Personal Computer), a POS (Point of Sales) terminal, or the like. In the present embodiment, the device main body 10 corresponds to a reset target unit.

  The device body 10 includes a CPU (Central Processing Unit) 11, a chip set 12, a power supply circuit 13, an AND circuit 15, a gate array 16, and a storage unit 17.

  The CPU 11 executes a basic input / output system (BIOS) and a predetermined control program stored in the storage unit 17, and controls the operation of each unit constituting the electronic device 1. A storage unit 17, a power switch 14, a display (not shown), a keyboard (not shown), and the like are connected to the CPU 11 via a chipset 12. The CPU 11 is mounted on a motherboard (not shown) together with the chipset 12, the storage unit 17, and an input / output unit (I / O) (not shown). The CPU 11 constitutes a control unit with the chip set 12. The CPU 11 executes the BIOS stored in the storage unit 17 and executes processing such as predetermined initialization processing. The CPU 11 corresponds to an execution unit that executes BIOS.

  The chip set 12 executes the BIOS stored in the storage unit 17 and executes processing such as predetermined initialization processing. A power switch 14 is connected to the chip set 12 via an AND circuit 15. Further, the reset unit 23 of the reset circuit 20 is connected to the chip set 12 via the AND circuit 15. The chip set 12 corresponds to an execution unit that executes BIOS.

  The storage unit 17 includes a ROM (Read Only Memory), a RAM (Random Access Memory), and the like. The storage unit 17 stores a BIOS and a control program in the ROM. The BIOS includes programs and settings related to initialization processing of each unit included in the electronic device 1. The BIOS also includes a program for causing the CPU 11 to output a clear signal for clearing a count value counted by a watch dog timer, which will be described later, from the CPU 11 at a predetermined cycle.

  The gate array 16 has a watchdog timer 16a. The watchdog timer 16a starts measuring time when power supply from the power supply circuit 13 is started by pressing the power switch 14 or the like. Further, when the watchdog timer 16a receives a clear signal from the CPU 11, the watchdog timer 16a clears the counted value and then starts counting again. The gate array 16 monitors the count value of the watchdog timer 16 a, and inputs a WDT (watchdog timer) signal to the input unit 21 of the reset circuit 20 when the count value passes a predetermined time (timeout value). To do. That is, the gate array 16 monitors the device body 10 by monitoring a clear signal from the CPU 11. Here, in the present embodiment, the WDT signal corresponds to an abnormality detection signal output from the abnormality detection unit. Note that the clear signal may be output from the chip set 12 instead of the CPU 11.

  The power supply circuit 13 is a power supply unit that supplies power to each unit of the electronic device 1. The power supply circuit 13 switches between on and off in response to the user pressing the power switch 14 and starts supplying power to each unit when the power is on. Further, the power supply circuit 13 shifts its own state from off (power-off state) to on (power supply state) or from off to on according to the control of the reset circuit 20.

  The reset circuit 20 is configured by a programmable logic device. Specifically, the reset circuit 20 is configured by a CPLD (Complex Programmable Logic Device). In other words, the reset circuit 20 is a power cycle reset circuit. The reset circuit 20 is connected to the gate array 16, the AND circuit 15, and the power supply circuit 13. The reset circuit 20 includes an input unit 21, a voltage detection unit 22, and a reset unit 23. The reset circuit 20 is constantly supplied with power from the power supply circuit 13 and operates even when the device main body 10 is in an off state. Further, the reset circuit 20 does not execute the BIOS of the device main body 10. That is, the reset circuit 20 operates independently with respect to the BIOS of the device body 10.

  The WDT signal output from the gate array 16 provided in the device main body 10 is input to the input unit 21.

  The voltage detection unit 22 monitors the power supply circuit 13 and detects the voltage value of the power supply used in the device main body 10.

  The reset unit 23 inputs a power-on (ON) signal to the AND circuit 15 of the device body 10 when the WDT signal is not input to the input unit 21, that is, when the device body 10 is in a normal state. Therefore, when the device main body 10 is in a normal state, when the power switch 14 is turned on, the power ON signal from the power switch 14 and the power ON signal from the reset unit 23 are input to the AND circuit 15. The power ON signal is input from the AND circuit 15 to the power supply circuit 13 via the chip set 12. Thereby, the power supply circuit 13 supplies starting power to each part of the apparatus main body 10. On the other hand, when the power switch 14 is turned off while the power ON signal is input from the reset unit 23 to the AND circuit 15, a power OFF (OFF) signal is input from the power switch 14 to the AND circuit 15. A power off signal is input from 15 to the power supply circuit 13 via the chipset 12. Thereby, the power supply circuit 13 interrupts | blocks the electric power supply to each part.

  On the other hand, when the power switch 14 is turned on and the WDT signal is input to the input unit 21, that is, when the device main body 10 is in an abnormal state, the reset unit 23 resets the device main body 10. Specifically, when the device main body 10 is in an abnormal state, the reset unit 23 turns off and on the power of the device main body 10 to restart the device main body 10. In the present embodiment, the reset unit 23 outputs a power-on signal to the device body 10 after a specified time has elapsed since the power-off signal was output to the device body 10. More specifically, when the voltage value detected by the voltage detection unit 22 after a specified time has elapsed after the power-off signal is output, the reset unit 23 turns on the power to the device body 10. Output a signal. The specified time is, for example, the time required for each part of the device body 10 in the on state to successfully shift to the off state.

  At this time, since the power switch 14 is turned on in the device main body 10, when a power off signal is input from the reset unit 23 to the AND circuit 15, the power off signal is transmitted from the AND circuit 15 via the chip set 12. Input to the power supply circuit 13. Thereby, the power supply circuit 13 interrupts | blocks the electric power supply to each part. On the other hand, when a power-on signal is input from the reset unit 23 to the AND circuit 15, the power-on signal is input from the AND circuit 15 to the power circuit 13 via the chip set 12. Thereby, the power supply circuit 13 supplies starting power to each part. As described above, the reset unit 23 functions as an output unit that outputs a signal (power-on signal, power-off signal) for resetting the device body 10 to the device body 10.

  Hereinafter, the flow of reset processing executed by the reset circuit 20 will be described with reference to FIG.

  First, the input unit 21 waits for input of a WDT signal from the gate array 16 of the device body 10 (No in step S1). When the WDT signal is input to the input unit 21 (Yes in step S1), the reset unit 23 outputs a power-off signal to the device body 10 (step S2). Thereby, in the apparatus main body 10, the power supply circuit 13 starts the interruption | blocking of electric power supply.

  If the reset unit 23 outputs a power-off signal, the reset unit 23 waits for a specified time (step S3), and then determines whether the power supply voltage of the device body 10 has become lower than a specified threshold (step S4). The value of the power supply voltage of the device main body 10 is a voltage value detected by the voltage detection unit 22. If the power supply voltage of the device body 10 is not lower than the prescribed threshold (No in step S4), the reset unit 23 returns to step S3 and repeats the processes in steps S3 and S4.

  The reset unit 23 outputs a power-on signal to the device main body 10 when the power supply voltage of the device main body 10 becomes lower than the specified threshold (Yes in Step S4) (Step S5). Thereby, in the apparatus main body 10, the power supply circuit 13 starts electric power supply. In this way, the device main body 10 is reset.

  As described above, in this embodiment, the abnormality detection signal output from the gate array 16 provided in the device main body 10 having the CPU 11 and the chipset 12 that executes the BIOS is input to the input unit 21 of the reset circuit 20. When the reset is performed, the reset unit 23 of the reset circuit 20 resets the device main body 10. Therefore, even if an error occurs in the device main body 10 due to hardware such as the CPU 11, the device main body 10 can be satisfactorily reset by the reset circuit 20 without depending on the BIOS.

  The reset unit 23 outputs a power-on signal to the device body 10 after a specified time has elapsed since the power-off signal was output to the device body 10. Therefore, it can suppress that each part of the apparatus main body 10 blocks | interrupts with a power-on signal that it transfers to an OFF state.

  In addition, the reset unit 23 outputs a power-on signal to the device body 10 when the voltage value detected by the voltage detection unit 22 is lower than a predetermined threshold after a predetermined time has elapsed since the power-off signal was output. To do. Therefore, the apparatus main body 10 can be made to perform a reset operation satisfactorily.

  In the present embodiment, the example in which the reset circuit 20 is configured by a programmable logic device has been described. However, the present invention is not limited thereto, and the reset circuit 20 may be configured by a circuit other than the programmable logic device.

  Although the embodiment of the present invention has been described, the above embodiment is presented as an example, and is not intended to limit the scope of the invention. The novel embodiment can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

DESCRIPTION OF SYMBOLS 1 ... Electronic device 10 ... Main part (reset object part)
11 ... CPU (execution unit)
12 ... Chipset (execution unit)
16 ... Gate array (abnormality detection unit)
DESCRIPTION OF SYMBOLS 20 ... Reset circuit 21 ... Input part 22 ... Voltage detection part 23 ... Reset part

JP 2008-140072 A

Claims (6)

An input unit to which an abnormality detection signal output from an abnormality detection unit provided in a reset target unit having an execution unit that executes BIOS is input;
When the abnormality detection signal is input to the input unit, a reset unit that resets the reset target unit;
A reset circuit comprising:   2. The reset circuit according to claim 1, wherein the reset unit outputs a power-on signal to the reset target unit after a predetermined time has elapsed since the power-off signal was output to the reset target unit. A voltage detection unit for detecting a voltage value of a power source used in the reset target unit;
The reset unit outputs the power-on signal to the reset target unit when a voltage value detected by the voltage detection unit is lower than a predetermined threshold after a predetermined time has elapsed since the power-off signal was output. The reset circuit according to claim 2.   The reset circuit according to any one of claims 1 to 3, wherein the reset circuit is configured by a programmable logic device. A reset target unit having an execution unit and an abnormality detection unit for executing BIOS;
An input unit to which an abnormality detection signal output from the abnormality detection unit is input, and a reset circuit having a reset unit that resets the reset target unit when the abnormality detection signal is input to the input unit;
Electronic equipment comprising.   The electronic device according to claim 5, wherein the reset unit outputs a power-on signal to the reset target unit after a predetermined time has elapsed since the power-off signal was output to the reset target unit.

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