JP2013037608A - Arrangement/wiring device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an arrangement/wiring device for achieving the shortening of a revision period and the reduction of mask revision costs.SOLUTION: A comparison part 32 specifies a revision place of logic from an existing net and revision information, and extracts logical connection information for matching logic. A determination part 33 determines the possibility/impossibility of the reconnection of wiring in order from the highest layer of a metal layer on the basis of layout information and the logical connection information extracted by the comparison part. Then, a replacement part 34 performs the reconnection of wiring in the metal layer whose reconnection is determined to be possible by the determination part 33. Therefore, it is possible to achieve the shortening of the revision period and the reduction of mask revision costs by revising only a higher layer.

Description

  The present invention relates to a technique for performing automatic placement and routing of a semiconductor integrated circuit, and more particularly to a placement and routing apparatus that efficiently revises wiring in a metal layer.

  In recent years, higher integration of semiconductor integrated circuits has progressed, and accordingly, the multilayer of metal layers has also progressed. Conventionally, when the revision is limited to the metal layer by changing the logic circuit, etc., it is not possible to know how many layers each net is connected to. It is common to confirm this.

  If a violation occurs by revising the metal layer, the violation is corrected and repeated revisions until the violation disappears. After that, since it is necessary to perform timing verification to check whether there is any problem, a very long revision period was required. As a technique related to this, there are inventions disclosed in the following Patent Documents 1 and 2.

  In Patent Document 1, it is difficult to modify a wiring by limiting a wiring layer to be modified and minimizing a change in timing and a wiring route in the conventional automatic wiring correcting method. The purpose is to solve the problem of increasing the design period and the development cost. The difference between the netlist before correction and the netlist after correction is taken to recognize the net to be corrected or added, and the range where there is a net to be corrected in the layout before correction is defined as the wiring correction area. On the other hand, timing constraints are applied to the timing difference value and the corrected or added net. While verifying the timing of the wiring path, change the wiring path from the top layer wiring and perform correction net or additional net wiring to limit the wiring layer to be corrected and minimize timing and wiring path changes It is possible to correct the wiring.

  Patent Document 2 aims to facilitate layout pattern creation when a logic circuit is revised after creating a layout pattern, and to reduce the number of revisions of the mask process. Collect three feed-through cells, create several of them, replace the feed-through cells collected three by three with feed-through cells with an inverter layout pattern, and create a layout pattern. When the circuit is revised, only the input of the feedthrough cell having the layout pattern of the inverter inserted by the feedthrough cell correcting means and the inter-cell wiring are corrected.

JP 2002-297683 A JP 05-326708 A

  However, in the revision method limited to the metal layer described above, there is no information on how many layers each net is connected to. Therefore, when a netlist is revised, it is used as a layout tool after the netlist is created. Read and check the metal layer. When a metal layer other than the required metal layer is used, the net list is corrected repeatedly, so that it takes a long time to correct the net list.

  In addition, when there are many correction points, these operations require a very long period. For this reason, in most varieties, the revision period has priority and the netlist has not been revised with only a minimum number of metal layers. For example, when a semiconductor device having six metal layers is formed, a process is used in which layers from the first layer to the sixth layer are formed in order. Since it takes a considerable amount of time to create the first layer to the sixth layer, when the metal layer of the first layer is revised, all the masks and wafers created so far are wasted. As a result, there is a problem in that unnecessary mask revision costs are incurred.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide a placement and routing apparatus capable of shortening the revision period and reducing the mask revision cost.

  According to one embodiment of the present invention, there is provided a placement and routing apparatus for switching the wiring of a semiconductor device having a plurality of metal layers. The comparison unit identifies a logic revision part from the existing net and the revision information, and extracts logical connection information for matching the logic. Based on the layout information and the logical connection information extracted by the comparison unit, the determination unit determines whether or not it is possible to change the wiring in order from the uppermost layer of the metal layer. The replacement unit performs wiring connection in the metal layer that is determined to be connectable by the determination unit.

  Based on the layout information and the logical connection information extracted by the comparison unit, the determination unit determines whether or not to change the wiring in order from the top layer of the metal layer. It becomes possible to reduce the mask revision cost.

It is a flowchart for demonstrating the process sequence of a general metal layer revision. It is a block diagram which shows the hardware structural example of the place-and-route apparatus in the 1st Embodiment of this invention. It is a block diagram which shows the functional structure of the arrangement | positioning wiring apparatus in the 1st Embodiment of this invention. It is a flowchart for demonstrating the process sequence of the arrangement | positioning wiring apparatus in the 1st Embodiment of this invention. It is a figure for demonstrating the revision of a net concretely. It is a flowchart for demonstrating the process sequence of the arrangement | positioning wiring apparatus in the 2nd Embodiment of this invention. It is a flowchart for demonstrating the process sequence of the arrangement | positioning wiring apparatus in the 3rd Embodiment of this invention. It is a flowchart for demonstrating the process sequence of the arrangement | positioning wiring apparatus in the 4th Embodiment of this invention. It is a flowchart for demonstrating the process sequence of the arrangement | positioning wiring apparatus in the 5th Embodiment of this invention. It is a figure which shows an example of the usage method of a dummy cell. It is a flowchart for demonstrating the process sequence of the arrangement | positioning wiring apparatus in the 6th Embodiment of this invention. It is a figure which shows an example of reconnection of the location where setup violation has generate | occur | produced. It is a flowchart for demonstrating the process sequence of the arrangement | positioning wiring apparatus in the 7th Embodiment of this invention. It is a figure which shows an example of reconnection of the location where setup violation has generate | occur | produced. It is a flowchart for demonstrating the process sequence of the arrangement | positioning wiring apparatus in the 8th Embodiment of this invention. It is a figure which shows an example of reconnection of the location where setup violation has generate | occur | produced. It is a flowchart for demonstrating the process sequence of the arrangement | positioning wiring apparatus in the 9th Embodiment of this invention. It is a figure which shows an example of reconnection of the location where setup violation has generate | occur | produced. It is a flowchart for demonstrating the process sequence of the arrangement | positioning wiring apparatus in the 10th Embodiment of this invention. It is a figure which shows an example of the change of the location where the hold violation has generate | occur | produced. It is a flowchart for demonstrating the process sequence of the arrangement | positioning wiring apparatus in the 11th Embodiment of this invention. It is a figure which shows an example of the change of the location where the hold violation has generate | occur | produced. It is a flowchart for demonstrating the process sequence of the arrangement | positioning wiring apparatus in the 12th Embodiment of this invention. It is a figure which shows an example of the change of the location where the transition violation has generate | occur | produced. It is a flowchart for demonstrating the process sequence of the arrangement | positioning wiring apparatus in the 13th Embodiment of this invention. It is a figure which shows an example of the change of the location where the transition violation has generate | occur | produced. It is a flowchart for demonstrating the process sequence of the arrangement | positioning wiring apparatus in the 14th Embodiment of this invention. It is a figure which shows an example of the change of the location where the transition violation has generate | occur | produced.

  FIG. 1 is a flowchart for explaining a general metal layer revision processing procedure. First, since it is not known how many layers each net is connected to, a net list is created from the logic circuit information (S11). Then, the created netlist is read into the layout tool (S12), and the metal layer (used metal layer) used for the netlist revision and whether the wiring converges are confirmed (S13). If there is a problem in the confirmation result (S13, NG), the process returns to step S11 and the subsequent processing is repeated.

  If there is no problem in the confirmation result (S13, OK), STA (Static Timing Analysis) is performed using the revised netlist (S14), and the timing is confirmed (S15). If there is a violation in the timing confirmation (S15, VIOLATION), the process returns to step S11 and the subsequent processing is repeated. If there is no violation in the timing confirmation (S15, MET), the process is terminated.

  As described above, since it is necessary to repeatedly correct the netlist until there is no violation in the timing confirmation, it took a long time to correct the netlist. The placement and routing apparatus according to the embodiment of the present invention confirms whether or not the wiring can be changed in order from the upper layer of the metal layer, thereby shortening the revision period and reducing the revision cost.

(First embodiment)
FIG. 2 is a block diagram illustrating a hardware configuration example of the placement and routing apparatus according to the first embodiment of the present invention. The placement and routing apparatus is realized by a general computer, and includes a computer main body 1, a display device 2, an FD drive 3 to which an FD (Flexible Disk) 4 is mounted, a keyboard 5, a mouse 6, and a CD-ROM (Compact Disc-Read Only). A CD-ROM device 7 to which a memory 8 is mounted, and a network communication device 9. The placement and routing program is supplied by a recording medium such as FD4 or CD-ROM8. By executing the placement and routing program by the computer main body 1, a layout after the metal layer revision is generated. Further, the placement and routing program may be supplied to the computer main body 1 from another computer via a communication line.

  The computer main body 1 includes a CPU 10, a ROM (Read Only Memory) 11, a RAM (Random Access Memory) 12, and a hard disk 13. The CPU 10 performs processing while inputting / outputting data to / from the display device 2, FD drive 3, keyboard 5, mouse 6, CD-ROM device 7, network communication device 9, ROM 11, RAM 12 or hard disk 13. The placement and routing program recorded in the FD 4 or the CD-ROM 8 is stored in the hard disk 13 by the CPU 10 via the FD drive 3 or the CD-ROM device 7. The CPU 10 loads a layout and wiring program from the hard disk 13 to the RAM 12 and executes it appropriately, thereby generating a layout after the metal layer revision.

  FIG. 3 is a block diagram showing a functional configuration of the placement and routing apparatus according to the first embodiment of the present invention. In this placement and routing apparatus, the CPU 10 of the computer main body 1 executes the program 21 stored in the RAM 12 or the like, thereby realizing the functions of the placement unit 31, the comparison unit 32, the determination unit 33, and the replacement unit 34. The storage unit 22 such as the RAM 12 stores information such as existing net information 41, revision information 42, timing violation information 43, and transition violation information 44. The designer inputs the existing net information 41 and the revision information 42, or the timing violation information 43 and the transition violation information 44 that do not require a logic change, and stores the information in the storage unit 22 of the design tool 20.

  The placement unit 31 extracts placement information and wiring information around the revised portion of the netlist from the layout information.

  When the revised part is between flip-flops (hereinafter abbreviated as F / F), the comparison unit 32 searches the logic circuit from the revised part to the F / F in the direction of the input side. In the case between the terminal and the F / F, a logic circuit is generated by searching for a logic circuit from the revised part to the terminal or the F / F in the direction of the input side. Then, the logic matrix of the existing net is compared with the logic matrix of the created revised net, and a plurality of candidates are extracted in the order in which the revision contents are easy with respect to the specific part of the logic change and the revision contents.

  The determination unit 33 extracts, from the layout information, information on how many layers of candidate portions for logic change are connected and information on how many layers a cell that needs to be added exists. For example, in the case of six metal layers, is it possible to switch to a logic circuit net having the same function as the logic change information extracted by the comparison unit 32 only in the sixth layer, which is the highest layer first? Confirm whether or not. If any of the logic change candidates is connected in the sixth layer, and cells that need to be added are also in the sixth layer, switching in only the sixth layer is possible. If it is impossible only with the sixth layer, it is determined whether or not the net can be reconnected only with the fifth layer. If this is not possible, it is determined whether or not it is possible to reconnect the net between the fifth layer and the sixth layer. In the same manner, it is determined whether or not the nets can be reconnected, such as the fourth layer, the sixth layer, the fourth layer to the sixth layer, and so on.

  The replacement unit 34 switches the logic circuit after the change extracted by the comparison unit 32 to the net in the hierarchy determined to be switchable by the determination unit 33.

  FIG. 4 is a flowchart for explaining the processing procedure of the placement and routing apparatus according to the first embodiment of the present invention. First, the arrangement unit 31 refers to the revision information 52 and identifies a logic revision part (S21). Then, the comparison unit 32 generates a logic matrix from the external terminal or F / F to the revised part (S22).

  Next, the comparison unit 32 compares the logic matrix of the existing logic and the logic matrix of the revised logic (S23), and extracts logic / connection information for matching the logic (S24). Only the logic correction points are extracted here.

  Next, the determination unit 33 confirms whether or not it is possible to change the net only in the sixth layer of the metal layer (S25). When reconnection is possible only in the sixth layer (S25, OK), the process proceeds to step S29, and reconnection is performed only in the sixth layer.

  In addition, when reconnection only in the sixth layer is impossible (S25, NG), it is confirmed whether or not reconnection of the net is possible only in the fifth layer (S26). If reconnection is possible only in the fifth layer (S26, OK), the process proceeds to step S29, and reconnection is performed only in the fifth layer.

  In addition, when reconnection only at the fifth layer is impossible (S26, NG), whether or not reconnection of nets at the fifth layer and the sixth layer is possible is confirmed (S27). If reconnection at the fifth layer and the sixth layer is possible (S27, OK), the process proceeds to step S29, and reconnection at the fifth layer and the sixth layer is performed.

  Then, the same processing is performed, and it is confirmed whether or not reconnection of nets in the first to sixth layers is possible (S28). If reconnection in the first layer to the sixth layer is possible (S28, OK), the process proceeds to step S29, and reconnection in the first layer to the sixth layer is performed.

  In step S29, the replacement unit 34 generates the revised net 53, which is information on the net after reconnection, and the revision result information 54, which is layout information to which the net has been reconnected. .

  FIG. 5 is a diagram for specifically explaining the revision of the net. FIG. 5A shows an example of the existing net information 51 and the revision information 52. The revision information 52 describes information on which hierarchy (instance) and how many cells of which type, and can be revised by a net. FIG. 5A describes that one inverter (INV) is required for the output of the buffer S4.

  FIG. 5B shows a net when the revision information 52 is virtually reflected in the existing net information 51. As shown in FIG. 5B, an inverter is added between the buffer S4 and the AND gate S7.

  FIG. 5C is a diagram showing a logic matrix from F / F to the revised part. Going back to the input side from the revision information change location, all conditions (eight in the case of 3 bits) are simulated from all F / Fs, and logic matrix information up to the revision location is generated.

  In the existing net, the output of the AND gate S7 becomes “1” when the output of the F / F (S1 to S3) is “111”, and the output of the AND gate S7 becomes “0” otherwise. Is shown.

  In the logic revision net, the output of the AND gate S7 is “1” when the output of the F / F (S1 to S3) is “011”, and the output of the AND gate S7 is “0” otherwise. It is shown that.

  FIG. 5D shows a logic circuit generated by comparison of logic matrices. The logic matrix of the existing net and the logic matrix of the logic revised net are combined and compared in a matrix or circuit, and where and what logic is required is specified.

  FIG. 5E is a diagram showing logical connection information for matching logic. As locations that can be connected, a net (candidate 1) that connects F / F (S1) and buffer S4 and a net (candidate 2) that connects buffer S4 and AND gate S7 are extracted.

  FIG. 5F is a diagram showing confirmation of whether or not reconnection is possible. From the layout information, it is extracted how many layers of the candidate are connected to the metal layer and how many layers of necessary dummy cells are arranged in the periphery, and it is determined whether or not reconnection is possible in order from the upper layer.

  As described above, the placement and routing apparatus according to the present embodiment compares the logic matrix of the existing net with the logic matrix of the revised logic net, and generates correction information for matching the logic. Then, the nets and the layout are generated by checking whether or not the nets can be reconnected in order from the top layer. In the metal revision, the slicing process is sequentially performed from the first metal layer. Therefore, the revision of only the upper layer can shorten the revision period and reduce the mask revision cost, and the revision can be performed with the minimum number of metals.

(Second Embodiment)
In the first embodiment, the logic matrix from the terminal or F / F to the logic revision location is generated, the logic / connection information for matching the logic is extracted, and the nets are switched. In the second embodiment of the present invention, a plurality of candidates are extracted in the order in which the logic can be easily changed in the logic including the logic matching portion.

  The hardware configuration and functional configuration of the placement and routing apparatus in the second embodiment of the present invention are the same as the hardware configuration and functional configuration of the placement and routing apparatus in the first embodiment shown in FIGS. It is. Therefore, detailed description of overlapping configurations and functions will not be repeated.

  FIG. 6 is a flowchart for explaining the processing procedure of the placement and routing apparatus according to the second embodiment of the present invention. First, the placement unit 31 refers to the revision information 52 and identifies a logic revision part (S31). Then, the comparison unit 32 generates a logic matrix from the external terminal or F / F to the revised part (S32).

  Next, the comparison unit 32 compares the logic matrix of the existing logic and the logic matrix of the revised logic (S33), and extracts logic / connection information for matching the logic (S34). What is extracted here includes not only the logic correction portion but also the logic matching portion. For example, several logic cells connected from the logic correction point to the output side are included.

  Next, the determination unit 33 confirms whether or not it is possible to change the net only in the sixth layer of the metal layer (S35). If reconnection is possible only in the sixth layer (S35, OK), the process proceeds to step S39, and reconnection is performed only in the sixth layer.

  In addition, when it is impossible to change only the sixth layer (S35, NG), it is confirmed whether or not the net can be changed only in the fifth layer (S36). If reconnection is possible only in the fifth layer (S36, OK), the process proceeds to step S39, and reconnection is performed only in the fifth layer.

  In addition, if reconnection only at the fifth layer is impossible (S36, NG), whether or not reconnection of nets at the fifth layer and the sixth layer is possible is confirmed (S37). If reconnection at the fifth layer and the sixth layer is possible (S37, OK), the process proceeds to step S39, and reconnection at the fifth layer and the sixth layer is performed.

  Then, the same processing is performed, and it is confirmed whether or not reconnection of nets in the first to sixth layers is possible (S38). If reconnection at the first layer to the sixth layer is possible (S38, OK), the process proceeds to step S39, and reconnection at the first layer to the sixth layer is performed.

  As described above, according to the placement and routing apparatus of the present embodiment, a plurality of candidates are extracted in the order in which the logic can be easily changed in the logic including the logic matching portion, and the possibility of reconnection is confirmed. Therefore, it is possible to achieve the same effect as the effect described in the first embodiment.

(Third embodiment)
In the first to second embodiments, when a logic matrix from a terminal or F / F to a logic revision location is generated and logic / connection information for matching logic is extracted, logic cells are particularly limited. It was not a thing. In the third embodiment of the present invention, when a logic cell for matching logic is extracted, a nearby one of dummy cells arranged in advance is used. The dummy cell includes an AND gate, an OR gate, an inverter, an F / F, and the like.

  The hardware configuration and functional configuration of the placement and routing apparatus in the third embodiment of the present invention are the same as the hardware configuration and functional configuration of the placement and routing apparatus in the first embodiment shown in FIGS. It is. Therefore, detailed description of overlapping configurations and functions will not be repeated. Note that dummy cell arrangement information, which will be described later, is stored in the storage unit 22 shown in FIG.

  FIG. 7 is a flowchart for explaining the processing procedure of the placement and routing apparatus according to the third embodiment of the present invention. First, the placement unit 31 refers to the revision information 52 and identifies a logic revision part (S41). Then, the comparison unit 32 generates a logic matrix from the external terminal or F / F to the revised part (S42).

  Next, the comparison unit 32 compares the logic matrix of the existing logic with the logic matrix of the revised logic (S43), and extracts logic / connection information for matching the logic (S44). What is extracted here is a dummy cell close to the logic correction location.

  Next, the determination unit 33 confirms whether or not it is possible to change the net only in the sixth layer of the metal layer (S45). If reconnection is possible only in the sixth layer (S45, OK), the process proceeds to step S49, and reconnection is performed only in the sixth layer.

  In addition, when it is impossible to change only the sixth layer (S45, NG), it is confirmed whether or not the net can be changed only in the fifth layer (S46). If reconnection is possible only in the fifth layer (S46, OK), the process proceeds to step S49, and reconnection is performed only in the fifth layer.

  In addition, when reconnection only at the fifth layer is impossible (S46, NG), whether or not reconnection of nets at the fifth layer and the sixth layer is possible is confirmed (S47). If reconnection at the fifth layer and the sixth layer is possible (S47, OK), the process proceeds to step S49, and reconnection at the fifth layer and the sixth layer is performed.

  Then, the same processing is performed, and it is confirmed whether or not reconnection of nets in the first to sixth layers is possible (S48). If reconnection at the first layer to the sixth layer is possible (S48, OK), the process proceeds to step S49, and reconnection at the first layer to the sixth layer is performed.

  As described above, according to the placement and routing apparatus of the present embodiment, when extracting a logic cell for matching logic, the closest one of dummy cells placed in advance is used. It is possible to achieve the same effects as those described in the embodiment.

(Fourth embodiment)
In the third embodiment, when a logic cell for matching logic is extracted, a nearby one of dummy cells arranged in advance is used. In the fourth embodiment of the present invention, when a logic cell for matching logic is extracted, if there is no appropriate dummy cell nearby, a part of the dummy cell input of each layer is fixed or a plurality of dummy cells are fixed. By combining these dummy cells, an appropriate logic circuit is obtained.

  The hardware configuration and functional configuration of the placement and routing apparatus in the fourth embodiment of the present invention are the same as the hardware configuration and functional configuration of the placement and routing apparatus in the first embodiment shown in FIGS. It is. Therefore, detailed description of overlapping configurations and functions will not be repeated. Note that dummy cell arrangement information, which will be described later, is stored in the storage unit 22 shown in FIG.

  FIG. 8 is a flowchart for explaining the processing procedure of the placement and routing apparatus according to the fourth embodiment of the present invention. First, the comparison unit 32 refers to the revision information 52 and identifies a logical revision location (S51). Then, the placement unit 31 generates a logic matrix from the external terminal or F / F to the revised part (S52).

  Next, the comparison unit 32 compares the logic matrix of the existing logic and the logic matrix of the revised logic (S53), and extracts logic / connection information for matching the logic (S54). Here, when there is no appropriate dummy cell nearby, an appropriate logic circuit is obtained by fixing a part of the input of the dummy cell of each layer or combining a plurality of dummy cells.

  Next, the determination unit 33 confirms whether or not it is possible to change the net only in the sixth layer of the metal layer (S55). If reconnection is possible only in the sixth layer (S55, OK), the process proceeds to step S59, and reconnection is performed only in the sixth layer.

  In addition, when it is impossible to change only the sixth layer (S55, NG), it is confirmed whether or not the net can be changed only in the fifth layer (S56). If reconnection is possible only in the fifth layer (S56, OK), the process proceeds to step S59, and reconnection is performed only in the fifth layer.

  In addition, when reconnection only in the fifth layer is impossible (S56, NG), it is confirmed whether or not reconnection of nets in the fifth layer and the sixth layer is possible (S57). If reconnection at the fifth layer and the sixth layer is possible (S57, OK), the process proceeds to step S59, and reconnection at the fifth layer and the sixth layer is performed.

  Then, the same processing is performed, and it is confirmed whether or not reconnection of nets in the first to sixth layers is possible (S58). If reconnection in the first layer to the sixth layer is possible (S58, OK), the process proceeds to step S59, and reconnection in the first layer to the sixth layer is performed.

  As described above, according to the placement and routing apparatus of the present embodiment, when a logic cell for matching logic is extracted, if there is no appropriate dummy cell nearby, a part of the input of the dummy cell in each layer Since an appropriate logic circuit is obtained by fixing a plurality of dummy cells or combining a plurality of dummy cells, an effect similar to the effect described in the first embodiment can be achieved.

(Fifth embodiment)
The hardware configuration and functional configuration of the placement and routing apparatus in the fifth embodiment of the present invention are the same as the hardware configuration and functional configuration of the placement and routing apparatus in the first embodiment shown in FIGS. It is. Therefore, detailed description of overlapping configurations and functions will not be repeated. Note that dummy cell placement information, layout parameters, and placement / wiring information described later are stored in the storage unit 22 shown in FIG.

  FIG. 9 is a flowchart for explaining a processing procedure of the placement and routing apparatus according to the fifth embodiment of the present invention. First, the placement unit 31 refers to the revision information 52 and identifies a logic revision location (S61). Then, the comparison unit 32 generates a logic matrix from the external terminal or F / F to the revised part (S62).

  Next, the comparison unit 32 compares the logic matrix of the existing logic and the logic matrix of the revised logic (S63), and extracts layout parameters and arrangement / wiring information in each metal layer corresponding to the target location (S64). ). Here, the layout parameter includes information such as resistance, capacitance, and inductance.

  Next, the comparison unit 32 extracts logic / connection information for matching logic (S65). Here, dummy cells of the same type as the adaptive cells in the existing net are extracted around the target location.

  Next, the determination unit 33 confirms whether or not it is possible to change the net only in the sixth layer of the metal layer (S66). If reconnection is possible only in the sixth layer (S66, OK), the process proceeds to step S70, and reconnection is performed only in the sixth layer.

  In addition, when it is impossible to change only the sixth layer (S66, NG), it is confirmed whether or not the net can be changed only on the fifth layer (S67). If reconnection is possible only in the fifth layer (S67, OK), the process proceeds to step S70, and reconnection is performed only in the fifth layer.

  In addition, when reconnection only at the fifth layer is impossible (S67, NG), whether or not reconnection of nets at the fifth layer and the sixth layer is possible is confirmed (S68). If reconnection at the fifth layer and the sixth layer is possible (S68, OK), the process proceeds to step S70, and reconnection at the fifth layer and the sixth layer is performed.

  Then, the same processing is performed, and it is confirmed whether or not reconnection of nets in the first to sixth layers is possible (S69). If reconnection at the first layer to the sixth layer is possible (S69, OK), the process proceeds to step S70, and reconnection at the first layer to the sixth layer is performed.

  FIG. 10 is a diagram illustrating an example of a method of using dummy cells. FIG. 10A shows an example of a logic circuit and a net before revision. Here, it is assumed that an inverter is added between the AND gate S1 and the buffer S2 in the circuit to be revised.

  FIG. 10B shows an example of the revised logic circuit and net. Normally, an inverter S6, which is a dummy cell, is added between the AND gate S1 and the buffer S2, but if this dummy cell S6 is not nearby, it is determined in the existing existing circuit from the layout parameter (placement / wiring) information. Is checked for an appropriate cell, and an inverter S4 in an existing circuit nearby is used. Then, an inverter S6, which is a dummy cell, is connected between the OR gate S3 and the OR gate S5 of the existing circuit.

  As described above, according to the placement and routing apparatus in the present embodiment, when there is no appropriate dummy cell around the circuit to be revised, the cells in the existing circuit are reconnected, so the first implementation It is possible to achieve the same effect as described in the embodiment.

(Sixth embodiment)
The hardware configuration and functional configuration of the placement and routing apparatus in the sixth embodiment of the present invention are the same as the hardware configuration and functional configuration of the placement and routing apparatus in the first embodiment shown in FIGS. It is. Therefore, detailed description of overlapping configurations and functions will not be repeated. The layout parameters and the placement / wiring information are stored in the storage unit 22 shown in FIG.

  FIG. 11 is a flowchart for explaining the processing procedure of the placement and routing apparatus according to the sixth embodiment of the present invention. First, the placement unit 31 refers to the existing net 51 and the timing violation information 55, and separates the location that satisfies the timing from the timing violation location (S71). It is assumed that the timing violation information 55 is created in advance by timing verification.

  Next, the placement unit 31 extracts placement / wiring information for several cells before and after the place that can be bypassed in the setup violation path (S72). Then, layout parameters and arrangement / wiring information in each metal layer are extracted corresponding to the target location (S73). That is, layout parameter information such as resistance, capacitance, and inductance is extracted for each cell in the path where the setup is violated, and placement / wiring for several cells before and after the cell whose logic does not change even if it is bypassed such as a buffer Extract information.

  Next, in the case of virtually bypassing, the comparison unit 32 refers to the layout parameter information and calculates whether or not the delay is faster than the current state (S74). For example, the timing when the buffer is bypassed is calculated, and if it is earlier than the current state, the bypass is switched to the layout.

  Next, the determination unit 33 confirms whether or not the net can be reconnected only in the sixth layer of the metal layer (S75). When reconnection is possible only in the sixth layer (S75, OK), the process proceeds to step S79, and reconnection is performed only in the sixth layer.

  In addition, when it is impossible to change only the sixth layer (S75, NG), it is confirmed whether or not the net can be changed only on the fifth layer (S76). If reconnection is possible only in the fifth layer (S76, OK), the process proceeds to step S79, and reconnection is performed only in the fifth layer.

  In addition, when reconnection only at the fifth layer is impossible (S76, NG), whether or not reconnection of nets at the fifth layer and the sixth layer is possible is confirmed (S77). If reconnection at the fifth layer and the sixth layer is possible (S77, OK), the process proceeds to step S79, and reconnection at the fifth layer and the sixth layer is performed.

  Then, the same processing is performed, and it is confirmed whether or not reconnection of nets in the first to sixth layers is possible (S78). If reconnection at the first layer to the sixth layer is possible (S78, OK), the process proceeds to step S79, and reconnection at the first layer to the sixth layer is performed.

  FIG. 12 is a diagram illustrating an example of reconnection at a location where a setup violation has occurred. FIG. 12A shows a layout before the change, and a buffer S2 is connected between the AND gate S1 and the inverter S3. Here, it is assumed that a setup violation has occurred in the F / F connected to the output side of the AND gate S1.

  FIG. 12B shows the layout after the change. When the delay becomes faster when the buffer S2 is bypassed, the nets are reconnected so that the AND gate S1 and the inverter S3 are directly connected. .

  In the above description, the nets are reconnected to eliminate the setup error. However, when it is desired to reduce power consumption, a cell having a lower through current than the existing cell among the dummy cells near the corresponding path. If the arrangement / wiring information is extracted and the current value when the cell is replaced is calculated and the condition is satisfied, the nets may be connected to generate the net list and layout.

  In order to reduce power consumption, the cell placement / wiring information is extracted from the dummy cells near the corresponding path and the total wiring length from the existing cell to the driving cell is shorter, and the cell is replaced. If the current value is calculated and the condition is satisfied, the nets may be connected to generate the net list and layout.

  Further, since the clock line always repeats the H / L operation, power consumption can be reduced by reducing the number of stages. Referring to the clock line layout parameter (resistance, capacity, inductance) information, cell information on the clock line with a small capacity is extracted, and the timing verification when the target cell is virtually bypassed is performed to satisfy the timing. In this case, the net list and the layout may be generated by changing the net.

  As described above, according to the placement and routing apparatus of the present embodiment, the placement / routing of several cells before and after cells whose logic does not change even when a buffer or the like is bypassed with respect to the path where the setup violation has occurred. When the wiring information is extracted and the delay is faster than the current state, the wiring is switched in order from the upper layer, and the net and layout are generated so as to satisfy the timing. It became possible to cope with the revision.

(Seventh embodiment)
In the sixth embodiment, a cell whose logic does not change even if it is bypassed, such as a buffer, is extracted to eliminate the setup violation. In the seventh embodiment of the present invention, the setup violation is resolved by replacing the cell with the same function having a high drive capability.

  The hardware configuration and functional configuration of the placement and routing apparatus in the seventh embodiment of the present invention are the same as the hardware configuration and functional configuration of the placement and routing apparatus in the first embodiment shown in FIGS. It is. Therefore, detailed description of overlapping configurations and functions will not be repeated. Note that layout parameters and arrangement / wiring information described later are stored in the storage unit 22 shown in FIG.

  FIG. 13 is a flowchart for explaining the processing procedure of the placement and routing apparatus according to the seventh embodiment of the present invention. First, the placement unit 31 refers to the existing net 51 and the timing violation information 55, and separates the location that satisfies the timing from the timing violation location (S81). It is assumed that the timing violation information 55 is created in advance by timing verification.

  Next, the placement unit 31 extracts information on the same cell having a high drive capability among the dummy cells near the setup violation location or a composite cell having the same function by fixing a part of the input terminal ( S82). Then, layout parameters and arrangement / wiring information in each metal layer are extracted corresponding to the target location (S83).

  Next, the comparison unit 32 refers to the layout parameter information, calculates the timing when the target cell is replaced with a dummy cell, and calculates whether the delay is faster than the current state (S84).

  Next, the determination unit 33 confirms whether or not the net can be reconnected only in the sixth layer of the metal layer (S75). If reconnection is possible only in the sixth layer (S85, OK), the process proceeds to step S89, and reconnection is performed only in the sixth layer.

  In addition, when reconnection only at the sixth layer is impossible (S85, NG), whether or not reconnection of the net can be performed only at the fifth layer is confirmed (S86). If reconnection is possible only in the fifth layer (S86, OK), the process proceeds to step S89, and reconnection is performed only in the fifth layer.

  In addition, when reconnection only at the fifth layer is impossible (S86, NG), whether or not reconnection of nets at the fifth layer and the sixth layer is possible is confirmed (S87). If reconnection at the fifth layer and the sixth layer is possible (S87, OK), the process proceeds to step S89, and reconnection at the fifth layer and the sixth layer is performed.

  Then, the same processing is performed, and it is confirmed whether or not it is possible to reconnect nets in the first to sixth layers (S88). If reconnection in the first layer to the sixth layer is possible (S88, OK), the process proceeds to step S89, and reconnection in the first layer to the sixth layer is performed.

  FIG. 14 is a diagram illustrating an example of reconnection at a location where a setup violation has occurred. FIG. 14A shows a layout before change, and an inverter S2 is connected between the AND gate S1 and the AND gate S4. Here, it is assumed that a setup violation has occurred in the F / F connected to the output side of the AND gate S1.

  FIG. 14B shows the layout after the change. When the inverter S2 between the AND gate S1 and the AND gate S4 is replaced with the dummy cell S3, the delay becomes faster, and the AND gate S1 and the AND gate S1 are ANDed. The net is reconnected so that the dummy cell S3 is connected to the gate S4.

  As described above, according to the placement and routing apparatus according to the present embodiment, when the path where the setup violation occurs is replaced with a dummy cell having a high drive capability, the delay becomes faster than the current state. Since the wiring was changed in order from the upper layer, and the net and layout were generated so as to satisfy the timing, it became possible to cope with the minimum revision of the metal layer.

(Eighth embodiment)
In the seventh embodiment, the setup violation is solved by replacing the dummy cell having the same function with high drive capability. In the eighth embodiment, when there is no appropriate dummy cell around the circuit to be revised, the cells in the existing circuit are switched.

  The hardware configuration and functional configuration of the placement and routing apparatus according to the eighth embodiment of the present invention are the same as the hardware configuration and functional configuration of the placement and routing apparatus according to the first embodiment shown in FIGS. It is. Therefore, detailed description of overlapping configurations and functions will not be repeated. Note that layout parameters, arrangement / wiring information, and timing margin information described later are stored in the storage unit 22 shown in FIG.

  FIG. 15 is a flowchart for explaining the processing procedure of the placement and routing apparatus according to the eighth embodiment of the present invention. First, the placement unit 31 refers to the existing net 51 and the timing violation information 55, and separates the location that satisfies the timing from the timing violation location (S91). It is assumed that the timing violation information 55 is created in advance by timing verification.

  Next, the comparison unit 32 extracts combination information of dummy cells of the same type as the adaptive cells in the existing net around the target location (S92). Then, layout parameters and arrangement / wiring information in each metal layer are extracted corresponding to the target location (S93). Here, it is assumed that the comparison unit 32 refers to the timing margin information 56 and extracts an adaptive cell in the existing net having a large setup margin.

  Next, the comparison unit 32 refers to the layout parameter information, calculates the timing when the target cell is replaced with a cell in the existing net, and calculates whether the delay is faster than the current state (S94). .

  Next, the determination unit 33 confirms whether or not it is possible to change the net only in the sixth layer of the metal layer (S95). If reconnection is possible only in the sixth layer (S95, OK), the process proceeds to step S99, and reconnection is performed only in the sixth layer.

  In addition, when reconnection only in the sixth layer is impossible (S95, NG), it is confirmed whether or not reconnection of the net is possible only in the fifth layer (S96). If reconnection is possible only in the fifth layer (S96, OK), the process proceeds to step S99, and reconnection is performed only in the fifth layer.

  In addition, when reconnection only at the fifth layer is impossible (S96, NG), whether or not reconnection of nets at the fifth layer and the sixth layer is possible is confirmed (S97). If reconnection at the fifth layer and the sixth layer is possible (S97, OK), the process proceeds to step S99, and reconnection at the fifth layer and the sixth layer is performed.

  Then, the same processing is performed, and it is confirmed whether or not reconnection of nets in the first to sixth layers is possible (S98). If reconnection at the first layer to the sixth layer is possible (S98, OK), the process proceeds to step S99, and reconnection at the first layer to the sixth layer is performed.

  FIG. 16 is a diagram illustrating an example of reconnection at a location where a setup violation has occurred. FIG. 16A shows the layout before the change, and it is assumed that a buffer having a high drive capability is added between the AND gate S1 and the buffer S2 in the circuit to be revised.

  FIG. 16B shows an example of the revised logic circuit and net. Normally, a dummy cell S6 having a high drive capability is added between the AND gate S1 and the buffer S2. If this dummy cell S6 is not nearby, the existing existing circuit around the layout parameter (placement / wiring) information. Check whether there is a suitable cell in the buffer, and use the buffer S4 in the existing circuit nearby. If the delay time is earlier than the current time, the nets are switched and the dummy cell S6 is connected between the OR gate S3 and the OR gate S5 of the existing circuit.

  As described above, according to the placement and routing apparatus of the present embodiment, when there is no dummy cell with high drive capability near the path where the setup violation has occurred, it is connected to the cell of the existing circuit. If the delay is faster than the current situation, the wiring is reconnected in order from the upper layer, and the net and layout are generated so as to satisfy the timing. Became possible.

(Ninth embodiment)
In the eighth embodiment, when there is no appropriate dummy cell around the circuit to be revised, the cells in the existing circuit are connected. In the ninth embodiment of the present invention, when the drive capability of a cell in a path in which a setup violation has occurred is low, a path having the same type of cell as that cell is extracted and the cell is replaced. Is.

  The hardware configuration and functional configuration of the placement and routing apparatus in the ninth embodiment of the present invention are the same as the hardware configuration and functional configuration of the placement and routing apparatus in the first embodiment shown in FIGS. It is. Therefore, detailed description of overlapping configurations and functions will not be repeated. Note that layout parameters, arrangement / wiring information, and timing margin information described later are stored in the storage unit 22 shown in FIG.

  FIG. 17 is a flowchart for explaining the processing procedure of the placement and routing apparatus according to the ninth embodiment of the present invention. First, the placement unit 31 refers to the existing net 51 and the timing violation information 55, and separates the location that satisfies the timing from the timing violation location (S101). It is assumed that the timing violation information 55 is created in advance by timing verification.

  Next, the comparison unit 32 extracts information on dummy cells of the same type in the existing net around the target location (S102). Here, the comparison unit 32 refers to the timing margin information 56 and extracts an adaptive cell in the existing net having a large setup margin. Then, layout parameters and arrangement / wiring information in each metal layer are extracted corresponding to the target location (S103).

  Next, the comparison unit 32 refers to the layout parameter information, calculates the timing when the target cell is replaced with a cell in the existing net, and calculates whether the delay is faster than the current state (S104). .

  Next, the determination unit 33 confirms whether or not it is possible to change the net only in the sixth layer of the metal layer (S105). When reconnection is possible only in the sixth layer (S105, OK), the process proceeds to step S109, and reconnection is performed only in the sixth layer.

  In addition, when it is impossible to change only the sixth layer (S105, NG), it is confirmed whether or not the net can be changed only on the fifth layer (S106). If reconnection is possible only in the fifth layer (S106, OK), the process proceeds to step S109, and reconnection is performed only in the fifth layer.

  In addition, when it is impossible to change only the fifth layer (S106, NG), it is confirmed whether or not the net can be changed in the fifth and sixth layers (S107). If reconnection at the fifth layer and the sixth layer is possible (S107, OK), the process proceeds to step S109, and reconnection at the fifth layer and the sixth layer is performed.

  Then, the same processing is performed, and it is confirmed whether or not reconnection of nets in the first to sixth layers is possible (S108). If reconnection in the first layer to the sixth layer is possible (S108, OK), the process proceeds to step S109, and reconnection in the first layer to the sixth layer is performed.

  FIG. 18 is a diagram illustrating an example of reconnection at a location where a setup violation has occurred. FIG. 18A shows the layout before the change, and the AND gate S1 and the inverter S2 are connected at the setup violation location. Further, the EX-OR gate S3 and the inverter S4 are connected in a net having a setup margin.

  FIG. 18B shows an example of the revised logic circuit and net. The inverter S2 connected to the AND gate S1 at the setup violation location is replaced with a net inverter S4 having a setup margin, and the timing calculation is performed. If the delay time is earlier than the current time, the nets are switched, the inverter S4 is connected to the AND gate S1, and the inverter S2 is connected to the EX-OR gate S3.

  As described above, according to the placement and routing apparatus of the present embodiment, the path where the setup violation has occurred is replaced with a cell of a path that has a setup margin and includes the same type of cell. If the delay is earlier than that, the wiring is switched in order from the upper layer, and the net and layout are generated to satisfy the timing, so it is possible to cope with the minimum revision of the metal layer It became.

(Tenth embodiment)
The hardware configuration and functional configuration of the placement and routing apparatus in the tenth embodiment of the present invention are the same as the hardware configuration and functional configuration of the placement and routing apparatus in the first embodiment shown in FIGS. It is. Therefore, detailed description of overlapping configurations and functions will not be repeated. Note that dummy cell placement / wiring information, which will be described later, is stored in the storage unit 22 shown in FIG.

  FIG. 19 is a flowchart for explaining the processing procedure of the placement and routing apparatus according to the tenth embodiment of the present invention. First, the placement unit 31 refers to the existing net 51 and the timing violation information 55, and separates the location that satisfies the timing from the timing violation location (S111). It is assumed that the timing violation information 55 is created in advance by timing verification.

  Next, the placement unit 31 extracts layout parameter information such as resistance, capacitance, and inductance in each metal layer, and extracts placement / wiring information (S112). Then, the placement / wiring information of the dummy cell near the corresponding part in each metal layer is extracted (S113).

  Next, when the dummy cell is virtually added, the comparison unit 32 refers to the layout parameter information and calculates whether or not the delay is slower than the current state (S114). For example, the timing when a buffer is added is calculated, and if it is later than the current state, the buffer is added to the layout. Then, it is confirmed whether or not the hold violation is resolved (S115).

  If the hold violation has not been resolved (S115, NG), the process returns to step S113 and the subsequent processing is repeated. If the hold violation has been resolved (S115, OK), the determination unit 33 confirms whether or not it is possible to change the net only in the sixth layer of the metal layer (S116). If reconnection is possible only in the sixth layer (S116, OK), the process proceeds to step S120, and reconnection is performed only in the sixth layer.

  In addition, if reconnection only in the sixth layer is impossible (S116, NG), whether or not reconnection of the net is possible only in the fifth layer is confirmed (S117). If reconnection is possible only in the fifth layer (S117, OK), the process proceeds to step S120, and reconnection is performed only in the fifth layer.

  In addition, if reconnection only at the fifth layer is impossible (S117, NG), whether or not reconnection of nets at the fifth layer and the sixth layer is possible is confirmed (S118). If reconnection at the fifth layer and the sixth layer is possible (S118, OK), the process proceeds to step S120, and reconnection at the fifth layer and the sixth layer is performed.

  Then, the same processing is performed, and it is confirmed whether or not reconnection of nets in the first to sixth layers is possible (S119). If reconnection at the first layer to the sixth layer is possible (S119, OK), the process proceeds to step S120, and reconnection at the first layer to the sixth layer is performed.

  FIG. 20 is a diagram illustrating an example of reconnection at a location where a hold violation has occurred. FIG. 20A shows a layout before change, and an AND gate S2 is connected between F / F (S1) and F / F (S4). Assume that a hold violation has occurred in F / F (S4).

  FIG. 20B shows the layout after the change, and when the delay is delayed when the dummy cell S3 is added between the AND gate S2 and the F / F (S4), the AND gates S2 and F The net is switched so that the dummy cell S3 is connected to / F (S4).

  As described above, according to the placement and routing apparatus of the present embodiment, when a cell whose logic is not changed, such as a buffer, is added to the path in which the hold violation occurs, the delay becomes slower than the current state. In order to meet the timing, nets and layouts are generated by switching the wiring in order from the upper layer, so that it is possible to cope with the minimum revision of the metal layer.

(Eleventh embodiment)
In the tenth embodiment, a hold violation is resolved by inserting a cell whose logic does not change even if a buffer or the like is added. In the eleventh embodiment of the present invention, the hold violation is eliminated by replacing the cell with the same function in the path having a margin in the hold margin.

  The hardware configuration and functional configuration of the placement and routing apparatus in the eleventh embodiment of the present invention are the same as the hardware configuration and functional configuration of the placement and routing apparatus in the first embodiment shown in FIGS. It is. Therefore, detailed description of overlapping configurations and functions will not be repeated. Note that the arrangement / wiring information of a route having a margin in the hold margin described later is stored in the storage unit 22 shown in FIG.

  FIG. 21 is a flowchart for explaining the processing procedure of the placement and routing apparatus according to the eleventh embodiment of the present invention. First, the placement unit 31 refers to the existing net 51 and the timing violation information 55, and separates the location that satisfies the timing from the timing violation location (S121). It is assumed that the timing violation information 55 is created in advance by timing verification.

  Next, the placement unit 31 extracts layout parameter information such as resistance, capacitance, and inductance in each metal layer, and extracts placement / wiring information (S122). Then, arrangement / wiring information of a path having a margin in the hold margin is extracted in the vicinity of the corresponding portion of each metal layer (S123).

  Next, the comparison unit 32 refers to the layout parameter information and calculates whether or not the delay is slower than the current state when the virtual function is replaced with a cell having the same function on the path having a margin in the hold margin ( S124). For example, the timing when the buffer is replaced is calculated, and if it is later than the current state, the buffer is replaced for the layout. Then, it is confirmed whether or not the hold violation has been resolved (S125).

  If the hold violation has not been resolved (S125, NG), the process returns to step S123 and the subsequent processing is repeated. If the hold violation has been resolved (S125, OK), the determination unit 33 confirms whether or not it is possible to change the net only in the sixth layer of the metal layer (S126). If reconnection is possible only in the sixth layer (S126, OK), the process proceeds to step S130, and reconnection is performed only in the sixth layer.

  In addition, when it is impossible to change only the sixth layer (S126, NG), it is confirmed whether or not the net can be changed only in the fifth layer (S127). If reconnection is possible only in the fifth layer (S127, OK), the process proceeds to step S130, and reconnection is performed only in the fifth layer.

  In addition, when reconnection only at the fifth layer is impossible (S127, NG), whether or not reconnection of nets at the fifth layer and the sixth layer is possible is confirmed (S128). If reconnection at the fifth layer and the sixth layer is possible (S128, OK), the process proceeds to step S130, and reconnection at the fifth layer and the sixth layer is performed.

  Then, the same processing is performed, and it is confirmed whether or not reconnection of nets in the first to sixth layers is possible (S129). When reconnection in the first layer to the sixth layer is possible (S129, OK), the process proceeds to step S130, and reconnection in the first layer to the sixth layer is performed.

  FIG. 22 is a diagram illustrating an example of reconnection at a location where a hold violation has occurred. FIG. 22A shows a layout before change, and an AND gate S2 is connected between F / F (S1) and F / F (S3). Assume that a hold violation has occurred in F / F (S3). Buffers S5 to S7 are connected between F / F (S4) and F / F (S8). Assume that the hold margin has a margin in F / F (S8).

  FIG. 22B shows the layout after the change, and when the delay becomes slow when the buffers S6 and S7 are connected between the AND gate S2 and the F / F (S3), the AND gate S2 The nets are reconnected so that the buffers S6 and S7 are connected between F and F / F (S3).

  As described above, according to the placement and routing apparatus of the present embodiment, a cell having the same function in a path having a margin in the hold margin is connected to a path in which a hold violation has occurred, resulting in a delay from the current state. When the delay is slow, the wiring is switched in order from the upper layer, and the net and layout are generated so as to satisfy the timing, so it is possible to cope with the minimum revision of the metal layer .

(Twelfth embodiment)
The hardware configuration and functional configuration of the placement and routing apparatus in the twelfth embodiment of the present invention are the same as the hardware configuration and functional configuration of the placement and routing apparatus in the first embodiment shown in FIGS. It is. Therefore, detailed description of overlapping configurations and functions will not be repeated. It should be noted that the arrangement / wiring information and layout parameter information of the meiselle described later are stored in the storage unit 22 shown in FIG.

  FIG. 23 is a flow chart for explaining the processing procedure of the placement and routing apparatus in the twelfth embodiment of the present invention. First, the placement unit 31 refers to the existing net 51 and the transition violation information 57, and extracts the placement / connection information of the cell driving the transition violation location and its surrounding cells (S131). It is assumed that the transition violation information 57 is created in advance by timing verification or the like.

  Next, the placement unit 31 extracts layout parameter information such as resistance, capacitance, and inductance in each metal layer, and extracts placement / wiring information (S132). Then, the placement / wiring information of the dummy cell near the corresponding part in each metal layer is extracted (S133).

  Next, the comparison unit 32 calculates whether or not the value of the transition error is smaller than the current value by referring to the layout parameter information when a dummy cell is virtually added (S134).

  If the transition violation has not been resolved (S135, NG), the process returns to step S133 and the subsequent processing is repeated. If the transition violation is resolved (S135, OK), the determination unit 33 confirms whether or not it is possible to change the net only in the sixth layer of the metal layer (S136). If reconnection is possible only in the sixth layer (S136, OK), the process proceeds to step S140, and reconnection is performed only in the sixth layer.

  In addition, when it is impossible to change only the sixth layer (S136, NG), it is confirmed whether or not the net can be changed only on the fifth layer (S137). If reconnection is possible only in the fifth layer (S137, OK), the process proceeds to step S140, and reconnection is performed only in the fifth layer.

  In addition, when reconnection only at the fifth layer is impossible (S137, NG), whether or not reconnection of nets at the fifth layer and the sixth layer is possible is confirmed (S138). If reconnection at the fifth layer and the sixth layer is possible (S138, OK), the process proceeds to step S140, and reconnection at the fifth layer and the sixth layer is performed.

  Then, the same process is performed, and it is confirmed whether or not reconnection of nets in the first to sixth layers is possible (S139). If reconnection at the first layer to the sixth layer is possible (S139, OK), the process proceeds to step S140, and reconnection at the first layer to the sixth layer is performed.

  FIG. 24 is a diagram illustrating an example of reconnection at a location where a transition violation occurs. FIG. 24A shows a layout before the change, and the inverter S4 is connected to the AND gates S1 to S3. A transition violation has occurred in this route.

  FIG. 24B shows the layout after the change. When the dummy cell S5 is added between the inverter S4 and the AND gates S1 to S3, the inverter S4 and the AND gate are eliminated. The net is reconnected so that the dummy cell S5 is connected between S1 and S3.

  As described above, according to the placement and routing apparatus of the present embodiment, a cell whose logic is not changed, such as a buffer, is added to the path in which the transition violation occurs, and the transition error becomes smaller than the current state. In some cases, the wiring was switched in order from the upper layer, and the net and layout were generated so that the transition violation was resolved, so it was possible to cope with the minimum revision of the metal layer.

(Thirteenth embodiment)
In the twelfth embodiment, the transition violation is eliminated by adding a dummy cell to the net where the transition violation occurs. In the thirteenth embodiment, a transition violation is divided into a plurality of nets to eliminate the transition violation.

  The hardware configuration and functional configuration of the placement and routing apparatus in the thirteenth embodiment of the present invention are the same as the hardware configuration and functional configuration of the placement and routing apparatus in the first embodiment shown in FIGS. It is. Therefore, detailed description of overlapping configurations and functions will not be repeated. It should be noted that the arrangement / wiring information and layout parameter information of the meiselle described later are stored in the storage unit 22 shown in FIG.

  FIG. 25 is a flowchart for explaining the processing procedure of the placement and routing apparatus in the thirteenth embodiment of the present invention. First, the placement unit 31 refers to the existing net 51 and the transition violation information 57, and extracts the placement / connection information of the cell driving the transition violation location and its surrounding cells (S141). It is assumed that the transition violation information 57 is created in advance by timing verification or the like.

  Next, the placement unit 31 extracts layout parameter information such as resistance, capacitance, and inductance in each metal layer, and extracts placement / wiring information (S142). Then, the placement / wiring information of the dummy cell near the corresponding part in each metal layer is extracted (S143).

  Next, the comparison unit 32 calculates whether or not the value of the transition error is smaller than the current value with reference to the layout parameter information when the nets of the transition violation portions are virtually divided (S144).

  If the transition violation has not been resolved (S145, NG), the process returns to step S143 and the subsequent processing is repeated. If the transition violation is resolved (S145, OK), the determination unit 33 confirms whether or not it is possible to change the net only in the sixth layer of the metal layer (S146). If reconnection is possible only in the sixth layer (S146, OK), the process proceeds to step S150, and reconnection is performed only in the sixth layer.

  In addition, when it is impossible to change only the sixth layer (S146, NG), it is confirmed whether or not the net can be changed only in the fifth layer (S147). When reconnection is possible only in the fifth layer (S147, OK), the process proceeds to step S150, and reconnection is performed only in the fifth layer.

  In addition, when reconnection only at the fifth layer is impossible (S147, NG), whether or not reconnection of nets at the fifth layer and the sixth layer is possible is confirmed (S148). If reconnection at the fifth layer and the sixth layer is possible (S148, OK), the process proceeds to step S150, and reconnection at the fifth layer and the sixth layer is performed.

  Then, the same processing is performed, and it is confirmed whether or not reconnection of nets in the first to sixth layers is possible (S149). If reconnection at the first layer to the sixth layer is possible (S149, OK), the process proceeds to step S150, and reconnection at the first layer to the sixth layer is performed.

  FIG. 26 is a diagram illustrating an example of reconnection at a location where a transition violation occurs. FIG. 26A shows a layout before change, and an inverter S9 is connected to the buffers S1 to S6. A transition violation has occurred in this route.

  FIG. 26B shows the layout after the change. The net connecting the inverter S9 and the buffers S1 to S6 is divided into two, and dummy cells S7 and S8 are added to the respective nets. When the transition violation is resolved, the nets are reconnected as shown in FIG.

  As described above, according to the placement and routing apparatus of the present embodiment, the net is divided into a plurality of paths for the path in which the transition violation occurs, and when the transition error becomes smaller than the current state, the upper layer is used. Wiring was switched in order, and nets and layouts were generated so that transition violations were resolved, so it was possible to cope with the minimum revision of the metal layer.

(Fourteenth embodiment)
In the thirteenth embodiment, a transition violation is divided into a plurality of nets to eliminate the transition violation. In the fourteenth embodiment, cells in the path in which the transition violation occurs are replaced with cells having the same function in the path having a margin in setup, hold, and transition near the corresponding path to eliminate the transition violation. It is.

  The hardware configuration and functional configuration of the placement and routing apparatus in the fourteenth embodiment of the present invention are the same as the hardware configuration and functional configuration of the placement and routing apparatus in the first embodiment shown in FIGS. It is. Therefore, detailed description of overlapping configurations and functions will not be repeated. Note that layout parameter information, which will be described later, and arrangement / wiring information of existing circuits with margins in setup, hold, and transition are stored in the storage unit 22 shown in FIG.

  FIG. 27 is a flow chart for explaining the processing procedure of the placement and routing apparatus in the fourteenth embodiment of the present invention. First, the placement unit 31 refers to the existing net 51 and the transition violation information 57, and extracts the placement / connection information of the cell driving the transition violation location and its surrounding cells (S151). It is assumed that the transition violation information 57 is created in advance by timing verification or the like.

  Next, the placement unit 31 extracts layout parameter information such as resistance, capacitance, and inductance in each metal layer, and extracts placement / wiring information (S152). Then, arrangement / wiring information of an existing circuit having a margin in setup, hold, and transition in the vicinity of the corresponding portion of each metal layer is extracted (S153).

  Next, the comparison unit 32 refers to the layout parameter information, and the transition error value is smaller than the current value when the cell of the path of the transition violation portion is virtually replaced with the cell of the existing circuit having a margin. Is calculated (S154).

  If the transition violation has not been resolved (S155, NG), the process returns to step S153 and the subsequent processing is repeated. If the transition violation is resolved (S155, OK), the determination unit 33 confirms whether or not it is possible to change the net only in the sixth layer of the metal layer (S156). If reconnection is possible only in the sixth layer (S156, OK), the process proceeds to step S150, and reconnection is performed only in the sixth layer.

  In addition, when it is impossible to change only the sixth layer (S156, NG), it is confirmed whether or not the net can be changed only on the fifth layer (S157). If reconnection is possible only in the fifth layer (S157, OK), the process proceeds to step S160, and reconnection is performed only in the fifth layer.

  In addition, when it is impossible to change only the fifth layer (S157, NG), it is confirmed whether or not the net can be changed in the fifth and sixth layers (S158). If reconnection at the fifth layer and the sixth layer is possible (S158, OK), the process proceeds to step S160, and reconnection at the fifth layer and the sixth layer is performed.

  Then, the same process is performed, and it is confirmed whether or not reconnection of nets in the first to sixth layers is possible (S159). If reconnection in the first layer to the sixth layer is possible (S159, OK), the process proceeds to step S160, and reconnection in the first layer to the sixth layer is performed.

  FIG. 28 is a diagram illustrating an example of reconnection at a location where a transition violation occurs. FIG. 28A shows the layout before the change, and the buffer S6 is connected to the AND gates S1 to S3. A transition violation has occurred in this route.

  FIG. 28B shows the layout after the change, in which the output-side net of the buffer S6 is replaced with the output-side net of the buffer S4 in the existing circuit. As a result, when the transition violation is resolved, the nets are reconnected as shown in FIG.

  As described above, according to the placement and routing apparatus of the present embodiment, a cell in a path in which a transition violation has occurred is defined as a cell having the same function in a path with a margin in setup, hold, and transition near the corresponding path. Since the net and layout are generated so that the transition violation is eliminated, it is possible to cope with the minimum metal layer revision.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  DESCRIPTION OF SYMBOLS 1 Computer main body, 2 Display apparatus, 3 FD drive, 4 FD, 5 Keyboard, 6 Mouse, 7 CD-ROM apparatus, 8 CD-ROM, 9 Network communication apparatus, 10 CPU, 11 ROM, 12 RAM, 13 Hard disk, 20 Design tool, 21 program, 22 storage unit, 31 placement unit, 32 comparison unit, 33 determination unit, 34 replacement unit, 41 existing net information, 42 revision information, 43 timing violation information, 44 transition violation information.

Claims (15)

A placement and routing apparatus for switching the wiring of a semiconductor device having a plurality of metal layers,
An extraction means for identifying the logic revision part from the existing net and the revision information and extracting the logical connection information for matching the logic;
A determination unit that determines whether or not to change the wiring in order from the top layer of the metal layer based on the layout information and the logical connection information extracted by the extraction unit;
A placement and routing apparatus including replacement means for changing wiring in a metal layer determined to be changeable by the determination means.   The extraction means searches the logic from the logic revision location to the terminal or flip-flop in the input direction, and creates and compares the logic matrix of the existing logic and the logic matrix of the revision logic to extract the logic connection information The placement and routing apparatus according to claim 1.   3. The placement and routing apparatus according to claim 1, wherein the extraction unit extracts the logical connection information so as to be connected to a dummy cell previously placed in the semiconductor device. The extraction means extracts the logic connection information so as to be connected to a cell in an existing logic circuit around the logic revision location,
3. The placement and routing apparatus according to claim 1, wherein the replacement unit replaces a cell in the existing logic circuit with a dummy cell having the same function. A placement and routing apparatus for switching the wiring of a semiconductor device having a plurality of metal layers,
An extraction means for identifying a setup violation path from the existing net and timing violation information, and extracting logical connection information so as to reduce the delay of the setup violation path;
A determination unit that determines whether or not to change the wiring in order from the top layer of the metal layer based on the layout information and the logical connection information extracted by the extraction unit;
A placement and routing apparatus including replacement means for changing wiring in a metal layer determined to be changeable by the determination means.   The placement and routing apparatus according to claim 5, wherein the extraction unit extracts the logical connection information so as to bypass cells that can be bypassed in the setup violation path.   The placement and routing apparatus according to claim 5, wherein the extraction unit extracts the logical connection information so that a dummy cell having high drive capability is connected to the setup violation path. The extraction means extracts the logical connection information to be connected to a cell in an existing logic circuit around the setup violation path,
6. The placement and routing apparatus according to claim 5, wherein the replacement means replaces a cell in the existing logic circuit with a dummy cell having the same function.   9. The placement and routing apparatus according to claim 8, wherein when extracting cells in the existing logic circuit, the extraction means refers to timing margin information and extracts cells in the existing logic circuit having a large setup margin. A placement and routing apparatus for switching the wiring of a semiconductor device having a plurality of metal layers,
An extraction means for identifying a hold violation path from the existing net and timing violation information, and extracting logical connection information so as to increase a delay of the hold violation path;
A determination unit that determines whether or not to change the wiring in order from the top layer of the metal layer based on the layout information and the logical connection information extracted by the extraction unit;
A placement and routing apparatus including replacement means for changing wiring in a metal layer determined to be changeable by the determination means.   The placement and routing apparatus according to claim 10, wherein the extraction unit extracts the logical connection information so as to add a dummy cell to the hold violation path. The extraction means extracts the logical connection information to be connected to a cell in an existing logic circuit around the hold violation path,
11. The placement and routing apparatus according to claim 10, wherein the replacement means replaces a cell in the existing logic circuit with a dummy cell having the same function. A placement and routing apparatus for switching the wiring of a semiconductor device having a plurality of metal layers,
An extraction means for identifying a transition violation path from existing net and transition violation information, and extracting logical connection information so as to reduce a transition error of the transition violation path;
A determination unit that determines whether or not to change the wiring in order from the top layer of the metal layer based on the layout information and the logical connection information extracted by the extraction unit;
A placement and routing apparatus including replacement means for changing wiring in a metal layer determined to be changeable by the determination means.   14. The placement and routing apparatus according to claim 13, wherein the extraction means extracts the logical connection information so as to add a dummy cell to the transition violation path.   The placement and routing apparatus according to claim 13, wherein the extraction unit extracts the logical connection information so that the transition violation path is divided into a plurality of paths.

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