JP6405970B2 - Semiconductor device design method, design apparatus, and semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device design method, a design apparatus, and a semiconductor device.

  In recent LSI (Large Scale Integration) designs, different voltages are often used between blocks for the purpose of lower power consumption and higher performance.

  There is known a level shift circuit in which a voltage drop circuit and a switch circuit are provided in parallel so that a voltage drop is caused by a voltage drop circuit when a high level is inputted and a voltage is raised by a switch circuit when a low level is inputted.

  In a level converter having a first buffer that receives a lower power supply voltage signal and a second buffer that is supplied with a higher power supply voltage and is driven by the first buffer, the output of the second buffer is A technique or the like has been proposed in which a power supply selection mechanism is selectively switched and an apparent power supply V is supplied to a first buffer so that it can operate with a single power supply voltage.

JP 2004-112310 A JP 2005-160073 A JP 2005-57542 A

  The above-described technology is a technology related to a circuit that outputs a level-shifted voltage of an input signal. In addition to a cell that realizes the operation of a circuit in a chip, the above-described circuit can be used in a low power region and a high power region. It is necessary to prepare near the boundary.

  When the block size is subdivided with the expansion of the scale of the LSI, the increase in level shifter cells (LS cells) such as level shift circuits and level converters increases the cell layout area and the layout area. The signal propagation delay can no longer be ignored.

  Accordingly, in one aspect, the present invention is directed to automatically generating an optimal level shifter.

  According to one aspect, the first circuit supplied with the first power supply includes a gate connected to the output of the second circuit supplied with the second power supply whose voltage value is lower than that of the first power supply. The first transistor to be extracted, and whether the first transistor shares a source with a second transistor different from the first transistor, and if the source is not shared, In the case where one of a plurality of third transistors arranged in advance is connected in series between the source and the first power supply, and the source is shared, the source and the first power supply There is provided a method for designing a semiconductor device that causes a computer to execute a process of connecting two of the plurality of third transistors arranged in advance in series with one power source.

  Further, as means for solving the above-described problems, an apparatus for performing the above-described method, a program for causing a computer to execute the above-described processing, and a storage medium storing the program may be used.

  Further, according to another aspect, the second circuit is included in the first circuit to which the first power is supplied, and the second circuit is supplied with the second power whose gate is lower in voltage than the first power. When the first transistor connected to the output of the first transistor does not share a source with a second transistor different from the first transistor, one transistor is connected between the source and the first power supply. Connected in series, and the gate of the one transistor is connected to the output of the second circuit, and the first transistor shares the source with a second transistor different from the first transistor. A semiconductor in which two or more transistors are connected in series between the source and the first power supply, and the gates of the two or more transistors are connected to a negative power supply voltage or ground. Location is provided.

  An optimum level shifter can be automatically generated.

It is a figure for demonstrating the signal transmission method between different electric power areas. It is a figure for demonstrating the case of the direct connection of FIG. 1 (A). It is a figure for demonstrating the case where the LS cell of FIG. 1 (B) is inserted. It is a figure for demonstrating the case where the cell with an LS function of FIG.1 (C) is used. It is a figure for demonstrating this embodiment. It is a figure for demonstrating the method to add a level shifter function to a cell without a source share. It is a figure for demonstrating the method to add a level shifter function to a cell with a source share. It is a figure which shows the hardware constitutions of the design apparatus which concerns on this embodiment. It is a figure which shows the function structural example of the design apparatus in 1st Example. It is a figure which shows the example of a change of a net list. It is a flowchart figure for demonstrating the design process in 1st Example. It is a figure which shows the example of a layout change in the case of no source sharing in 1st Example. It is a figure which shows the example of a layout change in the case of source sharing with 1st Example. It is a figure for demonstrating the effect of 1st Example. It is a figure which shows the function structural example of the design apparatus in 2nd Example. It is a flowchart for demonstrating the design process in 2nd Example. It is a figure which shows the example of a layout change in the case of pMOS transistor addition of the 3rd stage in the 2nd Example with source sharing. It is a figure for demonstrating the structure of the cell after LS optimization of FIG. 17 (B). It is a figure which shows the example of a layout change in the case of 3rd and 4th stage pMOS transistor additions with source sharing in 2nd Example. FIG. 20 is a diagram for explaining a configuration of a cell after LS optimization in FIG. 19B. It is a figure for demonstrating the effect of this embodiment. It is a figure which shows the logic cell without source sharing other than an inverter. It is a flowchart for demonstrating the design process which does not apply this embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. First, a signal transmission method between a low power region and a high speed region (also referred to as a high power region) in the chip will be described. FIG. 1 is a diagram for explaining a signal transmission method between different power regions.

  In each example of FIG. 1A, FIG. 1B, and FIG. 1C, 0.7V power supply 2a is supplied to the cell 3a in the low power region 1a, and 0. 0 is supplied to the cell 3b in the high speed region 1b. The case where the 9V power supply 2b is supplied is shown as an example. The power supply voltage of each region 1a and 1b is not limited to these values.

  FIG. 1A shows an example in which one of the cells 3a in the low power region 1a and one of the cells 3b in the direct high speed region 1b are directly connected. FIG. 1B shows an example in which the level shifter (LS) cell 3c is inserted at the boundary between the regions 1a and 1b. FIG. 1C shows an example of the cell 3d with LS function. The cell 3d with LS function is a cell in which a level shifter function is added to the first cell 3b that receives an output signal from the cell 3a in the low power region 1a of the high speed region 1b.

  The problem of each signal transmission method will be discussed below. FIG. 2 is a diagram for explaining the case of direct connection in FIG. In FIG. 2, direct connection in the case where the cells 3a and 3b are inverter (INV) cells is shown as an example.

  In FIG. 2, a cell 3a is an inverter cell composed of a pMOS transistor 3a_p and an nMOS transistor 3a_n. The pMOS transistor 3a_p is connected to the 0.7V power supply 2a, and the nMOS transistor 3a_n is connected to Vss2g.

  The cell 3b is an inverter cell composed of a pMOS transistor 3b_p and an nMOS transistor 3b_n. The pMOS transistor 3b_p is connected to the 0.9 power supply 2b, and the nMOS transistor 3b_n is connected to Vss2g.

  Since the cell 3a and the cell 3b are directly connected, when the pMOS transistor 3b_p of the cell 3b is turned off, the cell 3a and the cell 3b cannot be turned off unless the potential is the same as the potential on the source side of the pMOS transistor 3b_p.

  However, since a voltage lower than the source-side potential (0.9 V) (that is, the voltage (0.7 V) of the output signal from the cell 3a) flows to the gate of the cell 3b, it cannot be completely turned off and leaks. Current will increase. In the first stage cell 3b of the high speed region 1b that first receives the output signal from the low power region 1a, there is a problem that the leakage current when the pMOS transistor 3b_p is off increases.

  FIG. 3 is a diagram for explaining a case where the LS cell of FIG. 1B is inserted. In FIG. 3, a cross coupling type LS cell 3c is shown as an example. The LS cell 3c has a configuration in which two different element structures, a first element structure that receives supply of a 0.7V power supply 2a and a second element structure that receives supply of a 0.9V power supply 2b, are connected. This type is usually used as a level shifter.

  The first element structure corresponds to a buffer structure (a structure in which two inverter cells are connected in parallel), the two pMOS transistors 3c_p1 and 3c_p2 are connected to the 0.7V power supply 2a, and the two nMOS transistors 3c_n1 and 3c_n2 are , Vss2g.

  The second element structure corresponds to a flip-flop structure, the two pMOS transistors 3c_p3 and 3c_p4 are connected to the 0.9V power supply 2b, and the two nMOS transistors 3c_n3 and 3c_n4 are connected to Vss2g.

  Since no 0.7V current flows directly through the pMOS transistors 3c_p3 and 3c_p4 supplied with the 0.9V power supply 2b in the high-speed region 1b, there is no problem of leakage current in this example. However, the LS cell 3c is a logically unnecessary cell, and there is a problem that the area increases due to the insertion of such an unnecessary cell, and therefore the delay increases.

  FIG. 4 is a diagram for explaining the case where the cell with the LS function of FIG. 1C is used. FIG. 4 shows an example of the cell 3d with LS function. The cell 3d with LS function is represented by a combination of, for example, a NOT cell and a NAND cell, and a recent design method has proposed a method of optimal design in terms of timing without defining a different potential boundary. In that case, there is a problem that the voltage boundary is not known until timing design is performed after logic synthesis.

  In addition, in the high-speed region 1b, the LS-functional cell 3d creates a functional cell for each initial cell 3b to which a signal from the low power region 1a is input, that is, for each cell such as a NAND cell or a NOT cell I have to keep it. In order to create the cells 3d with various LS functions, it is necessary to add information to physical information, a cell library, and the like.

1 and FIG. 2 to FIG. 4 are summarized, the following problems exist in the signal transmission method between existing different power domains.
・ Direct connection (Fig. 1 (A), Fig. 2)
Leakage current increases.
・ In the case of LS cell insertion (FIG. 1 (B), FIG. 3)
As the area increases, the delay increases.
In the case of a cell with LS function (FIG. 1 (C), FIG. 4)
A lot of special cells need to be created. Physical information, cell library, etc. become large. In addition, it is not known which cells have different potential boundaries before designing.

  In the present embodiment, one or more pMOS transistors of filler cells (or ECO (Engineering Change Order) cells) are connected to the first cell 3b in the high-speed region 1b without using the LS cell 3c and the cell 3d with LS function. Thus, the LS function is realized.

  Hereinafter, in the present embodiment, a design method for detecting whether the source of the transistor of the input unit is shared with other transistors and inserting one or more transistors according to the presence or absence of source sharing, A design apparatus and the circuit structure comprised in that way are shown.

  FIG. 5 is a diagram for explaining the present embodiment. The filler cell is a cell that is automatically arranged in a region where the cell 3b is not placed for power connection between the cells 3b and process flattening. The filler cell also has a function as an ECO cell having a NAND-type or inverter-type element shape in advance so that only wiring revision is required at the time of revision.

  The inventor has focused on using a pMOS transistor that forms a filler cell (ECO).

  For the first cell 3b of the high speed region 1b close to the boundary between the low power region 1a and the high speed region 1b, the filler cell pMOS transistor 3f_p1 close to the cell 3b is connected to the 0.9V power supply 2b side. By changing the wiring, the pMOS transistor 3f_p1 can be added to the upper stage of the cell 3b.

  The gate potential, that is, the connection 3e is changed according to the logic of the cell 3b. Inverter cells, 2 NAND cells, NOR cells, etc. (hereinafter referred to as “cells without source sharing”) that do not share the source terminal of the pMOS transistor in the layout are connected to the input terminals. In the layout, a cell sharing the source terminal of the pMOS transistor (hereinafter referred to as “cell with source sharing”) is Vss clip (connected to a negative power supply voltage or ground) and vertically stacked pMOS transistors. The number of pMOS transistors is increased and connected in series.

  The case of a cell without source sharing will be described with reference to FIG. FIG. 6 is a diagram for explaining a method of adding a level shifter function to a cell without source sharing.

  FIG. 6A shows an additional connection example of the pMOS transistor 3f_p1 when the cell 3b is an inverter cell. In this embodiment, the gate potential of the pMOS transistor 3f_p1 of the filler cell is shared with the input signal of the cell 3b. That is, the pMOS transistor 3f_p1 is connected to the node 3p of the cell 3b by the connection 3e. This connection 3e enables gate control of the pMOS transistor 3f_p1.

  FIG. 6B shows a layout example of a cell without source sharing. In this example, the inverter cell is taken as an example, and only the portion necessary for the description of the present embodiment is shown. In the cell 3b, one gate pattern 3b_g1 is formed for the pMOS element region 3b_pd and the nMOS element region 3b_nd.

  The pMOS element region 3b_pd is connected to the 0.9V power source 2b by the wiring pattern 3b_m1 and the via 6v, and the pMOS element region 3b_pd and the nMOS element region 3b_nd are connected by the wiring pattern 3b_m2 and the via 6v. The nMOS element region 3b_nd is connected to Vss2g by the wiring pattern 3b_m1 and the via 6v.

  Such a layout of the cell 3b is indicated by layout information. By referring to the layout information, since the wiring pattern 3b_m1 that connects the pMOS element region 3b_pd and the 0.9V power supply 2b is only the gate pattern 3b_g1 on one side in the pMOS element region 3b_pd, the source is not shared. It can be judged. Judge that there is no source sharing.

  In this embodiment, if the pMOS transistor does not share the source terminal in the cell 3b, a filler cell pMOS transistor 3f_p1 is added to the cell 3b. Also, the gate voltage of the pMOS transistor 3f_p1 can be controlled by sharing the gate voltage with the input signal of the original cell 3b.

  The case of a cell with source sharing will be described with reference to FIG. FIG. 7 is a diagram for explaining a method of adding a level shifter function to a cell with source sharing.

  FIG. 7A shows an example in which two pMOS transistors 3f_p1 and 3f_p2 are additionally connected when the cell 3b is a buffer. In the cell 3b in this example, two inverter cells each composed of a pMOS transistor 3b_p and an nMOS transistor 3b_n are connected to form a buffer.

  In the present embodiment, two pMOS transistors 3f_p1 and 3f_p2 of the filler cell are vertically stacked in two stages and wired. The two pMOS transistors 3f_p1 and 3f_p2 are connected in series, and connected to the Vss2g side (Vss clip) by the connection 3e. The gate voltages of the two pMOS transistors 3f_p1 and 3f_p2 are always turned on.

  FIG. 7B shows a layout example of a cell with source sharing. In this example, the buffer cell is taken as an example, and only the part necessary for the description of the present embodiment is shown. In the cell 3b, two gate patterns 3b_g2 and 3b_g3 are formed for the pMOS element region 3b_pd and the nMOS element region 3b_nd.

  In the pMOS element region 3b_pd, the wiring pattern 3b_m5 is disposed between the two gate patterns 3b_g2 and 3b_g3, and connects the pMOS element region 3b_pd and the 0.9V power source 2b by the via 6v.

  In the pMOS element region 3b_pd and the nMOS element region 3b_nd, a pair of transistors is wired by the wiring pattern 3b_m6. The wiring pattern 3b_m6 is connected to the pMOS element region 3b_pd, the gate pattern 3b_g3, and the nMOS element region 3b_nd, respectively. Are connected by vias 6v. Another pair of transistors is wired by the wiring pattern 3b_m8. The wiring pattern 3b_m8 has one end connected to the pMOS element region 3b_pd and the other end connected to the nMOS element region 3b_nd through the via 6b.

  In the nMOS element region 3b_nd, the wiring pattern 3b_m7 is disposed between the two gate patterns 3b_g2 and 3b_g3, and connects the nMOS element region 3b_nd and the 0.7V power source 2a.

  Such a layout of the cell 3b is indicated by layout information. By referring to the layout information, in the wiring pattern 3b_m5 connecting the pMOS element region 3b_pd and the 0.9V power source 3b, the gate patterns 3b_g2 and 3b_g3 exist on both sides in the pMOS element region 3b_pd, respectively. It can be determined that it is shared. It is determined that “source sharing exists”.

  The design process of the semiconductor device (hereinafter referred to as LSI) according to the present embodiment that generates the level shifter function using the filler cell as described above is performed by the design apparatus 100 described below. FIG. 8 is a diagram illustrating a hardware configuration of the design apparatus 100 according to the present embodiment.

  In FIG. 8, a design apparatus 100 is an information processing apparatus controlled by a computer, and includes a CPU (Central Processing Unit) 11, a main storage device 12, an auxiliary storage device 13, an input device 14, and a display device 15. And a communication I / F (interface) 17 and a drive device 18 are connected to the bus B.

  The CPU 11 controls the design device 100 according to a program stored in the main storage device 12. The main storage device 12 uses a RAM (Random Access Memory), a ROM (Read Only Memory) or the like, and is obtained by a program executed by the CPU 11, data necessary for processing by the CPU 11, and processing by the CPU 11. Store or temporarily store the data.

  The auxiliary storage device 13 uses an HDD (Hard Disk Drive) or the like, and stores data such as programs for executing various processes. A part of the program stored in the auxiliary storage device 13 is loaded into the main storage device 12 and executed by the CPU 11, whereby various processes are realized.

The input device 14 includes a mouse, a keyboard, and the like, and is used by a designer to input various information necessary for processing by the design device 100. The display device 15 displays various information required under the control of the CPU 11. The communication I / F 17 performs communication through a wired or wireless network. Communication by the communication I / F 17 is not limited to wireless or wired.
A program for realizing the processing performed by the design apparatus 100 is provided to the design apparatus 100 by a storage medium 19 such as a CD-ROM (Compact Disc Read-Only Memory).

  The drive device 18 performs an interface between the storage medium 19 (for example, a CD-ROM) set in the drive device 18 and the design device 100.

  The storage medium 19 stores a program that realizes various processes according to the present embodiment, which will be described later. The program stored in the storage medium 19 is installed in the design apparatus 100 via the drive device 18. . The installed program can be executed by the design apparatus 100.

The storage medium 19 for storing the program is not limited to a CD-ROM, but one or more non-transitory tangible media having a structure that can be read by a computer. If it is. As a computer-readable storage medium, in addition to a CD-ROM, a portable recording medium such as a DVD disk or a USB memory, or a semiconductor memory such as a flash memory may be used.
FIG. 9 is a diagram illustrating a functional configuration example of the design apparatus according to the first embodiment. In FIG. 9, the design apparatus 100 includes a logic synthesis unit 51, an initial placement unit 52, a clock tree generation unit 53, a wiring unit 54, a filler cell insertion unit 55, and an LS function generation unit 56 as processing units. And a timing analysis unit 57. Each processing unit 51 to 57 is realized by executing a corresponding program by the CPU 11.

  Further, the auxiliary storage device 13 includes RTL (Register Transfer Level) data 31, timing constraints 32, a floor plan 33, a netlist 34, timing constraints after logic synthesis 32-2, layout information 35, a voltage setting file 36, a cell GDS. Data 37, cell timing information 38, post-processing netlist 34-2, post-processing layout information 35-2, processing result 39, and the like are stored.

  The logic synthesizer 51 logically synthesizes the RTL data 31 according to the timing constraint 32 and generates a gate level netlist 34. Further, the logic synthesis unit 51 outputs a timing constraint 32-2 after logic synthesis.

  The initial placement unit 52 performs initial placement and optimization of cells using the floor plan 33, the netlist 34, and the post-discussion synthesis timing constraint 32-2. Based on the cell arrangement, the clock tree generator 53 performs arrangement and wiring of the clock signal and optimizes it. The wiring unit 54 performs the optimization by wiring the cells.

  The filler cell insertion unit 55 arranges filler cells in a region where no cells are arranged for power connection between the cells, process flattening, and the like. The filler cell has a function as an ECO cell having NAND-type and inverter-type element shapes in advance so that only the wiring change is required at the time of revision.

  The LS function generation unit 56 uses the pMOS transistor of the disposed filler cell to change the wiring so that the cell in the high speed region 1b has the LS function. The LS function can be provided without newly inserting a filler cell and without changing the arrangement of the cells in the high-speed region 1b.

  The LS function generation unit 56 extracts a path through which the different potential signal propagates based on the net list 34, the layout information 35, and the voltage setting file 36, refers to the cell GDS data 37, and shares the source. The wiring with the filler cell is adjusted according to the presence or absence. As a result, a post-processing netlist 34-2, post-processing layout information 35-2, a processing result 39, and the like are output. The processing result 39 indicates cell GDS data, timing values, and the like.

  The timing analysis unit 57 analyzes the delay of the designed LSI based on the post-processing netlist 34-2, the post-processing layout information 35-2, the processing result 39, and the like.

  The RTL data 31 is a data file that describes a logic circuit in a hardware description language. Prepared in advance by the designer. The timing constraint 32 is a data file indicating timing constraints required for the LSI to be designed. The floor plan 33 is a data file indicating the arrangement of circuit blocks.

  The net list 34 is a data file indicating connection information between logical cells. The post-logic synthesis timing constraint 32-2 is a data file indicating timing constraints obtained by logic synthesis.

  The layout information 35 is a data file indicating physical connection information between cells. The voltage setting file 36 is a data file indicating the voltage setting for each circuit block. The cell GDS data 37 is a data file indicating physical information of each cell and layout design data based on the physical information. The cell timing information 38 is a data file indicating timing values and power information for each cell.

  The post-processing netlist 34-2 is a netlist after generation of the LS function. In the post-processing netlist 34-2, the name of the first stage cell in the high-speed region 1b is changed based on the presence / absence of sharing and the number of stages of pMOS transistors added to the cell.

  The post-processing layout information 35-2 is layout information after generation of the LS function. In post-processing layout information 35-2, physical connection information between the filler cell and the first cell is added.

  The processing result 39 indicates a result after generation of the LS function, and includes information such as cell GDS data and timing values. In the cell GDS data of the processing result 39, the wiring connection layer is added to the connection portion with Vdd with respect to the wiring pattern of the cell before the addition of the LS function. In the cell timing value of the processing result 39, a new cell timing value is defined for each source presence / absence and the number of added pMOS transistors.

  FIG. 10 is a diagram illustrating an example of changing the netlist. In FIG. 10, when the cell “INVXXX” is the first cell in the high-speed region 1b in the net list 34 before the generation of the LS function, the LS function is generated, and the cell “INVXXX” has the LS function. The cell name is changed from the original “INVXXX” to “INVXXX2” on the basis of the presence or absence and the number of added pMOS transistors. The post-processing netlist 34-2 in which the cell name is changed to “INVXXX2” is stored in the auxiliary storage device 13.

  Each value obtained by changing the timing value and power value of the original cell is associated with the new cell name. The processing result 39 indicates a new cell name, a new cell timing value, and a power value. In the processing result 39, post-processing cell timing information in which a new cell name, a new cell timing value, and a power value are added to the cell timing information 38 is output.

  The design process in the first embodiment will be described. FIG. 11 is a flowchart for explaining the design process in the first embodiment. The processing in each step shown in FIG. 11 is realized by the CPU 11 executing a corresponding program. Various data referred to in the design process shown in FIG. 11 and various data to be output are stored in the auxiliary storage device 13.

  In FIG. 11, the logic synthesis unit 51 reads RTL data 31 and timing constraints 32, and performs logic synthesis on the RTL data 31 according to the timing constraints 32 (step S11). A netlist 34 is created. Also, a post-logic synthesis timing constraint 32-2 is output.

  When logic synthesis is performed, the initial arrangement unit 52 refers to the floor plan 33, arranges cells so as to satisfy the post-logic synthesis timing constraint 32-2, and performs optimization in accordance with the connection information of the netlist 34 ( Step S12).

  Next, the clock tree generation unit 53 generates a clock tree based on the initial arrangement of cells and performs optimization (step S13). The wiring unit 54 performs wiring between the cells and optimizes them (step S14).

  Thereafter, the filler cell insertion unit 55 arranges filler cells in an area where no cells are arranged for power connection between cells, process flattening, and the like (step S15).

  After the filler cell is inserted, the LS function generation unit 56 inputs a signal from the low power region 1a to the first cell in the high speed region 1b by using the pMOS transistor of the filler cell around the cell. A function is generated (step S16).

  The timing analysis unit 57 performs timing analysis using the post-processing netlist 34-2, the post-processing layout information 36-2, the processing result 39, and the like obtained after the change of the wiring for generating the LS function ( Step S17).

  If an error is detected by the timing analysis, the cell arrangement is changed, the process returns to step S13, and the same processing as described above is repeated. When the timing analysis ends normally, the design process ends.

  With reference to FIG. 10, the LS function generation processing by the LS function generation unit 56 will be further described. The LS function generation unit 56 refers to the net list 34 after the logic synthesis, the layout information 35, and the voltage setting file 36, and extracts a path through which a signal having a voltage different from the power supply voltage supplied to the cell propagates ( Step S161).

  The LS function generation unit 56 refers to the cell GDS data 37, extracts the layout information of the first stage cell (logic) on the high-speed region 1b side in the extracted path (step S162), and selects one filler cell. (Step S163). Of the filler cells arranged around the extracted cell, it is desirable to select the shortest filler cell from the extracted cells that is located on the Vdd side of the extracted cell.

  The LS function generation unit 56 determines whether to share the source terminal from the extracted cell layout (steps S164 and S165).

  When there is no source sharing (step S164), wiring corresponds to the example of FIG. 6 and wiring corresponding to the circuit diagram of FIG. The LS function generation unit 56 inserts a wiring deletion layer into the Vdd wiring unit of the extracted cell (step S166). The cell GDS data 37 is updated by the insertion of the wiring deletion layer.

  Then, the LS function generation unit 56 connects the extracted cell and the pMOS transistor of the filler cell, and the gate of the pMOS transistor of the filler cell is connected to the signal wiring (step S167). The pMOS transistors of the filler cell are vertically stacked one stage above the extracted cell. The gates of the vertically stacked pMOS transistors are connected to the input signal from the low power region 1a. That is, the pMOS transistor of the filler cell is connected between the pMOS transistor of the extracted cell and Vdd (connected in series on one stage), and shares the input signal with the extracted cell.

  The LS function generation unit 56 changes the timing value of the first-stage cell (extracted cell) in the high-speed region 1b in the cell timing information 38 (step S169). A delay corresponding to one stage of the pMOS transistor of the connected filler cell is added.

  On the other hand, when the source is shared (step S165), this corresponds to the example of FIG. 7, and wiring corresponding to the circuit diagram of FIG. The LS function generation unit 56 inserts a wiring deletion layer into the Vdd wiring unit of the extracted cell (step S166). The cell GDS data 37 is updated by the insertion of the wiring deletion layer.

  Then, the LS function generation unit 56 connects the extracted cell and the two pMOS transistors of the filler cell, and the gates of the two pMOS transistors of the filler cell are clipped to Vss (step S168). The pMOS transistors of the filler cell are vertically stacked on the upper stage of the extracted cell. Each gate of the two-stage pMOS transistors stacked vertically is clipped to Vss. That is, the two pMOS transistors of the filler cell are connected between the pMOS transistor of the extracted cell and Vdd (stacked in two stages by series connection), and the gate is connected to Vss and is always on.

  The LS function generation unit 56 changes the timing value of the first stage cell (the extracted cell) in the high speed region 1b in the cell timing information 38 (step S170). A delay corresponding to two stages of pMOS transistors in the connected filler cell is added.

  By changing the wiring connection by the above-described LS function generation process, a post-processing netlist 34-2, post-processing layout information 36-2, and a processing result 39 are output.

  FIG. 12 is a diagram illustrating a layout change example in the first embodiment when source sharing is not performed. FIG. 12 shows a layout change example after the LS function generation process in the first embodiment, using the example of the inverter described in FIG.

  FIG. 12A shows a state before the LS function generation in the first embodiment after the filler cell 3f is inserted. The layout example which shows arrangement | positioning of the cell 3a and the cell 3b adjacent to the boundary of the low electric power area | region 1a and the high speed area | region 1b before producing | generating an LS function, and the filler cell 3f adjacent to the cell 3b is shown. The signal wiring pattern 3sig_m is formed directly from the wiring pattern 3a_m1 of the cell 3a to the wiring pattern 3b_m4 of the cell 3b.

  The filler cell 3f is a cell having an element shape such as a pMOS element region 3f_pd, an nMOS element region 3f_nd, and gate patterns 3f_g1 and 3f_g2.

  FIG. 12B shows a layout after generation of the LS function described above. The wiring pattern 3f_m1 is added to connect the gate pattern 3f_g1 of the filler cell 3f and the signal wiring pattern 3sig_m by the LS function generation unit 56 in the first embodiment. An input signal from the cell 3a is supplied to the gate pattern 3f_g1 by the wiring pattern 3f_m1 and the via 6v.

  The LS function generation unit 56 adds a wiring pattern 3f_m2 to connect the pMOS element region 3f_pd of the filler cell 3f and the pMOS element region 3b_pd of the cell 3b. One end of the wiring pattern 3f_m2 is connected to the pMOS element region 3f_pd of the filler cell 3f by a via 6v, and the other end is connected to the pMOS element region 3b_pd of the cell 3b by a via 6v.

  Further, a wiring pattern 3f_m3 is added to connect the pMOS element region 3f_pd between the gate patterns 3f_g1 and 3f_g2 of the filler cell 3f and the 0.9V power source 2b. The pMOS element region 3f_pd is connected to the wiring pattern 3b_m3 through the via 6v.

  Then, the LS function generation unit 56 inserts the wiring deletion layer 3b_d1 into the wiring pattern 3b_m3 that connects the pMOS element region 3b_pd of the cell 3b and the 0.9V power supply 2b.

  The wiring patterns 3f_m1, 3f_m2, and 3f_m3 described above may be arranged in either the metal 1 layer or the metal 2 layer.

  FIG. 13 is a diagram showing an example of layout change in the case of source sharing in the first embodiment. FIG. 13 shows a layout change example after the LS function generation processing in the first embodiment, using the example of the buffer described in FIG.

  FIG. 13A shows a state before the LS function generation in the first embodiment after the insertion of the filler cell 3f. The layout example which shows arrangement | positioning of the cell 3a and the cell 3b adjacent to the boundary of the low electric power area | region 1a and the high speed area | region 1b before producing | generating an LS function, and the filler cell 3f adjacent to the cell 3b is shown. The signal wiring pattern 3sig_m is formed directly from the wiring pattern 3a_m1 of the cell 3a to the wiring pattern 3b_m4 of the cell 3b.

  The filler cell 3f is a cell having an element shape such as a pMOS element region 3f_pd, an nMOS element region 3f_nd, and gate patterns 3f_g1 and 3f_g2.

  FIG. 13B shows a layout after generation of the LS function. The LS function generation unit 56 adds a wiring pattern 3f_m5 to connect the gate patterns 3f_g1 and 3f_g2 of the filler cell 3f to Vss2g. The wiring pattern 3f_m5 is connected to each of the gate patterns 3f_g1 and 3f_g2 by the via 6v.

  The LS function generation unit 56 adds a wiring pattern 3f_m6 to connect the pMOS element region 3f_pd of the filler cell 3f and the pMOS element region 3b_pd of the cell 3b. One end of the wiring pattern 3f_m6 is connected to the pMOS element region 3f_pd of the filler cell 3f by a via 6v, and the other end is connected to the pMOS element region 3b_pd of the cell 3b by a via 6v.

  In addition, a wiring pattern 3f_m7 is additionally arranged in order to connect the 0.9V power supply 2b so that the pMOS transistor of the gate pattern 3f_g2 of the filler cell 3f is at the uppermost stage. The wiring pattern 3f_m7 is connected to the pMOS element region 3f_pd of the filler cell 3f by the via 6v.

  Then, the LS function generation unit 56 inserts the wiring deletion layer 3b_d2 into the wiring pattern 3b_m5 that connects the pMOS element region 3b_pd of the cell 3b and the 0.9V power source 2b.

  The wiring patterns 3f_m5, 3f_m6, and 3f_m7 described above may be arranged in either the metal 1 layer or the metal 2 layer.

  FIG. 14 is a diagram for explaining the effect of the first embodiment. In FIG. 14A, the case where the cell 3b is an inverter is shown as an example of no source sharing, and the effect of the first embodiment will be described. In the case of no source sharing, the voltage drops due to the addition of the pMOS transistor 3f_p1 of the filler cell 3f on the source side of the cell 3b, so that the potential of the low power region 1a approaches 0.7V. Therefore, the leakage current Ioff can be reduced.

  For example, it is considered that the voltage drops to 0.8 V by 0.7 V signal input. In this case, the leakage current Ioff can be reduced by 70%. Since the source potential of the pMOS transistor 3b_p of the cell 3b can be lowered, the off state can be realized with high accuracy.

  Thus, in the case of no source sharing, the pMOS transistor 3f_p1 added when the input is 0.7V is turned off, and the original voltage (0.9V in this example) is lowered to the voltage threshold Vth for turning off. The leakage current Ioff can be greatly reduced.

  In FIG. 14B, the case where the cell 3b is a buffer is shown as an example with source sharing, and the effect of the first embodiment will be described. When the source is shared, the pMOS transistors 3f_p1 and 3f_p2 of the filler cell 3f are added to the source side of the cell 3b. Since the logic breaks down, the added pMOS transistors 3f_p1 and 3f_p2 can only be turned on. Therefore, the original voltage (0.9 V in this example) divided by the on-resistance cannot be lowered, but there is an effect of reducing the leakage current Ioff.

  For example, the leakage current Ioff can be reduced by 10% by adding two pMOS transistors 3f_p1 and 3f_p2 vertically to the cell 3b. In the case of the 0.9V power supply 2b, the voltage can be lowered to about 0.89V.

  The leakage current Ioff can be further reduced by further increasing the number of vertically stacked stages. In this case, the driving capability of the cell 3b is reduced by the delay due to the increase of the additional pMOS transistor. Therefore, when three or more stages are added, the number of pMOS transistors may be determined in a trade-off relationship with delay.

  Specifically, the LS function is added to the extracted cell by the design process of the first embodiment, so that in the high speed region 1b, LS is inserted in the path through which the signal from the low power region 1a propagates. It will be in the state. If there is a margin in the timing of the LS inserted path, a pMOS transistor is further added and connected to the cell with the shared source.

  FIG. 15 is a diagram illustrating a functional configuration example of the design apparatus according to the second embodiment. 15, in addition to the processing unit in the first embodiment described above, the design apparatus 100 further includes an LS optimization unit 58. Except for the LS optimizing unit 58, the description is omitted because it is as described above.

  If there is a timing margin in the LS inserted path after the LS function generation processing by the LS function generation unit 56, the LS optimization unit 58 uses the filler cell to further process the post-processing netlist 34-2, Using the layout information 35-2 and the cell timing information 38, the number of pMOS transistors connected to the cell is increased. The power consumption can be further reduced by increasing the number of stages of the pMOS transistors.

  After the LS optimization, the post-optimization netlist 34-4, post-optimization layout information 35-4, post-optimization cell timing information 38-4, and the like are output and stored in the auxiliary storage unit 13.

  FIG. 16 is a flowchart for explaining the design process in the second embodiment. The processing in each step shown in FIG. 16 is realized by the CPU 11 executing a corresponding program. Further, various data referred to in the design process shown in FIG. 16 and various data to be output are stored in the auxiliary storage device 13.

  In the second embodiment of the design process, if the cell having the LS function in the timing analysis after the design process of the first embodiment is a cell with source sharing and there is a margin in the timing of the path, a filler is further added. The pMOS transistors of the cell are connected to increase from two stages to three stages or more.

  In the second embodiment, the processing from steps S11 to S17 is the same as the processing in the first embodiment (FIG. 11), and thus the description thereof is omitted.

  The timing analysis unit 57 determines whether there is a path with sufficient timing based on the timing analysis result (step S18). Optimization target path information 40 indicating a path with sufficient timing and a timing margin is stored in the auxiliary storage device 13.

  If there is no path with sufficient timing, the design process by the design apparatus 100 is terminated. On the other hand, if there is a path with sufficient timing, LS optimization processing by the LS optimization unit 58 is performed (step S19). The LS optimization process will be described.

  The LS optimizing unit 58 refers to the post-processing netlist 34-2 and the post-processing layout information 35-2, and the first stage cell on the high-speed area 2b side of the optimization target path indicated by the optimization target path information 40. The layout information is extracted (step S191).

  Further, the LS optimizing unit 58 determines the additional number of pMOS transistors based on the timing margin acquired by the timing analyzing unit 57 (step S192). The LS optimizing unit 58 refers to the cell timing information 38 to acquire filler cell timing information, and calculates the number of pMOS transistors that can be added within the timing margin.

  Then, the LS optimization unit 58 determines the number of filler cells to be newly added from the element shape of the filler cells based on the added number of pMOS transistors, and selects the filler cells for the determined number (step S193). ).

  If the filler cell has an element shape of two pMOS transistors, and the additional number indicates 1 or 2 in step S192, the LS optimization unit 58 is the first stage other than the filler cell used in the LS function generation unit 56. One other filler cell close to this cell is selected. When the added number indicates 3 or 4, the LS optimizing unit 58 selects two other filler cells close to the first stage cell other than the filler cells used in the LS function generating unit 56.

  When the filler cell is selected, the LS optimizing unit 58 connects the pMOS transistor to be added to the first stage cell to which the pMOS transistor to be added is further added, and Vss-clips the gate of the additional pMOS transistor (step S194).

  After the connection of the additional pMOS transistors, the LS optimization unit 58 determines the timing value of the first cell according to the total of the two pMOS transistors added by the LS function generation unit 56 and the added pMOS transistors. Change (step S195).

  When a total of three pMOS transistors are added to the first stage cell, the delay for one stage is added to the delay of the first stage cell. As a result, together with the LS function generation process in the LS function generation unit 56, the delay of three stages of the pMOS transistor is added to the delay of the first stage cell. When a total of four pMOS transistors are added to the first stage cell, the delay of two stages is added to the delay of the first stage cell. As a result, together with the LS function generation processing in the LS function generation unit 56, the delay of four stages of the pMOS transistors is added to the delay of the first stage cell. Similarly, in the case of 5 stages, 6 stages,..., The timing value of the first stage cell is changed according to the number of stages of the pMOS transistors.

  Through the LS optimization process by the LS optimization unit 58 described above, the post-optimization netlist 34-4 that updates the post-process netlist 34-2, and the post-optimization layout information 35- that updates the post-process layout information 35-2. 4. The post-optimization cell timing information 38-4 updated from the cell timing information 38 is output and stored in the auxiliary storage device 13.

  FIG. 17 is a diagram showing a layout change example in the case of adding a third-stage pMOS transistor with source sharing in the second embodiment. FIG. 17 shows a layout change example after the LS optimization process in the second embodiment, using the example of the buffer described in FIG. In FIG. 17, cells other than those necessary for the description are simply shown as logic cells.

FIG. 17A shows a state before LS optimization processing in the second embodiment after LS function generation and timing analysis. The cell 3a and the cell 3b adjacent to the boundary of the LS optimization process before the low power region 1a and the high-speed region 1b, a filler cell 3f ₁ adjacent to the cell 3b, the arrangement of filler cells 3f ₂ existing around the cell 3b The layout example which shows is shown.

In this layout, pMOS transistor of filler cells 3f ₁ indicates two connected state. Further, the wiring deletion layer 3b_d2 is inserted into the cell 3b.

  If it is determined by timing analysis that the signal path propagating through the cell 3b has sufficient timing, LS optimization processing by the LS optimization unit 58 is performed.

FIG. 17B shows a layout after LS optimization. The LS optimization unit 58, other than the filler cell 3f _1, selects the closest filler cells 3f ₂ to the cell 3b, with the pMOS transistor of the filler cells 3f _2, adding a pMOS transistor of the third stage in the cell 3b .

LS optimization unit 58, a wiring pattern for connecting the filler cell 3f ₁ and 0.9V Current 2b 3f_m7 (FIG 17 (A)), and a pMOS transistor of the pMOS transistor and the filler cell 3f ₂ of filler cells 3f ₁ The wiring pattern 3f_m7 ′ to be connected is changed. And the wiring pattern 3f_m7 'pMOS device region 3f_pd filler cell 3f _2, is connected by a via 6v.

LS optimization unit 58, a gate pattern 3p_g1 of the pMOS transistor of filler cells 3f _2, is clipped to Vss2g by a wiring pattern 3F_m8. The wiring pattern 3f_m8 is connected to the gate pattern 3p_g1 through the via 6v.

Also, LS optimization unit 58 includes a pMOS device region 3f_pd between gate patterns 3p_g1 and 3p_g2 filler cell 3f _2, and a 0.9V power supply 2b, connected by wiring patterns 3F_m9. Wiring patterns 3f_m9 is connected to the pMOS device region 3f_pd of filler cells 3f ₂ by a via 6v.

  A circuit diagram relating to the cell 3b after the wiring is changed as described above is shown in FIG. FIG. 18 is a diagram for explaining the cell configuration after the LS optimization of FIG. Since FIG. 18A is the same as FIG. 17B, description thereof is omitted.

  FIG. 18B shows a circuit diagram in which the cell 3b is a buffer and three stages of pMOS transistors 3f_p1, 3f_p2, and 3f_p3 are connected. Three pMOS transistors 3f_p1, 3f_p2, and 3f_p3 that operate as the LS function for the cell 3b are indicated by dotted arrows in corresponding portions on the layout.

18 from (A) and FIG. 18 (B), the pMOS transistor 3f_p1 and 3f_p2 the first and second stages that are added to the cell 3b is obtained by utilizing the pMOS transistor of the filler cells 3f ₁ adjacent, 3 pMOS transistor 3f_p3 th stage, it is seen that utilizes the pMOS transistors of different filler cells 3f ₂ is a filler cell 3f _1.

  The configuration of the cell 3b ′ having the LS function shown in FIG. 18B can be realized without inserting the LS cell and without replacing with a special cell to which the LS function is added.

  FIG. 19 is a diagram showing an example of layout change when the third and fourth-stage pMOS transistors are added with source sharing in the second embodiment. FIG. 19 shows a layout change example after the LS optimization process in the second embodiment, using the buffer example described in FIG. In FIG. 19, cells other than those necessary for the description are simply shown as logic cells.

FIG. 19A shows a state before LS optimization processing in the second embodiment after LS function generation and timing analysis, and corresponds to the state of FIG. In this layout, pMOS transistor of filler cells 3f ₁ indicates two connected state. Further, the wiring deletion layer 3b_d2 is inserted into the cell 3b.

  If it is determined by timing analysis that the signal path propagating through the cell 3b has sufficient timing, LS optimization processing by the LS optimization unit 58 is performed.

FIG. 19B shows a layout after LS optimization. The LS optimization unit 58, other than the filler cell 3f _1, selects the closest filler cells 3f ₂ to the cell 3b, with the pMOS transistor of the filler cells 3f _2, the pMOS transistor in the cell 3b of the third and fourth stage to add.

LS optimization unit 58, a wiring pattern 3F_m7 for connecting the filler cell 3f ₁ and 0.9V current 2b, the wiring pattern 3F_m7 'for connecting the pMOS transistor of the pMOS transistor and the filler cell 3f ₂ of filler cells 3f ₁ change. And the wiring pattern 3f_m7 'pMOS device region 3f_pd filler cell 3f _2, is connected by a via 6v.

LS optimization unit 58, a gate pattern 3p_g1 and 3p_g2 of the pMOS transistor of filler cells 3f _2, is clipped to Vss2g by a wiring pattern 3F_m8. The wiring pattern 3f_m8 is connected to the gate patterns 3p_g1 and 3p_g2 by the via 6v.

Also, LS optimization unit 58, the source side of the gate pattern 3p_g2 in pMOS device region 3f_pd filler cell 3f _2, connected by a wiring pattern 3f_m10 to 0.9V power supply 2b. Wiring patterns 3f_m10 is connected to the pMOS device region 3f_pd of filler cells 3f ₂ by a via 6v.

  A circuit diagram relating to the cell 3b after the wiring is changed as described above is shown in FIG. FIG. 20 is a diagram for explaining the cell configuration after the LS optimization of FIG. Since FIG. 20A is the same as FIG. 19B, description thereof is omitted.

  FIG. 20B shows a circuit diagram in which the cell 3b is a buffer, and four-stage pMOS transistors 3f_p1, 3f_p2, 3f_p3, and 3f_p4 are connected. Three pMOS transistors 3f_p1, 3f_p2, 3f_p3, and 3f_p4 that operate as the LS function for the cell 3b are indicated by dotted arrows in corresponding portions on the layout.

20 from (A) and FIG. 20 (B), the pMOS transistor 3f_p1 and 3f_p2 the first and second stages that are added to the cell 3b is obtained by utilizing the pMOS transistor of the filler cells 3f ₁ adjacent, 3 pMOS transistors 3f_p3 and 3f_p4 th stage, it is seen that utilizes the pMOS transistors of different filler cells 3f ₂ is a filler cell 3f _1.

  The configuration of the cell 3b ″ having the LS function shown in FIG. 20B can be realized without inserting the LS cell and without replacing with a special cell to which the LS function is added.

  Comparison between the related technology described in FIGS. 1 to 4 and the present embodiment (including the first and second examples) will be described with reference to FIG. FIG. 21 is a diagram for explaining the effect of the present embodiment. The table shown in FIG. 21 shows items such as power (Dynamic + Static), delay, increased area, and creation of a new cell, and shows a comparison between the related technology described in FIGS. 1 to 4 and the present embodiment. As related technologies, direct connection (FIGS. 1A and 2), LS insertion (FIGS. 1B and 3), and a cell with an LS function (FIGS. 1C and 4) are shown.

  Power (Dynamic + Static) includes both dynamic power consumption and static power consumption. The direct connection is “1” and is shown in comparison with the direct connection. Delay indicates the rate of cell delay. The direct connection is “1”, and the degree of increase in delay is shown in comparison with the case of direct connection. The increase area indicates an area that increases when the LS is provided by the unit grid. New cell creation indicates whether or not a new cell needs to be created.

  In the direct connection (FIG. 1A, FIG. 2), power “1”, delay “1”, increase region “0”, and new cell creation “unnecessary”. In the LS insertion (FIG. 1B, FIG. 3), when a cross coupling type LS cell is inserted, the power is “0.8”, the delay is “1.08”, the increase region is “45 grid x2”, and the new Cell creation is “unnecessary”. The increased area “45 grid x2” corresponds to one LS cell 3c in FIG.

  Further, the cell with the LS function (FIG. 1C, FIG. 4) has the power “0.74”, the delay “1.05”, the increase region “about +5 grid”, and the new cell creation “necessary”. The increased area “about +5 grid” is an area necessary for adding the LS function to the original cell in the cell 3d with the LS function.

  On the other hand, in the present embodiment, including the first and second examples, the average power including the presence / absence of source sharing includes power “0.74”, delay “1.05”, increase region “0”, and new cell. Created “unnecessary”. Regarding the increase area “0”, since the ECO cell is arranged in the empty area as a filler cell, the increase in the area may be considered as “0”, but the area for the wiring is slightly increased. Since the amount of increase is small compared to the cell arrangement region, the increase region is set to “0”.

  The present embodiment for generating the LS function can realize the performance of the cell 3d with the LS function with respect to power and delay, and can eliminate the need for creating a new cell.

  As described above, according to the present embodiment, an optimal level shifter function can be realized by cutting and connecting wiring to an existing cell without designing a new cell. That is, in the present embodiment, the number of pMOS transistors to be added is determined according to the function of the cell, and optimal wiring connection for generating the level shifter function is performed based on the layout information 35.

  In the above-described embodiment, the case where there is no source sharing has been described using an inverter as an example, but another logic cell is illustrated in FIG. FIG. 22 is a diagram showing a logic cell without source sharing other than the inverter. Each logic cell shown in FIG. 22 has a CMOS structure having a pMOS element region 3b_pd and an nMOS element region 3b_nd.

  FIG. 22A shows a layout example of a logic cell of 2 NAND. Wiring patterns 81m and 82m for connecting Vdd2v and the pMOS element region 3b_pd are arranged for the 2NAND cell 71 of FIG.

  The gate pattern 81g is arranged only on one side with respect to the wiring pattern 81m. Similarly, the gate pattern 82g is arranged only on one side with respect to the wiring pattern 82m. If the 2NAND cell 71 is the first cell 3b in the high-speed region 1b at the boundary between the low power region 1a and the high-speed region 1b, the cell is a cell without source sharing by referring to the netlist 34 and the layout information 35. It can be judged.

  FIG. 22B shows a layout example of a 2NOR logic cell. A wiring pattern 83m that connects Vdd2v and the pMOS element region 3b_pd is arranged for the 2NOR cell 73 of FIG.

  Gate pattern 83g is arranged only on one side with respect to wiring pattern 83m. When the 2NOR cell 73 is the first cell 3b of the high speed region 1b at the boundary between the low power region 1a and the high speed region 1b, the cell is a cell without source sharing by referring to the netlist 34 and the layout information 35. It can be judged.

  FIG. 22C shows a layout example of a 3NOR logic cell. A wiring pattern 84m that connects Vdd2v and the pMOS element region 3b_pd is arranged for the 3NOR cell 74 of FIG.

  The gate pattern 84g is arranged only on one side with respect to the wiring pattern 84m. When the 3NOR cell 74 is the first cell 3b of the high speed region 1b at the boundary between the low power region 1a and the high speed region 1b, the cell is a cell without source sharing by referring to the netlist 34 and the layout information 35. It can be judged.

  Similarly to the inverter cell described above, the pMOS transistor 3f_p1 of the filler cell 3f is connected to the 2NAND cell 71, 2NOR cell 73, and 3NOR cell 74 in a single-stage stack in the circuit diagram, and the signal input is By sharing, an LS function can be added.

  Next, a design process when this embodiment is not applied will be described. FIG. 23 is a flowchart for explaining a design process to which the present embodiment is not applied. In FIG. 23, processes similar to those described in FIG. 11 are denoted by the same step numbers.

  FIG. 23A shows a flowchart of a design process using the RTL data 31a in which the designer designed the LSI including the LS description. In FIG. 23A, logic synthesis is performed based on the RTL data 31a including the LS description and the timing constraint 32 (step S11), and the net list 34 ′ including the LS cell is output. The post-logic synthesis timing constraint 32 ′ indicates a timing constraint after the logic synthesis including the LS cell.

  Steps S12, S13, S14, S15, and S17 are the same as those in FIG.

  As a result of the timing analysis, if the timing constraint 32 ′ after logic synthesis is not satisfied and the RTL data 31a needs to be reviewed by the designer, the designer reviews it including the LS description. In addition, optimal LS cell placement is not always possible.

  FIG. 23B shows a flowchart of a design process using the RTL data 31b that does not include the LS description, in which the designer designs the LSI. In FIG. 23B, after logic synthesis is performed based on the RTL data 31b having no LS description and the timing constraint 32 (step S11), an LS cell is inserted (step S11-2). A net list 34 ′ including LS cells is output. The post-logic synthesis timing constraint 32 ′ indicates a timing constraint after the logic synthesis including the LS cell.

  Steps S12, S13, S14, and S17 are the same as those in FIG. 11, and thus detailed description thereof is omitted.

  Compared to the case of FIG. 23A, the designer does not need to consider the LS description, but it is necessary to create the RTL data 31b in which the LSI is designed after the power domain is defined in advance.

  In both cases of FIGS. 23A and 23B, a cross coupling type LS cell is usually used. As described with reference to FIG. 21, the power consumption, the delay, and the increase region are inferior when compared with the present embodiment.

  In the present embodiment, in addition to the comparison items in FIG. 21, the designer can reduce the design work burden of the designer in that the LSI can be designed without considering the LS cell insertion.

  In the design apparatus according to the present embodiment, an optimal level shifter function can be realized by cutting and connecting wiring to an existing cell without designing a new cell. The number of pMOS transistors to be added is determined according to the function of the cell, and optimal wiring connection for generating a level shifter function is performed based on the layout information 35.

  The present invention is not limited to the specifically disclosed embodiments, and can be principally modified and changed without departing from the scope of the claims.

Regarding the embodiment including the first to second examples, the following additional notes are disclosed.
(Appendix 1)
A first transistor included in a first circuit supplied with a first power supply and having a gate connected to an output of a second circuit supplied with a second power supply whose voltage value is lower than that of the first power supply Extract
Identifying whether the first transistor shares a source with a second transistor different from the first transistor;
When the source is not shared, one transistor of a plurality of third transistors arranged in advance is connected in series between the source and the first power source,
When the source is shared, the computer performs processing for connecting two of the plurality of third transistors arranged in series between the source and the first power source in series. A method for designing a semiconductor device to be executed.
(Appendix 2)
The method for designing a semiconductor device according to appendix 1, wherein the output of the second circuit is connected to the one transistor when the source is not shared.
(Appendix 3)
3. The semiconductor device design method according to appendix 1 or 2, wherein when the source is shared, the gates of the two transistors are connected to a negative power supply voltage or a ground.
(Appendix 4)
When the source is shared and there is a margin in the timing of the path passing through the first circuit, the two connected between the source and the first power source In addition to the transistors, one or more transistors are further connected in series from the plurality of third transistors according to the timing margin.
4. The method of designing a semiconductor device according to appendix 3, further comprising connecting a gate of the one or more transistors connected to a negative power supply voltage or a ground.
(Appendix 5)
5. The semiconductor device design method according to claim 1, wherein the plurality of third transistors are filler cell transistors around the first circuit.
(Appendix 6)
A first transistor included in a first circuit supplied with a first power supply and having a gate connected to an output of a second circuit supplied with a second power supply whose voltage value is lower than that of the first power supply An extraction unit for extracting
An identification unit for identifying whether the first transistor shares a source with a second transistor different from the first transistor;
When the source is not shared, a no-sharing processing unit that connects in series one of the plurality of third transistors arranged in advance between the source and the first power supply;
In the case where the source is shared, a shared processing unit for connecting two of the plurality of third transistors arranged in series between the source and the first power source in series A design apparatus for designing a semiconductor device having
(Appendix 7)
The design apparatus for designing a semiconductor device according to appendix 6, wherein the plurality of third transistors are pMOS transistors of a filler cell having an element shape.
(Appendix 8)
A first transistor included in a first circuit supplied with a first power supply and having a gate connected to an output of a second circuit supplied with a second power supply whose voltage value is lower than that of the first power supply However, when the source is not shared with a second transistor different from the first transistor, one transistor is connected in series between the source and the first power source, and the one transistor And the gate of the transistor is connected to the output of the second circuit,
In the case where the first transistor shares the source with a second transistor different from the first transistor, two or more transistors are connected in series between the source and the first power supply. And the gates of the two or more transistors are connected to a negative power supply voltage or ground.

11 CPU
12 Main storage device 13 Auxiliary storage device 14 Input device 15 Display device 16 Output device 17 Communication I / F
18 drive 19 storage medium 31 RTL data 32 timing constraint 32-2 timing constraint after logic synthesis 33 floor plan 34 netlist 34-2 post-processing netlist 34-4 post-optimization netlist 35 layout information 35-2 post-processing layout information 35-4 Layout information after optimization 36 Voltage setting file 37 Cell GDS data 38 Cell timing information 38-4 Cell timing information after optimization 39 Processing result (cell GDS data, timing value)
DESCRIPTION OF SYMBOLS 51 Logic synthesis part 52 Initial arrangement part 53 Clock tree generation part 54 Wiring part 55 Filler cell insertion part 56 LS function generation part 57 Timing analysis part 100 Design apparatus

Claims (6)

A first transistor included in a first circuit supplied with a first power supply and having a gate connected to an output of a second circuit supplied with a second power supply whose voltage value is lower than that of the first power supply Extract
Identifying whether the first transistor shares a source with a second transistor different from the first transistor;
When the source is not shared, one transistor of a plurality of third transistors arranged in advance is connected in series between the source and the first power source,
When the source is shared, the computer performs processing for connecting two of the plurality of third transistors arranged in series between the source and the first power source in series. A method for designing a semiconductor device to be executed.   2. The method of designing a semiconductor device according to claim 1, wherein when the source is not shared, an output of the second circuit is connected to the one transistor.   3. The method of designing a semiconductor device according to claim 1, wherein when the source is shared, the gates of the two transistors are connected to a negative power supply voltage or a ground. When the source is shared and there is a margin in the timing of the path passing through the first circuit, the two connected between the source and the first power source In addition to the transistors, one or more transistors are further connected in series from the plurality of third transistors according to the timing margin.
4. The method of designing a semiconductor device according to claim 3, further comprising connecting a gate of the one or more transistors connected to a negative power supply voltage or a ground. A first transistor included in a first circuit supplied with a first power supply and having a gate connected to an output of a second circuit supplied with a second power supply whose voltage value is lower than that of the first power supply An extraction unit for extracting
An identification unit for identifying whether the first transistor shares a source with a second transistor different from the first transistor;
When the source is not shared, a no-sharing processing unit that connects in series one of the plurality of third transistors arranged in advance between the source and the first power supply;
In the case where the source is shared, a shared processing unit for connecting two of the plurality of third transistors arranged in series between the source and the first power source in series A design apparatus for designing a semiconductor device having A first transistor included in a first circuit supplied with a first power supply and having a gate connected to an output of a second circuit supplied with a second power supply whose voltage value is lower than that of the first power supply However, when the source is not shared with a second transistor different from the first transistor, one transistor is connected in series between the source and the first power source, and the one transistor And the gate of the transistor is connected to the output of the second circuit,
In the case where the first transistor shares the source with a second transistor different from the first transistor, two or more transistors are connected in series between the source and the first power supply. And the gates of the two or more transistors are connected to a negative power supply voltage or ground.

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