JP2013027221A - Power conversion apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem in an MMCC-DSCC that, to prevent a power semiconductor element from getting broken down by overcurrent arising from an accident, etc. in a power system, it is necessary to use a power semiconductor element having larger current tolerance than ever for protection against overcurrent, which, however, results in an increased body size of a power conversion apparatus.SOLUTION: A power conversion apparatus is composed of a plurality of arms, each having a plurality of unit converters cascaded thereto, which are star or delta connected or connected in a bridge form. The power conversion apparatus provided by the present invention includes a control device incorporating at least two or more partial arithmetic units which operate in at least two or more kinds of control cycles.

Description

  The present invention relates to a power conversion device, and more particularly to a power conversion device configured using an arm in which a plurality of unit converters configured by bidirectional chopper circuits, single-phase full bridge circuits, and the like are cascade-connected.

  Modular Multilevel Cascade Converter (MMCC) is a multi-cascade connection of unit converters composed of bidirectional chopper circuits, single-phase full bridge circuits, etc. It is a power conversion device configured to be connected or connected in a bridge shape, and has a feature that a voltage exceeding the withstand voltage of a power semiconductor element used in each unit converter can be output.

  Non-Patent Document 1 discloses four classifications and application examples of MMCC.

  In MMCC-DSCC (Double Star Chopper Cells) shown in Non-Patent Document 1, a bidirectional chopper circuit is used as a unit converter, and a series body of an arm and a reactor that is a serial body of a plurality of unit converters is 2 Three legs connected in series are connected in parallel.

  The MMCC-DSCC has an AC terminal and a DC terminal.

  For example, the AC terminal of the first MMCC-DSCC is connected to the first AC power system via a transformer, the DC terminal of the first MMCC-DSCC is connected to one end of the DC cable, If the DC terminal of the second MMCC-DSCC is connected to the end and the AC terminal of the second MMCC-DSCC is connected to the second AC power system via a transformer, the first AC power system and the second A direct-current power transmission system (HVDC) that accommodates electric power between the two alternating-current power systems via the direct-current cable can be configured.

H. Akagi, “Classification, terminology, and applications of the modular multilevel converter (MMCC)”, IPEC 2010, pp.508-515.

  When the AC terminal of the MMCC-DSCC is connected to the AC power system and the active / reactive power that the MMCC-DSCC exchanges with the AC power system is controlled, it is necessary to feedback control the current flowing through each arm of the MMCC-DSCC, for example. . In this specification, the feedback control of the arm current is simply referred to as current control.

  The current flowing through each arm is proportional to the time integral of the difference between the voltage of the AC power system and the fundamental AC component of the output voltage of each arm of the MMCC-DSCC, and the inductance of the reactor and the leakage inductance of the transformer Inversely proportional to the sum.

  Therefore, the current flowing through each arm can be controlled by controlling the difference between the voltage of the AC power system and the fundamental AC component of the output voltage of each arm of the MMCC-DSCC.

  When the current control is executed by a control device using a digital arithmetic unit such as a CPU (Central Processing Unit), a DSP (Digital Signal Processor), or an FPGA (Field-Programmable Gate Array), a finite calculation time is required. is there. Therefore, it is necessary to execute time-discrete current control with an interval longer than the finite calculation time. The execution period of the time discrete current control is referred to as a control period.

  When current control is executed using a digital arithmetic unit, the following calculation is generally performed in each control cycle.

  First, the current flowing through each arm and the voltage of the AC power system are sampled. Next, the current command value and the current flowing through each arm are compared, for example, the command value of the output voltage component used for current control of each arm is calculated using a proportional / integral controller, and the output used for the current control is calculated. The output voltage command value of each arm is calculated by adding or subtracting the sampling result of the voltage of the AC power system to the command value of the voltage component.

  Here, the operation of “adding or subtracting the sampling result of the voltage of the AC power system to the command value of the output voltage component used for the current control” is referred to as system voltage feedforward in this specification.

  Finally, based on the output voltage command value, ON / OFF of the power semiconductor element of each unit converter belonging to each arm is determined using, for example, triangular wave comparison PWM (Pulse Width Modulation) and the result is controlled. Transmit from the device to each unit converter.

  If the MMCC-DSCC connected to the AC power system is performing time-discrete current control, for example, even if the voltage of the AC power system changes suddenly due to a ground fault caused by lightning, the control cycle will continue. Then, the on / off state of the power semiconductor element belonging to each unit converter is not updated.

  Therefore, the voltage between the AC power system and the AC terminal of the MMCC-DSCC is a period from the time when the voltage of the AC power system suddenly changes to the time when the on / off state of the power semiconductor element belonging to each unit converter is updated. Since the difference between the two is larger than that during normal operation, the current flowing through each arm greatly increases, which may cause overcurrent.

  In order to prevent the power semiconductor element from being damaged due to the overcurrent, it is necessary to use a power semiconductor element with a larger current withstanding that an overcurrent flows. There was a problem that the physique would increase in size.

  Further, in order to reduce the magnitude of the overcurrent, there is a problem that the control cycle must be increased and a high-speed CPU, DSP, FPGA, or the like must be used.

  The present invention relates to a power converter configured by connecting a plurality of arms, each having a plurality of unit converters connected in cascade, in a star connection, a delta connection, or a bridge, and the power converter includes at least two types of control cycles. A power conversion device comprising a control device having at least two or more partial arithmetic devices that operate in (1) is provided.

  According to the present invention, the unit converter includes at least two power semiconductor elements and an energy storage element.

  Further, the present invention is characterized in that the unit converter is a bidirectional chopper circuit or a single-phase full bridge circuit.

  Further, the present invention provides a power conversion device configured by connecting a plurality of arms, each having a plurality of unit converters connected in cascade, in a star connection, a delta connection, or a bridge, and connected to an AC power system. The apparatus includes a control device having at least two or more partial arithmetic devices that operate in at least two kinds of control cycles, and at least one of the partial arithmetic devices is faster than other partial arithmetic devices. The power converter is characterized in that the voltage of the AC power system is sampled.

  Further, the present invention provides a power conversion device configured by connecting a plurality of arms, each having a plurality of unit converters connected in cascade, in a star connection, a delta connection, or a bridge, and connected to an AC power system. The apparatus includes a control device having at least two or more partial arithmetic devices that operate in at least two kinds of control cycles, and at least one of the partial arithmetic devices is higher than the other partial arithmetic devices. The power converter is characterized by sampling the voltage of the AC power system at a frequency and transmitting a control signal to each unit converter.

  Further, the present invention provides a power conversion device configured by connecting a plurality of arms, each having a plurality of unit converters connected in cascade, in a star connection, a delta connection, or a bridge, and connected to an AC power system. The apparatus includes a control device having at least two or more partial arithmetic devices that operate in at least two kinds of control cycles, and at least one of the partial arithmetic devices is higher than the other partial arithmetic devices. The present invention provides a power converter characterized by sampling a current flowing through the AC power system and / or a current flowing through each arm at a frequency.

  Further, the present invention provides a power conversion device configured by connecting a plurality of arms, each having a plurality of unit converters connected in cascade, in a star connection, a delta connection, or a bridge, and connected to an AC power system. The apparatus includes a control device having at least two or more partial arithmetic devices that operate in at least two kinds of control cycles, and at least one of the partial arithmetic devices is higher than the other partial arithmetic devices. The present invention provides a power converter characterized by sampling a current flowing through the AC power system and / or a current flowing through each arm at a frequency and transmitting a control signal to each unit converter.

  Further, the present invention provides a power conversion device configured by connecting a plurality of arms, each having a plurality of unit converters connected in cascade, in a star connection, a delta connection, or a bridge, and connected to an AC power system. The apparatus includes a control device having at least two or more partial arithmetic devices that operate in at least two kinds of control cycles, and at least one of the partial arithmetic devices is higher than the other partial arithmetic devices. When the current flowing through the AC power system and / or the current flowing through each arm is sampled at a frequency, and the difference between the sampled current and the corresponding command value exceeds the upper limit or the lower limit, each arm described above Having a function of inverting the switching state of switching elements belonging to some or all of the unit converters belonging to There is provided a force transducer device.

  According to the present invention, it is possible to reduce an overcurrent that occurs when a voltage suddenly changes in an AC power system without improving the calculation performance of the entire control device. Therefore, the size of the power converter can be reduced.

The MMCC-DSCC system power converter based on this invention. Bidirectional chopper circuit type unit converter. Current control block diagram. An example of a timing chart. An example of a voltage / current waveform based on the prior art. An example of the voltage and electric current waveform at the time of performing the system voltage feedforward based on this invention. An example of a voltage and a current waveform at the time of performing current control based on the present invention. An example of a schematic waveform at the time of applying this invention.

  A first embodiment of the present invention will be described.

  In this embodiment, the MMCC-DSCC control device connected to the AC power system via a transformer performs a high-speed partial calculation device that performs high-speed calculations and a calculation that is slower than the high-speed partial calculation devices. It is characterized by comprising a low-speed partial arithmetic unit.

  In this embodiment, it is possible to reduce the overcurrent generated when the voltage of the AC power system suddenly changes without improving the calculation performance of the entire control device. Therefore, the effect that the physique of a power converter device can be reduced is acquired.

  The overall configuration of this embodiment will be described below with reference to FIG.

  The power conversion apparatus 102 is connected to the AC power system 101 via the transformer 103.

  The power conversion device 102 includes a transformer 103 and six arms 104RP, RN, SP, SN, TP, TN, six reactors 106, a voltage sensor 108, a current sensor 109, a low-speed partial calculation device 110S, a high-speed partial calculation device 110F, A control communication line 111 is used. Hereinafter, the low-speed partial calculation device 110S and the high-speed partial calculation device 110F will be collectively referred to as a control device.

  Each arm 104RP, RN, SP, SN, TP, TN is a serial body of n unit converters 105. The internal configuration and operation principle of the unit converter 105 will be described later.

  Hereinafter, the connection of the six arms 104RP, RN, SP, SN, TP, TN, and the six reactors 106 of the power conversion device will be described in more detail.

  A series body of the arm 104RP, the two reactors 106, and the arm 104RN is referred to as an R-phase leg. The connection point between the two reactors is referred to as an R point. R point is connected to the R phase terminal of the secondary winding of transformer 103.

  A series body of the arm 104SP, the two reactors 106, and the arm 104SN is referred to as an S-phase leg. The connection point between the two reactors is referred to as S point. The point S is connected to the S phase terminal of the secondary winding of the transformer 103.

  A series body of the arm 104TP, the two reactors 106, and the arm 104TN is referred to as a T-phase leg. The connection point between the two reactors is referred to as a T point. The T point is connected to the T phase terminal of the secondary winding of the transformer 103.

  The R phase leg, the S phase leg, and the T phase leg are connected in parallel, and the parallel connection points are referred to as P point and N point.

  A DC device 107 is connected between the P point and the N point. The DC device 107 is drawn as a representative of a DC power system, a DC load device, and / or another power converter connected via a DC cable.

  Next, the connection between the voltage sensor 108 and the current sensor 109 will be described.

  The voltage sensor 108 detects, for example, line voltages vGRS, vGST, and vGTR of the AC power system 101, and transmits them to the high-speed partial calculation device 110F.

  The current sensor 109 detects currents iRP, iRN, iSP, iSN, iTP, and iTN flowing through the arms 104RP, RN, SP, SN, TP, and TN, and transmits them to the high-speed partial arithmetic unit 110F.

  Next, the internal configuration and operation principle of the unit converter 105 will be described with reference to FIG. FIG. 2 shows the internal configuration of the k-th unit converter 105 belonging to the arm 104j as a representative. Here, j = RP, RN, SP, SN, TP, TN, k = 1, 2,..., N.

  The main circuit portion of the unit converter 105 includes a series body of a first parallel body of a switching element 201H and an anti-parallel diode 202H, a serial body of a switching element 201L and a second parallel body of an anti-parallel diode 202L, and a capacitor 203 in parallel. Consists of the body.

  The unit converter 105 includes a unit converter control device 204 having a function of supplying gate-emitter voltages of the switching elements 201H and 201L and a function of sampling each DC capacitor voltage VCjk). The unit converter controller 204 is connected to the high-speed partial arithmetic unit 110F via the control communication line 111.

  Hereinafter, the relationship between the switching states of the switching elements 201H and 201L and the output voltage Vjk of the unit converter 105 will be described.

  When the switching element 201H is controlled to be on and 201L is controlled to be off, Vjk can be made substantially equal to the voltage VCjk of the capacitor 203.

  When the switching element 201H is turned off and 201L is turned on, Vjk can be made substantially zero.

  When both the switching elements 201H and 201L are controlled to be on, the capacitor 203 is short-circuited, and thus such an operation is prohibited.

  When both switching elements 201H and 201L are controlled to be off, Vij depends on the polarity of current ij. When ij is positive, Vjk is approximately zero. When ij is negative, Vjk is approximately equal to VCjk.

  Hereinafter, the calculation performed by the control device will be described with reference to FIG.

  The low-speed partial calculation block 301S is a block executed by the low-speed partial calculation device 110S, and the high-speed partial calculation block 301F is a block executed by the high-speed partial calculation device 110F.

  The feature of the present invention is that the high-speed partial calculation unit 110F executes the calculation of the high-speed partial calculation block 301F more frequently than the low-speed partial calculation unit 110S, and the high-speed partial calculation block 301F performs partial hysteresis control 302 described later. It is a point that has.

  First, the calculation of the low-speed partial calculation block 301S will be described.

  The low speed partial calculation block 301S receives the currents iR, iS, and iT flowing from the transformer 103 to the R point, the S point, and the T point from the high speed partial calculation block 301F. Note that iR, iS, and iT can be calculated by equations (1) to (3) from currents flowing through the arms 104RP, RN, SP, SN, TP, and TN.

(Equation 1)
iR = iRP-iRN (1)
(Equation 2)
iS = iSP-iSN (2)
(Equation 3)
iT = iTP-iTN (3)

  The low-speed partial calculation block 301S performs the αβ converter 303 and the dq converter 304 on iR, iS, and iT to obtain a d-axis current id and a q-axis current iq.

  The phase angle θ used for the dq converter 304 is matched with the phase of the phase voltage vGR of the AC power system 101 using means such as a PLL (Phase Locked Loop) not shown. Further, the phase voltages vGR, vGS, vGT of the AC power system 101 can be calculated using the equations (4) to (6) from the line voltages vGRS, vGST, vGTR of the AC power system 101 detected by the voltage sensor 108. .

(Equation 4)
vGR = (vGRS−vGTR) / 3 (4)
(Equation 5)
vGS = (vGST−vGRS) / 3 (5)
(Equation 6)
vGT = (vGTR-vGST) / 3 (6)

The obtained id and iq are subtracted from the respective command values id ^* and iq ^* to obtain errors id ^* -id and iq ^* -iq. The command values id ^* and iq ^* are given from a host control system not shown.

The error id ^* −id, iq ^* −iq is multiplied by the gain 305, and the non-interference term obtained from the non-interference control block 306 is added to the voltage component command value vdGCR ^* on the dq axis used for current control. Get vqGCR ^* .

The obtained vdGCR ^* and vqGCR ^* are subjected to a dq inverse converter 307 and an αβ inverse converter 308 to obtain voltage component command values vRGCR ^* , vSGCR ^* and vTGCR ^* used for current control. Furthermore, the obtained vRGCR ^* , vSGCR ^* , and vTGCR ^* are transmitted to the high-speed partial calculation block 301F.

The low-speed partial computation block 301S further applies an inverse dq converter 307 and an inverse αβ converter 308 to the current command values id ^* and iq ^* on the dq axis, and obtains three-phase current command values iR, iS, and iT. These are transmitted to the high-speed partial calculation block 301F.

  Next, the calculation of the high-speed partial calculation block 301F will be described.

The high-speed partial calculation block 301F adds the phase voltages vGR, vGS, and vGT of the AC power system 101 to vRGCR ^* , vSGCR ^* , and vTGCR ^* obtained from the low-speed calculation block. Further, voltage component command values vRPHC ^* , vSPHC ^* , vTPHC ^* from a partial hysteresis control 302 described later are added, respectively, so that an R-phase voltage command value vR ^* , an S-phase voltage command value vS ^* , and a T-phase voltage command value vT ^*. Get.

Although not shown in FIG. 3, the command values vRP ^* and vRN ^* of the output voltages vRP and vRN of the arms 104RP and 104RN can be obtained by applying the equations (7) and (8) to vR ^*. .

(Equation 7)
vRP ^* = vDC ^* / 2-vR ^* (7)
(Equation 8)
vRN ^* = vDC ^* / 2 + vR ^* (8)

Here, vDC ^* is a command value of the voltage vDC applied to the DC device 107 between the points P and N in FIG.

Based on the obtained vRP ^* and vRN ^* , a switching command is transmitted to the switching elements 201H and 201L of the unit converter 105 included in the arms 104RP and 104RN via the control communication line 111.

Similarly, vS ^* (9), by applying the equation (10), arm 104SP and 104SN output voltage VSP, each command value VSN VSP ^*, obtained the VSN ^*.

(Equation 9)
vSP ^* = vDC ^* / 2-vS ^* (9)
(Equation 10)
vSN ^* = vDC ^* / 2 + vS ^* (10)

Based on the obtained vSP ^* and vSN ^* , a switching command is transmitted via the control communication line 111 to the switching elements 201H and 201L of the unit converter 105 included in the arms 104SP and 104SN.

Similarly, the command values vTP ^* and vTN ^* of the output voltages vTP and vTN of the arms 104TP and 104TN can be obtained by applying the equations (11) and (12) to vT ^* .

(Equation 11)
vTP ^* = vDC ^* / 2-vT ^* (11)

(Equation 12)
vTN ^* = vDC ^* / 2 + vT ^* (12)

Based on the obtained vTP ^* and vTN ^* , a switching command is transmitted to the switching elements 201H and 201L of the unit converter 105 included in the arms 104TP and 104TN via the control communication line 111.

  Hereinafter, the operation of the partial hysteresis control 302 will be described with reference to FIG. Here, the control of the R phase will be described as an example.

First, the partial hysteresis control 302, the IRH ^* obtained by adding Iband the current command value of the R-phase iR ^*, generates a iRL ^* 2 two signals obtained by subtracting the Iband from iR ^*. In this specification, iRH ^* is referred to as a hysteresis upper limit, and iRL ^* is referred to as a hysteresis lower limit.

Partial hysteresis control state machine 309, the actual current iR and IRH ^*, compares the magnitude of iRL ^*, performs state transition as shown in FIG. 4 based on the comparison result. There are three states, for example, and the output signal vRPHC ^* of the partial hysteresis control 302 is different in each state.

The initial state is state 0 (START), and in state 0, vRPHC ^* = 0.

When iR> iRH ^* is detected in the state 0 (START), the state transits to the state 1 (HBC). In state 1 (HBC), vRPHC ^* = − VPHC.

  Note that VPHC is a positive value between 0 and VDC / 2.

Similarly, when iR <iRL ^* is detected in the state 0 (START), the state transits to the state 2 (LBC). In state 2 (LBC), vRPHC ^* = VPHC.

In state 1 (HBC), iR <iRH ^* and iR> iRL ^* are detected, and a new control cycle (a low-speed control cycle to be described later) of the low-speed partial calculation device 110S executing the low-speed partial calculation block 301S ) Starts, the state transitions to state 0 (START).

When iR <iRL ^* is detected in state 1 (HBC), the state transits to state 2 (LBC).

When iR> iRH ^* is detected in state 2 (LBC), the state transits to state 1 (HBC).

In state 2 (HBC), iR <iRH ^* and iR> iRL ^* are detected, and a new control cycle (a low-speed control cycle to be described later) of the low-speed partial calculation device 110S executing the low-speed partial calculation block 301S ) Starts, the state transitions to state 0 (START).

  Hereinafter, referring to FIG. 5, the low-speed partial calculation device 110S executing the low-speed partial calculation block 301S and the low-speed partial calculation block 301S, and the high-speed partial calculation executing the high-speed partial calculation block 301F and the high-speed partial calculation block 301F. The operation timing of the apparatus 110F will be described.

  The low-speed partial calculation device 110S executes the calculation shown in the low-speed partial calculation block 301S in a low-speed control cycle with TScont as one cycle.

  Specifically, the following operation is executed in one low speed control cycle.

  First, detection results of currents iRP, iRN, iSP, iSN, iTP, and iTN are received from the high-speed partial calculation device 110F. Next, the calculation shown in the low-speed partial calculation block 301S in FIG. 3 is executed. When the calculation is completed, the process waits until the next low-speed control cycle starts.

  The high-speed partial calculation device 110F executes the calculation shown in the high-speed partial calculation block 301F with a high-speed control cycle in which TFcont is one cycle. Further, TFcont <TScont is set.

  Specifically, the following operation is executed in one high-speed control cycle.

  First, the current iRP, iRN, iSP, iSN, iTP, iTN and the line voltages vGRS, vGST, vGTS of the AC power system 101 are sampled. Next, the calculation shown in the high-speed partial calculation block 301F in FIG. 3 is executed. Next, on / off commands of the switching elements 201H and 201L belonging to each unit converter 105 are transmitted to the unit converter control device 204 of each unit converter 105 via the control communication line 111. When the transmission is completed, it waits until the next high-speed control period starts.

  Hereinafter, the effects of the present invention will be described with reference to FIGS.

  FIG. 6 shows a state in which the high-speed partial calculation device 110F described above is operating at the same frequency as the low-speed partial calculation device 110S (ie, TFCont = TScont) and the partial hysteresis control 302 is not operating (ie, VPHC). = 0), the schematic waveform of the voltage and current of the R phase is drawn. Therefore, FIG. 6 is a schematic waveform in the prior art to which the present invention is not applied.

  The upper part of FIG. 6 shows a waveform of (vRN−vRP) / 2 obtained by dividing the difference between the waveform of the R-phase voltage vGR of the AC power system 101 and the output voltage waveform of the arms 104RP and 104RN by 2.

The lower part of FIG. 6 shows waveforms of the current iR and its command value iR ^* .

  6 to 8, the waveform of (vRN−vRP) / 2 is a step wave, and one step is approximately equal to the voltage vCjk of the DC capacitor 203 of one unit converter 105. If the number of unit converters 105 included in one arm (= n) is sufficiently large, the step width relative to vGR becomes small, and harmonics can be reduced.

  Note that the current iR is proportional to the time integral of the difference between vGR and (vRN−vRP) / 2 as expressed in the equation (13), and is 1/2 of the inductance LB of the reactor 106 and the leakage of the transformer. It is inversely proportional to the sum L with the inductance Ltr.

(Equation 13)
iR = (1 / L) ∫ {vGR− (vRN−vRP) / 2} dt (13)

  When a fault (Grid Fault) occurs in the AC power system 101, the voltage vGR changes suddenly. In the worst case, it takes TScont time from when the vGR suddenly changes until the low speed control cycle starts.

  During this time, the current iR rapidly increases and significantly increases from the command value as shown in FIG. This increase is proportional to TScont.

  In the prior art, the power converter 102 having a resistance to an increase in current when a fault (Grid Fault) occurs in the AC power system 101 must be designed, which leads to an increase in the size of the power converter 102.

  FIG. 7 shows a state in which the high-speed partial calculation device 110F described above is operating more frequently than the low-speed partial calculation device 110S (ie, TFCont <TScont) and the partial hysteresis control 302 is not operating (ie, This is a schematic waveform of R-phase voltage / current in the case of VPHC = 0). Therefore, FIG. 7 is a schematic waveform when a portion other than the partial hysteresis control 302 of the present invention is applied.

  When a fault (Grid Fault) occurs in the AC power system 101, the voltage vGR changes suddenly. From when the vGR suddenly changes until the high-speed control cycle of the high-speed partial arithmetic unit 110F that generates the on / off command of the switching elements 201H and 201L belonging to each unit converter 105 is reached based on the detected value of vGR In the worst case, it takes TFcont time.

  During this time, the current iR rapidly increases and significantly increases from the command value as shown in FIG. This increase is proportional to TFcont.

  Here, since TFcont <TScont as described above, the increase in current is smaller than that in FIG. Therefore, compared with the case of FIG. 6 to which the conventional technique is applied, the current withstand capability of the power converter 102 can be designed to be small in the case of FIG.

However, the control to decrease the increased current and follow the command value iR ^* is not executed until the low-speed control cycle of the low-speed partial arithmetic unit 110S is reached. Therefore, in the worst case, the current does not decrease during the period of TScont.

  On the other hand, FIG. 8 shows a state in which the high-speed partial calculation device 110F described above is operating more frequently than the low-speed partial calculation device 110S (ie, TFCont <TScont) and the partial hysteresis control 302 is operating. FIG. 6 is a schematic waveform diagram of R-phase voltage / current when VPHC is a finite value. Therefore, FIG. 8 is a schematic waveform when the present invention is applied.

  When a fault (Grid Fault) occurs in the AC power system 101, the voltage vGR changes suddenly. From when the vGR suddenly changes until the high-speed control cycle of the high-speed partial arithmetic unit that generates the on / off command of the switching elements 201H and 201L belonging to each unit converter 105 based on the detected value of the vGR comes around. In the worst case, TFcont time is required.

  During this time, the current iR rapidly increases and significantly increases from the command value as shown in FIG. This increase is proportional to TFcont.

Here, when the current iR exceeds the hysteresis upper limit iRH ^* of the command value iR ^* , the partial hysteresis control state machine 309 of the partial hysteresis control 302 transits from the state 0 (START) to the state 1 (HBC), and the R phase VPHC is subtracted from the voltage command value vR ^* . Further, the output pressure command values vRP ^* and vRN ^{* of the} arms 104RP and 104RN belonging to the R-phase leg also change by vPHC according to the equations (7) and (8).

  In this case, since the voltage that decreases the current iR is applied to the reactor 106 and the leakage inductance of the transformer, the current iR decreases.

If the iRL ^* <iR <iRH ^* is satisfied when the low speed control cycle has come, the partial hysteresis control state machine 309 transitions from the state 1 (HBC) to the state 0 (START), and the partial hysteresis control 302 The output voltage component command value is zero.

  Therefore, in FIG. 8 to which the partial hysteresis control 302 is applied, overcurrent can be suppressed in a shorter time than in FIG.

  In this embodiment, although MMCC-DSCC is targeted, the other three methods of MMCC disclosed in Non-Patent Document 1, namely, MMCC-SSBC, MMCC-SDBC, and MMCC-DSBC, are slightly It can be applied by modifying it.

  In this embodiment, the currents flowing through the six arms of the MMCC-DSCC are detected by the current sensor 109, but the currents flowing from the respective terminals of the secondary winding of the transformer to the R point, the S point, and the T point. The present invention can also be applied when the current is detected by a current sensor.

101 AC power system 102 Power conversion device 103 Transformer 104RP, RN, SP, SN, TP, TN Arm 105 Unit converter 106 Reactor 107 DC device 108 Voltage sensor 109 Current sensor 110F High-speed partial calculation device 110S Low-speed partial calculation device 111 Control Communication line 201H, L Switching element 202H, L Reverse parallel diode 203 Capacitor 204 Unit converter controller 301F High speed partial calculation block 301S Low speed partial calculation block 302 Partial hysteresis control 303 αβ converter 304 dq converter 305 Gain 306 Non-interference control block 307 dq inverse converter 308 αβ inverse converter 309 Partial hysteresis control state machine

Claims (8)

  In a power converter configured by connecting a plurality of arms, each having a plurality of unit converters connected in cascade, in a star connection, a delta connection, or a bridge, the power converter operates at least in two or more control cycles. A power conversion device comprising a control device having two or more partial arithmetic devices.   In a power conversion apparatus configured by connecting a plurality of unit converters connected in cascade in a star connection, a delta connection, or a bridge, and connected to an AC power system, the power conversion apparatus includes at least two or more types A control device having at least two partial arithmetic devices that operate in the control cycle of the AC power system, wherein at least one of the partial arithmetic devices is faster than the other partial arithmetic devices. A power converter characterized by sampling a voltage.   In a power conversion apparatus configured by connecting a plurality of unit converters connected in cascade in a star connection, a delta connection, or a bridge, and connected to an AC power system, the power conversion apparatus includes at least two or more types A control device having at least two or more partial arithmetic devices that operate in a control cycle of the AC power system, wherein at least one of the partial arithmetic devices is more frequently used than the other partial arithmetic devices. A power conversion device characterized by sampling the voltage of the power supply and transmitting a control signal to each unit converter.   In a power conversion apparatus configured by connecting a plurality of unit converters connected in cascade in a star connection, a delta connection, or a bridge, and connected to an AC power system, the power conversion apparatus includes at least two or more types A control device having at least two or more partial arithmetic devices that operate in a control cycle of the AC power system, wherein at least one of the partial arithmetic devices is more frequently used than the other partial arithmetic devices. And / or a current flowing through each arm is sampled.   In a power conversion apparatus configured by connecting a plurality of unit converters connected in cascade in a star connection, a delta connection, or a bridge, and connected to an AC power system, the power conversion apparatus includes at least two or more types A control device having at least two or more partial arithmetic devices that operate in a control cycle of the AC power system, wherein at least one of the partial arithmetic devices is more frequently used than the other partial arithmetic devices. And / or a current flowing through each arm, and a control signal is transmitted to each unit converter.   In a power conversion apparatus configured by connecting a plurality of unit converters connected in cascade in a star connection, a delta connection, or a bridge, and connected to an AC power system, the power conversion apparatus includes at least two or more types A control device having at least two or more partial arithmetic devices that operate in a control cycle of the AC power system, wherein at least one of the partial arithmetic devices is more frequently used than the other partial arithmetic devices. When the difference between the sampled current and the command value corresponding to each sampled current exceeds the upper limit or the lower limit, a part or all of the arms belonging to each arm is sampled. A power conversion device having a function of inverting a switching state of a switching element belonging to the unit converter.   7. The power converter according to claim 1, wherein the unit converter includes at least two power semiconductor elements and an energy storage element.   8. The power conversion device according to claim 1, wherein the unit converter is a bidirectional chopper circuit or a single-phase full bridge circuit.