JP2013026910A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce current consumption.SOLUTION: A semiconductor device includes: a differential amplifier (MN1, MN2 in Fig. 2) for amplifying a potential difference appearing between first and second input terminals on the basis of first and second power supplies; a bias transistor (MN3 in Fig. 2) for controlling a bias current for operating the differential amplifier; a current mirror circuit (MP1, MP2 in Fig. 2) for loading the differential amplifier; and a bias control circuit having first and second transistors (MP4, MP6 in Fig. 2) opposite in conductivity type to the bias transistor having control ends connected to a diode connection side of the current mirror circuit and connected in series between the first and second power supplies, and having a connection node between the first and second transistors connected to a control end of the bias transistor.

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a differential amplifier as an input circuit.

  Differential amplifiers are widely used in input circuits and the like in semiconductor devices. In recent years, power supply voltages used in analog circuits tend to decrease for the purpose of reducing power consumption and speeding up. For the purpose of applying to such an analog circuit, a differential amplifier with high output accuracy that can be used with a low-voltage power supply is disclosed in Patent Document 1 and the like.

  FIG. 5 is a circuit diagram of the differential amplifier described in Patent Document 1. In FIG. In FIG. 5, a differential amplifier 110 amplifies a signal output from the main differential amplifier circuit 111 and the main differential amplifier circuit 111 including a differential amplifier, and outputs an output signal amplified by the open drain output circuit 131. To do. The bias control differential amplifier circuit 121 detects an offset voltage included in the differential output signal of the differential amplifier unit of the main differential amplifier circuit 111, and the differential of the main differential amplifier circuit 111 is based on the detected offset voltage. The offset voltage included in the output signal is reduced by controlling the operating point of the amplifier.

  In the main differential amplifier circuit 111, the gate of the NMOS MN1 is connected to the negative input terminal IN (−). The NMOS MN2 has a gate connected to the positive input terminal IN (+) and a source connected to the source of the NMOS MN1. The NMOS MN3 has a source connected to the ground potential VSS, a drain connected to the source of the NMOS MN1, and a gate as a circuit point BCONT1. The source of the PMOS MP1 is connected to the power supply VDD, the drain indicating the circuit point DOP1 is connected to the drain of the NMOS MN1, and the gate is connected to its own drain. The source of the PMOS MP2 is connected to the power supply VDD, the drain indicating the circuit point DON1 is connected to the drain of the NMOS MN2, and the gate is connected to the gate of the PMOS MP1.

  The bias control differential amplifier circuit 121 includes an NMOS MN4, an NMOS MN5, a PMOS MP4, and a PMOS MP5. In the bias control differential amplifier circuit 121, the source of the PMOS MP4 is connected to the power supply VDD, and the gate indicating the circuit point DIP1 is connected to the drain of the PMOS MP1 (circuit point DOP1). In the PMOS MP5, the source is connected to the power supply VDD, the gate indicating the circuit point DIN1 is connected to the drain of the PMOS MP2 (circuit point DON1), and the drain indicating the circuit point SO1 is connected to the gate of the NMOS MN3. The NMOS MN4 has a source connected to the ground potential VSS, a drain connected to the drain of the PMOS MP4, and a gate connected to its own drain. The NMOS NM5 has a source connected to the ground potential VSS, a drain connected to the drain of the PMOS MP5, and a gate connected to the gate of the NMOS MN4.

  The open drain output circuit 131 includes a PMOS MP3. In the open drain output circuit 131, the PMOS MP3 has a source connected to the power supply VDD, a gate connected to the drain of the PMOS MP2 (circuit point DON1), and a drain connected to the output terminal OUT.

  When the connections between the components are arranged, the differential input terminals (DIP1, DIN1) of the bias control differential amplifier circuit 121 are connected to the differential output terminals (DOP1, DON1) of the main differential amplifier circuit 111. The positive output terminal DOP1 and the negative output terminal DON1 of the differential output terminal to be paired with the main differential amplifier circuit 111 are the differential input of the positive input terminal DIP1 and the negative input terminal DIN1 to be paired with the bias control differential amplifier circuit 121. The control terminal BCONT1 of the main differential amplifier circuit 111 is connected to the output SO1 of the bias control differential amplifier circuit 121 connected to each terminal.

  According to such a differential amplifier 110, it is possible to reduce the influence of the power supply voltage fluctuation on the output signal voltage output from the open drain output circuit 131 connected to the complementary output terminal of the main differential amplifier circuit 111. Thus, a differential amplifier with high stability against power supply voltage fluctuations can be obtained.

JP 2010-056889 A

  The following analysis is given in the present invention.

  By the way, in the bias control differential amplifier circuit 121 of FIG. 5, there are two current paths from the power supply VDD to the ground potential VSS: a series circuit of PMOS MP4 and NMOS MN4 and a series circuit of PMOS MP5 and NMOS MN5. However, current consumption is large.

  A semiconductor device according to one aspect of the present invention operates a differential amplifier that amplifies a potential difference appearing at first and second input terminals based on first and second power supplies, and a differential amplifier. A bias transistor for controlling a bias current, a current mirror circuit serving as a load of the differential amplifier, a diode connection side of the current mirror circuit and respective control terminals are connected, and in series between the first and second power supplies A bias control circuit having first and second transistors of opposite conductivity type to the bias transistor connected, and connecting a connection node between the first and second transistors to a control terminal of the bias transistor. .

  According to the present invention, since there is only one power supply path in the bias control circuit, current consumption can be reduced.

It is a figure which shows the structure of the semiconductor device which concerns on one Example of this invention. It is a figure which shows the circuit diagram and operating waveform of an input circuit which concern on one Example of this invention. It is a figure which shows the signal level of each part when the reference signal VREF shifts from high to low at a certain timing. 1 is a configuration diagram of a system in which an input circuit according to an embodiment of the present invention is used. It is a circuit diagram of the conventional differential amplifier.

  Hereinafter, an embodiment for carrying out the present invention will be outlined. Note that the reference numerals of the drawings attached to the following outline are only examples for facilitating understanding, and are not intended to be limited to the illustrated embodiments.

  A semiconductor device according to an embodiment of the present invention includes a differential amplifier (corresponding to MN1 and MN2 in FIG. 2) that amplifies a potential difference appearing at first and second input terminals based on first and second power supplies. A bias transistor for controlling a bias current for operating the differential amplifier (corresponding to MN3 in FIG. 2), a current mirror circuit (corresponding to MP1 and MP2 in FIG. 2) serving as a load of the differential amplifier, and a current mirror circuit The first and second transistors (MP4 and MP6 in FIG. 2) having a conductivity type opposite to that of the bias transistor are connected to the diode connection side and the respective control terminals and connected in series between the first and second power supplies. And a bias control circuit that connects a connection node between the first and second transistors to a control terminal of the bias transistor.

  The semiconductor device is a semiconductor memory device, and the input circuit in the semiconductor memory device may include a differential amplifier, a bias transistor, a current mirror circuit, and a bias control circuit.

  The input circuit may be included in an address input circuit, a command input circuit, and an input / output circuit in the semiconductor memory device.

  The semiconductor device is a control device that controls the semiconductor memory device, and an input circuit connected to the semiconductor memory device in the control device includes a differential amplifier, a bias transistor, a current mirror circuit, and a bias control circuit. Also good.

  According to the semiconductor device as described above, since the power supply path in the bias control circuit is only one system of the first and second transistors, current consumption can be reduced.

  Hereinafter, it will be described in detail with reference to the drawings in accordance with embodiments.

  FIG. 1 is a diagram showing a configuration of a semiconductor device according to one embodiment of the present invention. In FIG. 1, the semiconductor device is an SDRAM (Synchronous Dynamic Random Access Memory), which includes an address input circuit 11, an address latch circuit 12, a command input circuit 13, a command decode circuit 14, a mode register 15, a refresh control circuit 16, and a column. A decoder 17, a row decoder 18, a memory cell array 19, a clock input circuit 20, a timing generator 21, a DLL circuit 22, a FIFO circuit 23, an input / output circuit 24, and an internal power generation circuit 25 are provided.

  The address input circuit 11 receives an address signal ADD and a reference signal VREF from the outside, buffers them, and outputs them to the address latch circuit 12. The address latch circuit 12 latches the address signal ADD at the timing of the clock signal ICLK and outputs it to the mode register 15, the column decoder 17, and the row decoder 18.

  The command input circuit 13 inputs a row address strobe signal / RAS, a column address strobe signal / CAS, a reference signal VREF, and a reset signal / RST from the outside, and outputs a signal related to the command to the command decode circuit 14. The command decode circuit 14 latches and decodes the signal related to the command at the timing of the clock signal ICLK, outputs the decode timing of the column address to the column decoder 17, and outputs the decode timing of the row address to the row decoder 18. The setting timing is output to the mode register 15, the refresh timing is output to the refresh control circuit 16, and the reset signal DLLRESET is output to the DLL circuit 22.

  The mode register 15 sets the operation mode of the DRAM in accordance with the mode setting timing. The refresh control circuit 16 controls the row decoder 18 so as to generate a refresh address from the row decoder 18 in accordance with the refresh timing.

  The column decoder 17 outputs a column address to the memory cell array 19, the row decoder 18 outputs a row address to the memory cell array 19, and the memory cell array 19 accesses memory cells corresponding to the column address and the row address.

  The clock input circuit 20 receives and buffers the clock signals CK and / CK from the outside, and outputs the clock signal ICLK to the address latch circuit 12, the command decode circuit 14, the timing generator 21, and the DLL circuit 22. The timing generator 21 distributes various timing signals synchronized with the clock signal ICLK to each unit as necessary, and controls each timing at which each timing signal is transmitted through the semiconductor device. The DLL circuit 22 receives the clock signal ICLK and the reset signal DLLRESET, and outputs the clock signal LCLK in which the phase of the clock signal ICLK is adjusted to the FIFO circuit 23 and the input / output circuit 24.

  The FIFO circuit 23 is located between the memory cell array 19 and the input / output circuit 24 and buffers input / output data. The input / output circuit 24 outputs the write data input from the DQ terminal to the FIFO circuit 23, and outputs the read data input from the FIFO circuit 23 to the DQ terminal. In this case, the phase of the clock signal LCLK is adjusted so that the data signal output from the DQ terminal is synchronized with the external clock signal CK in synchronization with the clock signal LCLK.

  The internal power supply generation circuit 25 inputs power supply VDD and VSS from the outside, changes the internal power supply voltage, and supplies power to each unit.

  Here, in each input circuit included in the address input circuit 11, the command input circuit 13, and the input / output circuit 24, each signal related to the address, command, and data input from the outside is compared with the reference signal VREF, and the comparison result is obtained. Accordingly, the logical H / L level is determined.

  Next, the input circuit will be described. FIG. 2 is a diagram showing a circuit diagram and operation waveforms of one input circuit corresponding to one input signal. 2A, the same reference numerals as those in FIG. 5 represent the same items, and the description thereof is omitted.

  The PMOS transistor MP4 has a source connected to the power supply VDD, a gate connected to the drain of the PMOS transistor MP1, and a drain connected to the source of the PMOS transistor MP6 and the gate of the NMOS transistor MN3. The PMOS transistor MP6 has a gate connected to the drain of the PMOS transistor MP1, and a drain connected to the power supply VSS. The PMOS transistors MP4 and MP6 constitute a bias control circuit that controls the voltage VN of the gate of the NMOS transistor MN3 in accordance with the voltage NOT of the drain of the PMOS transistor MP1.

  The PMOS transistor MP7 has a source connected to the power supply VDD, a gate connected to the drain of the NMOS transistor MN1, and a drain connected to the drain and gate of the NMOS transistor MN6. The NMOS transistor MN6 has a source connected to the power supply VSS. The NMOS transistor MN7 has a drain connected to the drain of the PMOS transistor MP3 and outputs an output signal OUT, a gate connected to the drain of the NMOS transistor MN6, and a source connected to the power supply VSS. The PMOS transistor MP3 functions as an output circuit having driving capability on the power supply VDD side when inverting the signal NOB of the drain of the NMOS transistor MN2 and outputting the inverted signal NOB as the output signal OUT. The NMOS transistor MN7 functions as an output circuit having a driving capability on the power supply VSS side when the signal NOT of the drain of the NMOS transistor MN1 is normally rotated and output as the output signal OUT.

  As shown in FIG. 2B, the input circuit configured as described above includes a reference signal VREF (1.1 V as an example) and an input signal IN (amplitude is a level of 1.0 V to 1.2 V = VDD). The output signal OUT (amplitude is VDD: 1.2 V to VSS: 0 V) is output from the level comparison of.

  Next, an operation when the reference signal VREF is shifted from high to low at a certain timing will be described. FIG. 3 is a diagram illustrating signal levels of the respective parts when the reference signal VREF is shifted from high to low at a certain timing.

  First, when the reference signal VREF decreases (1.1 V → 0.72 V), the NOT level increases (0.57 → 0.57 + α) due to a decrease in the capability of the NMOS transistor MN1. NOT is given to the gates of both PMOS transistors MP4 and MP6, and the PMOS transistors MP4 and MP6 operate in the triode region and the saturation region, respectively. The current change due to the NOT change is more strongly received by the MP6 operating in the saturation region, and the ability of the MP6 is greatly reduced as compared with that of the MP4, raising the level of VN (0.92V + α). Then, the capability of the NMOS transistor MN3 increases, and the operation is performed in a direction of decreasing the NOT level via the NMOS transistor MN1 (0.57 → 0.57 + α → 0.63). The drop in the NOT level also acts on each of the PMOS transistors MP4 and MP6, and as a result, the respective contacts settle down to the signal levels shown in FIG.

  By suppressing the final level change of NOT and NOB, it is possible to suppress the change in the operation speed due to the change in the level of the reference signal VREF. Further, since the bias control circuit is composed of only one system including the PMOS transistors MP4 and MP6, the voltage constraint is VDD> | VTP | + Vod. The restrictions of the differential amplifier main body and the pseudo differential amplifier in the subsequent stage are VDD> VTN + Vod, and the restrictions on the connection part of each part are also these two restrictions. Here, VTP is a threshold voltage of the PMOS transistor, VTN is a threshold voltage of the NMOS transistor, and Vod is a saturation voltage of the PMOS transistor and the NMOS transistor.

  FIG. 4 is a configuration diagram of a system in which an input circuit according to an embodiment of the present invention is used. In the above description, the input circuit in the memory device 40 has been described as an example, but the present invention is not limited to this. That is, in FIG. 4, the controller 30 receives the read data DATA from the memory device 40 in the same manner as the memory device 40 receives the address signal ADD and the command signal COM from the controller 30. It goes without saying that the input circuit shown in FIG. 2A can also be used in the input circuit 35 of the controller 30.

  Further, as described above, the input circuit in the memory device has been described as an example. However, the present invention is not limited to this, and the input circuit in the present invention can be applied to all circuits related to data transfer and the like.

  It should be noted that the disclosure of the aforementioned patent document is incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

11 address input circuit 12 address latch circuit 13 command input circuit 14 command decode circuit 15 mode register 16 refresh control circuit 17 column decoder 18 row decoder 19 memory cell array 20 clock input circuit 21 timing generator 22 DLL circuit 23 FIFO circuit 24 input / output circuit 25 Internal power generation circuit 30 Controller 35 Input circuit 40 Memory devices MN1 to MN7 NMOS transistors MP1 to MN7 PMOS transistors

Claims (4)

A differential amplifier that amplifies the potential difference appearing at the first and second input terminals based on the first and second power sources;
A bias transistor for controlling a bias current for operating the differential amplifier;
A current mirror circuit serving as a load of the differential amplifier;
The first and second transistors having a conductivity type opposite to that of the bias transistor are connected to the diode connection side of the current mirror circuit and the respective control terminals and connected in series between the first and second power supplies. A bias control circuit for connecting a connection node between the first and second transistors to a control terminal of the bias transistor;
A semiconductor device comprising: The semiconductor device according to claim 1 is a semiconductor memory device,
An input circuit in the semiconductor memory device includes the differential amplifier, the bias transistor, the current mirror circuit, and the bias control circuit.   3. The semiconductor device according to claim 2, wherein the input circuit is included in an address input circuit, a command input circuit, and an input / output circuit in the semiconductor memory device. The semiconductor device according to claim 1 is a control device that controls the semiconductor memory device,
An input circuit connected to the semiconductor memory device in the control device includes the differential amplifier, the bias transistor, the current mirror circuit, and the bias control circuit.

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