JP2013026470A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem in 1T-DRAM that a high GIDL current is mainly caused by a leak current at a PN junction, and it may be a cause of generating a leak current at data holding, which reduces a charge holding time in DRAM.SOLUTION: A portion of a drain diffusion layer which overlaps with a gate electrode is divided into two portions being different in impurity concentration. One portion of the two portions is lower in impurity concentration, which adjoins a body part to reduce electric field, thereby suppressing a leak current. At the other portion which is high in impurity concentration, which is insulated from the body part, a relatively large tunnel effect is available at an interface to a gate insulating layer. As a result, while GIDL current is increased, a leak current caused by PN junction is suppressed, to allow extension of the data holding time.

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a dynamic random access memory structure.

  As a kind of DRAM (Dynamic Random Access Memory), 1T-1C-DRAM (1 Transistor 1 Condenser DRAM: 1 transistor 1 capacitor DRAM) and 1T-DRAM (1 Transistor DRAM: 1 transistor DRAM) are known. It has been.

  In the current general 1T-1C-DRAM, one transistor and one capacitor are used for each bit. However, the existence of this capacitor makes further miniaturization difficult.

  Therefore, 1T-DRAM that uses only one transistor per bit without requiring a capacitor has been attracting attention. 1T-DRAM can be used as a single DRAM, but it can also be used as an embedded SoC (System On Chip) that forms a logic circuit and DRAM (Dynamic Random Access Memory) in the same process. There is an advantage that it is possible.

  In 1T-DRAM, a technique is known in which when a bit state “1” is written, a gate is turned off and holes generated by a GIDL (Gate Induced Drain Leakage) current are accumulated in the body. . This is described in Non-Patent Document 1 (Eiji Yoshida et al., “A Design of a Capacitorless 1T-DRAM Cell Using Gate-induced Drain Leakage (GIDL) Current for Low-EdM”. Dig., Pp. 913-916, 2003.).

  In relation to the above, Patent Document 1 (Japanese Patent Application Laid-Open No. 2003-31696) discloses a description relating to a semiconductor memory device. This semiconductor memory device is characterized by the following. In this semiconductor memory device, a memory cell is constituted by one transistor including a gate, first and second sources / drains, and a floating channel body. Here, the first and second sources / drains are formed apart from each other in the semiconductor element formation region. The floating channel body stores a first data state set to a first potential and a second data state set to a second potential, and includes a first source / drain and a second source. The conductivity type is opposite to those between the drains. In the first data state of the transistor, the second source / drain is set as a reference potential, a first control voltage having a polarity for turning on the channel is applied to the gate, and the first control voltage is applied to the first source / drain. Writing is performed by applying a second control voltage of the same polarity, causing impact ionization in the vicinity of the first source / drain junction, and injecting majority carriers into the channel body. In the second data state of the transistor, the first source / drain is a reference potential, the first control voltage is applied to the gate, and the third source having the same polarity as the first control voltage is applied to the second source / drain. Writing is performed by applying a control voltage to release majority carriers in the channel body to the first source / drain.

Patent Document 2 (Japanese Patent Laid-Open No. 2005-51186) discloses a description relating to a semiconductor memory device. This semiconductor memory device is characterized by the following. The semiconductor memory device includes an insulating film, a first conductivity type silicon layer, a second conductivity type source diffusion layer and a drain diffusion layer, a gate insulating film, and a gate electrode. Here, the first conductivity type silicon layer is formed on the insulating film. The source diffusion layer and drain diffusion layer of the second conductivity type are formed on the insulating film, and a silicon layer is sandwiched between them. The gate insulating film is formed on the silicon layer. The gate electrode is formed on the gate insulating film. The drain diffusion layer has a first impurity diffusion layer and a second impurity diffusion layer. Here, the first impurity diffusion layer overlaps with the gate electrode in plan view and has an impurity concentration of 1 × 10 ¹⁹ cm ⁻³ or more. The second impurity diffusion layer is formed under the first impurity diffusion layer, is in contact with the silicon layer, and has an impurity concentration lower than that of the first impurity diffusion layer.

  Patent Document 3 (Japanese Unexamined Patent Application Publication No. 2009-59859) discloses a description relating to a semiconductor memory device. This semiconductor memory device includes an insulating film, a semiconductor layer, a source, a drain, a floating body, a gate insulating film, a gate electrode, a source / drain insulating film, and a silicide layer. Here, the semiconductor layer is provided on the insulating film. The source is provided in the semiconductor layer. The drain is provided in the semiconductor layer. The floating body is provided between the source and the drain, is in an electrically floating state, and accumulates or emits carriers to store data. The gate insulating film is provided on the floating body. The gate electrode is provided on the gate insulating film. The source / drain insulating film is provided on the source and drain and is thinner than the gate insulating film. The silicide layer is provided on the source / drain insulating film.

  The 1T-DRAM according to Patent Document 2 will be described in more detail. FIG. 1 is a cross-sectional view showing a configuration of a 1T-DRAM according to Patent Document 2. As shown in FIG. First, components of the 1T-DRAM in FIG. 1 will be described. The 1T-DRAM of FIG. 1 includes a silicon substrate 1, a buried oxide film 2, a P-type body 3, a gate electrode 4, a gate insulating film 5, a sidewall insulating film 6, a source diffusion layer 7, a drain. And a diffusion layer 8. The source diffusion layer 7 includes a low concentration impurity diffusion layer 7a, a first high concentration impurity diffusion layer 7b, and a second high concentration impurity diffusion layer 7c. The drain diffusion layer 8 includes a low-concentration impurity diffusion layer 8a, a first high-concentration impurity diffusion layer 8b, and a second high-concentration impurity diffusion layer 8c.

  Next, the connection relationship of the components of the 1T-DRAM in FIG. 1 will be described. A buried oxide film 2 is laminated on the silicon substrate 1. On the buried oxide film 2, an aggregate of a P-type body 3, a source diffusion layer 7, and a drain diffusion layer 8 is laminated. On the aggregate of the P-type body 3, the source diffusion layer 7, and the drain diffusion layer 8, an aggregate of the gate electrode 4, the gate insulating film 5, and the sidewall insulating film 6 is laminated.

  The positional relationship among the P-type body 3, the source diffusion layer 7, and the drain diffusion layer 8 will be described. In the drain diffusion layer 8, the first high-concentration impurity diffusion layer 8 b is disposed above the P-type body 3 and overlaps the gate electrode 4. Below the first high-concentration impurity diffusion layer 8b, the second high-concentration impurity diffusion layer 8c is disposed so as to be offset from the gate electrode 4. A low-concentration impurity diffusion layer 8a is disposed between the second high-concentration impurity diffusion layer 8c and the P-type body 3. The source diffusion layer 7 has a symmetrical structure with the drain diffusion layer 8 with the P-type body 3 interposed therebetween.

  A gate insulating film 5 and a gate electrode 4 are stacked in this order above the P-type body 3. A sidewall insulating film 6 is formed around the gate insulating film 5 and the gate electrode 4 in the horizontal direction. A word line (not shown) is connected to the gate electrode 4. A ground line (not shown) is connected to the first high-concentration impurity diffusion layer 7 b in the source diffusion layer 7. A bit line (not shown) is connected to the first high-concentration impurity diffusion layer 8 b in the drain diffusion layer 8.

  As described above, the 1T-DRAM of FIG. 1 has a MOSFET structure formed on an SOI (Silicon On Insulator) substrate.

The operation of the 1T-DRAM in FIG. 1 will be described. The first high-concentration impurity diffusion layer 8b in the drain diffusion layer 8 has an impurity concentration of 10 ¹⁹ cm ⁻³ or more, more preferably 10 ²⁰ cm ⁻³ or more, and increases the GIDL current. The On the other hand, the first high-concentration impurity diffusion layer 8b has a PN junction formed between the P-type body 3 and the low-concentration impurity diffusion layer 8a, so that the electric field at these interfaces is relaxed. As a result, the leakage current is suppressed and the charge retention time is improved.

JP 2003-31696 A JP-A-2005-511186 JP 2009-59859 A

Eiji Yoshida et al. “A Design of a Capacitorless 1T-DRAM Cell Using Gate-Induced Drain Leakage (GIDL) Current for Low-power and High-speed Embedded Memory,” I. Dig. , Pp. 913-916, 2003. (Fujitsu Micro Electronics)

Generally, in order to improve the operation speed of DRAM, the longer the refresh time, the better. This is equivalent to a long charge retention time in the DRAM. Here, in the 1T-DRAM described in Patent Document 2, the impurity concentration in the first high-concentration impurity diffusion layer 8b is set to a relatively high value of 10 ¹⁹ cm ⁻³ or more. For this reason, the band-to-band tunneling current in the direction perpendicular to the substrate at the interface with the gate insulating film 5 is small. On the other hand, the interband tunnel current or the trap assist tunnel current at the PN junction with the P-type body 3 is large. That is, the high GIDL current is mainly due to the leakage current at the PN junction, which also causes a leakage current during data retention, and reduces the charge retention time in the DRAM.

  The means for solving the problem will be described below using the numbers used in the (DETAILED DESCRIPTION). These numbers are added to clarify the correspondence between the description of (Claims) and (Mode for Carrying Out the Invention). However, these numbers should not be used to interpret the technical scope of the invention described in (Claims).

  A semiconductor device according to the present invention includes a silicon substrate (101 or the like) and a MOSFET. Here, the MOSFET is formed on a silicon substrate (101 or the like). The MOSFET includes a source / drain diffusion layer, a gate insulating film (such as 105), a gate electrode (such as 104), and a sidewall insulating film (such as 106). Here, the gate insulating film (105 or the like) is stacked on the source / drain diffusion layer. The gate electrode (such as 104) is stacked on the gate insulating film (such as 105). The sidewall insulating film (such as 106) is formed around the gate insulating film (such as 105) and the gate electrode (such as 104). The source / drain diffusion layer includes a body portion (103, etc.), a first drain diffusion layer (108a, etc.), a second drain diffusion layer (108c, etc.), and a third drain diffusion layer (108b, etc.). It has. Here, the body part (103 or the like) is formed in a lower region of the gate insulating film (105 or the like) and is an intrinsic that is doped with an impurity of one polarity or is not doped. The first drain diffusion layer (108a and the like) is formed in a region adjacent to the body portion (103 and the like) and overlapping with the gate insulating film (105 and the like). Doped in concentration. The second drain diffusion layer (such as 108c) is formed in a region offset from the gate insulating film (such as 105), and the other polarity impurity is doped with the second concentration. The third drain diffusion layer (108b or the like) is formed in a region adjacent to the first drain diffusion layer and the second drain diffusion layer and overlapping the gate insulating film (105 or the like). Polar impurities are doped at a third concentration. The third concentration is included in a range where a tunnel effect occurs in the gate insulating film (105 or the like). The first concentration is included in a range that is lower than the third concentration and in which the tunnel effect occurs less in the gate insulating film (such as 105) than in the third concentration. The second concentration is higher than the first concentration and is included in a range where the tunnel effect is suppressed in the gate insulating film (105 and the like).

  In the semiconductor device of the present invention, the portion of the drain diffusion layer that overlaps the gate electrode is divided into two portions having different impurity concentrations. Of these two portions, one portion having a lower impurity concentration is adjacent to the body portion, and a relatively small tunnel effect is obtained at the interface with the gate insulating layer. Further, the other portion having a higher impurity concentration is insulated from the body portion, and a relatively large tunnel effect can be obtained at the interface with the gate insulating layer. As a result, while increasing the GIDL current, it is possible to suppress the leakage current due to the PN junction and increase the data retention time.

FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device according to a related technique. FIG. 2 is a cross-sectional view showing the configuration of the semiconductor device according to the first embodiment of the present invention. FIG. 3 is a graph showing the relationship between the impurity concentration in the drain diffusion layer and the interband tunnel current generated at the junction of the drain diffusion layer and the gate insulating film in the semiconductor device according to the first embodiment of the present invention. . FIG. 4A shows the relationship between the band bending amount and the tunnel length in the high-concentration impurity diffusion layer when the gate voltage is applied in the negative direction with respect to the drain voltage in the semiconductor device according to the first embodiment of the present invention. It is an energy band figure showing. FIG. 4B shows the relationship between the band bending amount and the tunnel length in the intermediate concentration impurity diffusion layer when the gate voltage is applied in the negative direction with respect to the drain voltage in the semiconductor device according to the first embodiment of the present invention. It is an energy band figure showing. FIG. 4C shows the relationship between the band bending amount and the tunnel length in the low-concentration impurity diffusion layer when the gate voltage is applied in the negative direction with respect to the drain voltage in the semiconductor device according to the first embodiment of the present invention. It is an energy band figure showing. FIG. 5 is a cross-sectional view showing the configuration of the semiconductor device according to the second embodiment of the present invention. FIG. 6 is a cross-sectional view showing the configuration of the semiconductor device according to the third embodiment of the present invention. FIG. 7A is an overhead view showing the configuration of the semiconductor device according to the fourth embodiment of the present invention. FIG. 7B is a cross-sectional view of the semiconductor device of FIG. 7A along the cutting line A-A ′. FIG. 7C is a cross-sectional view of the semiconductor device of FIG. 7A along the cutting line B-B ′.

  DESCRIPTION OF EMBODIMENTS Embodiments for implementing a semiconductor device according to the present invention will be described below with reference to the accompanying drawings.

(First embodiment)
FIG. 2 is a cross-sectional view showing the configuration of the semiconductor device according to the first embodiment of the present invention. Components of the semiconductor device in FIG. 2 will be described. The semiconductor device shown in FIG. 2 roughly includes first, second, and third layers. The first layer includes a silicon substrate 101 and a buried oxide film 102. The second layer includes a P-type body 103 as a body portion, a source diffusion layer 107, and a drain diffusion layer 108. The third layer includes a gate electrode 104, a gate insulating film 105, and a sidewall insulating film 106. The source diffusion layer 107 includes a low concentration impurity diffusion layer 107a and a high concentration impurity diffusion layer 107b. The drain diffusion layer 108 includes a low concentration impurity diffusion layer 108a, a medium concentration impurity diffusion layer 108b, and a high concentration impurity diffusion layer 108c.

  The positional relationship and connection relationship of the components of the semiconductor device in FIG. 2 will be described. The first, second and third layers are stacked in this order from the bottom to the top. In the first layer, the silicon substrate 101 and the buried oxide film 102 are stacked in this order from the bottom to the top. At this time, the first layer functions as an SOI substrate. Hereinafter, the first layer is referred to as a substrate layer.

  In the second layer, the high concentration impurity diffusion layer 107b, the low concentration impurity diffusion layer 107a, the P-type body 103, the low concentration impurity diffusion layer 108a, the medium concentration impurity diffusion layer 108b, and the high concentration impurity diffusion layer 108c. Are arranged in this order from left to right. Hereinafter, the second layer is referred to as a source / drain diffusion layer.

  In the third layer, the gate insulating film 105 and the gate electrode 104 are stacked in this order from bottom to top. A sidewall insulating film 106 is provided around the gate insulating film 105 and the gate electrode 104. Hereinafter, the third layer is referred to as a gate layer.

  The positional relationship of the drain diffusion layer 108 with respect to the gate electrode 104 will be described. Of the drain diffusion layer 108, the low-concentration impurity diffusion layer 108a overlaps the gate electrode 104, and is disposed between the P-type body 103 and the medium-concentration impurity diffusion layer 108b. Of the drain diffusion layer 108, the high concentration impurity diffusion layer 108 c is offset from the gate electrode 104. Among the drain diffusion layers 108, the medium concentration impurity diffusion layer 108b is disposed between the low concentration impurity diffusion layer 108a and the high concentration impurity diffusion layer 108c, and a part thereof overlaps the gate electrode 104. The remaining part is offset from the gate electrode 104. In other words, the P-type body 103, the low-concentration impurity diffusion layer 108a, the medium-concentration impurity diffusion layer 108b, and the high-concentration impurity diffusion layer 108c are arranged in this order from left to right in FIG. Yes.

  The positional relationship of the source diffusion layer 107 with respect to the gate electrode 104 will be described. Of the source diffusion layer 107, the low-concentration impurity diffusion layer 107a partially overlaps the gate electrode 104, and is disposed between the P-type body 103 and the high-concentration impurity diffusion layer 107b. Of the source diffusion layer 107, the high concentration impurity diffusion layer 107 b is offset from the gate electrode 104. In other words, the P-type body 103, the low concentration impurity diffusion layer 107a, and the high concentration impurity diffusion layer 107b are arranged in this order from right to left in FIG.

  Unlike the case of FIG. 2, the source diffusion layer 107 may have, for example, a configuration that is in contrast to the drain diffusion layer 108 of FIG. That is, a part of the low concentration impurity diffusion layer 107a on the high concentration impurity diffusion layer 107b side may be replaced with a medium concentration impurity diffusion layer (not shown) having the same shape, positional relationship and impurity concentration as the drain diffusion layer 108b. I do not care. In this case, there is an advantage that the source diffusion layer 107 can be manufactured simultaneously with the drain diffusion layer 108.

  An operation of the semiconductor device in FIG. 2 will be described. First, the meaning of the difference in concentration between the low concentration impurity diffusion layer 108a, the medium concentration impurity diffusion layer 108b, and the high concentration impurity diffusion layer 108c in the drain diffusion layer 108 will be described.

FIG. 3 shows the relationship between the impurity concentration in the drain diffusion layer 108 and the interband tunneling current generated at the junction between the drain diffusion layer 108 and the gate insulating film 105 in the semiconductor device according to the first embodiment of the present invention. It is a graph. In the graph of FIG. 3, the horizontal axis represents the drain impurity concentration, and the vertical axis represents the interband tunnel current. In the example of FIG. 3, there is a peak where the band-to-band tunneling current is the highest value in the range of the drain impurity concentration of 10 ¹⁸ cm ⁻³ to 10 ¹⁹ cm ⁻³ .

Here, the explanation is continued by using 10 ¹⁸ cm ⁻³ and 10 ¹⁹ cm ⁻³ as the drain impurity concentrations as threshold values for defining low concentration, medium concentration and high concentration. That is, the drain impurity concentration in the drain diffusion layer 108 is less than 10 ¹⁸ cm ^{−3 in the} low concentration impurity diffusion layer 108 a, and is 10 ¹⁸ cm ⁻³ or more and less than 10 ¹⁹ cm ^{−3 in} the medium concentration impurity diffusion layer 108 b. In the high-concentration impurity diffusion layer 108c, it is 10 ¹⁹ cm ⁻³ or more. However, these threshold values are merely examples, and actually depend on all parameters related to the configuration and manufacturing method of the semiconductor device, and do not limit the present invention.

  FIG. 4A shows the band bending amount 401a, the tunnel length, and the like in the high concentration impurity diffusion layer 108c when the gate voltage is applied in the negative direction with respect to the drain voltage in the semiconductor device according to the first embodiment of the present invention. It is an energy band figure showing these relationships. In FIG. 4A, the horizontal axis indicates the space extending from the left to the right across the gate electrode 104, the gate insulating film 105, and the high-concentration impurity diffusion layer 108c, and the vertical axis indicates the energy level. In the case of FIG. 4A, the band bending amount 401a is smaller than the band gap. For this reason, in the high concentration impurity diffusion layer 108c, a sufficient tunnel length cannot be obtained, and the generation of the interband tunnel current is suppressed.

  FIG. 4B shows a band bending amount 401b and a tunnel length 402b in the intermediate concentration impurity diffusion layer 108b when the gate voltage is applied in the negative direction with respect to the drain voltage in the semiconductor device according to the first embodiment of the present invention. It is an energy band figure showing the relationship with. In FIG. 4B, the horizontal axis indicates the space extending from the left to the right across the gate electrode 104, the gate insulating film 105, and the medium concentration impurity diffusion layer 108b, and the vertical axis indicates the energy level. In the case of FIG. 4B, since the band bending amount 401b is larger than the band gap, a tunnel effect by electrons from the valence band at the interface of the gate insulating film 105 to the back valence band is obtained. In particular, in the case of FIG. 4B, since the tunnel length 402b is short, a large tunnel current can be obtained.

  FIG. 4C shows a band bending amount 401c, a tunnel length, and a tunnel length in the low-concentration impurity diffusion layer 108a when the gate voltage is applied in the negative direction with respect to the drain voltage in the semiconductor device according to the first embodiment of the present invention. It is an energy band figure showing these relationships. In FIG. 4C, the horizontal axis indicates the space extending from the left to the right, the gate electrode 104, the gate insulating film 105, and the low-concentration impurity diffusion layer 108a, and the vertical axis indicates the energy level. In the case of FIG. 4C, although the band bending amount 401c is larger than the band gap, since the tunnel length 402c is relatively long and the probability of occurrence of the tunnel effect is low, only a relatively small tunnel current can be obtained.

  On the other hand, the region in contact with the P-type body 103 is the low-concentration impurity diffusion layer 107a in the source diffusion layer 107 and the low-concentration impurity diffusion layer 108a in the drain diffusion layer 108. In either case, the electric field is reduced. Yes. Therefore, in the semiconductor device according to the present embodiment, the PN junction leakage current when holding the “0” state is suppressed, and as a result, the retention time can be improved.

(Second Embodiment)
FIG. 5 is a cross-sectional view showing the configuration of the semiconductor device according to the second embodiment of the present invention. The semiconductor device according to the present embodiment is equivalent to the semiconductor device according to the first embodiment of the present invention with the following changes added as variations of the source diffusion layer 107.

  That is, the low concentration impurity diffusion layer 107a is removed from the source diffusion layer 107 according to the first embodiment of the present invention, and the remaining high concentration impurity diffusion layer 107b is used as the source diffusion layer 207 according to the present embodiment. With this change, the volume of the P-type body 203 according to the present embodiment is the sum of the volume of the P-type body 103 according to the first embodiment of the present invention and the volume of the low-concentration impurity diffusion layer 107a. .

  Since the other configuration of the semiconductor device according to the present embodiment is the same as that of the first embodiment of the present invention, further detailed description is omitted.

The operation of the semiconductor device according to the present embodiment will be described in comparison with the case of the first embodiment of the present invention.
In the first embodiment of the present invention, as described above, the impurity concentration in the portion of the source diffusion layer 107 adjacent to the P-type body 103, that is, the low concentration impurity diffusion layer 107a is reduced. By doing so, the depletion layer of the N-type layer is extended and the electric field is lowered. On the other hand, in this embodiment, the source diffusion layer 207, that is, the high concentration impurity diffusion layer 107b is offset from the body. Although the potential of the region under the gate electrode of the P-type body 203 is modulated by the gate electrode, the electric field can be reduced by spreading the depletion layer in the offset region. Therefore, also in the semiconductor device according to the present embodiment, as in the case of the first embodiment of the present invention, the leakage current at the PN junction is reduced, and the length of time that the P-type body holds the state “0”. Can be improved.

  Since other operations of the semiconductor device according to the present embodiment are the same as those of the first embodiment of the present invention, further detailed description is omitted.

(Third embodiment)
FIG. 6 is a cross-sectional view showing the configuration of the semiconductor device according to the third embodiment of the present invention. The semiconductor device according to the present embodiment is equivalent to the semiconductor device according to the second embodiment of the present invention with the following modifications added as variations of the drain diffusion layer 108.

  That is, in the drain diffusion layer 308 according to the second embodiment of the present invention, a portion of the drain diffusion layer 108 obtained by removing the portion of the medium concentration impurity diffusion layer 108b adjacent to the buried oxide film 102 in the drain diffusion layer 308 according to the present embodiment. The intermediate concentration impurity diffusion layer 308b is used. Along with this change, the volume of the low concentration impurity diffusion layer 308a in the drain diffusion layer 308 according to the present embodiment is the same as the volume of the low concentration impurity diffusion layer 108a according to the second embodiment of the present invention. The volume of the removed portion of the layer 108b is combined.

  Since the other configuration of the semiconductor device according to the present embodiment is the same as that of the second embodiment of the present invention, further detailed description is omitted.

  The operation of the semiconductor device according to the present embodiment will be described in comparison with the case of the second embodiment of the present invention. In the second embodiment of the present invention, the medium concentration impurity diffusion layer 108b in the drain diffusion layer 108 is formed over the entire vertical direction of the source / drain diffusion layer. In contrast, in the present embodiment, the medium concentration impurity diffusion layer 308b in the drain diffusion layer 308 is formed on the gate electrode 104 side. In the semiconductor device according to the present invention, the intermediate-concentration impurity diffusion layers 108b and 308b play a role of increasing the band-to-band tunnel current near the interface with the gate insulating film 105. Therefore, if the medium concentration impurity diffusion layer 308b in the drain diffusion layer 308 according to the present embodiment is formed at least in the region where the bending of the band exists, at least in the vicinity of the gate insulating film 105, the above-described role can be sufficiently achieved. Is possible.

  Since other operations of the semiconductor device according to the present embodiment are the same as those of the second embodiment of the present invention, further detailed description is omitted.

(Fourth embodiment)
FIG. 7A is an overhead view showing the configuration of the semiconductor device according to the fourth embodiment of the present invention. FIG. 7B is a cross-sectional view of the semiconductor device of FIG. 7A along the cutting line AA ′. FIG. 7C is a cross-sectional view of the semiconductor device of FIG. 7A along the cutting line BB ′. The semiconductor device according to the present embodiment is the same as the semiconductor device according to the third embodiment of the present invention, with the following modifications as variations in the drain diffusion layer 308, the gate electrode 104, the gate insulating film 105, and the substrate layer. Is equal to

  That is, first, regarding the gate electrode 104, the gate insulating film 105, and the sidewall insulating film 106 according to the third embodiment of the present invention, the gate electrode 404 whose shape is changed to a so-called fin structure, the gate insulating film 405, Then, the sidewall insulating film 406 is replaced. Here, the fin structure refers to a fin upper surface portion formed in a plane perpendicular to the first direction in which a substrate layer, a source / drain diffusion layer, and a gate layer are stacked, a fin side surface portion, and a fin upper portion. And the connection part which connects a fin side part is added. The fin side surface portion is formed in parallel to a plane including the first direction and the second direction in which the source diffusion layer 407, the P-type body 403, and the drain diffusion layer 408 are arranged side by side. The fin side surface portion is adjacent to the substrate layer in the first direction. Further, the fin side surface portion of the gate insulating film 405 is adjacent to the P-type body 403 in a third direction orthogonal to both the first direction and the second direction.

  Next, in the drain diffusion layer 308 according to the third embodiment of the present invention, a portion of the low concentration impurity diffusion layer 308a adjacent to the substrate layer is replaced with a low concentration impurity diffusion layer 408b. In other words, the low-concentration impurity diffusion layer 408 a of the drain diffusion layer 408 is insulated from the substrate layer by the P-type body 403. The medium concentration impurity diffusion layer 308b of the drain diffusion layer is insulated from the P-type body 403 by the low concentration impurity diffusion layer 408a of the drain diffusion layer 408, as in the case of the third embodiment of the present invention. As a result, the low-concentration impurity diffusion layer 408a and the medium-concentration impurity diffusion layer 308b in the drain diffusion layer 408 are adjacent to the upper region of the fin side surface portion of the gate insulating film 405 near the connection portion in the third direction. ing.

  Further, in the semiconductor device according to the present embodiment, the buried oxide film 102 can be omitted. In this case, the substrate layer functions as a bulk substrate. At this time, the P-type body 403 is adjacent to the silicon substrate 101 on the lower surface thereof. 7A to 7C show a case where the substrate layer is a bulk substrate in which the buried oxide film 102 is omitted and only the silicon substrate 101 remains. However, in this embodiment as well, as in the first to third embodiments of the present invention, the substrate layer may be an SOI substrate in which the buried oxide film 102 is stacked on the silicon substrate 101.

  The operation of the semiconductor device according to the present embodiment will be explained. Since the middle-concentration impurity diffusion layer 408b of the drain diffusion layer 408 overlaps with the gate electrode 404, an interband tunnel current is generated. The generation of the interband tunnel current is limited to the upper surface portion of the fin and the upper portion of the side surface portion of the fin. Here, the regions other than the above that overlap with the gate electrode 404 are only the low-concentration impurity diffusion layer 408 a of the drain diffusion layer 408 and the P-type body 403. Therefore, for the same reason as the source diffusion layers 107 and 207 described in the first to third embodiments of the present invention, the semiconductor device according to the present embodiment having the high-concentration impurity diffusion layer 407b as the source diffusion layer 407 is also “ Leakage current generated when holding the “0” state is suppressed. As a result, the retention time can be improved also in this embodiment. It is obvious that the same effect can be obtained even with a planar MOSFET having the cross section of FIG. 7B.

  As described above, in any of the first to fourth embodiments, the semiconductor device according to the present invention can simultaneously increase the GIDL current, suppress the leakage current, and increase the data retention time. Here, the various configurations in the first to fourth embodiments can be freely combined as long as no technical contradiction arises. Specifically, all of the three types of source diffusion layers described in the first and second embodiments and the three types of drain diffusion layers described in the first to third embodiments can be combined. is there. Further, these combinations can be combined with the fin structure described in the fourth embodiment.

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Embedded oxide film 3 P-type body 4 Gate electrode 5 Gate insulating film 6 Side wall insulating film 7 Source diffusion layer 7a Low concentration impurity diffusion layer (source diffusion layer)
7b (first) high concentration impurity diffusion layer (source diffusion layer)
7c (second) high-concentration impurity diffusion layer (source diffusion layer)
8 Drain diffusion layer 8a Low-concentration impurity diffusion layer (drain diffusion layer)
8b (first) high concentration impurity diffusion layer (drain diffusion layer)
8c (Second) high concentration impurity diffusion layer (drain diffusion layer)
DESCRIPTION OF SYMBOLS 101 Silicon substrate 102 Embedded oxide film 103 P-type body 104 Gate electrode 105 Gate insulating film 106 Side wall insulating film 107 Source diffusion layer 107a Low concentration impurity diffusion layer (source diffusion layer)
107b High concentration impurity diffusion layer (source diffusion layer)
108 Drain diffusion layer 108a Low-concentration impurity diffusion layer (drain diffusion layer)
108b Medium-concentration impurity diffusion layer (drain diffusion layer)
108c High concentration impurity diffusion layer (drain diffusion layer)
203 P-type body 207 Source diffusion layer 308 Drain diffusion layer 308a Low-concentration impurity diffusion layer (drain diffusion layer)
308b Medium concentration impurity diffusion layer (drain diffusion layer)
401a Band bending amount 401b Band bending amount 401c Band bending amount 402b Tunnel length 402c Tunnel length 403 P-type body 404 Gate electrode 405 Gate insulating film 406 Side wall insulating film 407 Source diffusion layer 407b High concentration impurity diffusion layer (source diffusion layer)
408 Drain diffusion layer 408a Low-concentration impurity diffusion layer (drain diffusion layer)
408c High concentration impurity diffusion layer (drain diffusion layer)

Claims (8)

A silicon substrate;
MOSFET (Metal Oxide Semiconductor Field Effect Transistor) formed on the silicon substrate,
The MOSFET is
A source / drain diffusion layer;
A gate insulating film stacked on the source / drain diffusion layer;
A gate electrode laminated on the gate insulating film,
The source / drain diffusion layer comprises:
A body part formed in a lower region of the gate insulating film;
A first drain diffusion layer formed in a region adjacent to the body portion and overlapping the gate insulating film and doped with an impurity of one polarity at a first concentration;
A second drain diffusion layer formed in a region offset from the gate insulating film and doped with the one polarity impurity at a second concentration;
Formed in a region adjacent to the first drain diffusion layer and the second drain diffusion layer and overlapping the gate insulating film, wherein the one polarity impurity is doped at a third concentration A third drain diffusion layer,
The third concentration is included in a range where a tunnel effect occurs in the gate insulating film,
The first concentration is included in a range where the tunnel concentration is lower than the third concentration and the tunnel effect occurs less in the gate insulating film than in the third concentration;
The second concentration is higher than the first concentration and is included in a range in which a tunnel effect is suppressed in the gate insulating film. The semiconductor device according to claim 1,
Further comprising a buried oxide film stacked between the silicon substrate and the MOSFET;
The buried oxide film is adjacent to each of the first, second and third drain diffusion layers. Semiconductor device. The semiconductor device according to claim 1,
Further comprising a buried oxide film stacked between the silicon substrate and the MOSFET;
The buried oxide film is adjacent to each of the first and second drain diffusion layers;
The third drain diffusion layer is insulated from the buried oxide film by the first drain diffusion layer. The semiconductor device according to claim 1,
The third drain diffusion layer is insulated from the body by the first drain diffusion layer;
The first drain diffusion layer is insulated from the silicon substrate by the body. The semiconductor device according to claim 4,
The gate insulating film is
Also in the third direction orthogonal to the first direction in which the silicon substrate and the body are stacked and the second direction in which the body and the second drain diffusion layer are arranged, the body, the first Having a fin shape adjacent to the drain diffusion layer and the third diffusion layer,
The gate electrode is
A semiconductor device having a fin shape adjacent to the gate insulating film also in the third direction. In the semiconductor device according to claim 1,
The source / drain diffusion layer comprises:
A semiconductor device further comprising a source diffusion layer formed in a region adjacent to the body portion and offset from the gate insulating film and doped with the one polarity impurity at the second concentration. In the semiconductor device according to claim 1,
The source / drain diffusion layer comprises:
A first source diffusion layer formed in a region offset from the gate insulating film and doped with the one polarity impurity at the second concentration;
A second region formed adjacent to the body portion and the first source diffusion layer and overlapping with the gate insulating film and doped with the one polarity impurity at the first concentration A semiconductor device further comprising a source diffusion layer. In the semiconductor device according to claim 1,
The source / drain diffusion layer comprises:
A first source diffusion layer formed in a region offset from the gate insulating film and doped with the one polarity impurity at the second concentration;
A second source diffusion layer doped with the first concentration in a region adjacent to the body portion and overlapping the gate insulating film;
Formed in a region adjacent to the first source diffusion layer and the second source diffusion layer and overlapping the gate insulating film, and the impurity of one polarity is doped at the third concentration And a third source diffusion layer.

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