JP2013026367A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device including an interconnection consisting of an underlying metal layer and an upper metal layer on an insulating film, in which deterioration of adhesion between the insulating film and the upper metal layer due to side etching of the underlying metal layer can be minimized, and to provide a manufacturing method therefor.SOLUTION: In the upper surface of an insulating film 14 on which an interconnection body 16 is formed, a recess 14a corresponding to the pattern of the interconnection body 16 and having a predetermined depth from the upper surface of the insulating film 14 is provided. On the upper surface of the insulating film 14 including the recess 14a, the interconnection body 16 is provided via a titanium thin film 15 that is a part of the interconnection, and an adhesion layer. The recess 14a has a width which is set narrower than that of the interconnection body 16. The titanium thin film 15 is formed narrower than the width of the interconnection body 16.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  In recent years, portable electronic devices such as cellular phones, portable information terminals, digital cameras, and multimedia players have been widely used. In portable electronic devices, market demands for miniaturization and higher functionality are high, and high-density mounting technology for semiconductor devices mounted on electronic devices plays an important role in order to meet such demands.

  Conventionally, as a semiconductor device using a high-density mounting technology, a chip size package (hereinafter referred to as “CSP”) that can bring the size of the semiconductor device close to the external dimensions of the individual semiconductor chips. A semiconductor device having a package structure called “abbreviated”) is known. In recent years, as one form of the CSP, a wafer level CSP (or WLP; Wafer) which is completed by forming a sealing layer while maintaining the size of the semiconductor wafer and then singulating into individual CSPs. A semiconductor device called “Level Package” (hereinafter simply abbreviated as “semiconductor device”) has been put into practical use.

  In this semiconductor device, desired semiconductor elements and integrated circuits are formed on one side (hereinafter referred to as an upper surface) side of a semiconductor substrate, and an insulating film is provided on the upper surface side so as to cover these semiconductor elements and the like. ing. A rewiring is further provided on the insulating film. The rewiring is connected to a connection pad of a semiconductor element or the like formed on the upper surface of the semiconductor substrate through an opening provided on one side of the insulating film, and the other side has an arbitrary wiring pattern on the insulating film. It is formed to extend. A protective insulating film is further provided on the upper surface side of the semiconductor substrate including the rewiring and the insulating film. Here, the protective insulating film is provided with an opening through which the land on the other end of the rewiring is exposed, and a solder ball or a protruding electrode (solder bump) as an external connection electrode is provided through the opening. It is connected.

  Such a semiconductor device is generally manufactured as follows. First, a semiconductor wafer is prepared in which semiconductor elements and integrated circuits are formed in each of a plurality of semiconductor device formation regions partitioned on the upper surface of a semiconductor substrate. The semiconductor wafer is subjected to a wiring forming process including insulating film formation and rewiring process. Next, after each process of forming a protective insulating film and forming an external connection electrode in the state of a semiconductor wafer, the semiconductor device is completed by dicing and cutting out as individual semiconductor chips.

  According to such a semiconductor device, it is possible to achieve a reduction in size and performance, an increase in packaging density, and an increase in manufacturing process efficiency. For example, Patent Documents 1 and 2 describe a semiconductor device having a wafer level CSP type package structure as described above and a manufacturing method thereof.

JP 2009-246218 A JP 2011-114133 A

  In the semiconductor device as described above, an insulating film is formed on a semiconductor substrate surface on which a semiconductor element or the like is formed, and a rewiring is formed on the insulating film, thereby being connected to one end side of the rewiring. A connection pad such as a semiconductor element is electrically connected to an external connection electrode connected to the land on the other end side. Here, in Patent Documents 1 and 2 described above, as a wiring structure for rewiring, a plated wiring layer made of copper (Cu) or the like is laminated on a base metal layer for plating made of titanium (Ti) or the like. A configuration is disclosed. The metal layer for plating serves as a seed layer when the plated wiring layer is formed by electrolytic plating, and has an effect of improving the adhesion between the lower insulating film and the upper plated wiring layer. .

  A rewiring having such a wiring structure is generally manufactured as follows. First, after forming an insulating film having an opening on a semiconductor substrate, a base metal layer for plating such as titanium is formed so as to cover the entire surface of the semiconductor substrate. Next, after forming a photoresist having an opening corresponding to a predetermined wiring pattern on the base metal layer for plating, by performing electroplating, only on the plated metal layer exposed in the opening, copper or the like A plated wiring layer is formed. Next, after removing the photoresist, by using the plated wiring layer formed in a predetermined pattern shape as a mask and etching the underlying metal layer for plating, the underlying metal layer for plating only under the plated wiring layer Thus, a rewiring having a laminated structure in which is left is formed.

  However, as shown in the manufacturing method described above, in the step of etching the underlying metal layer for plating using the plated wiring layer formed in a predetermined pattern shape as a mask, the end of the wiring pattern of the plated wiring layer Side etching may occur in which the underlying metal layer for plating just below the portion is removed by etching. In this case, the base metal layer for plating does not exist in the vicinity of the end of the wiring pattern of the plated wiring layer, so that the adhesion width between the lower insulating film and the upper plated wiring layer by the base metal layer for plating is narrowed. As a result, there is a problem that the adhesiveness is deteriorated and the manufacturing yield and reliability of the semiconductor device are lowered. In particular, the side etching of the base metal layer for plating has a substantially constant etching amount depending on the material of the base metal layer for plating and the etching conditions, so that the semiconductor device can be miniaturized and highly integrated. As the wiring pattern of the rewiring becomes finer, the ratio of the etching amount increases relatively, the contact width between the lower insulating film and the upper plated wiring layer becomes narrower, and the adhesiveness deteriorates significantly. Have the problem of

  Therefore, in view of the above-described problems, the present invention suppresses deterioration in adhesion between an insulating film and an upper metal layer in a semiconductor device including a wiring made of a base metal layer and an upper metal layer on the insulating film. It is an object of the present invention to provide a semiconductor device that can perform the same and a manufacturing method thereof.

A semiconductor device according to the present invention includes:
A semiconductor substrate having connection pads on one side;
An opening provided on the semiconductor substrate and exposing a part of the connection pad; an insulating film having a recess on an upper surface;
An adhesion layer provided on the insulating film in the recess;
A wiring layer provided on the adhesion layer;
It is characterized by having.

In addition, a method for manufacturing a semiconductor device according to the present invention includes:
Prepare a semiconductor substrate provided with an insulating film so as to cover the connection pad provided on one side,
In the insulating film, an opening that exposes one side of the connection pad is formed, and a recess is formed in a part of the upper surface of the insulating film.
Forming a base metal layer including an adhesion layer on the upper surface of the insulating film in which the recess and the recess are formed;
An upper metal layer having a predetermined pattern is formed in a region including the inside of the recess on the upper surface side of the base metal layer.

  According to the semiconductor device and the method for manufacturing the same according to the present invention, in the semiconductor device having the wiring composed of the base metal layer and the upper metal layer on the insulating film, the insulating film and the upper metal layer formed by side etching of the base metal layer It is possible to provide a wiring structure with high manufacturing yield and high reliability by suppressing deterioration of adhesion.

1 is a schematic plan view showing an embodiment of a semiconductor device according to the present invention. It is a schematic sectional drawing of the semiconductor device which concerns on this embodiment. It is process sectional drawing (the 1) which shows an example of the manufacturing method of the semiconductor device which concerns on this embodiment. It is process sectional drawing (the 2) which shows an example of the manufacturing method of the semiconductor device which concerns on this embodiment. It is process sectional drawing (the 3) which shows an example of the manufacturing method of the semiconductor device which concerns on this embodiment. It is process sectional drawing (the 4) which shows an example of the manufacturing method of the semiconductor device which concerns on this embodiment. It is process sectional drawing (the 5) which shows an example of the manufacturing method of the semiconductor device which concerns on this embodiment. It is a schematic process figure which shows the comparative example of the semiconductor device which concerns on this embodiment. FIG. 6 is a schematic process diagram compared with a comparative example in order to explain the operation effect of the semiconductor device according to the embodiment. It is a schematic sectional drawing for demonstrating the other effect of the semiconductor device which concerns on this embodiment. It is a schematic sectional drawing which shows the other structural example of the recessed part of the upper surface of the insulating film applied to the semiconductor device which concerns on this embodiment.

Hereinafter, a semiconductor device and a manufacturing method thereof according to the present invention will be described in detail with reference to embodiments.
First, a semiconductor device according to the present invention will be described. Here, a semiconductor device having a wafer level CSP type package structure is shown as an example.

(Semiconductor device)
FIG. 1 is a schematic plan view showing an embodiment of a semiconductor device according to the present invention, and FIG. 2 is a schematic cross-sectional view of the semiconductor device according to this embodiment. 2A is a IIA-IIA line in the semiconductor device shown in FIG. 1 (in this specification, “II” is conveniently used as a symbol corresponding to the Roman numeral “2” shown in FIG. 2 is a diagram showing a cross section taken along line IIB-IIB in the semiconductor device shown in FIG.

  In the semiconductor device 10 according to the present embodiment, for example, as shown in FIGS. 1, 2A, and 2B, an integrated circuit (not shown) having a predetermined function is provided on the upper surface 11a side (the surface of FIG. 1). A semiconductor substrate 11 made of silicon, GaAs, or the like is formed on the side or the upper surface side of FIG. 2A and FIG. Here, the integrated circuit is formed by a known element such as a transistor, a diode, a resistor, or a capacitor.

  As shown in FIGS. 1, 2A, and 2B, the upper surface 11a of the semiconductor substrate 11 is provided with a plurality of connection pads 12 made of an aluminum-based metal or the like connected to each element of the integrated circuit. ing. A passivation film 13 made of silicon oxide, silicon nitride, or the like is provided on the upper surface 11a of the semiconductor substrate 11. Here, for example, the passivation film 13 is formed in a rectangular shape or a square shape in the central portion excluding the peripheral portion of the upper surface 11 a of the semiconductor substrate 11. Further, the passivation film 13 is not formed on the peripheral portion of the upper surface 11a of the semiconductor substrate 11, and the upper surface 11a of the semiconductor substrate 11 is exposed in a substantially frame shape at the peripheral portion. The passivation film 13 is provided with a plurality of openings 13 h that expose, for example, the central portion of the upper surface of each connection pad 12.

  An insulating film 14 made of polyimide resin or the like is formed on the upper surface of the passivation film 13 when viewed from the normal direction with respect to the upper surface 11a of the semiconductor substrate 11, that is, when the semiconductor substrate 11 is viewed in plan view, for example, with the passivation film 13 They are provided so as to have substantially the same shape. An opening 14 h is provided in a portion of the insulating film 14 corresponding to the opening 13 h of the passivation film 13. That is, the upper surface of each connection pad 12 is exposed through the opening 13 h provided in the passivation film 13 and the opening 14 h provided in the insulating film 14. In the present embodiment, a configuration in which the plurality of connection pads 12 are arranged so as to form a substantially rectangular frame as a whole along the outer peripheral edge of the upper surface 11a of the semiconductor substrate 11 is shown. The arrangement of is not limited to this.

  Here, as shown in FIGS. 2A and 2B, the upper surface of the insulating film 14 is in a region corresponding to the pattern of the wiring main body 16 to be described later, from the upper surface of the insulating film 14 toward the semiconductor substrate 11. A concave recess 14a having a predetermined depth is provided. Specifically, the recess 14a has a depth of, for example, about 1/3 of the film thickness of the insulating film 14 from the upper surface of the insulating film 14, and is narrower than the wiring width of the wiring body 16 described later. And it is provided so as to continuously extend along the pattern of the wiring body 16.

  Further, as shown in FIGS. 2A and 2B, the upper surface of the insulating film 14 is a region corresponding to a pattern of the wiring body 16 described later and a region including the concave portion 14a. A thin film (hereinafter referred to as a titanium thin film) 15 such as titanium (Ti) which is a part of a metal layer (under bump metal; UBM) is provided. Specifically, the titanium thin film 15 is etched using the wiring main body 16 composed of the copper thin film 16-1 and the copper wiring layer 16-2 formed in the upper layer as a mask, as shown in a manufacturing method described later. It is formed by. At this time, since the titanium thin film 15 is side-etched, the region near the end of the wiring body 16 (side-etched portion 15x) is removed. For example, as shown in FIGS. The wiring body 16 is formed to be narrower than the wiring width. Here, the titanium thin film 15 has a function as an adhesion layer that enhances the adhesion between the lower insulating film 14 and the upper wiring body 16, and the copper thin film 16-1 constituting the wiring body 16 and Along with the copper wiring layer 16-2, it also functions as a part of the wiring (underlying metal layer).

  A wiring main body 16 is provided on the upper surface of the titanium thin film 15 on the insulating film 14 as shown in FIGS. 1, 2A, and 2B. The wiring body 16 is, for example, a thin film such as copper (Cu) (hereinafter referred to as a copper thin film) that forms a base metal layer together with the titanium thin film 15 described above, and an upper metal layer provided on the upper surface of the copper thin film. A wiring structure in which a wiring layer of copper or the like (hereinafter referred to as a copper wiring layer) is laminated can be applied. Specifically, as shown in a manufacturing method to be described later, the wiring body 16 performs electrolytic plating using the copper thin film formed on the titanium thin film 15 that is the adhesion layer described above as a seed layer, and is formed on the upper surface of the copper thin film. It is formed by growing a copper wiring layer which is an upper metal layer. At this time, since the metal layer composed of two layers of the copper thin film of the base metal layer and the copper wiring layer of the upper metal layer is formed so as to be integrated, in FIGS. Illustration is omitted.

  Here, one end portion 16 a of each wiring body 16 provided on the upper surface of the insulating film 14 is connected to each other through the titanium thin film 15 in the openings 14 h and 13 h provided in the insulating film 14 and the passivation film 13. It is connected to the pad 12. A land 16 b is formed at the other end of each wiring body 16. The one end portion 16a and the other end portion (land 16b) of each wiring body 16 are connected by a lead wire portion 16c formed integrally therewith.

  Further, as shown in FIGS. 2A and 2B, a protective insulating film 17 made of a thermosetting epoxy resin or the like is provided on each upper surface of the wiring body 16, the insulating film 14, and the semiconductor substrate 11. Yes. The protective insulating film 17 is provided with a plurality of openings 17 h that expose the upper surface of the land 16 b of each wiring body 16. On the upper surface of the protective insulating film 17, there are provided solder balls 18 for external connection connected to the lands 16b exposed through the openings 17h.

  As described above, in the semiconductor device 10 according to the present embodiment, the upper surface of the insulating film 14 in the region corresponding to the pattern of the wiring body 16 is provided with the recess 14a having a predetermined depth from the upper surface of the insulating film 14. A wiring body 16 is provided on the upper surface of the insulating film 14 including the recess 14a via a titanium thin film 15 which is a part of the wiring and is an adhesion layer. Thereby, even if the titanium thin film 15 is formed by side etching so as to be narrower than the wiring width of the wiring main body 16, it is insulated from the wiring main body 16 via the titanium thin film 15 by the recess 14 a on the upper surface of the insulating film 14. It is possible to ensure a sufficiently large area where the film 14 is in close contact. In other words, even when the wiring is miniaturized as the semiconductor device is miniaturized and highly integrated, a sufficient contact area is ensured by the titanium layer interposed between the wiring and the insulating film. Means that you can. Therefore, according to the present embodiment, it is possible to provide a highly reliable semiconductor device by improving the adhesion between the wiring body 16 and the insulating film 14.

  In the present embodiment, a concave recess 14 a is provided on the upper surface of the insulating film 14, and a wiring body 16 is provided in a region including the recess 14 a via a titanium thin film 15. Thereby, even if it is a case where the film thickness of the wiring main body 16 is thickened, the height from the upper surface 11a of the semiconductor substrate 11 to the upper surface of the wiring main body 16 can be suppressed. Therefore, even when the protective insulating film 17 or the like is formed on the semiconductor substrate 11 on which the wiring body 16 is formed, a highly reliable semiconductor in which bubbles are difficult to enter between the insulating film 14 and the protective insulating film 17. An apparatus can be provided.

(Method for manufacturing semiconductor device)
Next, a method for manufacturing the semiconductor device according to the present embodiment will be described.
3 to 7 are process cross-sectional views illustrating an example of a semiconductor device manufacturing method according to the present embodiment. Here, a manufacturing method for the semiconductor device having the cross-sectional structure shown in FIG.

  In the method of manufacturing the semiconductor device 10 described above, first, as shown in FIG. 3A, an integrated circuit whose illustration is omitted on an upper surface 21a of a silicon substrate in a wafer state (hereinafter referred to as a semiconductor wafer 21; semiconductor substrate). In addition, a device in which connection pads 12 made of aluminum light metal or the like connected to the integrated circuit are formed is prepared in advance. Here, on the upper surface 21 a of the semiconductor wafer 21, a passivation film 13 made of silicon oxide or the like and a photosensitive insulating film 14 made of polyimide resin or the like are laminated so as to cover the integrated circuit and the connection pads 12. ing.

  Next, as shown in FIGS. 3B and 4A, an opening 13h in which, for example, the central portion of the upper surface of the connection pad 12 is exposed to the passivation film 13 and the insulating film 14 by using a photolithography method. , 14h are formed at the same time, and a concave recess 14a corresponding to the pattern of the wiring body 16 and having a predetermined depth is formed on the upper surface of the insulating film 14. Specifically, as shown in FIG. 3B, at least in a region corresponding to the positions where the openings 13h and 14h are formed, light (exposure light) 40 from the light source of the exposure apparatus has a high ratio (transmittance). ), And the region corresponding to the position where the recess 14a is formed is exposed when the transmission ratio of the exposure light 40 in the transmission portion 32 is 1. For example, it has a 1/3 transmission part (second transmission part) 33 that transmits light 40 at a ratio of 1/3 (or a 2/3 light shielding part that blocks exposure light 40 at a ratio of 2/3, for example). In the region where the passivation film 13 and the insulating film 14 remain, an exposure mask (reticle) 40 having a light shielding portion 31 that blocks the exposure light 40 is prepared.

  By using such a mask 30 in the exposure process of the photolithography method, as shown in FIG. 3B, the transmissive part 32 has a high light energy that approximates the exposure light 40 with respect to the exposure light 40, for example. The transmitted light 41 is irradiated to the insulating film 14 and the passivation film 13, and the transmitted light 42 having a light energy of 1/3 of the exposure light 40 is irradiated to the insulating film 14 and the passivation film 13 in the 1/3 transmitting portion 33. The Since the photosensitive depth of the insulating film 14 and the passivation film 13 is different depending on the light energy in the exposure process, the insulating film 14 and the passivation film are formed in a region corresponding to the transmission part 32 of the mask 30 in the developing process. 13 is completely removed to form openings 13h and 14h in which the upper surface of the underlying connection pad 12 is exposed. At the same time, in the region corresponding to the 1/3 transmission portion 33 of the mask 30, the upper surface of the insulating film 14 is formed. Thus, a recess 14a from which only about 1/3 of the film thickness is removed is formed.

  In the step of forming the openings 13h and 14h and the recess 14a, the insulating film 14 and the passivation film in the dicing street 22 when the semiconductor wafer 21 is divided into individual semiconductor devices 10 and the adjacent regions on both sides thereof are formed. At the same time, the film 13 is completely removed, and as shown in FIG. 4A, the upper surface 21a of the semiconductor wafer 21 in the region is exposed. Then, the insulating film 14 and the passivation film 13 in which the openings 13h and 14h and the recess 14a are formed are baked and solidified.

  Next, as shown in FIGS. 4B and 4C, the connection pad 12 exposed through the entire upper surface side of the semiconductor wafer 21, that is, through the openings 13 h and 14 h of the passivation film 13 and the insulating film 14. On the upper surface 21a, the upper surface of the insulating film 14, and the upper surface 21a of the semiconductor wafer 21 corresponding to the dicing street 22 and the adjacent regions on both sides thereof, the titanium thin film 15 constituting the base metal layer, and the copper thin film 16-1. Form. Here, the titanium thin film 15 and the copper thin film 16-1 are formed using, for example, a sputtering method.

  Next, as shown in FIG. 5A, a plating resist film 23 made of a positive liquid resist is patterned on the upper surface of the copper thin film 16-1. Here, an opening 23h is formed in a portion of the plating resist film 23 corresponding to a formation region of a copper wiring layer 16-2 described later. Next, as shown in FIG. 5B, by performing copper electroplating using the copper thin film 16-1 as a plating current path, the upper surface of the copper thin film 16-1 in the opening 23h of the plating resist film 23 is formed. Copper wiring layer 16-2 is formed. Thereafter, the plating resist film 23 is peeled off from the upper surface of the copper thin film 16-1.

  Next, as shown in FIG. 6A, using the copper wiring layer 16-2 as an etching mask, a region where the copper wiring layer 16-2 is not formed (that is, covered with the copper wiring layer 16-2). The copper thin film 16-1 in the exposed region) is removed by etching, so that the copper thin film 16-1 remains only directly under the copper wiring layer 16-2. As a result, the copper wiring layer 16-2 and the copper thin film 16-1 remaining immediately below the copper wiring layer 16-2 are integrally formed as the wiring body 16.

  Next, as shown in FIG. 6B, using the wiring main body 16 as an etching mask, titanium in a region where the wiring main body 16 is not formed (that is, a region exposed without being covered by the wiring main body 16). By removing the thin film 15 by wet etching, the titanium thin film 15 remains only directly under the wiring body 16. Thereby, the structure which the wiring main body 16 contact | adhered to the upper surface of the insulating film 14 through the titanium thin film 15 which is an adhesion layer is obtained. Further, the titanium thin film 15 together with the wiring body 16 constitutes a part of the wiring. Here, in the step of etching the titanium thin film 15, it is completely removed so that the residue of the titanium thin film 15 does not exist on the insulating film 14 or the semiconductor wafer 21 by performing a process like over-etching. As a result, residues of the titanium thin film 15 remaining on the insulating film 14 and the semiconductor wafer 21 are removed to prevent conduction failure such as a short circuit between wirings, and a protective insulating film 17, the insulating film 14, and the semiconductor wafer described later. Adhesion with 21 can be improved. At this time, when the titanium thin film 15 is over-etched, side etching in which the titanium thin film 15 is removed in a region near the end of the wiring body 16 (side etching portion 15x) is performed as shown in FIG. Arise.

  Next, as shown in FIG. 7A, the entire region on the upper surface side of the semiconductor wafer 21, that is, the upper surface of the wiring body 16, the upper surface of the insulating film 14, and the portions corresponding to the dicing street 22 and the neighboring regions on both sides thereof. A protective insulating film 17 made of a thermosetting epoxy resin or the like is formed on the upper surface 21 a of the semiconductor wafer 21. Here, the protective insulating film 17 is formed with an opening 17 h through which the land 16 b of the wiring body 16 is exposed.

  7A, solder balls 18 for external connection are formed so as to be connected to the lands 16b of the wiring body 16 through the openings 17h formed in the protective insulating film 17. . Although the case where the solder balls 18 are formed has been described here, a protruding electrode pad is formed by solder printing as applied to a land grid array (LGA) type package. There may be.

  Next, as shown in FIG. 7B, the semiconductor wafer 21 on which the protective insulating film 17 and the solder balls 18 are formed is cut along the dicing street 22 into individual pieces, so that FIGS. A plurality of semiconductor devices 10 shown in (a) and (b) are obtained.

  In such a manufacturing method of the semiconductor device 10, the openings 14 h and 13 h exposing the upper surfaces of the connection pads 12 covered with the insulating film 14 and the passivation film 13, and the pattern of the wiring body 16 on the upper surface of the insulating film 14. And a concave recess 14a having a predetermined depth can be formed by the same process. Therefore, it is possible to provide a highly reliable semiconductor device by improving the adhesion between the wiring body 16 and the insulating film 14 without increasing or changing the manufacturing process.

  Next, operational effects of the semiconductor device and the manufacturing method thereof according to the above-described embodiment will be described in detail with reference to a wiring structure to be compared (hereinafter referred to as a comparative example). Here, as a comparative example of the semiconductor device described in the above-described embodiment, a configuration in which wiring is directly provided on the upper surface of an insulating film formed on a silicon substrate without providing a concave portion which is a feature of the present invention. Show.

  FIG. 8 is a schematic process diagram showing a comparative example of the semiconductor device according to the present embodiment, and FIG. 9 is a schematic process diagram compared with the comparative example in order to explain the operation effect of the semiconductor device according to the present embodiment. It is. Here, FIGS. 8A and 8C are schematic plan views of the wiring manufacturing process in the comparative example, and FIGS. 8B and 8D are FIGS. 8A and 8C, respectively. Sections along line VIIIB-VIIIB and line VIIID-VIIID (in this specification, “VIII” is used as a symbol corresponding to the Roman numeral “8” shown in FIG. 8 for convenience). FIG. FIGS. 9A and 9C are schematic plan views of the wiring manufacturing process according to this embodiment. FIGS. 9B and 9D are FIGS. 9A and 9C, respectively. It is a figure which shows the cross section along the IXB-IXB line | wire and IXD-IXD line | wire which were shown in FIG. FIG. 10 is a schematic cross-sectional view for explaining another function and effect of the semiconductor device according to the present embodiment. Here, in order to simplify the comparison with the semiconductor device according to the present embodiment, the same components are denoted by the same reference numerals.

First, a comparative example will be described.
As shown in FIGS. 8A and 8B, the wiring manufacturing process in the comparative example of the present embodiment is such that the upper surface of the semiconductor wafer 21 is covered with the connection pads 12 as shown in FIGS. A substantially flat passivation film 13 and an insulating film 14 are sequentially stacked, and a semiconductor in a region including the openings 13 h and 14 h where the upper surface of the connection pad 12 is exposed and the dicing street 22 are exposed on the passivation film 13 and the insulating film 14. An opening through which the upper surface 21a of the wafer 21 is exposed is formed.

  Next, a titanium thin film 15 and a copper thin film 16-1 are formed on the upper surface of the semiconductor wafer 21 on which the passivation film 13 having the openings 13 h and 14 h and the insulating film 14 are formed. Here, the titanium thin film 15 and the copper thin film 16-1 are connected to each connection pad 12 through the openings 13h and 14h. Next, a copper wiring layer 16-2, which is an upper metal layer having a predetermined pattern, is formed on the upper surface of the copper thin film 16-1 by electrolytic plating, and the copper wiring layer 16-2 is used as a mask. By sequentially etching the copper thin film 16-1 and the titanium thin film 15 in the exposed region that is not covered with 2, the titanium thin film is formed on the upper surface of the insulating film 14 as shown in FIGS. 15, a configuration in which the wiring body 16 including the copper thin film 16-1 and the copper wiring layer 16-2 is formed is obtained. The copper thin film 16-1 and the copper wiring layer 16-2 are integrally formed.

  Here, as described above, the side etching amount when the titanium thin film 15 is removed in an over-etched manner as described above will be examined in detail using the wiring main body 16 including the copper wiring layer 16-2 and the copper thin film 16-1 as a mask. For example, by setting the film thickness of the titanium thin film 15 to 180 nm and applying predetermined etching conditions, as shown in FIG. 8D, side etching leads from the end of the wiring body 16 to the lower part of the wiring body 16. The dimension of the titanium thin film 15 to be removed (that is, the dimension of the side etching portion 15x; the amount of side etching) is set to 2 μm. Here, since the side etching amount of the titanium thin film 15 depends on the film thickness, material, etching conditions and the like of the titanium thin film 15, it is known that the side etching amount becomes a substantially constant value regardless of the width of the wiring body 16. . Since the side etching on the titanium thin film 15 occurs in the vicinity of the end of the entire periphery of the pattern of the wiring main body 16, as shown in FIG. The dimensions are approximately (2 × 2 =) 4 μm in the vicinity of the left and right ends of the wiring body 16. From this, for example, in the case of the wiring body 16 having a wiring width of 15 μm, the remaining dimension of the titanium thin film 15 is calculated as (15−2 × 2 =) 11 μm. Therefore, the wiring main body 16 and the insulating film 14 are in close contact with each other through the titanium thin film 15 in a region of 2/3 or more of the width (15 μm) of the wiring main body 16, and mutual adhesion is generally ensured.

  However, in the future, when the wiring is further miniaturized as the semiconductor device is miniaturized and highly integrated, for example, when the wiring width of the wiring body 16 is 10 μm or less, side etching having the same dimensions as described above is performed. As a result, the remaining dimension of the titanium thin film 15 is calculated as, for example, (10−2 × 2 =) 6 μm. This remaining dimension is 2/3 or less of the width (10 μm) of the wiring body 16, the adhesion area by the titanium thin film 15 interposed between the wiring body 16 and the insulating film 14 is reduced, and the mutual adhesion is impaired. Have the problem of being

  Further, since the wiring main body 16 is formed on the insulating film 14 having a flat upper surface via the titanium thin film 15, the upper surface of the semiconductor substrate 11 is increased when the wiring main body 16 is thickened. The height from 11a to the upper surface of the wiring body 16 increases. For this reason, when the protective insulating film 17 or the like is formed on the semiconductor substrate 11 on which the wiring body 16 is formed, there is a problem that bubbles easily enter between the insulating film 14 and the protective insulating film 17.

  In contrast, in the present embodiment described above, first, as shown in FIGS. 9A and 9B, the passivation film 13 formed so as to cover the connection pads 12 on the semiconductor wafer 21 and the insulating film 13 are insulated. Openings 13h and 14h in which the upper surfaces of the connection pads 12 are exposed are formed in the film 14. At the same time, a concave recess 14a corresponding to the pattern of the wiring body 16 formed on the insulating film 14 and from which, for example, 1/3 of the thickness of the insulating film 14 is removed is formed. Here, the width of the recess 14a is set to be, for example, several μm narrower than the width of the wiring body 16, for example. And after forming the titanium thin film 15 and the copper thin film 16-1 which are base metal layers in the whole surface on the upper surface of the insulating film 14 in which the recessed part 14a was formed, it is an upper metal layer on the upper surface of the copper thin film 16-1. A patterned copper wiring layer 16-2 is formed. Next, by using the copper wiring layer 16-2 as a mask, the exposed copper thin film 16-1 and titanium thin film 15 are sequentially etched, as shown in FIGS. 9C and 9D. A configuration is obtained in which the wiring body 16 composed of the copper thin film 16-1 and the copper wiring layer 16-2 is formed on the concave portion 14a on the upper surface via the titanium thin film 15.

Here, the recess 14a formed on the upper surface of the insulating film 14 is formed to have a depth of about 1 μm when the thickness of the insulating film 14 is set to 3 μm, for example. The end of the recess 14a has an inclined surface of approximately 45 ° by forming the openings 13h and 14h and the recess 14a in the insulating film 14 and the passivation film 13 and then solidifying by baking. . At this time, the dimension of the titanium thin film 15 in the wiring width direction is larger than the width of the wiring body 16 by [(√2-1) × 2≈] 0.828 μm. Thus, as in the comparative example, for example, even when 4 μm side etching occurs in the wiring body 16 having a wiring width of 10 μm, the remaining dimension of the titanium thin film 15 is calculated to be 6.828 μm. Therefore, the wiring main body 16 and the insulating film 14 are in close contact with each other through the titanium thin film 15 in a region of 2/3 or more of the width (10 μm) of the wiring main body 16. Good adhesion is ensured.
As described above, since the recess 14a is formed on the upper surface of the insulating film 14, the adhesion area between the insulating film 14 and the titanium thin film 15 and the adhesion area between the titanium thin film 15 and the wiring body 16 can be increased. Therefore, the adhesion can be improved and a highly reliable semiconductor device can be realized.

  Further, a concave recess 14 a is provided on the upper surface of the insulating film 14, and the wiring body 16 is formed via the titanium thin film 15 so as to cover the recess 14 a, so that the upper surface of the wiring body 16 from the upper surface 11 a of the semiconductor substrate 11. The height up to can be suppressed. Therefore, even when the protective insulating film 17 or the like is formed on the semiconductor substrate 11 on which the wiring body 16 is formed, it is possible to prevent bubbles from entering between the insulating film 14 and the protective insulating film 17.

  Furthermore, by setting the width of the recess 14a to be narrower than the width of the wiring body 16, depending on the depth and width of the recess 14a, the film thickness of the wiring body 16, and physical properties, as shown in FIG. In addition, irregularities 16d corresponding to the shape of the recesses 14a may occur on the upper surface of the lands 16b provided at the other end of the wiring body 16. In this embodiment, as shown in FIG. 10B, by forming external connection electrodes such as solder balls 18 on the upper surface of the land 16b having such a cross-sectional shape, as shown in FIG. As described above, since the contact area between the land 16b and the solder ball 18 can be increased as compared with the case where the upper surface of the land 16b is flat, the adhesion can be improved and a highly reliable semiconductor device can be obtained. Can be realized.

(Other configuration examples)
FIG. 11 is a schematic cross-sectional view showing another configuration example of the concave portion on the upper surface of the insulating film applied to the semiconductor device according to the present embodiment.

  In the above-described embodiment, as shown in FIG. 9A, when the concave portion 14a corresponding to the pattern of the wiring body 16 and having a predetermined depth is provided on the upper surface of the insulating film 14. However, the present invention is not limited to this. That is, the shape of the recess has various cross-sectional shapes as shown below, for example, as long as the adhesion area by the titanium thin film 15 interposed between the wiring body 16 and the insulating film 14 can be sufficiently secured. It may be a thing.

  For example, the recess shown in FIG. 11A has a narrow V-shaped groove 14 b immediately below the wiring near the both ends of the wiring body 16. Further, the concave portion shown in FIG. 11B has a shallow groove portion 14c narrower than the wiring width, and a narrow and deep V-shaped groove portion 14b directly below the wiring in the vicinity of both ends of the wiring body 16 of the shallow groove portion 14c. Is. Further, the concave portion shown in FIG. 11C is one having fine irregularities 14d on the bottom surface in the concave portion 14a narrower than the wiring width, or the surface of the bottom surface is roughly processed. Moreover, the recessed part shown to FIG.11 (d), (e) has 1 or several protrusion part e in the recessed part 14a wider than a wiring width.

  Also in the semiconductor device 10 having the concave portion 14a having such a configuration, as described above, good adhesion between the wiring body 16 and the insulating film 14 is ensured through the titanium thin film 15, and the wiring body 16 The height can be suppressed and bubbles can be prevented from entering when the protective insulating film 17 is formed, and a highly reliable semiconductor device can be realized.

  The present invention is not limited to the configuration shown in the above-described embodiment. For example, as shown in FIG. 11 (f), the protrusion 14 f narrower than the width of the wiring body 16 on the upper surface of the insulating film 14. Even if it has 1 or more, among the effects mentioned above, the adhesiveness of the wiring main body 16 and the insulating film 14 can be improved.

  In the embodiment described above, specific numerical values of various parameters such as the width and depth of the recess 14a formed on the upper surface of the insulating film 14 are shown. However, the present invention is not limited to this. Absent. That is, according to the present invention, even when predetermined side etching occurs in the titanium thin film 15 interposed between the wiring main body 16 and the insulating film 14, a sufficient mutual contact area can be secured. If it exists, it may have other shapes and numerical values.

  Furthermore, in the present embodiment, a semiconductor device having a wafer level CSP type package structure is shown as a configuration to which the present invention is applied, but the present invention is not limited to this. That is, the present invention may be another semiconductor device as long as it has a configuration in which a wiring including a metal layer susceptible to side etching is formed on the upper surface of a photosensitive insulating film and a manufacturing process. However, the present invention can be satisfactorily applied even to electronic parts other than semiconductor devices.

As mentioned above, although some embodiment of this invention was described, this invention is not limited to embodiment mentioned above, It includes the invention described in the claim, and its equivalent range.
Hereinafter, the invention described in the scope of claims of the present application will be appended.

(Appendix)
The invention described in claim 1
A semiconductor substrate having connection pads on one side;
An opening provided on the semiconductor substrate and exposing a part of the connection pad; an insulating film having a recess on an upper surface;
An adhesion layer provided on the insulating film in the recess;
A wiring layer provided on the adhesion layer;
It is a semiconductor device characterized by having.

The invention described in claim 2
2. The semiconductor device according to claim 1, wherein a width of the adhesion layer is narrower than a width of the wiring layer, and a width of the concave portion is narrower than a width of the wiring layer.

The invention according to claim 3
The adhesion layer constitutes a base metal layer, the wiring layer constitutes an upper metal layer, and constitutes a wiring in which the base metal layer and the upper metal layer are integrally formed. Item 3. The semiconductor device according to Item 1 or 2.

The invention according to claim 4
4. The semiconductor device according to claim 1, wherein the insulating film includes polyimide, the adhesion layer is a metal layer including titanium, and the wiring layer is a metal layer including copper. is there.

The invention described in claim 5
One end side of the wiring is connected to one surface side of the connection pad through the opening,
5. The semiconductor device according to claim 1, wherein an external connection terminal is provided on the other end side of the wiring.

The invention described in claim 6
Prepare a semiconductor substrate provided with an insulating film so as to cover the connection pad provided on one side,
In the insulating film, an opening that exposes one side of the connection pad is formed, and a recess is formed in a part of the upper surface of the insulating film.
Forming a base metal layer including an adhesion layer on the upper surface of the insulating film in which the recess and the recess are formed;
In the semiconductor device manufacturing method, an upper metal layer having a predetermined pattern is formed in a region including the inside of the concave portion on the upper surface side of the base metal layer.

The invention described in claim 7
The width of the adhesion layer becomes narrower than the width of the pattern of the upper metal layer by etching the base metal layer,
An exposure mask comprising: a first transmission part that transmits exposure light at a high transmittance; and a second transmission part that transmits the exposure light at a transmittance lower than the transmittance of the first transmission part. 7. The method of manufacturing a semiconductor device according to claim 6, wherein the opening and the recess are formed together by changing the photosensitive depth of the insulating film by one exposure process.

The invention according to claim 8 provides:
Forming a seed layer on one side of the adhesion layer;
8. The method of manufacturing a semiconductor device according to claim 6, wherein the upper metal layer having the predetermined pattern is formed by electrolytic plating using the seed layer.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Semiconductor substrate 12 Connection pad 13 Passivation film (insulating film)
14 Insulating film 14a Recess 15 Titanium thin film (adhesion layer, base metal layer)
15x side etching part 16 wiring body 16-1 copper thin film (underlying metal layer)
16-2 Copper wiring layer (upper metal layer)
17 Protective insulation film 18 Solder ball (external connection terminal)
21 Semiconductor wafer (semiconductor substrate)
22 Dicing Street

Claims (8)

A semiconductor substrate having connection pads on one side;
An opening provided on the semiconductor substrate and exposing a part of the connection pad; an insulating film having a recess on an upper surface;
An adhesion layer provided on the insulating film in the recess;
A wiring layer provided on the adhesion layer;
A semiconductor device comprising:   2. The semiconductor device according to claim 1, wherein a width of the adhesion layer is narrower than a width of the wiring layer, and a width of the concave portion is narrower than a width of the wiring layer.   The adhesion layer constitutes a base metal layer, the wiring layer constitutes an upper metal layer, and constitutes a wiring in which the base metal layer and the upper metal layer are integrally formed. Item 3. The semiconductor device according to Item 1 or 2.   4. The semiconductor device according to claim 1, wherein the insulating film contains polyimide, the adhesion layer is a metal layer containing titanium, and the wiring layer is a metal layer containing copper. One end side of the wiring is connected to one surface side of the connection pad through the opening,
The semiconductor device according to claim 1, wherein an external connection terminal is provided on the other end side of the wiring. Prepare a semiconductor substrate provided with an insulating film so as to cover the connection pad provided on one side,
In the insulating film, an opening that exposes one side of the connection pad is formed, and a recess is formed in a part of the upper surface of the insulating film.
Forming a base metal layer including an adhesion layer on the upper surface of the insulating film in which the recess and the recess are formed;
A method of manufacturing a semiconductor device, comprising: forming an upper metal layer having a predetermined pattern in a region including the inside of the recess on the upper surface side of the base metal layer. The width of the adhesion layer becomes narrower than the width of the pattern of the upper metal layer by etching the base metal layer,
An exposure mask comprising: a first transmission part that transmits exposure light at a high transmittance; and a second transmission part that transmits the exposure light at a transmittance lower than the transmittance of the first transmission part. 7. The method of manufacturing a semiconductor device according to claim 6, wherein the opening and the recess are formed together by changing the photosensitive depth of the insulating film by one exposure process. Forming a seed layer on one side of the adhesion layer;
8. The method of manufacturing a semiconductor device according to claim 6, wherein the upper metal layer having the predetermined pattern is formed by electrolytic plating using the seed layer.

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