JP2013021596A - Analog switch circuit and multiplexer circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a leakage current while suppressing the effect of noise of an external terminal.SOLUTION: An analog switch circuit includes: a first switch disposed between a first node and a second node; a second switch disposed between the second node and a third node; a third switch disposed between a fourth node supplied with a predetermined voltage and the second node; and a control unit which receives at least two kinds of control signals and performs, on the basis of a combination of the control signals, one of first control for turning on the first switch and the second switch and turning off the third switch, second control for turning off the first switch, the second switch, and the third switch, and third control for turning off the first switch and the second switch and turning on the third switch.

Description

  The present invention relates to an analog switch circuit and a multiplexer circuit.

  In an integrated circuit such as a microcontroller, a method of A / D converting a plurality of analog input signals with a single A / D conversion (analog / digital conversion) circuit is widespread. For example, the integrated circuit includes a multiplexer circuit that selects one analog input signal from a plurality of analog input signals (for example, Patent Document 1). The A / D conversion circuit A / D converts the analog input signal selected by the multiplexer circuit.

  The multiplexer circuit has an analog switch circuit between each external terminal of the plurality of external terminals and the A / D conversion circuit. For example, the analog switch circuit includes a first switch and a second switch connected in series between terminals of the analog switch circuit, and a node between the first switch and the second switch and a power supply terminal (or a ground terminal). And a third switch. The third switch performs an on / off operation opposite to the on / off of the first switch and the second switch (for example, Patent Document 2).

  For example, the third switch is turned on when the first switch and the second switch are turned off. As a result, in the analog switch circuit in which the first switch and the second switch are set to OFF, when an excessive voltage noise exceeding the range of the power supply voltage (or ground voltage) is input to the external terminal, the analog switch circuit The terminals of the switch circuit are kept off. As a result, noise or the like at the input terminal of the analog switch circuit is prevented from being transmitted to the output terminal of the analog switch circuit.

  In an integrated circuit, an analog terminal such as an input terminal of an A / D conversion circuit may also be used as an input / output terminal of a digital circuit due to the restriction on the number of external terminals.

JP 2010-41279 A Japanese Patent Laid-Open No. 02-4011

  During the period when the third switch is on, a leakage current flows through the third switch. That is, a leakage current flows in an analog switch circuit connected to a terminal not selected as an input terminal for an analog input signal. Therefore, the leakage current increases in proportion to the number of analog switch circuits in the multiplexer circuit.

  For example, in a multiplexer circuit that selects an analog input signal of an A / D conversion circuit, the analog input signal transmitted to the A / D conversion circuit may change due to an increase in leakage current. Therefore, an increase in leakage current may affect the A / D conversion result. Moreover, power consumption increases due to an increase in leakage current.

  An object of the present invention is to reduce a leakage current while suppressing the influence of noise of an external terminal.

  In one form of the present invention, the analog switch circuit includes a first switch disposed between the first node and the second node, a second switch disposed between the second node and the third node, A third switch disposed between a fourth node and a second node to which a predetermined voltage is supplied; and at least two kinds of control signals; turning on the first switch and the second switch; First control for turning off the switch, second control for turning off the first switch, the second switch, and the third switch, and a third control for turning off the first switch and the second switch and turning on the third switch And a control unit that implements any of the above based on a combination of control signals.

  Leakage current can be reduced while suppressing the influence of external terminal noise.

2 illustrates an example of an analog switch circuit according to an embodiment. An example of the operation of the control unit shown in FIG. 1 is shown. An example of the principal part of the multiplexer circuit which has the analog switch circuit shown in FIG. 1 is shown. 4 shows an example of an integrated circuit having the multiplexer circuit shown in FIG.

  Hereinafter, embodiments will be described with reference to the drawings.

  FIG. 1 shows an example of an analog switch circuit ASWC in one embodiment. A double circle in FIG. 1 indicates a shared terminal PAD that is also used as an analog circuit (for example, the A / D conversion circuit ADC shown in FIG. 4) and a digital circuit. The analog switch circuit ASWC is used for a multiplexer circuit, for example. For example, the analog switch circuit ASWC includes an analog switch unit ASWP and a control unit CLT.

  The analog switch unit ASWP is arranged between a node NDa connected to the shared terminal PAD and a node NDc connected to the analog circuit. For example, the analog switch unit ASWP includes switches SWa and SWb connected in series between the nodes NDa and NDc via the node NDb, and a switch SWc disposed between the ground line to which the ground voltage is supplied and the node NDb. And an inverter INVa.

  The switch SWa has an nMOS transistor MNa and a pMOS transistor MPa connected in parallel. For example, in the nMOS transistor MNa, one of the source and the drain is connected to the node NDa, and the other of the source and the drain is connected to the node NDb. The nMOS transistor MNa receives the control signal AEN output from the control unit CLT at the gate.

  In the pMOS transistor MPa, one of the source and the drain is connected to the node NDa, and the other of the source and the drain is connected to the node NDb. Then, the pMOS transistor MPa receives a signal (output of the inverter INVa) obtained by inverting the control signal AEN at the gate. Therefore, the transistors MNa and MPa are turned on when the control signal AEN is at a high level (for example, a power supply voltage), and turned off when the control signal AEN is at a low level (for example, a ground voltage).

  The switch SWb has an nMOS transistor MNb and a pMOS transistor MPb connected in parallel. For example, in the nMOS transistor MNb, one of the source and the drain is connected to the node NDb, and the other of the source and the drain is connected to the node NDc. The nMOS transistor MNb receives the control signal AEN at the gate.

  In the pMOS transistor MPb, one of the source and the drain is connected to the node NDb, and the other of the source and the drain is connected to the node NDc. The pMOS transistor MPb receives a signal (output of the inverter INVa) obtained by inverting the control signal AEN at the gate. Therefore, the transistors MNb and MPb are turned on when the control signal AEN is at a high level and turned off when the control signal AEN is at a low level.

  As described above, the switches SWa and SWb are turned on when the control signal AEN is at a high level and turned off when the control signal AEN is at a low level. That is, the nodes NDa and NDc become conductive when the control signal AEN is at a high level, and become non-conductive when the control signal AEN is at a low level.

  The switch SWc has an nMOS transistor MNc. For example, the nMOS transistor MNc has a source grounded and a drain connected to the node NDb. The nMOS transistor MNc receives the control signal PEN output from the control unit CLT at the gate. Therefore, the switch SWc (transistor MNc) is turned on when the control signal PEN is at a high level and turned off when the control signal AEN is at a low level. That is, the node NDb is grounded via the switch SWc when the control signal AEN is at a high level, and becomes floating when the control signal AEN is at a low level. Thus, the switch SWc functions as a pull-down resistor when turned on.

  The inverter INVa receives the control signal AEN from the control unit CLT and outputs an inverted signal of the control signal AEN to the gates of the pMOS transistors MPa and MPb. Note that the inverter INVa may be provided in the control unit CLT.

  The control unit CLT receives the control signals CNTa, CNTb, and CNTc, and outputs control signals AEN, PEN, DOEN, and DIEN. The control signal DOEN is a signal for controlling whether or not the shared terminal PAD is used as an output terminal of the digital circuit, for example. The control signal DIEN is a signal for controlling whether or not the shared terminal PAD is used as an input terminal of the digital circuit, for example.

  For example, the control unit CLT generates the control signals AEN, PEN, DOEN, and DIEN based on the combination of the control signals CNTa, CNTb, and CNTc. Then, the control unit CLT controls the switches SWa, SWb, and SWc using the control signals AEN and PEN. For example, the control unit CLT turns on the switches SWa and SWb and turns off the switch SWc by setting the control signals AEN and PEN to a high level and a low level, respectively. Further, the control unit CLT turns off the switches SWa, SWb, and SWc by setting the control signals AEN and PEN to a low level. Then, the control unit CLT turns off the switches SWa and SWb and turns on the switch SWc by setting the control signals AEN and PEN to a low level and a high level, respectively.

  Note that the configuration of the analog switch circuit ASWC is not limited to this example. For example, the control unit CLT may receive only two of the control signals CNTa, CNTb, and CNTc and generate only the control signals AEN and PEN without generating the control signals DOEN and DIEN. Further, the switches SWa and SWb may be formed to be turned on when the control signal AEN is at a low level, for example. Alternatively, the switch SWc may be formed to turn on when the control signal PEN is at a low level, for example. The switch SWc may be disposed between a power supply line to which a power supply voltage is supplied and the node NDb.

  FIG. 2 shows an example of the operation of the control unit CLT shown in FIG. Note that “1” in FIG. 2 indicates a high level, and “0” indicates a low level. 2 indicates that the level of the control signal CNTc does not affect the control signals AEN, PEN, DOEN, and DIEN. In the remarks column of FIG. 2, the states of the shared terminal PAD and the node NDb set by the control signals AEN, PEN, DOEN, and DIEN are shown.

  In the example of FIG. 2, the shared terminal PAD is used as an output terminal of the digital circuit when the control signal DOEN is “1”, and is used as an input terminal of the digital circuit when the control signal DIEN is “1”. The shared terminal PAD is used as an analog circuit terminal (for example, the input terminal ADIN of the A / D conversion circuit ADC shown in FIG. 4) when the control signal AEN is “1”. Hereinafter, the input terminal of the digital circuit, the output terminal of the digital circuit, and the terminal of the analog circuit are also referred to as a digital input terminal, a digital output terminal, and an analog terminal, respectively.

  The control unit CLT outputs control signals AEN, PEN, DOEN, and DIEN corresponding to the control signals CNTa, CNTb, and CNTc. For example, when the control signals CNTa, CNTb, and CNTc are all “0”, the control signals AEN, PEN, DOEN, and DIEN are “0”, “1”, “0”, and “1”, respectively. Thereby, the switches SWa, SWb, and SWc are set to off, off, and on, respectively, and the shared terminal PAD is set to a state that can be used as a digital input terminal (state 1 in FIG. 2).

  That is, in the state 1, the shared terminal PAD is set to a state that can be used as a digital input terminal, and the node NDb is pulled down to the ground voltage. In state 1, since the node NDb is pulled down to the ground voltage, the switch SWb is turned off even when excessive voltage noise exceeding the range of the power supply voltage (or ground voltage) is input to the shared terminal PAD. Maintained in a state.

  For example, even when the switch SWa malfunctions (changes from an off state to a weak on state) due to noise or the like input to the shared terminal PAD, the switch SWb is maintained in the off state. Thereby, the nodes NDa and NDc of the analog switch circuit ASWC are maintained in the off state. That is, in this embodiment, when the dual-purpose terminal PAD is used as a digital input terminal, by setting the state 1 in FIG. 2, the noise of the dual-purpose terminal PAD is transmitted to the analog circuit connected to the node NDc. Can be prevented.

  When the control signals CNTa, CNTb, and CNTc are “0”, “0”, and “1”, respectively, the control signals AEN, PEN, DOEN, and DIEN are “0”, “1”, “1”, and “0”, respectively. It is. Thereby, the switches SWa, SWb, and SWc are set to off, off, and on, respectively, and the shared terminal PAD is set to a state that can be used as a digital output terminal (state 2 in FIG. 2).

  That is, in the state 2, the shared terminal PAD is set to a state that can be used as a digital output terminal, and the node NDb is pulled down to the ground voltage. In state 2, since the node NDb is pulled down to the ground voltage, the switch SWb is maintained in the off state even when noise or the like is input to the shared terminal PAD. Therefore, in this embodiment, when the shared terminal PAD is used as a digital output terminal, by setting the state 2 in FIG. 2, the noise of the shared terminal PAD is transmitted to the analog circuit connected to the node NDc. Can be prevented.

  When the control signals CNTa, CNTb, and CNTc are “0”, “1”, and “0”, respectively, the control signals AEN, PEN, DOEN, and DIEN are “0”, “0”, “0”, and “1”, respectively. It is. As a result, the switches SWa, SWb, and SWc are all set to OFF, and the shared terminal PAD is set to a usable state as a digital input terminal (state 3 in FIG. 2). That is, in the state 3, the shared terminal PAD is set to a usable state as a digital input terminal, and the node NDb is set to a floating state.

  In state 3, since the node NDb is set to be floating, the leakage current flowing through the switch SWc (nMOS transistor MNc) is reduced. For example, when there is no possibility that an excessive voltage exceeding the range of the power supply voltage (or ground voltage) is input to the shared terminal PAD, the possibility that the switch SWa malfunctions even if the node NDb is set to be floating is low. .

  Therefore, in this embodiment, for example, when there is no possibility that an excessive voltage is input to the shared terminal PAD, by setting the state 3 in FIG. 2, the noise or the like of the shared terminal PAD is connected to the node NDc. Leakage current can be reduced while preventing transmission to the circuit. That is, in this embodiment, even when the shared terminal PAD is used as a digital input terminal, the leakage current can be reduced by setting the state 3 in FIG.

  When the control signals CNTa, CNTb, and CNTc are “0”, “1”, and “1”, respectively, the control signals AEN, PEN, DOEN, and DIEN are “0”, “0”, “1”, and “0”, respectively. It is. As a result, the switches SWa, SWb, and SWc are all set to OFF, and the shared terminal PAD is set to a usable state as a digital output terminal (state 4 in FIG. 2). That is, in the state 4, the shared terminal PAD is set to a usable state as a digital output terminal, and the node NDb is set to be floating. In state 4, since the node NDb is set to be floating, the leakage current flowing through the switch SWc is reduced.

  Therefore, in this embodiment, for example, when there is no possibility that an excessive voltage is input to the shared terminal PAD, by setting the state 4 in FIG. 2, the noise or the like of the shared terminal PAD is connected to the node NDc. Leakage current can be reduced while preventing transmission to the circuit. That is, in this embodiment, even when the shared terminal PAD is used as a digital output terminal, the leakage current can be reduced by setting the state 4 in FIG.

  When the control signals CNTa and CNTb are “1” and “0”, respectively, the control signals AEN, PEN, DOEN, and DIEN are all “0”. As a result, the switches SWa, SWb, and SWc are all set to OFF, and the shared terminal PAD is set to a state not used for the digital circuit (state 5 in FIG. 2). That is, in the state 5, the shared terminal PAD is set to unused (a state in which neither the analog circuit nor the digital circuit is used), and the node NDb is set to be floating. In state 5, since the node NDb is set to be floating, the leakage current flowing through the switch SWc is reduced. Therefore, in this embodiment, when the shared terminal PAD is not used, the leakage current can be reduced by setting the state 5 in FIG.

  When both the control signals CNTa and CNTb are “1”, the control signals AEN, PEN, DOEN, and DIEN are “1”, “0”, “0”, and “0”, respectively. Thereby, the switches SWa, SWb, and SWc are set to ON, ON, and OFF, respectively, and the shared terminal PAD is set to a state that is not used for the digital circuit (state 6 in FIG. 2). That is, in the state 6, the shared terminal PAD is set to a usable state as an analog terminal, and the node NDb is set to be floating. In state 6, since the node NDb is set in a floating state, for example, an analog signal input to the shared terminal PAD is correctly transmitted to the input terminal of the analog circuit via the switches SWa and SWb.

  As described above, in the example of FIG. 2, the control signals CNTa and CNTb are used to generate the control signals AEN and PEN, and the control signals CNTa and CNTc are used to generate the control signals DOEN and DIEN. That is, the control unit CLT controls the switches SWa, SWb, and SWc based on the combination of the control signals CNTa and CNTb.

  Note that the operation of the control unit CLT is not limited to this example. For example, the control unit CLT may set the shared terminal PAD to be usable as a terminal of the digital circuit when the control signal CNTa is “1”. The control unit CLT may set the shared terminal PAD to be usable as a digital input terminal when the control signal CNTc is “1”. Alternatively, the control unit CLT may generate the control signals AEN and PEN using the control signals CNTa and CNTc instead of the control signals CNTa and CNTb. That is, the relationship between the combination of the control signals CNTa, CNTb, and CNTc and the combination of the control signals AEN, PEN, DOEN, and DIEN is not limited to this example.

  The control unit CLT may be configured to select a setting for turning on the switch SWc and a setting for turning off the switch SWc when the shared terminal PAD is not used. For example, when the shared terminal PAD is not used, the control unit CLT may set the switch SWc to either on or off based on the level of the control signal CNTc.

  Alternatively, for example, the control unit CLT receives only the control signals CNTa and CNTb among the control signals CNTa, CNTb, and CNTc, and generates only the control signals AEN and PEN without generating the control signals DOEN and DIEN. Good. For example, when switching between the digital input terminal and the digital output terminal is controlled by a module other than the analog switch circuit ASWC, the control unit CLT may not generate the control signals DOEN and DIEN. Whether or not the shared terminal PAD is used in the digital circuit is determined based on, for example, the control signal CNTa. Further, for example, when the shared terminal PAD is shared by the digital input terminal and the analog terminal, the setting of the state 2 and the state 4 in FIG. 2 is not necessary. When the shared terminal PAD is used as both a digital output terminal and an analog terminal, the setting of the state 1 and the state 3 in FIG. 2 is not necessary.

  FIG. 3 shows an example of a main part of the multiplexer circuit MPX having the analog switch circuit ASWC shown in FIG. FIG. 3 shows an example of the switch circuit block BLK of the multiplexer circuit MPX.

  The multiplexer circuit MPX includes, for example, a plurality of switch circuit blocks BLK provided corresponding to the plurality of shared terminals PAD, respectively. For example, the nodes NDa of the plurality of switch circuit blocks BLK are connected to the plurality of shared terminals PAD, respectively. The nodes NDc of the plurality of switch circuit blocks BLK are connected to, for example, a common analog circuit. Note that in FIG. 3, one switch circuit block BLK is shown and the other switch circuit blocks BLK are omitted for easy understanding of the drawing.

  The switch circuit block BLK includes an analog switch circuit ASWC, a three-state buffer TSB, and an AND circuit ANDb. As described with reference to FIG. 2, the analog switch circuit ASWC sets the states of the shared terminal PAD and the node NDb according to the control signals CNTa, CNTb, and CNTc. For example, the control unit CLT of the analog switch circuit ASWC includes an AND circuit ANDa, NOR circuits NORa, NORb, NORc, and an inverter INVb.

  The AND circuit ANDa receives the control signals CNTa and CNTb, and outputs a logical product (control signal AEN) of the control signal CNTa and the control signal CNTb to the inverter INVa and the gates of the nMOS transistors MNa and MNb. The NOR circuit NORa receives the control signals CNTa and CNTb, and outputs a negative OR result (control signal PEN) of the control signal CNTa and the control signal CNTb to the gate of the nMOS transistor MNc.

  The inverter INVb receives the control signal CNTc and outputs an inverted signal of the control signal CNTc to the NOR circuit NORb. The NOR circuit NORb receives the control signal CNTa and the output of the inverter INVb (inverted signal of the control signal CNTc), and outputs the negative OR result (control signal DOEN) of the control signal CNTa and the inverted signal of the control signal CNTc as the three-state buffer TSB. Output to. The NOR circuit NORc receives the control signals CNTa and CNTc, and outputs a negative logical sum result (control signal DIEN) of the control signal CNTa and the control signal CNTc to the AND circuit ANDb.

  The three-state buffer TSB sets the output (shared terminal PAD, node NDa) to a high impedance state when the control signal DOEN received from the control unit CLT is at a low level. That is, the shared terminal PAD is not used as a digital output terminal when the control signal DOEN is at a low level.

  The three-state buffer TSB outputs the digital output signal DO as it is to the shared terminal PAD when the control signal DOEN is at a high level. The digital output signal DO is a signal output from a digital circuit, for example. That is, the shared terminal PAD is set to a state where it can be used as a digital output terminal when the control signal DOEN is at a high level.

  Therefore, the three-state buffer TSB is arranged between the node NDa and the output node of the digital circuit, and functions as a switch that is set to either the output-on state or the output-off state. The output on state is a state in which the output signal (digital output signal DO) of the digital circuit can be transmitted to the shared terminal PAD. The output off state is a state in which the digital output signal DO is not transmitted to the shared terminal PAD.

  The AND circuit ANDb outputs a logical product result (digital input signal DI) of the control signal DIEN received from the control unit CLT and the digital signal received via the shared terminal PAD. Therefore, when the control signal DIEN is at a low level, the digital input signal DI output from the AND circuit ANDb is at a low level regardless of the level of the shared terminal PAD. As a result, the connection between the shared terminal PAD and the internal circuit is cut off, and the bus conflict is suppressed. That is, the shared terminal PAD is not used as a digital input terminal when the control signal DIEN is at a low level.

  The AND circuit ANDb outputs the digital signal input to the shared terminal PAD as the digital input signal DI as it is when the control signal DIEN is at a high level. The digital input signal DI is a signal received by a digital circuit, for example. That is, the shared terminal PAD is set to a state where it can be used as a digital input terminal when the control signal DIEN is at a high level.

  Therefore, the AND circuit ANDb is disposed between the node NDa and the input node of the digital circuit, and functions as a switch set to either the input on state or the input off state. The input on state is a state in which an input digital signal input to the shared terminal PAD can be transmitted to the input node of the digital circuit. The input off state is a state in which the input digital signal input to the shared terminal PAD is not transmitted to the input node of the digital circuit.

  As described above, the control unit CLT controls the switches SWa, SWb, SWc, the three-state buffer TSB, and the AND circuit ANDb. For example, when the shared terminal PAD is not used for either an analog circuit or a digital circuit (state 5 in FIG. 2), the switches SWa, SWb, and SWc are set to OFF, the three-state buffer TSB is set to an output OFF state, The AND circuit ANDb is set to an input off state.

  For example, when the shared terminal PAD is used for an analog circuit (state 6 in FIG. 2), the switches SWa, SWb, and SWc are set to on, on, and off, respectively, and the three-state buffer TSB is set to an output off state. Then, the AND circuit ANDb is set to the input off state.

  When the shared terminal PAD is used as the output terminal of the digital circuit (state 2 and state 4 in FIG. 2), the switches SWa and SWb are set to OFF, the three-state buffer TSB is set to the output ON state, and AND The circuit ANDb is set to the input off state. The switch SWc is set to either on or off.

  When the shared terminal PAD is used as the input terminal of the digital circuit (state 1 and state 2 in FIG. 2), the switches SWa and SWb are set to OFF, the three-state buffer TSB is set to the output OFF state, and the AND circuit ANDb Is set to the input on state. The switch SWc is set to either on or off.

  As described above, the switch circuit block BLK switches the usage (connection destination) of the shared terminal PAD based on the control signals CNTa, CNTb, and CNTc. Note that the configuration of the switch circuit block BLK is not limited to this example. For example, the switch circuit block BLK may have a three-state buffer controlled by the control signal DIEN instead of the AND circuit ANDb.

  FIG. 4 shows an example of an integrated circuit having the multiplexer circuit MPX shown in FIG. The integrated circuit is, for example, a microcontroller. For example, the integrated circuit includes a multiplexer circuit MPX, an A / D conversion (analog / digital conversion) circuit ADC, a decoder DEC, and a central processing unit CPU.

  For example, the A / D conversion (analog / digital conversion) circuit ADC is an analog circuit, and the decoder DEC and the central processing unit CPU form at least a part of the digital circuit. The multiplexer circuit MPX, the A / D conversion circuit ADC, the decoder DEC, and the central processing unit CPU are connected to the bus BUS, for example. Therefore, in the example of FIG. 4, the bus BUS corresponds to the input node of the digital circuit, and the output terminal of the decoder DEC corresponds to the output node of the digital circuit. Note that the configuration of the integrated circuit is not limited to this example.

  The multiplexer circuit MPX includes, for example, four switch circuit blocks BLK (BLK1-BLK4). The number of switch circuit blocks BLK is not limited to four. In FIG. 4, the dual-purpose terminal PAD and the signals CNTa, CNTb, CNTc, DI, and DO corresponding to each switch circuit block BLK are given the same numbers as the numbers at the end of the switch circuit block BLK. ing.

  For example, the shared terminal PAD1 is connected to the switch circuit block BLK1. The switch circuit block BLK1 sets the usage of the shared terminal PAD1 based on the control signals CNTa1, CNTb1, and CNTc1. The digital input signal DO1 is output to the shared terminal PAD1 via the switch circuit block BLK1 when the shared terminal PAD1 is used as an output terminal of the digital circuit. Further, when the shared terminal PAD1 is used as an input terminal of the digital circuit, the switch circuit block BLK1 outputs a digital input signal input to the shared terminal PAD1 to the digital circuit as a digital input signal DI1.

  The nodes NDc of the switch circuit blocks BLK1 to BLK4 are connected to the input terminal ADIN of the A / D conversion circuit ADC. That is, the nodes NDc of the switch circuit blocks BLK1 to BLK4 are connected to each other. For example, when A / D converting an analog input signal input to the shared terminal PAD4, the switch circuit block BLK4 sets the shared terminal PAD4 and the node NDb in the state 6 of FIG. Thus, the A / D conversion circuit ADC receives the analog input signal input to the shared terminal PAD4 at the input terminal ADIN via the switch circuit block BLK4. Note that the switch circuit blocks BLK1 to BLK3 set the shared terminal PAD and the node NDb in any one of the states 1 to 5 in FIG.

  For example, when the digital output signal DO1 is transmitted to the shared terminal PAD1, the switch circuit block BLK1 sets the shared terminal PAD1 and the node NDb in either the state 2 or the state 4 in FIG. When there is no possibility that an excessive voltage exceeding the range of the power supply voltage (or ground voltage) is input to the shared terminal PAD1, the switch circuit block BLK1 sets the shared terminal PAD1 and the node NDb in the state 4 of FIG. Thereby, the leakage current flowing through the switch SWc of the switch circuit block BLK1 can be reduced.

  Further, for example, when the digital signal input to the shared terminal PAD2 is output to the bus BUS as the digital input signal DI2, the switch circuit block BLK2 is switched to the shared terminal PAD2 and the node NDb in any of the state 1 and the state 3 in FIG. Set. When there is no possibility that an excessive voltage is input to the shared terminal PAD2, the switch circuit block BLK2 sets the shared terminal PAD2 and the node NDb in the state 3 in FIG. Thereby, the leakage current flowing through the switch SWc of the switch circuit block BLK2 can be reduced.

  For example, when the shared terminal PAD3 is not used, the switch circuit block BLK3 sets the shared terminal PAD3 and the node NDb in the state 5 in FIG. Thereby, the leakage current flowing through the switch SWc of the switch circuit block BLK3 can be reduced.

  In this way, the multiplexer circuit MPX sets, for example, the shared terminals PAD1-PAD3 and the nodes NDb of the switch circuit blocks BLK1-BLK3 to any one of the states 1 to 5 in FIG. Thereby, in this embodiment, it is possible to prevent noise or the like of the shared terminals PAD1-PAD3 from being transmitted to the input terminal ADIN of the A / D conversion circuit. As a result, for example, an analog signal input to the shared terminal PAD4 is correctly transmitted to the input terminal ADIN of the A / D conversion circuit via the switches SWa and SWb of the switch circuit block BLK4. Thereby, a correct A / D conversion result is obtained. As described above, in this embodiment, the leakage current can be reduced while suppressing the influence of the noise of the external terminal.

  The A / D conversion circuit ADC receives the analog signal output from the multiplexer circuit MPX at the input terminal ADIN, and A / D converts the analog signal received at the input terminal ADIN. The digital signal A / D converted by the A / D conversion circuit ADC is output from the output terminal ADOUT of the A / D conversion circuit ADC to the bus BUS.

  For example, the central processing unit CPU controls the operation of the entire integrated circuit. The decoder DEC is controlled by the central processing unit CPU or the like and outputs digital output signals DO1-DO4, control signals CNTa1-CNTa4, CNTb1-CNTb4, and CNTc1-CNTc4 to the multiplexer circuit MPX. For example, the decoder DEC decodes the register value of the control register in which the setting related to the multiplexer circuit MPX is stored, and outputs the control signals CNTa1-CNTa4, CNTb1-CNTb4, and CNTc1-CNTc4 to the multiplexer circuit MPX.

  For example, in the setting relating to the switch circuit block BLK connected to the shared terminal PAD that is not likely to receive an excessive voltage, the user who uses the integrated circuit selects any one of the state 3 to the state 6 in FIG. Such a register value is set in the control register. Thereby, in this embodiment, the leakage current can be reduced while suppressing the influence of the noise of the external terminal.

  As described above, in this embodiment, the analog switch circuit ASWC includes the switches SWa, SWb, and SWc that are controlled to be turned on / off according to the control signals CNTa and CNTb. The node NDb between the switches SWa and SWb is set to be floating by turning off the switch SWc. Thereby, the leakage current flowing through the switch SWc can be reduced. In this embodiment, since ON / OFF of the switch SWc can be arbitrarily controlled by the control signals CNTa and CNTb, for example, when there is no possibility that an excessive voltage is input to the shared terminal PAD, regardless of the use of the shared terminal PAD. The switch SWc can be turned off. Thereby, in this embodiment, the leakage current can be reduced while suppressing the influence of the noise of the external terminal.

  From the above detailed description, features and advantages of the embodiments will become apparent. This is intended to cover the features and advantages of the embodiments described above without departing from the spirit and scope of the claims. Further, any person having ordinary knowledge in the technical field should be able to easily come up with any improvements and modifications, and there is no intention to limit the scope of the embodiments having the invention to those described above. It is also possible to rely on suitable improvements and equivalents within the scope disclosed in.

  ADC A / D conversion circuit; ANDa, ANDb AND circuit; ASWC, analog switch circuit; ASWP, analog switch unit; BLK, BLK1-BLK4, switch circuit block; CLT, control unit, CPU, central processing unit; Decoder; INVa, INVb ... Inverter; MNa, MNb, MNc ... nMOS transistor; MPa, MPb ... pMOS transistor; MPX ... Multiplexer circuit; NDa, NDb, NDc ... node; NORa, NORb, NORc ... NOR circuit; PAD4 ··· shared terminal; TSB · · · Three-state buffer

Claims (6)

A first switch disposed between the first node and the second node;
A second switch disposed between the second node and the third node;
A third switch disposed between a fourth node to which a predetermined voltage is supplied and the second node;
A first control that receives at least two types of control signals, turns on the first switch and the second switch, and turns off the third switch; and the first switch, the second switch, and the third switch A control for performing either of the second control for turning off the second control and the third control for turning off the first switch and the second switch and turning on the third switch based on the combination of the control signals. And an analog switch circuit. The first node is a node connected to a shared terminal used for both an analog circuit and a digital circuit,
The third node is a node connected to the analog circuit;
The said control part implements either said 2nd control and said 3rd control based on the combination of the said control signal, when the said shared terminal is used for the said digital circuit. The analog switch circuit described. The first node is a node connected to a shared terminal used for both an analog circuit and a digital circuit,
The third node is a node connected to the analog circuit;
The analog switch circuit according to claim 1, wherein the control unit performs the second control when the dual-purpose terminal is not used for either the analog circuit or the digital circuit. The first node is a node connected to a shared terminal used for both an analog circuit and a digital circuit,
The third node is a node connected to the analog circuit;
The analog switch circuit according to claim 1, wherein the control unit performs the first control when the dual-purpose terminal is used in the analog circuit. Provided in correspondence with a plurality of dual-purpose terminals that are also used for analog circuits and digital circuits, and provided with a plurality of switch circuits that switch the use of the dual-purpose terminals,
Each of the switch circuits is
A first switch formed between the first node and the second node;
A second switch formed between the second node and the third node;
A third switch disposed between a fourth node to which a predetermined voltage is supplied and the second node;
An output on state that is disposed between the first node and an output node of the digital circuit, and that can transmit an output signal of the digital circuit to the shared terminal; and an output off state that does not transmit the output signal to the shared terminal A fourth switch set to one of the following:
An input-on state that is arranged between the first node and the input node of the digital circuit and can transmit an input signal input to the dual-purpose terminal to the input node, and an input that does not transmit the input signal to the input node A fifth switch set to any of the OFF states;
A controller that controls the first switch, the second switch, the third switch, the fourth switch, and the fifth switch;
The first node of the plurality of switch circuits is a node connected to the shared terminal;
The third node of the plurality of switch circuits is a node connected to the common analog circuit;
The controller is
When the shared terminal is not used for either the analog circuit or the digital circuit, the first switch, the second switch, and the third switch are turned off, and the fourth switch is set to the output off state, Setting the fifth switch to the input off state;
When the shared terminal is used in the analog circuit, the first switch and the second switch are turned on, the third switch is turned off, the fourth switch is set in the output off state, and the fifth switch is turned on. Set the switch to the input off state,
When the shared terminal is used as an output terminal of the digital circuit, the first switch and the second switch are turned off, the third switch is set to either on or off, and the fourth switch is turned on Set the output on state, set the fifth switch to the input off state,
When the shared terminal is used as an input terminal of the digital circuit, the first switch and the second switch are turned off, the third switch is set to either on or off, and the fourth switch is turned on A multiplexer circuit, wherein an output is turned off and the fifth switch is set in the input on state. The control unit receives at least three types of control signals and controls the first switch, the second switch, the third switch, the fourth switch, and the fifth switch based on a combination of the control signals. The multiplexer circuit according to claim 5.

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