JP2013021073A - Electronic device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electronic device with high reliability in which when trying to suppress deformation due to the difference of coefficients of thermal expansion between the through electrode and a substrate or the like, the degradation of device characteristics due to a side surface shape of a through electrode can be suppressed without increasing a number of steps of a manufacturing process.SOLUTION: An electronic device includes: a substrate 1; wiring 18 formed above a surface of the substrate 1; and a through-via 30 penetrating the substrate 1 from a back surface of the substrate 1, and formed in a through-hole 1A in which a first opening hole 1Aa and a second opening hole 1Ab having a total area of the opening smaller than the first opening hole 1Aa are connected in a depth direction of the substrate 1. In the through-via 30, a first electrode portion 30a formed in the first opening hole 1Aa and a second electrode portion 30b formed in the second opening hole 1Ab are integrally formed on the outermost side surfaces.

Description

  The present invention relates to an electronic device and a manufacturing method thereof.

In recent years, integration of electronic devices typified by transistors such as MOS transistors, memory devices, and sensor devices such as MEMS has shifted from a planar (two-dimensional) structure to a three-dimensional (three-dimensional) structure.
For example, semiconductor chips mounted on mobile phones are becoming mainstream with so-called system-in-package structures. As a method for three-dimensional stacking in a semiconductor chip, a PoP method performed at a package level, a SiP method in which semiconductor chips are stacked and interconnected by wire bonding, or the like is used.

Recently, three-dimensional integration technology for stacking electronic devices on a chip level has been actively developed.
When a large number of electronic devices are three-dimensionally integrated, in order to electrically connect the electronic devices, a through electrode (through via) penetrating the substrate is provided in the electronic device, and the electronic devices can be interconnected using this. is necessary.

JP 2007-81304 A

  Polycrystalline silicon, tungsten (W), Cu, or the like is used as the electrode material for the through via of the electronic device. When polycrystalline silicon, W is used, the CVD method is applied. When Cu is used, an electrolytic plating method is applied. Since the latter can form vias at a lower temperature than the former, a through via using Cu as an electrode material has attracted attention.

  In an electronic device, the thickness of the substrate is larger than the size of a functional element such as a transistor. For this reason, the through via has an extremely high aspect ratio. In such a high aspect ratio through via, it is difficult to form a through hole in the substrate and to fill the through hole with an electrode material, and the manufacturing cost increases. Therefore, if there is a margin in the area of the substrate, it is desirable to form a through via having a low aspect ratio by increasing the diameter of the through via.

However, when the diameter of the through via is increased, the difference in thermal expansion coefficient between the electrode material of the through via, the substrate and the active layer (layer on which various functional elements and wirings are formed) increases, and the displacement in the peripheral portion of the through via is increased. The problem is that the amount increases.
A specific example is shown in FIG. In FIG. 17, in a semiconductor chip, a silicon substrate 101, an active layer 102 formed thereon, a through via 103 using Cu penetrating the silicon substrate 101, and a bump ball 104 for external connection are simplified. It shows. The through via 103 penetrates the silicon substrate 101 and is electrically connected to the wiring 102 a of the active layer 102. As the internal structure of the active layer 102, only the wiring 102a is shown, and the functional elements are not shown.

In the semiconductor chip manufacturing process, when the processing temperature T is higher than the Cu crystal rearrangement temperature T ₀ , the Cu in the through via 103 thermally expands to push up the active layer 102 as shown in FIG. The layer 102 is deformed into a convex shape. On the other hand, when the processing temperature T is lower than T ₀ , as shown in FIG. 18B, Cu of the through electrode 103 is thermally contracted to pull the active layer 102 and the active layer 102 is deformed into a concave shape. Thus, there is a problem that a so-called pumping reaction occurs in which the through electrode 103 fluctuates the active layer 102 in the vertical direction depending on the processing temperature, and the functional elements and wirings of the active layer 102 are mechanically destroyed.

  FIG. 19 shows a configuration that suppresses the displacement of the through via described above without reducing the amount of current. As shown in FIG. 19, the through-via 111 is formed by connecting a large-diameter first electrode portion 112 and a plurality of small-diameter second electrode portions 113, and the second electrode portion 113 is connected to the active layer 102. Connected. Patent Document 1 discloses an example thereof.

However, in order to connect and form two types of electrode portions having different shapes as described above, the end portion of the first electrode portion 112 with the second electrode portion 113 on the side surface of the through via 111 and the second electrode A bending point 114 is formed at the end of the portion 113 with the first electrode portion 112. At the bending point 114, it is difficult to form Cu as an electrode metal as expected, and a Cu non-formation portion may occur. As described above, due to the edge shape of the connection portion between the two types of electrode portions, a leakage current or the like is generated, which causes deterioration of device characteristics.
Further, in order to connect and form two types of electrode portions having different shapes as described above, it is necessary to perform the lithography process at least twice, which causes a problem that the number of processes is large and the manufacturing flow is complicated.

  The present invention has been made in view of the above problems, and in suppressing deformation due to a difference in thermal expansion coefficient between the through electrode substrate and the like, the side shape of the through electrode without increasing the number of steps of the manufacturing process It is an object of the present invention to provide a highly reliable electronic device and a method for manufacturing the same that suppress degradation of device characteristics due to the above.

  One aspect of the electronic device includes a substrate, wiring formed above the front surface of the substrate, penetrating the substrate from the back surface of the substrate, and in the depth direction of the substrate, a first opening, The second opening having a smaller total opening area than the first opening includes a through electrode formed in a through hole integrated on the outermost surface.

  One aspect of the method for manufacturing an electronic device includes a step of forming a wiring above the front surface of the substrate, a step of forming a through hole penetrating the substrate on the back surface of the substrate, and an electrical connection between the wiring and the wiring. Forming a through-electrode connected to the first through-hole in the depth direction of the substrate, and a second opening having a total opening area smaller than that of the first opening. The openings are collectively formed by etching so as to be integrated with the outermost surface.

  According to the above aspects, in suppressing the deformation caused by the difference in thermal expansion coefficient between the through electrode and the substrate, the device characteristics are deteriorated due to the side shape of the through electrode without increasing the number of steps of the manufacturing process. A highly reliable electronic device is realized.

It is a schematic sectional drawing which shows the manufacturing method of the semiconductor chip by 1st Embodiment in order of a process. FIG. 2 is a schematic cross-sectional view subsequent to FIG. 1 illustrating the semiconductor chip manufacturing method according to the first embodiment in the order of steps. FIG. 3 is a schematic cross-sectional view illustrating the semiconductor chip manufacturing method according to the first embodiment in the order of steps, following FIG. 2. In this embodiment, it is a schematic plan view which shows the resist mask for forming the through-hole of a through-via. It is a schematic sectional drawing which shows the dry etching using a normal resist mask. It is a schematic sectional drawing which shows the dry etching using the resist mask of this embodiment. It is a characteristic view which shows the relationship between inclination-angle (theta) of the resist mask of this embodiment, and the retraction rate of a resist mask. It is a schematic sectional drawing shown in the middle of dry etching of this embodiment including progress. It is a schematic plan view which shows the resist mask used at the time of through-via formation in the modification 1 of 1st Embodiment. 11 is a schematic plan view showing a resist mask for forming a through hole of a through via in Modification Example 1. FIG. It is a schematic sectional drawing which shows the process at the time of performing the collective dry etching at the time of through-via formation in the modification 2 of 1st Embodiment. In Modification 2, it is a schematic plan view showing a resist mask for forming a through hole of a through via. It is a schematic sectional drawing which shows the process at the time of performing the collective dry etching at the time of through-via formation in the modification 3 of 1st Embodiment. In Modification 3, it is a schematic plan view showing a resist mask for forming a through hole of a through via. It is a schematic sectional drawing which shows the main processes of the manufacturing method of the semiconductor chip by 2nd Embodiment. In 2nd Embodiment, it is a schematic plan view which shows the resist mask for forming the through-hole of a through-via. It is a schematic sectional drawing which shows the conventional through-via. It is a schematic sectional drawing for demonstrating the pumping reaction which arises in a penetration via. It is a schematic sectional drawing for demonstrating one method to solve the problem of FIG.

  Hereinafter, specific embodiments to which an electronic device and a manufacturing method thereof are applied will be described in detail with reference to the drawings. In each embodiment, a semiconductor chip on which a MOS transistor as a functional element is mounted is exemplified as an electronic device. The electronic device can be applied to a sensor device such as a memory device or a MEMS other than the semiconductor chip. Moreover, although a silicon substrate is illustrated as a board | substrate, it can apply also to compound semiconductor substrates, such as GaAs, insulating boards, such as resin, a printed circuit board.

(First embodiment)
1 to 3 are schematic cross-sectional views showing a method of manufacturing a semiconductor chip according to the first embodiment in the order of steps.
As shown in FIG. 1A, an active layer 2 is formed on the surface of a silicon substrate 1.
More specifically, first, a silicon semiconductor substrate is prepared, and the back surface of the semiconductor substrate is thinned to a predetermined thickness, for example, about 200 μm, by back grinding. Thereby, the silicon substrate 1 is formed.

A gate electrode 12 using polycrystalline silicon or the like is formed on the surface of the silicon substrate via a gate insulating film 11, and impurities of a predetermined conductivity type are ion-implanted to form source / drain regions 13. Thereby, the MOS transistor 10 which is a functional element is formed.
An interlayer insulating film 14 is formed on the silicon substrate 1 so as to cover the MOS transistor 10, and a connection plug 15 electrically connected to the source / drain region 13 and the like is formed on the interlayer insulating film 14 by, for example, electrolytic plating. At this time, simultaneously with the connection plug 15, the connection electrode 16 is formed on the silicon substrate 1 where a later-described through via is to be formed. An interlayer insulating film 17 is formed on the interlayer insulating film 14, and a wiring 18 electrically connected to the connection plug 15 is formed on the interlayer insulating film 17 by, for example, electrolytic plating. The formation of the interlayer insulating film, the connection plug, the interlayer insulating film, and the wiring is repeated several times (once in the illustrated example) to form the multilayer wiring layer 20. Thus, the active layer 2 including the MOS transistor 10 and the multilayer wiring layer 20 is formed.
In the active layer 2, the MOS transistor 10 is not shown in FIG.

Subsequently, a resist mask 21 is formed on the back surface of the silicon substrate 1 as shown in FIG.
More specifically, a resist is applied to a thickness of about 10 μm, for example, on a portion of the back surface of the silicon substrate 1 where a through via is to be formed (a portion that is aligned with the connection electrode 16), and is processed by lithography to form a resist pattern 21. Form. The state of the resist mask 21 is shown in the plan view of FIG. 4 together with FIG. A cross section taken along the broken line II in FIG. 4 corresponds to FIG. The resist mask 21 includes a first pattern 21a that exposes the back surface of the silicon substrate 1 in a predetermined shape, and a plurality of second patterns that are columnar protrusions in a portion exposed from the first pattern 21a of the silicon substrate 1. 21b. The first pattern 21a is, for example, a circular opening pattern having an opening diameter of about 200 μm. The second pattern 21b has a trapezoidal shape in which the upper base width is smaller than the lower base width in the longitudinal section so that the second pattern 21b disappears during the etching. In the present embodiment, the second pattern 21b is formed in the above-mentioned trapezoidal shape by performing lithography by so-called detuned exposure and adjusting the light intensity and light irradiation angle. As will be described later, the inclination angle of the second pattern 21b is regulated to a value within the range of 45 ° to 90 °.

Here, dry etching using the second pattern 21b will be described.
Normally, as shown in FIG. 5A, the resist mask 121 has a rectangular longitudinal cross-sectional shape, and the side surface is perpendicular to the processing surface 122. By subjecting the processed surface 122 to dry etching using the resist mask 121, the processed surface is processed together with the upper surface of the resist mask 121 according to the cross-sectional shape of the resist mask 121 as shown in FIGS. Surface 122 is etched.

  In contrast, the resist mask 123, which is the second pattern 21b in FIG. 6A, has a trapezoidal shape in which the upper base width is smaller than the lower base width in the longitudinal section. The inclination angle of the resist mask 123 is θ. When the processed surface 122 is dry-etched using the resist mask 123, the processed surface 122 is etched following the shape of the resist mask 123 as shown in FIG. At this time, the resist mask 123 is etched on its upper surface, but since the second pattern 21b has an inclination angle on its side surface, it is also etched on the side surface and recedes in the width direction. Then, by using the resist mask 123 with the inclination angle θ adjusted appropriately, the resist mask 123 disappears during the etching of the surface 122 to be processed. At this time, a projection-like pattern 122a having a predetermined height is formed on the surface 122 to be processed.

FIG. 7 is a characteristic diagram showing the relationship between the inclination angle θ of the resist mask and the receding rate of the resist mask.
Thus, it can be seen that the receding rate of the resist mask is the largest when the inclination angle θ is 45 ° and the smallest (approximately 0) at 90 °. This is because a resist mask having an inclination angle has high ionicity in dry etching, and the sputtered mask material does not re-adhere and scatters in the direction opposite to the ion incidence, thereby increasing the sputtering efficiency. In this embodiment, using this result, the receding rate of the resist mask 123 is selected from a value from 0 (when the inclination angle θ is 90 °) to a maximum value (when the inclination angle θ is 45 °), The height of the protruding pattern 122a is controlled.

Subsequently, as shown in FIG. 1C, the back surface of the silicon substrate 1 is dry-etched (anisotropic dry etching) using the resist mask 21, and the through-hole 1 </ b> A exposing a part of the connection electrode 16 is formed. Form. Dry etching is performed at an etching rate of about 20 μm / min using a mixed gas of, for example, SF ₆ and C ₄ H ₈ as an etching gas, a gas pressure of 0.1 Torr, an input power of 500 W, for example. Etching is stopped by time control.

The dry etching of this embodiment is shown in detail in FIG. In FIG. 8, only the connection electrode 16 is illustrated for the active layer 2.
When dry etching is started from the state of FIG. 8A, the etching proceeds as shown in FIGS. 8B and 8C. As the etching proceeds, a recess is formed by the first pattern 21a on the back surface of the silicon substrate 1, and silicon is left in a columnar shape by the second pattern 21b on the bottom surface of the recess. At the same time, the second pattern 21b is also etched away. Then, the second pattern 21b disappears during the etching. Thereafter, until the etching is completed, the recesses and the columnar portions of the silicon substrate 1 are similarly etched. Even in the absence of the second pattern 21b, the columnar part functions as a self-mask, so that the columnar part is etched while the shape is maintained, but the columnar part is also etched in the same manner as the depression and the height is increased. Lower. As shown in FIG. 8D, the etching is finished when a part of the connection electrode 16 is exposed. At this time, the columnar portion of silicon is defined as a columnar protrusion 1b. The columnar protrusion 1b is formed at a desired height defined from the receding rate of the second pattern 21b shown in FIG.

Through the above-described collective dry etching, the back surface of the silicon substrate 1 is dry-etched, and the through hole 1A exposing a part of the connection electrode 16 is formed in a self-aligning manner. The through-hole 1A is defined by a first hole 1Aa having a large diameter (about 200 μm) defined by the first pattern 21a and a plurality of columnar protrusions 1b defined by the second pattern 21b. 2 apertures 1Ab are connected. The first opening 1Aa is a low aspect ratio opening pattern that is easy to process. Due to the presence of the plurality of columnar protrusions 1b, the second opening 1Ab has a total opening area smaller than the opening area of the first opening 1Aa, and has an intricate beam-like opening pattern. In the present embodiment, the outermost surface of the through hole 1A is defined by the first opening 1Aa. That is, the through-hole 1A is formed by the batch dry etching so that the outermost surface S1 of the first opening 1Aa and the outermost surface S2 of the second opening 1Ab are smoothly integrated without having a bending point. The
The remaining first pattern 21a is removed by ashing or wet etching using a chemical solution.

  The through-hole 1A may be formed by collective dry etching so that the outermost surface is slightly tapered. Also in this case, the through hole 1A is formed by smoothly integrating the outermost surface S1 of the first opening 1Aa and the outermost surface S2 of the second opening 1Ab without a bending point.

Subsequently, as shown in FIG. 2A, a protective film 22 covering the inner wall surface of the through hole 1A is formed.
Specifically, an insulator having a function of preventing the diffusion of Cu into the silicon substrate 1 so as to cover the inner wall surface of the through hole 1A of the silicon substrate 1 by, for example, a CVD method, for example, SiN having a thickness of about 500 nm. accumulate. Thereby, the protective film 22 which covers the inner wall surface of the through hole 1A is formed.

Subsequently, as shown in FIG. 2B, the protective film 22 on the bottom portion of the through hole 1A (the bottom portion of the second opening 1Ab) is removed.
More specifically, a resist mask having an opening formed at a position aligned with the bottom portion of the bottom portion of the second opening 1Ab is formed on the back surface of the silicon substrate 1 in the through hole 1A, and this resist mask is used. Perform bottom etching. As a result, the protective film 22 is removed only at the bottom of the second opening 1Ab to form an opening 22a, and a part of the surface of the connection electrode 16 is exposed from the opening 22a.

Subsequently, as shown in FIG. 2C, a Cu layer 23 is formed.
More specifically, first, Ti is formed in order to have a thickness of about 20 μm and Cu to a thickness of about 100 nm so as to cover the inner wall surface of the through hole 1A of the silicon substrate 1 by physical sputtering, for example. As a result, a liner layer and a Cu seed layer (not shown) are formed to cover the inner wall surface of the through hole 1A of the silicon substrate 1 directly at the opening 22a of the protective film 22 and through the protective film 22 at other portions. The

Next, the Cu layer 23 is formed.
The Cu layer 23 is formed by, for example, an electrolytic plating method and a semi-additive method. Specifically, a resist mask 24 having a through hole 1A and an opening 24a that appropriately exposes the periphery thereof is formed on the back surface of the silicon substrate 1. Cu is plated to a thickness of, for example, about 5 μm to 20 μm on the portion exposed from the opening 24 a of the resist mask 24 by electrolytic plating. The Cu layer 23 may be formed so as to fill the through hole 1A. Thereby, the second opening 1Ab in the through hole 1A is filled with Cu, and the Cu layer 23 covering the inner wall surface of the first opening 1Aa is formed. Thus, the through via 30 in which the Cu layer 25 is arranged in the through hole 1A is formed. The through via 30 has a first electrode portion 30a formed in the first opening 1Aa in the through hole 1A and a second electrode portion 30b formed in the second opening 1Ab. The outermost surface does not have a bending point and is integrally formed smoothly. In the through via 30, the second electrode portion 30 b is electrically connected to the connection electrode 16 through the opening 22 a of the protective film 22. The second electrode portion 30b has a beam shape that is complicated by following the second opening 1Ab and has a shape that is difficult to be thermally deformed, and the occurrence of pumping reaction is suppressed.
The resist mask 24 is removed by ashing or wet etching using a chemical solution.

  Instead of plating the Cu layer 23, the metal layer may be formed by a metal filling method using a conductive paste. As a metal filling method, there is a method of filling the through hole 1A with powder metal by press fitting. As the powder metal, Cu, Al, In, or the like can be used, but an alloy in which In, Sn, or Cu is mixed may be used.

Subsequently, as shown in FIG. 3A, a wiring protective film 25 is formed.
Specifically, an insulator, here TEOS, is deposited to a thickness of, for example, about 2 μm on the entire surface including the inner wall surface of the through hole 1A on the back surface of the silicon substrate 1. A portion adjacent to the through hole 1A of the deposited TEOS is removed by lithography and dry etching. As described above, the opening 25a that covers the Cu layer 25 in the through hole 1A and extends to the back surface of the silicon substrate 1 and exposes a part of the surface of the Cu layer 25 in the vicinity of the through hole 1A on the back surface of the silicon substrate 1 is formed. A wiring protective film 27 is formed.

Subsequently, bump balls 26 are formed as shown in FIG.
Specifically, the bump ball 26 is disposed on the Cu layer 25 exposed at the opening 25 a of the wiring protective film 25.
Thereafter, each chip is cut out from the silicon substrate 1 by dicing to form the semiconductor chip according to the present embodiment.

  As described above, in the present embodiment, in suppressing the deformation due to the difference in thermal expansion coefficient between the through via 30 and the silicon substrate 1 or the like, it is caused by the side shape of the through via without increasing the number of steps of the manufacturing process. This realizes a highly reliable semiconductor chip that suppresses deterioration of device characteristics.

-Modification-
Hereinafter, various modifications of the first embodiment will be described. In these modified examples, in the collective dry etching described in the first embodiment, a through hole having a shape different from that of the above-described through hole 1A is formed. Other processes are the same as those in the first embodiment. In addition, about the structural member etc. similar to 1st Embodiment, the same code | symbol is attached | subjected and detailed description is abbreviate | omitted.

(Modification 1)
FIG. 9 is a schematic plan view showing a resist mask used in forming a through via in Modification 1 of the first embodiment.

In this example, a resist mask 31 is formed on the back surface of the silicon substrate 1 as shown in FIG.
In detail, a resist is applied to a thickness of about 10 μm, for example, on a portion of the back surface of the silicon substrate 1 where a later-described through via is to be formed (location aligned with the connection electrode 16), and is processed by lithography to form a resist pattern 31. Form. The state of the resist mask 31 is shown in the plan view of FIG. 10 together with FIG. A cross section taken along one-dot chain line II in FIG. 10 corresponds to FIG. The resist mask 31 includes a first pattern 31a that exposes the back surface of the silicon substrate 1 in a predetermined shape, and a plurality of second patterns that are formed in the shape of columnar protrusions at portions exposed from the first pattern 31a of the silicon substrate 1. 31b. The first pattern 31a has an opening shape in which an annular opening surrounding each second pattern 31b communicates in a rectangular shape as a whole.

Then, as shown in FIG. 9B, the back surface of the silicon substrate 1 is collectively dry etched using the resist mask 31. The etching conditions are the same as those in the first embodiment.
Through the collective dry etching described above, a through hole 1B exposing a part of the connection electrode 16 is formed on the back surface of the silicon substrate 1 in a self-aligning manner. The second pattern 31b disappears during the etching. The through hole 1B is a second opening defined by a first opening 1Ba having a large opening area defined by the first pattern 31a and a plurality of columnar protrusions 1c defined by the second pattern 31b. The hole 1Bb is connected. The first opening 1Ba is an opening pattern with a low aspect ratio that is easy to process. Due to the presence of the plurality of columnar protrusions 1c, the second opening 1Bb has a total opening area smaller than the opening area of the first opening 1Ba, and has an intricate beam-like opening pattern. In this example, the outermost surface of the through hole 1B is defined by the first opening 1Ba. That is, the through hole 1B is formed by the batch dry etching so that the outermost surface S1 of the first opening 1Ba and the outermost surface S2 of the second opening 1Bb are smoothly integrated without having a bending point. The
The remaining first pattern 31a is removed by ashing or wet etching using a chemical solution.

  As described above, in this example, in suppressing the deformation due to the difference in thermal expansion coefficient between the through via and the silicon substrate 1 or the like, the device resulting from the side shape of the through via without increasing the number of manufacturing process steps. A highly reliable semiconductor chip that suppresses deterioration of characteristics is realized.

(Modification 2)
FIG. 11 is a schematic plan view showing a resist mask used when forming a through via in Modification 2 of the first embodiment.

In this example, a resist mask 41 is formed on the back surface of the silicon substrate 1 as shown in FIG.
More specifically, a resist is applied to a thickness of, for example, about 10 μm in a through via formation planned site (a site aligned with the connection electrode 16), which will be described later, on the back surface of the silicon substrate 1 and processed by lithography to form a resist pattern 41. Form. The state of the resist mask 41 is shown in the plan view of FIG. 12 together with FIG. A cross section taken along one-dot chain line II in FIG. 12 corresponds to FIG. The resist mask 41 includes a first pattern 41a that exposes the back surface of the silicon substrate 1 in a predetermined shape, and a plurality of second patterns that are columnar protrusions exposed from the first pattern 41a of the silicon substrate 1. 41b. The 1st pattern 41a is made into the opening shape which the circular opening surrounding each 2nd pattern 41b becomes circular as a whole, and is connected.

Then, as shown in FIG. 11B, the back surface of the silicon substrate 1 is collectively dry etched using the resist mask 41. The etching conditions are the same as those in the first embodiment.
Through the collective dry etching described above, a through-hole 1C exposing a part of the connection electrode 16 is formed on the back surface of the silicon substrate 1 in a self-aligning manner. The second pattern 41b disappears during the etching. The through-hole 1C has a second opening defined by a first opening 1Ca having a large opening area defined by the first pattern 41a and a plurality of columnar protrusions 1d defined by the second pattern 41b. The hole 1Cb is connected. The first opening 1Ca is a low aspect ratio opening pattern that is easy to process. Due to the presence of the plurality of columnar protrusions 1d, the second opening 1Cb has a total opening area smaller than the opening area of the first opening 1Ca, and has an intricate beam-like opening pattern. In this example, the outermost surface of the through hole 1C is defined by the first opening 1Ca. That is, the through hole 1C is formed by smoothly integrating the outermost surface S1 of the first opening 1Ca and the outermost surface S2 of the second opening 1Cb without any bending point by the collective dry etching. The
The remaining first pattern 41a is removed by ashing or wet etching using a chemical solution.

  As described above, in this example, in suppressing the deformation due to the difference in thermal expansion coefficient between the through via and the silicon substrate 1 or the like, the device resulting from the side shape of the through via without increasing the number of manufacturing process steps. A highly reliable semiconductor chip that suppresses deterioration of characteristics is realized.

(Modification 3)
FIG. 13 is a schematic plan view showing a resist mask used when forming a through via in Modification 3 of the first embodiment.

In this example, a resist mask 51 is formed on the back surface of the silicon substrate 1 as shown in FIG.
More specifically, a resist is applied to a portion to be formed with a through via (to be aligned with the connection electrode 16), which will be described later, on the back surface of the silicon substrate 1 to a thickness of, for example, about 10 μm and processed by lithography to form a resist pattern 51. Form. The state of the resist mask 51 is shown in the plan view of FIG. 14 together with FIG. A cross section taken along one-dot chain line II in FIG. 14 corresponds to FIG. The resist mask 51 includes a first pattern 51a that exposes the back surface of the silicon substrate 1 in a predetermined shape, and a plurality of second patterns that are columnar protrusions formed at portions exposed from the first pattern 51a of the silicon substrate 1. 51b. The first pattern 51a has an opening shape that surrounds each second pattern 51b and communicates with a rectangular outer shape.

Then, as shown in FIG. 13B, the back surface of the silicon substrate 1 is collectively dry etched using the resist mask 51. The etching conditions are the same as those in the first embodiment.
Through the collective dry etching described above, a through hole 1D exposing a part of the connection electrode 16 is formed on the back surface of the silicon substrate 1 in a self-aligning manner. The second pattern 51b disappears during the etching. The through hole 1D is a second opening defined by a first opening 1Da having a large opening area defined by the first pattern 51a and a plurality of columnar protrusions 1e defined by the second pattern 51b. The hole 1Db is connected. The first opening 1Da is a low aspect ratio opening pattern that is easy to process. Due to the presence of the plurality of columnar protrusions 1e, the second opening 1Db has a total opening area smaller than the opening area of the first opening 1Da, and has an intricate beam-like opening pattern. In this example, the outermost surface of the through hole 1D is defined by the first opening 1Da. That is, the through hole 1D is formed by the batch dry etching so that the outermost surface S1 of the first opening 1Da and the outermost surface S2 of the second opening 1Db are smoothly integrated without having a bending point. The
The remaining first pattern 51a is removed by ashing or wet etching using a chemical solution.

  As described above, in this example, in suppressing the deformation due to the difference in thermal expansion coefficient between the through via and the silicon substrate 1 or the like, the device resulting from the side shape of the through via without increasing the number of manufacturing process steps. A highly reliable semiconductor chip that suppresses deterioration of characteristics is realized.

(Second Embodiment)
Hereinafter, the second embodiment will be described. In the present embodiment, a semiconductor chip is manufactured in the same manner as in the first embodiment, but differs in that the through via formed in the batch dry etching is different. In addition, about the structural member etc. similar to 1st Embodiment, the same code | symbol is attached | subjected and detailed description is abbreviate | omitted.
FIG. 15 is a schematic cross-sectional view showing the main steps of the semiconductor chip manufacturing method according to the second embodiment.

  First, as in the first embodiment, the process of FIG. 1A is executed to form the active layer 2 on the surface of the silicon substrate 1.

Subsequently, as shown in FIG. 15A, a resist mask 61 is formed on the back surface of the silicon substrate 1.
More specifically, a resist is applied to a thickness of about 10 μm, for example, on a portion of the back surface of the silicon substrate 1 where a through via is to be formed (a position aligned with the connection electrode 16), which will be described later, and is processed by lithography to form a resist pattern 61. Form. The state of the resist mask 61 is shown in the plan view of FIG. 16 together with FIG. A cross section taken along the broken line II in FIG. 16 corresponds to FIG. The resist mask 61 includes a first pattern 61a that exposes the back surface of the silicon substrate 1 in a predetermined shape, and a second pattern 61b that has a beam shape that is intricately exposed at a portion exposed from the first pattern 61a of the silicon substrate 1. It is comprised. The first pattern 61a is, for example, a circular opening pattern having an opening diameter of about 200 μm. The second pattern 61b has a trapezoidal shape in which the upper base width is smaller than the lower base width in the longitudinal section so that the second pattern 61b disappears during the etching. In the present embodiment, similarly to the first embodiment, lithography is performed by detuned exposure, and the second pattern 61b is formed in the above-described trapezoidal shape by adjusting the light intensity and the light irradiation angle. . The inclination angle of the second pattern 61b is defined as a value within the range of 45 ° to 90 °.

Subsequently, as shown in FIG. 15B, the back surface of the silicon substrate 1 is collectively dry-etched using a resist mask 61 to form a through hole 1 </ b> E that exposes a part of the connection electrode 16. Etching conditions are the same as the etching of FIG. 1C in the first embodiment.
Through this collective dry etching, the back surface of the silicon substrate 1 is dry-etched, and a through hole 1E exposing a part of the connection electrode 16 is formed in a self-aligning manner. The through hole 1E includes a first opening 1Ea having a large diameter (about 200 μm) defined by the first pattern 61a and a plurality of second openings having a small diameter (about 50 μm) defined by the second pattern 61b. The hole 1Eb is connected. The first opening 1Ea is a low aspect ratio opening pattern that is easy to process. Due to the presence of the plurality of beam-like structures 1f, the second opening 1Eb has a total opening area smaller than the opening area of the first opening 1Ea and has a circular opening pattern. In the present embodiment, the outermost surface of the through hole 1E is defined by the first opening 1Ea. That is, the through hole 1E is formed by the batch dry etching so that the outermost surface S1 of the first opening 1Ea and the outermost surface S2 of the second opening 1Eb are smoothly integrated without having a bending point. The
The remaining first pattern 61a is removed by ashing or wet etching using a chemical solution.

  Subsequently, similarly to the first embodiment, after the processes of FIGS. 2A to 2C, the process of FIG. 3A is performed. Thereby, as shown in FIG.15 (c), the through-via 40 by which the Cu layer 25 is distribute | arranged to the through-hole 1E is formed. In the through via 40, the first electrode portion 40a formed in the first opening 1Ea and the second electrode portion 40b formed in the second opening 1Eb are continuously formed in the through hole 1E. The outermost surface does not have a bending point and is integrally formed smoothly. In the through via 40, the second electrode portion 40 b is electrically connected to the connection electrode 16 through the opening 22 a of the protective film 22. The second electrode portion 40b has a small-diameter columnar shape that follows the second opening 1Eb and has a shape that is difficult to be thermally deformed, and the occurrence of pumping reaction is suppressed.

Then, after removing the resist mask 26, the bump ball 28 is formed through the steps shown in FIGS. 3B and 3C as in the first embodiment.
Thereafter, each chip is cut out from the silicon substrate 1 by dicing to form the semiconductor chip according to the present embodiment.

  As described above, in the present embodiment, in suppressing deformation due to the difference in thermal expansion coefficient between the through via 40 and the silicon substrate 1 or the like, it is caused by the side surface shape of the through via without increasing the number of steps of the manufacturing process. This realizes a highly reliable semiconductor chip that suppresses deterioration of device characteristics.

  In this embodiment as well, a through hole having a shape different from that of the above-described through hole 1E may be formed in the same manner as the various modifications of the first embodiment.

  Hereinafter, various aspects of the electronic device and the manufacturing method thereof will be collectively described as additional notes.

(Appendix 1) a substrate;
Wiring formed above the surface of the substrate;
The substrate penetrates from the back surface of the substrate, and in the depth direction of the substrate, a first opening and a second opening having a total opening area smaller than the first opening are the largest. An electronic device comprising: a through electrode formed in a through hole that is smoothly integrated on an outer surface.

  (Supplementary note 2) The through hole is formed such that the first opening is formed to a predetermined depth of the substrate, and the second opening is regulated by a columnar protrusion provided in the through hole. The electronic device according to appendix 1, characterized by:

  (Supplementary note 3) The electronic device according to Supplementary note 2, wherein the plurality of columnar protrusions made of a material of the substrate are arranged in parallel.

  (Additional remark 4) The said through-hole is formed by the said 1st opening being formed to the predetermined depth of the said board | substrate, and the said 2nd opening being controlled by the beam-like structure provided in the penetration. The electronic device as set forth in Appendix 1, wherein

(Appendix 5) A step of forming wiring above the surface of the substrate;
Forming a through-hole penetrating the substrate on the back surface of the substrate;
Forming a through electrode electrically connected to the wiring in the through hole, and
In the through-hole, in the depth direction of the substrate, the first opening and the second opening having a smaller total opening area than the first opening are smoothly integrated on the outermost surface. Thus, the manufacturing method of the electronic device characterized by forming in batch by an etching.

(Appendix 6) In the step of forming the through hole,
A mask having a first pattern opened corresponding to the first opening and a second pattern disappearing during etching corresponding to the second opening is formed on the back surface of the substrate. And
6. The method of manufacturing an electronic device according to appendix 5, wherein the first opening and the second opening are collectively formed by etching so as to penetrate the semiconductor substrate using the mask.

  (Additional remark 7) The said 2nd pattern is made into columnar shape, The manufacturing method of the electronic device of Additional remark 6 characterized by the above-mentioned.

  (Additional remark 8) The said 2nd pattern is made into beam shape, The manufacturing method of the electronic device of Additional remark 6 characterized by the above-mentioned.

  (Supplementary note 9) The mask according to any one of supplementary notes 6 to 8, wherein the mask has a trapezoidal shape in which the upper base width is smaller than the lower base width in the longitudinal section. Electronic device manufacturing method.

  (Supplementary Note 10) The second pattern is defined such that the trapezoidal taper angle is in a range of 45 ° to 90 °, and the depth of the second opening is controlled by the taper angle. The method for manufacturing an electronic device according to appendix 9, which is characterized by the above.

1,101 Silicon substrates 1A, 1B, 1C, 1D, 1E Through holes 1Aa, 1Ba, 1Ca, 1Da, 1Ea First openings 1Ab, 1Bb, 1Cb, 1Db, 1Eb Second openings 1b, 1c, 1d, 1e, 1f Columnar protrusion 2,102 Active layer 10 MOS transistor 11 Gate insulating film 12 Gate electrode 13 Source / drain region 14, 17 Interlayer insulating film 15 Connection plug 16 Connection electrode 18, 102a Wiring 20 Multilayer wiring layers 21, 24 31, 41, 51, 61, 121, 123 Resist masks 21a, 31a, 41a, 51a, 61a First pattern 21b, 31b, 41b, 51b, 61b Second pattern 22 Protective film 22a, 24a, 25a Opening 23 Cu Layer 25 Wiring protective film 26, 104 Bump ball 30, 40, 103, 111 30a, 40a, 112 a first electrode portion 30b, 40b, 113 patterns of the second electrode portion 114 bending point 122 the processed surface 122a protruding

Claims (6)

A substrate,
Wiring formed above the surface of the substrate;
The substrate penetrates from the back surface of the substrate, and in the depth direction of the substrate, a first opening and a second opening having a total opening area smaller than the first opening are the largest. An electronic device comprising: a through electrode formed in a through hole integrated on an outer surface.   The through hole is formed such that the first opening is formed to a predetermined depth of the substrate, and the second opening is restricted by a columnar protrusion provided in the through hole. The electronic device according to claim 1. Forming a wiring above the surface of the substrate;
Forming a through-hole penetrating the substrate on the back surface of the substrate;
Forming a through electrode electrically connected to the wiring in the through hole, and
In the through-hole, in the depth direction of the substrate, the first opening and the second opening having a smaller total opening area than the first opening are integrated on the outermost surface. , A method of manufacturing an electronic device, characterized by performing batch formation by etching. In the step of forming the through hole,
A mask having a first pattern opened corresponding to the first opening and a second pattern disappearing during etching corresponding to the second opening is formed on the back surface of the substrate. And
4. The method of manufacturing an electronic device according to claim 3, wherein the first opening and the second opening are collectively formed by etching so as to penetrate the semiconductor substrate using the mask. .   The method of manufacturing an electronic device according to claim 4, wherein the second pattern has a columnar shape.   The method of manufacturing an electronic device according to claim 4, wherein the second pattern has a beam shape.

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