JP2013020055A - Electro-optic device and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electro-optic device and an electronic apparatus in which conduction between substrates can be performed in a wide area without causing protrusion of a conducting material between substrates from a substrate edge, overlap of an electrode for conduction between substrates and a signal line, or the like.SOLUTION: When an electrode 6e on an element substrate side for conducting between substrates is formed on an element board 10 in an electro-optic device 100, a space 66 in a plurality of signal line formation regions 60 is used, where routing portions of a plurality of data lines 6a are extended from a substrate edge 10a into an image display region 100a. A sealing material 80 has a bent portion 85 formed to recess toward the image display region 100a, in a region where the electrode 6e in the element substrate side for conducting between substrates is disposed. A conducting material 90 between substrates is disposed inside the bent portion 85, the conducting material to extend along a substrate edge 20a of a counter substrate 20 opposing to the bent portion 85.

Description

  The present invention relates to an electro-optical device in which an inter-substrate conducting material is provided between a pair of substrates that hold an electro-optical material layer, and an electronic apparatus including the electro-optical device.

  Among various electro-optical devices, the liquid crystal device includes an element substrate having a pixel electrode or the like on one side and a counter substrate having a common electrode or the like bonded together with a sealing material, and the element substrate and the counter substrate. A liquid crystal layer as an electro-optical material layer is held in a region surrounded by a sealing material between the two. In such an electro-optical device, by providing an inter-substrate conductive material between the element substrate and the counter substrate, a common potential is supplied from the element substrate to the common electrode of the counter substrate via the inter-substrate conductive material. (See Patent Documents 1 and 2).

  Among Patent Documents 1 and 2, FIG. 3 of Patent Document 1 proposes a configuration in which an inter-substrate conductive material is provided in the form of a dot at the corner of the counter substrate between the element substrate and the counter substrate. . Further, FIG. 4 of Patent Document 2 proposes a configuration in which the inter-substrate conducting material is provided in a dotted shape at the bent portion of the sealing material.

FIG. 3 and the like of JP-A-2006-259691 Japanese Patent Laid-Open No. 10-228030, FIG.

  However, as in the configurations described in Patent Documents 1 and 2, when the inter-substrate conductive material is provided in a dot shape, the contact area between the element substrate side and the inter-substrate conductive material, and the counter substrate side and the inter-substrate conductive material Since the contact area is small, there is a problem that the resistance at the inter-substrate conductive portion using the inter-substrate conductive material is large. On the other hand, FIG. 2 of Patent Document 2 describes a configuration in which an inter-substrate conductive material is provided in a linear shape within a sealing material formation region. In such a configuration, a part of the width of the sealing material is used. Since the inter-substrate conductive material is provided, the formation width of the inter-substrate conductive material is extremely narrow. For this reason, it is difficult to solve the above problem.

  However, when the inter-substrate conductive material is provided so as to extend along the outer edge of the sealing material for the purpose of expanding the formation region of the inter-substrate conductive material, the cut surface of the counter substrate is cut when the counter substrate is cut. This causes problems such as the conductive material between the substrates overhanging. In addition, the inter-substrate conducting material can be provided in a wide area as long as the signal line such as the data line is formed. However, when the inter-substrate conducting electrode to which a common potential is applied is overlapped with the signal line, There is a problem that a parasitic capacitance is generated between the line and the inter-substrate conduction electrode, and a signal waveform is distorted.

  In view of the above problems, the problem of the present invention is that the inter-substrate conduction can be achieved over a wide area without causing the inter-substrate conduction material to protrude from the substrate edge or the overlap between the inter-substrate conduction electrode and the signal line. It is an object to provide an electro-optical device that can be performed, and an electronic apparatus including the electro-optical device.

  In order to solve the above problem, an electro-optical device according to the present invention includes a plurality of signal lines extending in a direction connecting a pixel electrode provided in an image display region, a substrate edge, and the image display region. A plurality of signal line forming regions existing in the extending direction of the substrate edge, and an element substrate provided on one surface side with an element substrate side inter-substrate conduction electrode provided between the plurality of signal line forming regions; A counter substrate provided on one side with a common electrode and a counter substrate side inter-substrate conduction electrode conducting to the common electrode at a position overlapping the element substrate side inter-substrate conduction electrode, and a substrate edge of the counter substrate The element substrate and the counter substrate are bonded to each other, and a bent portion bent so as to be recessed toward the image display region is provided in the region where the element substrate side inter-substrate conduction electrode is provided. Seal material provided An electro-optic material layer provided in a region surrounded by the sealing material between the element substrate and the counter substrate, and the bent portion and the bent portion are opposed between the element substrate and the counter substrate. Provided so as to extend along the substrate edge in a region sandwiched between the substrate edges of the counter substrate and to conduct the element substrate side inter-substrate conduction electrode and the counter substrate side inter-substrate conduction electrode. And a substrate-to-substrate conductive material.

  In the present invention, when the element substrate-side inter-substrate conduction electrode is provided on the element substrate, a plurality of signal line forming regions in which a plurality of signal lines extend from the substrate edge toward the image display region are used. Yes. As for the sealing material, a bent portion bent so as to be recessed toward the image display region is provided in the region where the element substrate side inter-substrate conductive electrode is provided, and the inter-substrate conductive material is bent inside the bent portion. Is provided so as to extend along the substrate edge of the counter substrate opposite to the substrate. Therefore, even when the inter-substrate conductive material is provided in a wide area to reduce the resistance at the inter-substrate conductive portion, the inter-substrate conductive material does not protrude from the substrate edge of the counter substrate, and the signal line and the element substrate It is possible to prevent the side-to-substrate conductive electrodes from overlapping.

  In the present invention, the end portion of the inter-substrate conductive material opposite to the image display region is closer to the image display region than a virtual line that linearly connects outer edges of both side portions sandwiching the bent portion in the sealing material. It is preferable to be located at. According to such a configuration, even when the sealing material and the substrate edge of the counter substrate are close to each other, the inter-substrate conductive material does not protrude from the substrate edge of the counter substrate.

  In the present invention, a pair of end portions of the signal lines located on both sides of the element substrate side inter-substrate conduction electrode in the plurality of signal line forming regions are inclined in the image display region so as to be close to each other. It is preferable that the bent portion has a hypotenuse extending toward the image display area while being inclined obliquely so as to be close to each other. According to such a configuration, the region surrounded by the bent portion can be maximized, so that the inter-substrate conductive material can be provided in a wide region.

  In the present invention, the bent portion has a side extending in parallel with the substrate edge of the counter substrate facing the bent portion, and the inter-substrate conductive material extends so as to be in contact with the side. Preferably it is. According to such a configuration, the inter-substrate conductive material can be provided in a wide region while reducing the size of the bent portion that is recessed toward the image display region.

  In the present invention, it is possible to adopt a configuration in which a part of the element substrate side inter-substrate conduction electrode overlaps with the sealing material in plan view.

  In the present invention, the sealing material includes a gap material for controlling a gap between the element substrate and the counter substrate, and the element substrate side inter-substrate conduction electrode is partially in a region overlapping with the sealing material. It is preferable that a portion having a low height from the surface of the element substrate is provided. According to this configuration, the element substrate side inter-substrate conduction electrode and the signal line are configured in the region where the seal material and the signal line formation region overlap and the region where the seal material overlaps the element substrate side inter-substrate conduction electrode. The difference in formation density of the conductive pattern can be reduced. Therefore, when the gap between the element substrate and the counter substrate is controlled by the gap material included in the sealing material, the region where the sealing material and the signal line forming region overlap, and the region where the sealing material overlaps the element substrate side inter-substrate conduction electrode The difference in the degree of contact between the gap material and the conductive pattern can be reduced. Therefore, variation in the gap between the element substrate and the counter substrate can be reduced.

  In the present invention, it is preferable that three or more signal line formation regions are provided in the extending direction of the substrate edge, and two or more element substrate side inter-substrate conduction electrodes are provided.

  An electro-optical device to which the present invention is applied is used in an electronic apparatus such as a liquid crystal television.

It is explanatory drawing of the electro-optical apparatus (display apparatus) to which this invention is applied. 1 is an exploded perspective view of an electro-optical device to which the present invention is applied. 1 is a block diagram showing an electrical configuration of an electro-optical device (liquid crystal device) to which the present invention is applied. It is explanatory drawing of the liquid crystal panel of the electro-optical apparatus to which this invention is applied. It is explanatory drawing of the pixel of the electro-optical apparatus to which this invention is applied. It is explanatory drawing of the conduction | electrical_connection part between board | substrates of the electro-optical apparatus to which this invention is applied. It is explanatory drawing which shows the structure of the drawing part of the electrode for element board | substrate side board | substrates of the element board | substrate used for the electro-optical apparatus to which this invention is applied, and a data line. FIG. 7 is an explanatory diagram illustrating a state in which a gap between an element substrate and a counter substrate is controlled by a gap material of a sealing material in an electro-optical device to which the invention is applied. It is explanatory drawing which expands and shows the electrode for element substrate side board | substrate conduction | electrical_connection provided in the electro-optical apparatus to which this invention is applied. It is explanatory drawing of the electrode for element | substrate board | substrate side board | substrate conduction | electrical_connection etc. which were provided in another electro-optical apparatus to which this invention is applied.

  An embodiment in which the present invention is applied to an electro-optical device for a liquid crystal television will be described with reference to the drawings. In the drawings to be referred to in the following description, the scales are different for each layer and each member so that each layer and each member have a size that can be recognized on the drawing. In addition, the number of wirings and terminals is also small. In the following description, directions that intersect each other in the in-plane direction of the light guide plate or the liquid crystal panel are defined as an X-axis direction and a Y-axis direction, and a direction that intersects the X-axis direction and the Y-axis direction is defined as a Z-axis direction. In the drawings referred to below, one side in the X-axis direction is the X1 side, the other side is the X2 side, one side in the Y-axis direction is the Y1 side, the other side is the Y2 side, and one side in the Z-axis direction The side is represented as the Z1 side (lower side), and the other side (the side from which illumination light or display light is emitted) is represented as the Z2 side (upper side).

[Configuration of electronic equipment]
FIG. 1 is an explanatory diagram of an electro-optical device (display device) to which the present invention is applied. FIGS. 1A and 1B are diagrams illustrating a state in which the electro-optical device is used in a liquid crystal television (electronic device). FIG. 3 is a perspective view of the electro-optical device. FIG. 2 is an exploded perspective view of the electro-optical device to which the present invention is applied.

  An electronic apparatus 2000 illustrated in FIG. 1A is a liquid crystal television, and includes the electro-optical device 100 illustrated in FIG. 1B, a television frame 2010, and the like. As shown in FIG. 2, the electro-optical device 100 includes a transmissive liquid crystal panel 100p as a display panel (electro-optical panel), and an illumination device 180 that supplies illumination light to the liquid crystal panel 100p. The illuminating device 180 includes a light guide plate 185 disposed so as to overlap the liquid crystal panel 100p, a plurality of light emitting elements disposed along a side end surface that is a light incident portion of the side end surfaces of the light guide plate 185, and the like (not shown). Z). In the electro-optical device 100, the illumination device 180 is held by a lower frame (not shown) such as a resin frame or a lower metal frame, and the liquid crystal panel 100p and the upper frame 150 are arranged on the upper side of the illumination device 180. Has been. The upper frame 150 is formed by pressing or the like on a thin metal plate such as a SUS plate, and has a rectangular upper plate portion 155 and four side plate portions 151 to 154 bent downward from the outer peripheral edge of the upper plate portion 155. It has. A rectangular window 156 that emits light emitted from the liquid crystal panel 100p is formed in the upper plate portion 155. The upper plate portion 155 covers the entire outer peripheral end portion of the display light emission side of the liquid crystal panel 100p. It covers all around.

  The liquid crystal panel 100p has a quadrangular planar shape, and as will be described in detail later, the element substrate 10 on which pixel electrodes (not shown) and the like are formed, and a predetermined gap with respect to the element substrate 10. And the counter substrate 20 disposed opposite to each other, and a sealing material for bonding the counter substrate 20 and the element substrate 10 together. The element substrate 10 and the counter substrate 20 are made of a light-transmitting substrate such as a glass substrate. In this embodiment, the counter substrate 20 is disposed on the display light emitting side, and the element substrate 10 is disposed on the lighting device 180 side. The liquid crystal panel 100p is configured as a TN (Twisted Nematic) method, an ECB (Electrically Controlled Birefringence) method, or a VAN (Vertical Aligned Nematic) method liquid crystal panel. A common electrode (not shown) is formed. An upper polarizing plate 118 is disposed on the upper surface of the liquid crystal panel 100p, and a lower polarizing plate 117 is disposed between the lower surface of the liquid crystal panel 100p and the lighting device 180. The element substrate 10 may be disposed on the display light emitting side with respect to the counter substrate 20. When the liquid crystal panel 100p is an IPS (In Plane Switching) type or FFS (Fringe Field Switching) type liquid crystal panel, the common electrode is provided on the element substrate 10 side. Even if the liquid crystal panel 100p is an IPS liquid crystal panel or an FFS liquid crystal panel, a common electrode may be formed on the counter substrate 20 side for the purpose of shielding or the like.

  Here, the element substrate 10 is larger than the counter substrate 20. For this reason, the element substrate 10 has an overhang region 110 projecting from the end portion of the counter substrate 20 to the one side Y1 in the Y-axis direction and an overhang region 120 projecting from the end portion of the counter substrate 20 to the other side X2 in the X-axis direction. have. A flexible wiring board 200 is connected to the upper surfaces of the overhang regions 110 and 120. The flexible wiring board 200 has a structure in which a plurality of flexible wiring boards 200 are connected to the overhanging regions 110 and 120. The flexible wiring board 200 or a circuit board (not shown) connected to the flexible wiring board 200 includes a liquid crystal panel. A driving IC (not shown) for supplying data signals and scanning signals to 100p and a light source driving IC (not shown) for the illumination device 180 are mounted.

[Configuration of the electro-optical device 100]
(overall structure)
FIG. 3 is a block diagram showing an electrical configuration of the electro-optical device 100 (liquid crystal device) to which the present invention is applied. In FIG. 3, the electro-optical device 100 has a liquid crystal panel 100p in a TN (Twisted Nematic) mode or a VA (Vertical Alignment) mode, and the liquid crystal panel 100p has a plurality of pixels 100c in a matrix in the central region. The image display area 100a (effective pixel area) is arranged. In the liquid crystal panel 100p, in an element substrate 10 (see FIG. 4 and the like) described later, a plurality of data lines 6a (image signal lines) and a plurality of scanning lines 3a extend vertically and horizontally inside the image display region 100a. The pixel 100c is configured at a position corresponding to the intersection. In each of the plurality of pixels 100c, a pixel transistor 100t made of a field effect transistor and a pixel electrode 9a described later are formed. The data line 6a is electrically connected to the source of the pixel transistor 100t, the scanning line 3a is electrically connected to the gate of the pixel transistor 100t, and the pixel electrode 9a is electrically connected to the drain of the pixel transistor 100t. Has been.

  The electro-optical device 100 includes a scanning line driving circuit 104 and a data line driving circuit 101 in a driving IC mounted on the flexible wiring board 200. The data line driving circuit 101 transmits a data signal to each data line 6a. (Image signal) is sequentially supplied. The scanning line driving circuit 104 sequentially supplies a scanning signal to each scanning line 3a.

  In each pixel 100c, the pixel electrode 9a opposes a common electrode formed on a counter substrate 20 (see FIG. 4 and the like), which will be described later, via a liquid crystal layer as an electro-optical material layer, and forms a liquid crystal capacitor 50a. Yes. Each pixel 100c is provided with a holding capacitor 55 in parallel with the liquid crystal capacitor 50a in order to prevent fluctuations in the image signal held in the liquid crystal capacitor 50a. In this embodiment, in order to form the storage capacitor 55, the capacitor line 5b extending in parallel with the scanning line 3a is formed across the plurality of pixels 100c. In this embodiment, the common potential Vcom is applied to the capacitor line 5b.

(Specific configuration example of the liquid crystal panel 100p)
FIG. 4 is an explanatory diagram of the liquid crystal panel 100p of the electro-optical device 100 to which the present invention is applied. FIGS. 4A and 4B show the liquid crystal panel 100p together with the respective components from the counter substrate 20 side. FIG. 6 is a plan view and a sectional view taken along the line HH ′. In FIG. 4, the number of pixel electrodes 9a, signal lines, terminals, and the like is small.

  As shown in FIG. 4, in the liquid crystal panel 100p, the element substrate 10 and the counter substrate 20 are both rectangular translucent substrates. Therefore, the element substrate 10 includes four substrate edges 10a to 10d, and the counter substrate 20 includes four substrate edges 20a to 20d extending along the four substrate edges 10a to 10d of the element substrate 10. . The element substrate 10 and the counter substrate 20 are bonded together by a sealing material 80 provided in a square frame shape along the four substrate edges 20a to 20d of the counter substrate 20, and the sealing material 80 includes four sides 80a to 80a. 80d. The sealing material 80 is an adhesive made of a photo-curing resin, a thermosetting resin, or the like, and is blended with a gap material 81 such as glass fiber or glass beads for setting the distance between both substrates to a predetermined value. . In this embodiment, the sealing material 80 extends along the substrate edges 20 a to 20 d of the counter substrate 20 with substantially the same width dimension. Note that a part of the side 80b is cut off as a liquid crystal injection port 80r in the sealing material 80, and the liquid crystal injection port 80r is filled with a sealing material 88 after injecting a liquid crystal material.

  In the approximate center of the liquid crystal panel 100p, the image display area 100a described with reference to FIG. 1 is provided as a rectangular area. In the liquid crystal panel 100p, in the projecting regions 110 and 120 of the element substrate 10 projecting from the substrate edge 20a of the counter substrate 20, a plurality of terminals 102a are arranged along the substrate edge 10a. In the projecting region 120 of the element substrate 10 projecting from 20d, a plurality of terminals 102b are arranged along the substrate edge 10d. The terminals 102 a and 102 b are terminals for connecting the flexible wiring board 200. In this embodiment, three flexible wiring boards 201, 202, and 203 are connected to the terminal 102a as the flexible wiring board 200, and two flexible wiring boards 206 and 207 are connected to the terminal 102b as the flexible wiring board 200. Has been.

  In the element substrate 10, extending portions of the plurality of data lines 6a extend from the terminal 102a (substrate edge 10a side) toward the image display region 100a, and the extending portions of the data lines 6a are connected to the substrate edge 10a. It extends in the direction connecting the image display area 100a. Here, the formation region of the routing portion of the data line 6a is divided into three signal line formation regions 60 (signal line formation regions 61, 62, 63) corresponding to the three flexible wiring boards 201, 202, 203. ing. For this reason, the space 66 between the three signal line forming regions 60 is an empty region where the data line 6a is not formed. Further, the drawn portion of the data line 6a extends obliquely outside the image display area 100a, but extends linearly in the Y-axis direction inside the image display area 100a and extends in the X-axis direction. Then, it is equally spaced.

  In the element substrate 10, a plurality of scanning lines 3 a are extended from the terminal 102 b (the substrate edge 10 d side) toward the image display region 100 a, and the scanning lines 3 a are connected to the substrate edge. 10d extends in a direction connecting the image display area 100a. Here, the formation region of the routing portion of the scanning line 3 a is divided into two signal line formation regions 30 (signal line formation regions 31 and 32) corresponding to the two flexible wiring boards 206 and 207. For this reason, a space between the two signal line formation regions 30 is an empty region where the scanning lines 3a are not formed. Further, the extended portion of the scanning line 3a extends obliquely outside the image display region 100a, but extends linearly in the X-axis direction inside the image display region 100a, and in the Y-axis direction. Then, it is equally spaced.

  As shown in FIG. 4B, the image display region 100a is described with reference to FIG. 3 on the one surface 10s of the element substrate 10 that faces the counter substrate 20 out of the one surface 10s and the other surface 10t. A pixel transistor (not shown) and a translucent pixel electrode 9a electrically connected to the pixel transistor are formed in a matrix, and an alignment film 16 is formed on the upper side of the pixel electrode 9a. . In addition, on one surface 10s of the element substrate 10, a dummy pixel formed simultaneously with the pixel electrode 9a in a rectangular frame-shaped peripheral region 100s sandwiched between the image display region 100a and the sealing material 80 in the outer peripheral region 100r. Electrode 9b is formed. In the dummy pixel electrode 9b, adjacent dummy pixel electrodes 9b are connected to each other by a narrow connecting portion. The dummy pixel electrode 9b is applied with the common potential Vcom, and prevents the disorder of the alignment of the liquid crystal molecules at the outer peripheral side end of the image display region 100a.

  A translucent common electrode 21 (liquid crystal driving electrode) is formed on the opposite substrate 20 on the one surface 20 s side facing the element substrate 10. The common electrode 21 is formed across the plurality of pixels 100c as substantially the entire surface of the counter substrate 20 or a plurality of strip electrodes.

  A light shielding layer 29 is formed on the lower side of the common electrode 21 on the one surface 20 s side facing the element substrate 10 out of the one surface 20 s and the other surface 20 t of the counter substrate 20. An alignment film 26 is laminated. In this embodiment, the light shielding layer 29 includes a frame portion 29a extending along the outer peripheral edge of the image display region 100a, and a black matrix portion 29b overlapping the inter-pixel region 10f sandwiched between adjacent pixel electrodes 9a. Here, the frame portion 29 a is formed at a position overlapping the dummy pixel electrode 9 b, and the outer peripheral edge of the frame portion 29 a is at a position with a gap between the inner peripheral edge of the sealing material 80. Accordingly, the frame portion 29a and the sealing material 80 do not overlap. As described with reference to FIG. 5, a color filter layer and the like are also formed on the one surface 20 s side of the counter substrate 20.

  In the liquid crystal panel 100p configured as described above, as will be described in detail later, between the substrate edge 10a of the element substrate 10 and the image display region 100a (between the substrate edge 20a of the counter substrate 20 and the image display region 100a). The inter-substrate conducting portion 190 that conducts the element substrate 10 and the counter substrate 20 is configured.

  More specifically, the element substrate side inter-substrate conduction electrode 6e is formed on the one surface 10s of the element substrate 10 at a position overlapping the counter substrate 20 outside the sealing material 80, and between the element substrate side substrates. A common potential Vcom is applied to the conducting electrode 6e. Further, on one surface 20s of the counter substrate 20, a counter substrate side inter-substrate conduction electrode 21e is formed in a region overlapping with the element substrate side inter-substrate conduction electrode 6e, and the counter substrate side inter-substrate conduction electrode 21e. Is electrically connected to the common electrode 21. In this embodiment, the counter substrate side inter-substrate conduction electrode 21 e is formed of a part of the common electrode 21. Further, between the element substrate 10 and the counter substrate 20, an inter-substrate conductive material 90 including conductive particles 91 is provided between the element substrate-side inter-substrate conductive electrode 6e and the counter substrate-side inter-substrate conductive electrode 21e. Has been placed. Therefore, the common potential Vcom is applied to the common electrode 21 from the element substrate 10 side. The conductive particles 91 have a configuration in which a metal layer such as a silver layer or a gold layer is formed on metal particles or glass or plastic particles.

(Specific pixel configuration)
5A and 5B are explanatory diagrams of the pixel 100c of the electro-optical device 100 to which the present invention is applied. FIGS. 5A and 5B are a plan view of a plurality of adjacent pixels in the element substrate 10, and FF. FIG. 6 is a cross-sectional view of the electro-optical device 100 cut at a position corresponding to the line '. In FIG. 5A, the semiconductor layer 1a is indicated by a thin and short dotted line, the scanning line 3a is indicated by a thick solid line, the data line 6a and a thin film formed simultaneously with it are indicated by a one-dot chain line, and the capacitance line 5b is indicated by two lines. The pixel electrode 9a is indicated by a long broken line, and the lower electrode layer 4a is indicated by a thin solid line. In the element substrate 10, the dielectric layer 42a is formed. However, since the dielectric layer 42a is formed in a region overlapping the capacitance line 5b, the illustration is omitted in FIG. Further, although there is an opening edge of the etching stopper layer 40a along the outer peripheral edge of the lower electrode layer 4a, the opening edge is not shown in FIG.

  As shown in FIG. 5A, a rectangular pixel electrode 9a is formed on each of the plurality of pixels 100c on one surface 10s of the element substrate 10 facing the counter substrate 20, and adjacent pixel electrodes 9a. A data line 6a and a scanning line 3a are formed along a region overlapping the inter-pixel region 10f sandwiched between the two. In this embodiment, the inter-pixel region 10f extends vertically and horizontally, and the scanning line 3a and the data line 6a are linearly formed so as to overlap the inter-pixel region 10f. More specifically, the data line 6a extends linearly along a region overlapping the first inter-pixel region 10g extending in the first direction (Y-axis direction) in the inter-pixel region 10f, and the second The scanning line 3a extends linearly along a region overlapping the second inter-pixel region 10h extending in the direction (X-axis direction).

  A pixel transistor 100t is formed corresponding to the intersection of the data line 6a and the scanning line 3a. In this embodiment, the pixel transistor 100t is formed in a region where the data line 6a and the scanning line 3a intersect. Yes. A capacitance line 5b is formed on the element substrate 10 so as to overlap the scanning line 3a, and a common potential Vcom is applied to the capacitance line 5b. In this embodiment, the capacitor line 5b includes a main line portion extending linearly so as to overlap the scanning line 3a, and a sub-line portion extending so as to overlap the data line 6a at the intersection of the data line 6a and the scanning line 3a. It has.

  As shown in FIG. 5B, the element substrate 10 is formed on the liquid crystal layer 50 side substrate surface (one surface 10s facing the counter substrate 20) of the translucent substrate body 10w such as a quartz substrate or a glass substrate. The pixel electrode 9a, the pixel transistor 100t for pixel switching, and the alignment film 16 are mainly used. The counter substrate 20 includes a translucent substrate body 20w such as a quartz substrate or a glass substrate, a light shielding layer 29 formed on a surface of the liquid crystal layer 50 side (one surface 20s facing the element substrate 10), a common electrode 21, And the alignment film 26 as a main component.

  In the element substrate 10, a pixel transistor 100t including the semiconductor layer 1a is formed in each of the plurality of pixels 100c. The semiconductor layer 1a includes a channel region 1g, a source region 1b, and a drain region 1c that are opposed to the gate electrode 3c, which is a part of the scanning line 3a, via the translucent gate insulating layer 2. The source region 1b and the drain region 1c each have a low concentration region and a high concentration region. The semiconductor layer 1a is composed of, for example, a polycrystalline silicon film or the like formed on a transparent base insulating film 12 made of a silicon oxide film or the like on the substrate body 10w, and the gate insulating layer 2 is formed by a CVD method or the like. The silicon oxide film and the silicon nitride film formed by the above. For the scanning line 3a, a conductive polysilicon film, a metal silicide film, or a metal film is used. In the case where a light shielding layer overlapping the scanning line 3a is formed between the substrate body 10w and the base insulating film 12 or between the two layers of the base insulating film 12, the light shielding layer is referred to as the scanning line 3a. A structure in which the gate electrode 3c is electrically connected may be employed.

  A translucent first interlayer insulating film 41 made of a silicon oxide film or the like is formed on the upper layer side of the scanning line 3a, and a lower electrode layer 4a is formed on the upper layer of the first interlayer insulating film 41. The lower electrode layer 4a is formed in a substantially L-shape extending along the scanning line 3a and the data line 6a with a position where the scanning line 3a and the data line 6a intersect as a base point. The lower electrode layer 4a is made of a conductive polysilicon film, a metal silicide film, a metal film, or the like, and is electrically connected to the drain region 1c through the contact hole 7c.

  On the upper layer side of the lower electrode layer 4a, a dielectric layer 42a made of an insulating film having a high dielectric constant such as an aluminum oxide film, a titanium oxide film, a tantalum oxide film, a niobium oxide film, a hafnium oxide film, a lanthanum oxide film, or a zirconium oxide film. Is formed. On the upper layer side of the dielectric layer 42a, a capacitor line 5b is formed so as to face the lower electrode layer 4a through the dielectric layer 42a. The capacitor line 5b, the dielectric layer 42a and the lower electrode layer 4a hold the capacitor line 5b. A capacitor 55 is formed. The capacitor line 5b is made of a conductive polysilicon film, a metal silicide film, a metal film, or the like. Here, the lower electrode layer 4a, the dielectric layer 42a, and the capacitor line 5b are formed on the upper layer side of the pixel transistor 100t, and the storage capacitor 55 is planar with respect to at least the pixel transistor 100t on the upper layer side of the pixel transistor 100t. It is formed in a region that overlaps visually.

  In this embodiment, the dielectric layer 42a has substantially the same shape as the capacitor line 5b and is formed in the same region. In addition, the end edge 42g of the dielectric layer 42a and the end edge 5g of the capacitance line 5b are in a position overlapping the lower electrode layer 4a. An etching stopper layer 40a made of a silicon oxide film or the like is formed between the lower electrode layer 4a and the dielectric layer 42a, and the etching stopper layer 40a is a region partially overlapping the lower electrode layer 4a. An opening 40b is formed in the opening. For this reason, the lower electrode layer 4a and the capacitor line 5b are opposed to each other through the dielectric layer 42a in the opening 40b to form a storage capacitor 55. The etching stopper layer 40a is formed in a region that overlaps at least the edge 42g of the dielectric layer 42a and the edge 5g of the capacitance line 5b. In some cases, the etching stopper layer 40a is formed only in a region overlapping with the edge 42g of the dielectric layer 42a and the edge 5g of the capacitor line 5b.

  A translucent second interlayer insulating film 43 made of a silicon oxide film or the like is formed on the upper side of the capacitor line 5b, and a data line 6a and a drain electrode 6b are formed on the upper layer of the second interlayer insulating film 43. Yes. Data line 6a is electrically connected to source region 1b through contact hole 7a. The drain electrode 6b is electrically connected to the lower electrode layer 4a through the contact hole 7b, and is electrically connected to the drain region 1c through the lower electrode layer 4a. The data line 6a and the drain electrode 6b are made of a conductive polysilicon film, a metal silicide film, a metal film, or the like.

  A light-transmitting third interlayer insulating film 44 made of a silicon oxide film or the like is formed on the upper side of the data line 6a and the drain electrode 6b. In the third interlayer insulating film 44, a contact hole 7d leading to the drain electrode 6b is formed. A rectangular pixel electrode 9a made of a light-transmitting conductive film such as an ITO (Indium Tin Oxide) film is formed on the third interlayer insulating film 44. The pixel electrode 9a is drained through a contact hole 7d. It is electrically connected to the electrode 6b. A dummy pixel electrode 9b (not shown in FIG. 5A) described with reference to FIG. 4B and the like is formed on the surface of the third interlayer insulating film 44, and the dummy pixel electrode 9b Consists of a translucent conductive film formed simultaneously with the pixel electrode 9a.

An alignment film 16 is formed on the surface of the pixel electrode 9a. In this embodiment, the alignment film 16 is an obliquely deposited film of SiO _x (x <2), SiO ₂ , TiO ₂ , MgO, Al ₂ O ₃ , In ₂ O ₃ , Sb ₂ O ₃ , Ta ₂ O ₅ or the like. In this embodiment, the alignment film 16 is an obliquely deposited film of a silicon oxide film.

  In the counter substrate 20, aluminum, titanium, molybdenum, tungsten, chrome, and the like are formed on the surface of the translucent substrate body 20 w such as a quartz substrate or a glass substrate on the liquid crystal layer 50 side (surface facing the element substrate 10). A conductive light shielding layer 29 made of a compound, an alloy, or the like is formed. Of the light shielding layer 29, the black matrix portion 29b formed in the image display region 100a is an inter-pixel region 10f (FIG. 5A ) Etc.)) and extend vertically and horizontally.

In this embodiment, an aluminum alloy layer (aluminum metal layer) is used for the light shielding layer 29. A color filter layer 27, a protective film 28, and a common electrode 21 are formed on the upper layer of the light shielding layer 29 (the surface facing the element substrate 10), and the common electrode 21 is made of an ITO film. An alignment film 26 is formed on the upper layer of the light shielding layer 29 (the surface facing the element substrate 10). The alignment film 26 is similar to the alignment film 16, and is composed of SiO _x (x <2), SiO ₂ , TiO ₂ . ₂ , an inorganic alignment film (vertical alignment film) made of an obliquely deposited film such as MgO, Al ₂ O ₃ , In ₂ O ₃ , Sb ₂ O ₃ , Ta ₂ O ₅ . In this embodiment, the alignment film 26 is composed of an oblique vapor deposition film of a silicon oxide film.

  In the electro-optical device 100 configured as described above, a nematic liquid crystal compound having a negative dielectric anisotropy is used as the liquid crystal material. The alignment films 16 and 26 vertically align the liquid crystal material. Operate as a Mariblack VA mode.

(Planar configuration of the inter-substrate conductive portion 190)
FIGS. 6A and 6B are explanatory diagrams of the inter-substrate conduction unit 190 of the electro-optical device 100 to which the present invention is applied. FIGS. 6A and 6B are diagrams in a state where the element substrate 10 and the counter substrate 20 are bonded to each other. It is explanatory drawing which shows planar structures, such as the board | substrate conduction | electrical_connection part 190, and explanatory drawing which shows planar structures, such as the board | substrate conduction | electrical_connection part 190 of the element substrate 10 in the state before bonding the opposing board | substrate 20. FIG. In FIG. 6, the number of openings 6f formed in the element substrate side inter-substrate conduction electrode 6e is reduced.

  As shown in FIG. 4, in the electro-optical device 100 of this embodiment, when supplying the common potential Vcom from the element substrate 10 side to the common electrode 21, the element substrate 10, the counter substrate 20, The inter-substrate conducting part 190 is configured in the region where the two overlap. In this embodiment, the inter-substrate conductive portion is located near the sealing material 80 between the substrate edge 10a of the element substrate 10 and the image display region 100a (between the substrate edge 20a of the counter substrate 20 and the image display region 100a). Two 190 are configured. Here, since the configuration of the two inter-substrate conductive portions 190 is the same, the inter-substrate conductive portion 190 provided in the vicinity where the flexible wiring substrates 202 and 203 are connected will be described as an example. The description of the inter-substrate conducting portion 190 provided in the vicinity where the 202 is connected is omitted.

  In this embodiment, when configuring the inter-substrate conducting portion 190, first, as shown in FIG. 6, in the element substrate 10, a plurality of data lines 6a are routed from the substrate edge 10a toward the image display region 100a ( An element substrate side inter-substrate conduction electrode 6e is formed between the signal line forming regions 60 where the signal lines extend (66 between the signal line forming regions 62 and 63). The element substrate side inter-substrate conduction electrode 6 e is formed in a region overlapping the counter substrate 20. Further, in the counter substrate 20, the common electrode 21 is formed on the substantially entire surface of the one surface 20s. Therefore, a region of the common electrode 21 that overlaps the element substrate side inter-substrate conduction electrode 6e is illustrated in FIG. It is used as the counter substrate side inter-substrate conduction electrode 21e shown.

  Next, the sealing material 80 is provided along the substrate edges 20a to 20b of the counter substrate 20, and the element substrate 10 and the counter substrate 20 are bonded together. Here, the sealing material 80 is bent so as to be recessed toward the image display region 100 a in the region where the element substrate side inter-substrate conduction electrode 6 e is provided, and the bent portion 85 is formed in the signal line forming region 60. It is located in the space 66 and does not overlap the data line 6a.

  In this embodiment, the data line 6a routing portion (signal line) located at the end of the signal line forming region 60 sandwiching the element substrate side inter-substrate conducting electrode 6e on both sides is inclined while being inclined so as to be close to each other. It extends toward the display area 100a. Corresponding to this shape, the bent portion 85 includes sides 851 and 852 (slanted sides) extending obliquely along the end portions of the signal line forming region 60 between the signal line forming regions 60. The bent portion 85 has a side 853 extending in parallel with the substrate edge 20 a of the counter substrate 20 facing the bent portion 85.

  The element substrate side inter-substrate conducting electrode 6e includes a side 6e1 extending in parallel to the substrate edge 20a, a side 6e2 extending in parallel to the side 6e1 on the image display region 100a side with respect to the side 6e1, Two sides 6e3 and 6e5 extending from both ends of the side 6e1 toward the image display region 100a, a side 6e4 connecting the ends of the sides 6e3 and 6e2, and a side 6e6 connecting the ends of the sides 6e5 and 6e2 have. Here, the element substrate side inter-substrate conduction electrode 6e is formed in a region overlapping the bent portion 85 of the sealing material 80, and the element substrate side inter-substrate conduction electrode 6e is larger than the bent portion 85. is there. For this reason, the sealing material 80 overlaps with the part located on the image display region 100a side in the element substrate side inter-substrate conduction electrode 6e.

  In addition, a plurality of slit-like openings 6f extending in the X-axis direction are arranged in parallel in the Y-axis direction on the element substrate side inter-substrate conduction electrode 6e. Therefore, the element substrate side inter-substrate conduction electrode 6e has a narrow portion sandwiched between the openings 6f. In this embodiment, the sealing material 80 is formed of the element substrate side inter-substrate conduction electrode 6e. Of these, the opening 6f overlaps the region that is the narrow portion. As will be described later with reference to FIG. 8, the opening 6 f forms a portion where the height from the surface of the element substrate 10 is partially reduced in a region overlapping the sealing material 80. Thus, the density of the conductive film in the region overlapping with the sealing material 80 is adjusted. Instead of the slit-shaped opening 6f, the openings 6f may be formed in a lattice shape.

  Next, the inter-substrate conductive member 90 extends along the substrate edge 20 a in a region sandwiched between the bent portion 85 of the sealing material 80 and the substrate edge 20 a of the counter substrate 20 facing the bent portion 85. It is provided in a band shape. In the present embodiment, the inter-substrate conductive member 90 extends so as to be in contact with the side 853 that extends in parallel with the substrate edge 20 a at the bent portion 85. Therefore, the end of the inter-substrate conductive member 90 opposite to the image display region 100a is closer to the image display region 100a than the imaginary line that linearly connects the outer edges 80g of both side portions sandwiching the bent portion 85 in the sealant 80. The inter-substrate conductive member 90 does not protrude from the imaginary line that linearly connects the outer edges 80g toward the substrate edge 20a.

  According to such a configuration, for example, after the sealing material 80 and the inter-substrate conductive material 90 are applied to the element substrate 10, the counter substrate 20 is sandwiched between the element substrate 10 and the sealing material 80 and the inter-substrate conductive material 90. If overlapped, the element substrate 10 and the counter substrate 20 are bonded to each other with a sealing material 80 containing a gap material 81 through a predetermined gap, and the element substrate side inter-substrate conduction electrode 6e and the counter substrate side inter-substrate conductor are connected. The common electrode 21e is electrically connected by the inter-substrate conductive material 90 including the conductive particles 91.

  In this embodiment, the wiring 6j formed at the end of the signal line forming region 60 sandwiching the element substrate side inter-substrate conducting electrode 6e on both sides electrically connects the adjacent signal line forming regions 60 to each other. ing. The wiring 6j is, for example, a shield line or a synchronization signal line.

(Specific configuration of element substrate side inter-substrate conduction electrode 6e and data line 6a)
FIG. 7 is an explanatory diagram showing the configuration of the routing portion of the element substrate side inter-substrate conduction electrode 6e and the data line 6a of the element substrate 10 used in the electro-optical device 100 to which the present invention is applied. , (A2) are an explanatory view schematically showing the planar configuration of the element substrate side inter-substrate conduction electrode 6e, and an EE ′ sectional view schematically showing the sectional configuration, FIG. 7 (b1), ( b2) is an explanatory view schematically showing a planar configuration of the data line 6a, and an FF ′ sectional view schematically showing a sectional configuration. FIG. 8 is an explanatory diagram showing a state in which the gap between the element substrate 10 and the counter substrate 20 is controlled by the gap material 81 of the sealing material 80 in the electro-optical device 100 to which the present invention is applied. b) AA 'sectional drawing of FIG. 6, and BB' sectional drawing. FIG. 9 is an explanatory diagram showing, in an enlarged manner, the element substrate side inter-substrate conduction electrode 6e provided in the electro-optical device 100 to which the present invention is applied. In FIG. 7, the number of openings 6f formed in the element substrate side inter-substrate conduction electrode 6e is reduced. In FIG. 8, the illustration of the base insulating film 12, the second interlayer insulating film 43, etc. shown in FIGS. 7A2 and 7B2 is omitted. Further, in FIG. 9, a portion where the opening 6 f is at least necessary (a portion overlapping with the sealing material 80) is indicated by a hatched area, and the conductive protection of the element substrate side inter-substrate conduction electrode 6 e is shown. The part where the film is required is indicated by a hatched area.

  As shown in FIG. 7, in the electro-optical device 100 according to the present embodiment, the element substrate side inter-substrate conduction electrode 6e is the same conductive material formed on the second interlayer insulating film 43 as in the routing portion of the data line 6a. It consists of a membrane. Here, for the purpose of adjusting the height position of the element substrate side inter-substrate conduction electrode 6e and the height position of the routing portion of the data line 6a, the lower side of the element substrate side inter-substrate conduction electrode 6e, and The same conductive films 3e, 3t, 4e, 4t, 5e, 5t, and the like such as the scanning line 3a, the lower electrode layer 4a, and the capacitor line 5b shown in FIG. 4 are formed on the lower layer side of the routing portion of the data line 6a. Yes. Further, on the lower layer side of the element substrate side inter-substrate conducting electrode 6e and the lower layer side of the routing portion of the data line 6a, the base insulating film 12, the gate insulating layer 2, the first interlayer insulating film 41, the dielectric layer 42a, A second interlayer insulating film 43 and the like are also formed.

  A third interlayer insulating film 44 is formed on the upper layer side of the element substrate side inter-substrate conduction electrode 6e. Since the opening 44e is formed in the third interlayer insulating film 44, the element substrate side substrate The surface of the inter-electrode 6e is exposed. The opening 44e is formed by etching the third interlayer insulating film 44. At this time, the element substrate side inter-substrate conduction electrode 6e functions as an etching stopper. Therefore, the etching stopper layer 40a and the first interlayer insulating film 41 are not etched. In this embodiment, in the surface side of the element substrate side inter-substrate conducting electrode 6e, the region where the inter-substrate conducting material 90 is provided is formed simultaneously with the pixel electrode 9a shown in FIG. A conductive protective film 9g made of an ITO film is formed, and the conductive protective film 9g is electrically connected to the element substrate side inter-substrate conductive electrode 6e through the opening 44e of the third interlayer insulating film 44. . The conductive protective film 9g exhibits a function of preventing the surface of the metal film constituting the element substrate side inter-substrate conduction electrode 6e from being oxidized to increase the contact resistance. In this embodiment, when the opening 44e is formed, the element substrate side inter-substrate conduction electrode 6e functions as an etching stopper, so that the opening 44e reaches the conductive film 5e and the element substrate side inter-substrate conduction. A structure is adopted in which the electrode 6e and the conductive film 5e are electrically connected by the conductive protective film 9g. On the other hand, a third interlayer insulating film 44 is formed on the upper side of the routing portion of the data line 6a, and a convex portion caused by the routing portion of the data line 6a is formed on the surface of the third interlayer insulating film 44. 44t is formed.

  Here, since the element substrate side inter-substrate conduction electrode 6e is formed with the slit-shaped opening 6f, the region where the sealing material 80 is provided on the surface side of the element substrate side inter-substrate conduction electrode 6e. In addition, a convex portion 44 t is formed on the surface of the third interlayer insulating film 44. Therefore, as described below with reference to FIG. 8, the gap between the element substrate 10 and the counter substrate 20 can be accurately controlled by the gap material 81 of the sealing material 80.

  First, as shown in FIG. 8A, between the element substrate side inter-substrate conduction electrode 6e of the element substrate 10 and the common electrode 21 (opposite substrate side inter-substrate conduction electrode 21e) of the counter substrate 20, Although the gap material 81 of the sealing material 80 and the conductive particles 91 of the inter-substrate conductive material 90 are interposed, a material harder than the conductive particles 91 is used as the gap material 81. Therefore, even when the gap material 81 and the conductive particles 91 are interposed between the element substrate side inter-substrate conduction electrode 6e and the common electrode 21 (counter substrate side inter-substrate conduction electrode 21e), The gap with the counter substrate 20 can be controlled by the gap material 81.

  Next, as shown in FIGS. 8A and 8B, the gap material 81 of the sealing material 80 includes the element substrate side inter-substrate conduction electrode 6 e of the element substrate 10 and the common electrode 21 (counter substrate) of the counter substrate 20. It is interposed between the side substrate conduction electrode 21 e) and also between the counter substrate 20 and the routing portion of the data line 6 a of the element substrate 10. In the present embodiment, the common electrode 21 is not formed on the counter substrate 20 in a region facing the signal line forming region 60 where the routing portion of the data line 6a is formed. However, the thickness of the common electrode 21 is 100 nm, which is thin when viewed from the thickness (for example, 300 nm to 500 nm) of the conductive film constituting the element substrate side inter-substrate conduction electrode 6e and the routing portion of the data line 6a. The presence or absence of the common electrode 21 does not significantly affect the gap between the element substrate 10 and the counter substrate 20.

  Here, in the signal line formation region 60 in which the routing portion of the data line 6a is formed, the routing portion of the data line 6a is formed with a space in between, so that the third portion is formed by the routing portion of the data line 6a of the element substrate 10. The density of the gap material 81 in contact with the convex portion 44t formed on the surface of the interlayer insulating film 44 and the counter substrate 20 is low. Therefore, in this embodiment, the element substrate side inter-substrate conduction electrode 6e is provided with a slit-shaped opening 6f, and the surface side of the element substrate side inter-substrate conduction electrode 6e is provided in a region where the sealing material 80 is provided. Also, a convex portion 44 t is formed on the surface of the third interlayer insulating film 44. In this way, by reducing the density in contact with the gap material 81 in the element substrate side inter-substrate conduction electrode 6e, the element substrate side inter-substrate conduction electrode 6e of the element substrate 10 and the common electrode 21 (opposing the counter substrate 20). The density of the gap material 81 in contact with the substrate-side inter-substrate conduction electrode 21e) is reduced. Therefore, the density of the gap material 81 in contact with the element substrate side inter-substrate conduction electrode 6e of the element substrate 10 and the common electrode 21 (counter substrate side inter-substrate conduction electrode 21e) of the counter substrate 20, and the third interlayer insulating film The density of the gap material 81 in contact with the convex portion 44t of 44 and the counter substrate 20 is equal. Further, the third interlayer insulation in the region where the seal material 80 is provided in the height of the surface of the third interlayer insulating film 44 that overlaps with the routing portion of the data line 6a and the element substrate side inter-substrate conduction electrode 6e. The height of the surface of the film 44 is equivalent. Therefore, according to this embodiment, the gap member 81 is interposed between the element substrate side inter-substrate conduction electrode 6e of the element substrate 10 and the common electrode 21 (opposite substrate side inter-substrate conduction electrode 21e) of the counter substrate 20. In addition, the gap between the element substrate 10 and the counter substrate 20 can be controlled by the gap material 81 even when the data substrate 6 is interposed between the routing portion of the data line 6 a of the element substrate 10 and the counter substrate 20.

  In FIG. 9, a portion where the opening 6 f is the minimum necessary (portion overlapping with the sealing material 80) is indicated by a hatched region, and among the element substrate side inter-substrate conduction electrodes 6 e, A portion where the conductive protective film 9g is necessary is shown by a hatched region. The conductive protective film 9g may be formed so as to overlap the sealing material 80.

(Main effects of this form)
As described above, in the electro-optical device 100 according to this embodiment, when the element substrate-side inter-substrate conduction electrode 6e is provided on the element substrate 10, a plurality of data lines 6a from the substrate edge 10a toward the image display region 100a. A plurality of signal line forming regions 60 between the extended portions 66 are utilized. As for the sealing material 80, a bent portion 85 bent so as to be recessed toward the image display region 100a is provided in the region where the element substrate side inter-substrate conduction electrode 6e is provided, and between the substrates is provided inside the bent portion 85. The conductive material 90 is provided so as to extend along the substrate edge 20 a of the counter substrate 20 facing the bent portion 85. For this reason, even when the inter-substrate conductive material 90 is provided in a wide area to reduce the resistance at the inter-substrate conductive portion 190, the inter-substrate conductive material 90 does not protrude from the substrate edge 20a of the counter substrate 20, and data It is possible to prevent parasitic capacitance from occurring due to overlapping between the lead-out portion of the line 6a and the element substrate side inter-substrate conduction electrode 6e.

  Further, the end of the inter-substrate conductive member 90 opposite to the image display region 100a is closer to the image display region 100a than the imaginary line that linearly connects the outer edges 80g of both side portions sandwiching the bent portion 85 in the sealant 80. positioned. For this reason, even when the sealing material 80 and the substrate edge 20a of the counter substrate 20 are close to each other, the inter-substrate conductive material 90 from the substrate edge 20a of the counter substrate 20 does not protrude.

  Further, in the plurality of signal line forming regions 60, a pair of end portions located on both sides of the element substrate side inter-substrate conducting electrode 6e extend toward the image display region 100a while being inclined obliquely so as to be close to each other. The bent portion 85 includes sides 851 and 852 (slanted sides) extending obliquely in accordance with the shape. For this reason, since the area | region enclosed by the bending part 85 can be enlarged as much as possible, the board | substrate conduction | electrical_connection material 90 can be provided in a wide area | region.

  The bent portion 85 has a side 853 extending in parallel with the substrate edge 20a of the counter substrate 20 facing the bent portion 85, and the inter-substrate conductive member 90 extends so as to be in contact with the side 853. Yes. For this reason, even if the inter-substrate conductive material 90 is provided in a wide region while reducing the dimension in which the bent portion 85 is recessed toward the image display region 100a, the inter-substrate conductive material 90 moves from the bent portion 85 toward the substrate edge 20a. Overhang can be prevented.

  Further, in this embodiment, since the inter-substrate conductive portion 190 is provided at two places, the inter-substrate conductive material 90 can be provided in a wide region, so that the resistance at the inter-substrate conductive portion 190 can be reduced.

[Another embodiment]
FIG. 10 is an explanatory diagram of an element substrate side inter-substrate conduction electrode 6e and the like provided in another electro-optical device 100 to which the present invention is applied, and shows a portion corresponding to FIG. More specifically, FIGS. 10A and 10B are a cross-sectional view of a region where the element substrate side inter-substrate conduction electrode 6e is formed, and a region where the routing portion of the data line 6a is formed. It is sectional drawing. In FIG. 1 to FIG. 9, a field effect transistor having a top gate structure using a polysilicon film as the semiconductor layer 1a is configured as the pixel transistor 100t, but a bottom gate structure using an amorphous silicon film as the semiconductor layer 1a. The present invention may be applied to the electro-optical device 100 using a field effect transistor or the like as the pixel transistor 100t. In this case, as shown in FIG. 10, the data line 6 a and the element substrate side inter-substrate conduction electrode 6 e are formed on the surface of the gate insulating layer 2.

[Other embodiments]
In the above embodiment, the inter-substrate conductive portion 190 is provided at two locations, but the present invention may be applied when the inter-substrate conductive portion 190 is provided at one location, or at three or more locations. Further, for example, in the above embodiment, the inter-substrate conductive portion 190 is provided on the side where the data line 6a extends, but the inter-substrate conductive portion 190 is provided on the side where the scanning line 3a extends. Alternatively, the inter-substrate conductive portion 190 may be provided on both the side where the data line 6a extends and the side where the scanning line 3a extends.

  In the above embodiment, by supplying signals from the plurality of flexible wiring boards 200 connected to the element substrate 10 to the image display region 100a, a plurality of signal line formations in which the routing portions of the plurality of data lines 6a extend are formed. The region 60 is provided, and the element substrate side inter-substrate conduction electrode 6e is provided using the space 66 between the signal line forming regions 60. For example, by mounting a plurality of driving ICs on the element substrate 10, a plurality of driving ICs are mounted. The signal line forming region 60 may be provided. Even when the drive circuit is built in the element substrate 10 itself, a plurality of signal line formation regions 60 may be provided by incorporating a plurality of drive circuits in the element substrate 10.

  In the above embodiment, the transmissive electro-optical device 100 is exemplified as the electro-optical device 100. However, the substrate is used in a reflective liquid crystal device, a plasma display, a field emission display, an organic electroluminescence display, an electrophoretic display, or the like. The present invention may be applied to the case of conducting electrical conduction.

[Example of mounting on electronic devices]
In the above-described embodiment, the liquid crystal television is exemplified as the electronic device 2000 on which the electro-optical device 100 is mounted. However, in addition to the liquid crystal television, electronic devices such as a display of a personal computer, a digital signage, a car navigation device, and a portable information terminal. The electro-optical device 100 to which the present invention is applied may be used for the display unit.

6e .. Electrode for substrate-to-substrate conduction, 9a .. Pixel electrode, 10 .. Element substrate, 20 .. Opposite substrate, 21 .. Common electrode, 21e. · Liquid crystal layer (electro-optic material layer), 60 ·· Signal line forming region, 80 ·· Sealing material, 85 · · Bending portion, 90 · · Inter-substrate conductive material, 81 · · Gap material, 91 · · Conductive particles, 100..Electro-optical device, 100a..Image display area

Claims (8)

A plurality of signal lines extending in a direction connecting the pixel display, the substrate edge and the image display area provided in the image display area, and a plurality of signal line forming areas existing in the extending direction of the substrate edge And an element substrate including an element substrate side inter-substrate conduction electrode provided between the plurality of signal line forming regions on one surface side,
A counter substrate provided on one side with a common electrode and a counter substrate side inter-substrate conduction electrode conducting to the common electrode at a position overlapping the element substrate side inter-substrate conduction electrode;
Provided along the substrate edge of the counter substrate, the element substrate and the counter substrate are bonded together, and is recessed toward the image display region in the region where the element substrate side inter-substrate conduction electrode is provided. A sealing material having a bent portion bent like
An electro-optic material layer provided in a region surrounded by the sealing material between the element substrate and the counter substrate;
Provided between the element substrate and the counter substrate so as to extend along the substrate edge in a region sandwiched between the bent portion and the substrate edge of the counter substrate facing the bent portion. An inter-substrate conducting material for conducting the element substrate-side inter-substrate conducting electrode and the counter-substrate-side inter-substrate conducting electrode;
An electro-optical device comprising:   An end portion of the inter-substrate conductive material opposite to the image display region is positioned on the image display region side from an imaginary line that linearly connects outer edges of both side portions sandwiching the bent portion in the sealing material. The electro-optical device according to claim 1. In the plurality of signal line formation regions, a pair of ends of the signal lines located on both sides of the element substrate side inter-substrate conduction electrode extend toward the image display region while being inclined obliquely so as to be close to each other. And
3. The electro-optical device according to claim 1, wherein the bent portion includes an oblique side extending toward the image display area while being inclined obliquely so as to be close to each other. The bent portion has a side extending in parallel with the substrate edge of the counter substrate facing the bent portion;
The electro-optical device according to claim 1, wherein the inter-substrate conductive material extends so as to be in contact with the side.   5. The electro-optical device according to claim 1, wherein a part of the element substrate side inter-substrate conduction electrode overlaps the sealing material in a plan view. The sealing material includes a gap material that controls a gap between the element substrate and the counter substrate;
6. The element substrate-side inter-substrate conduction electrode is provided with a portion having a low height from the surface of the element substrate in a region overlapping with the sealing material. The electro-optical device according to any one of the above. Three or more signal line forming regions are provided in the extending direction of the substrate edge,
The electro-optical device according to claim 1, wherein two or more element substrate-side inter-substrate conduction electrodes are provided.   An electronic apparatus comprising the electro-optical device according to claim 1.