JP2013011953A - Information processing system, power supply in information processing system, and control method for clock - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processing system capable of reducing power consumption, a power supply in the information processing system, and a control method for a clock.SOLUTION: A changeover control section 85 is shifted to a "clock supply stop" state when a standby time WT1 is an access detection waiting time AWT or more (WT1≥AWT) in an "access standby" state. In the "clock supply stop" state, a state dependent clock control signal CSS is set to an inactive level to stop the supply of a system clock to a sub system bus 40. Subsequently, when a standby time WT2 becomes a clock stop stable time CSST or more (CSST≤WT2), the changeover control section 85 is shifted to a "power supply stop state". In the "power supply stop state", a state dependent power supply control signal PSS is set to an inactive level to stop power supply to a non-interface section of the sub system bus 40.

Description

  The present invention relates to an information processing system including devices connected via a system bus, and a power source and clock control method in the information processing system.

  In an information processing system including a CPU, a ROM, a RAM, a DMA controller, a peripheral circuit, and the like, it is increasingly important to reduce power consumption. In order to reduce power consumption, fine control according to the operation state and configuration of the information processing system is required.

  For example, Patent Document 1 discloses a technique for stopping clock supply for each functional unit, that is, for each processor, ROM, RAM, DMA controller, peripheral circuit, and the like corresponding to a CPU. According to this, since the clock can be supplied and shut off for each functional unit, the power consumption can be finely reduced according to the operation state of the information processing system.

Japanese Patent Application Laid-Open No. 2002-2244761

  By the way, recent information processing systems realize a plurality of more complicated functions by providing, for example, a communication circuit, an information display circuit for displaying information on a display, or an audio reproduction circuit for reproducing audio information as peripheral circuits. It is supposed to be. These peripheral circuits are connected to the system bus together with the CPU, ROM, RAM, DMA controller and the like, and are controlled by the CPU (hereinafter, peripheral circuits, CPU, ROM connected to the system bus) RAM, DMA controller, etc. are simply called devices).

  It is desirable that these devices operate with a high-speed clock in order to improve processing capability. Therefore, in an information processing system that realizes the complicated functions as described above, for example, clock drivers are provided at various locations on the system bus to maintain the driving force of the high-speed clock supplied to the device.

  However, power consumption in the clock driver tends to increase as the clock speed increases. For this reason, in an information processing system including a system bus having a large number of clock drivers, the power consumption of the system bus cannot be ignored when considering a reduction in power consumption of the entire information processing system. That is, there is a concern that the power consumption of the entire information processing system cannot be sufficiently reduced only by stopping the clock supply to each device as in the past.

  The present invention has been made in view of these problems, and an object thereof is to provide an information processing system capable of reducing power consumption and a method for controlling a power source and a clock in the information processing system.

  In an information processing system according to claim 1, which is an invention made to achieve the above object, a device group consisting of a plurality of devices is connected to a system bus operated by a clock. An adjustment unit that adjusts at least the supply of the clock to the system bus is provided.

  The adjusting means stops the supply of the clock to the system bus until a new access request is generated after a preset access detection waiting time elapses after the access request to the system bus is interrupted. The “request to access the system bus” here means a request to use the system bus from each device constituting the device group.

  According to the information processing system configured as described above, when the access request is interrupted beyond the access detection waiting time, the clock supply to the system bus is stopped, so that the power consumption in the system bus can be reduced. . As a result, power consumption in the information processing system can be reduced.

  If a request to use the system bus is output from the device after the supply of the clock to the system bus has been stopped, restart the supply of the clock to the system bus to quickly operate the system bus. You can resume. In other words, the information processing system of the present invention is more effective when a device group is connected to the system bus so that access requests are frequently output.

By the way, depending on the function desired to be realized by the information processing system, a device group having a low frequency of outputting an access request may be connected to the system bus.
Therefore, as described in claim 2, the information processing system according to the present invention uses the system bus from each device for a preset clock stop stabilization time after the supply of the clock to the system bus is stopped. When the request to stop is interrupted, a power supply control unit that stops the power supplied to the system bus may be provided.

  In the information processing system configured in this manner, while the access request is not output, not only the clock supply to the system bus is stopped but also the power supply is stopped, so the clock supply is not stopped without stopping the power supply. The power consumption in the system bus can be further reduced as compared with the case where the operation is stopped. As a result, power consumption in the information processing system can be reduced.

For example, as shown in claim 3, the system bus may include a CPU as one of the device groups.
Further, for example, an information processing system according to the present invention may include a main bus to which a CPU is connected and a sub bus including a system bus, as shown in claim 4. The sub bus connects the main bus as one of the device groups. As a result, the device connected to the sub-bus and the device connected to the main bus can access each other.

In the information processing system configured as described above, a plurality of subsystem buses can be connected to the main bus.
For example, among a plurality of connected subsystem buses, for a system bus to which a device group having a high access request frequency is connected, the clock supply is stopped when the access request is interrupted, and the access request frequency is low. For the system bus to which the group is connected, the information system can be configured such that when the access request is interrupted, the supply of power is stopped in addition to the stop of supply of the clock.

  According to this, the power consumption can be reduced according to the frequency of access requests in each system bus, that is, the power consumption can be reduced according to the operating state of the information processing system. Thus, the effects of the present invention are further exhibited.

  The invention according to claim 5 is a method for controlling a power source and a clock in an information processing system, comprising a system bus operated by a clock and a plurality of devices connected to the system bus, A system bus clock stop step and a system bus power supply stop step.

  In the system bus clock stop step, a request to use the system bus from a plurality of devices is regarded as an access request, and after a predetermined access detection waiting time elapses after the access request is interrupted, a new access request is generated The clock supplied to the system bus is stopped.

  In the system bus power stop step, after the clock supplied to the system bus stops, it is supplied to the system bus until a new access request occurs after the preset clock stop stabilization time elapses after the access request stops. Turn off the power.

  According to the present invention, the same effect as that of the first aspect of the invention can be attained.

It is a block diagram which shows the structure of the information processing system of 1st Embodiment. It is a block diagram showing the structure of a subsystem bus. It is a block diagram showing the structure of a power supply clock adjustment part. It is a state transition diagram of a switching part. It is a timing chart explaining operation of an information processing system. It is a block diagram which shows the structure of the information processing system of 2nd Embodiment. It is a block diagram which shows the structure of the information processing system of 3rd Embodiment.

Embodiments of the present invention will be described below with reference to the drawings.
[First Embodiment]
[overall structure]
The configuration of the information processing system of this embodiment is shown in FIG. The information processing system 1 includes a main system 10 having a CPU 11 that executes various controls, and a subsystem 30 having a first functional device 44 and a second functional device 46 as a group of devices 43 for realizing a certain function. It has. The main system 10 and the subsystem 30 are mainly configured by a system bus including at least a data bus, an address bus, and signal lines for transmitting various control signals. Hereinafter, the system bus of the main system 10 is referred to as a backbone system bus 20, and the system bus of the subsystem 30 is referred to as a subsystem bus 40.

  Each system bus is connected via a master node connection terminal (hereinafter referred to as a master terminal) M0, M1,... That is a connection terminal with a device capable of outputting an access request to the system bus, and the system bus. Slave node connection terminals (hereinafter referred to as slave terminals) S0, S1,...

  The backbone system bus 20 and the subsystem bus 40 are connected so as to be able to exchange data with each other as a master / slave. Here, the slave terminal S1 of the backbone system bus 20 and the master terminal M0 of the subsystem bus 40 are connected, and the master terminal M1 of the backbone system bus 20 and the slave terminal S0 of the subsystem bus 40 are connected. .

[Main system]
In addition to the CPU 11, the main system includes a power supply control unit 50, a clock control unit 60, a memory 15, and a backbone system bus 20 that connects these devices.

  The CPU 11 is connected to the master terminal M0 of the backbone system bus 20, the memory 15 is connected to the slave terminal S3, the power control unit 50 is connected to the slave terminal S5, and the clock control unit 60 is connected to the slave terminal S4 ( (See FIG. 1).

  The power supply control unit 50 controls the power supply control signal PC1 for controlling power supply to the first functional device 44, the power supply control signal PC2 for controlling power supply to the second functional device 46, and the power supply to the subsystem bus 40. It consists of a register for setting the signal level of the power control command signal PCB for controlling the supply of. The register outputs power control signals PC1 and PC2 and a power control command signal PCB to the subsystem 30.

  The power supply control signals PC1, PC2 and the power supply control command signal PCB are set to an active level when the power supply Vcc is supplied to each device by the operation of the register by the CPU 11, and is not used when the supply of the power supply Vcc is stopped. Set to active level.

  The clock control unit 60 also includes a clock control signal CC1 that controls the supply of the system clock CLK to the first functional device 44, a clock control signal CC2 that controls the supply of the system clock CLK to the second functional device 46, and a sub It consists of a register for setting the signal level of the clock control command signal CCB for controlling the supply of the system clock CLK to the system bus 40. The register outputs clock control signals CC1 and CC2 and a clock control command signal CCB to the subsystem 30.

  The clock control signals CC1 and CC2 and the clock control command signal CCB are set to the active level when the system clock CLK is supplied to each device by the operation of the register by the CPU 11, and the supply of the system clock CLK is stopped. Is set to the inactive level.

  Specifically, the power control signals PC1 and PC2 and the clock control signals CC1 and CC2 need to operate the first functional device 44 or the second functional device 46 on the application operating in the information processing system 1. Set to active level when there is.

  Further, the power control command signal PCB and the clock control command signal CCB are normally used to force the subsystem to operate, such as an initialization setting process for setting various parameters for setting the subsystem operation after the power is turned on. Set active when needed.

[sub-system]
In addition to the first functional device 44 and the second functional device 46 as the device group 43, the subsystem 30 includes a subsystem bus 40 for connecting each device in the subsystem 30, a first functional device 44, and a second function. And a DMAC 42 that makes an access request to the subsystem bus 40 in accordance with a DMA transfer request from the device 46. The subsystem 30 also includes a power control signal BPC for controlling the switch 35 and a clock control signal for controlling the switch 36 based on a power control command signal PCB, a clock control command signal CCB, a request signal REQ0 and a request signal REQ1, which will be described later. A power supply clock adjusting unit 70 for generating BCC is provided (see FIG. 1).

  Here, the DMAC 42 is connected to the master terminal M1 of the subsystem bus 40, the power supply clock adjusting unit 70 is connected to the slave terminal S2, and the first functional device 44 and the second functional device 46 are connected to the slave terminals S3 and S4, respectively. Has been.

  The DMAC 42 and the power supply clock adjustment unit 70 are connected so that the request signal REQ1 among the signals output from the DMAC 42 to the M1 terminal of the subsystem bus 40 is input to the power supply clock adjustment unit 70.

  Furthermore, the power supply clock adjustment unit 70 is connected so that the request signal REQ1 is input from signals output from the S1 terminal of the backbone system bus 20 to the M0 terminal of the subsystem bus 40.

  Further, the subsystem 30 is controlled by the power control signal PC1 to switch the supply and stop of the power Vcc to the first function device 44, and the system clock CLK to the first function device 44 controlled by the clock control signal CC1. And a switch 32 for switching between supply and stop.

  Furthermore, the subsystem 30 is controlled by the power control signal PC2 and switches 33 for switching the supply and stop of the power Vcc to the second function device 46, and the system clock to the second function device 46 controlled by the clock control signal CC2. And a switch 34 for switching between supply and stop of CLK.

  In addition, the subsystem 30 includes a switch 35 that switches supply and stop of the power supply Vcc to the subsystem bus 40 and a switch 36 that switches supply and stop of the system clock CLK to the subsystem bus 40 according to the clock control signal BCC. ing. However, the subsystem bus 40 is provided with a first power supply receiving unit V1 and a second power supply receiving unit V2, and the first power supply receiving unit V1 is directly supplied with power from the power supply Vcc. The power supply Vcc is supplied to the second power supply receiving unit V2 through the switch 35 controlled according to the power control signal BPC.

[Functional device]
The first functional device 44 outputs the DMA request signal DREQ1 set to the active level to the DMAC 42 when there is a DMA transfer request as a signal indicating the presence or absence of the DMA transfer request, and the second functional device 46 outputs the DMA signal as a similar signal. The request signal DREQ2 is output to the DMAC 42.
[DMAC]
Based on the DMA request signals DREQ1 and DREQ2, the DMAC 42 generates a request signal REQ1 indicating whether or not there is an access request to the subsystem bus 40, and outputs the request signal REQ1 to the subsystem bus 40.

  When at least one of the DMA request signals DREQ1 and DREQ2 is at an active level, that is, when there is a DMA transfer request from at least one of the first functional device 44 and the second functional device 46, an access request to the subsystem bus 40 The DMAC 42 sets the request signal REQ1 to the active level.

  On the other hand, when both of the DMA request signals DREQ1 and DREQ2 are in an inactive level, that is, when there is no DMA transfer request from either the first functional device 44 or the second functional device 46, an access request to the subsystem bus 40 The DMAC 42 sets the request signal REQ1 to an inactive level.

  After outputting the request signal REQ1, when the permission signal ACK1 permitting access to the subsystem bus 40 is input from the subsystem bus 40, the DMAC 42 responds to the request from the first functional device 44 and the second functional device 46. The DMA transfer is executed according to the contents of a register (not shown) in which the contents of the DMA transfer based are set.

  However, when the DMA request signals DREQ1 and DREQ2 are both set to active, DMA transfer is executed in order from the device with the highest priority according to the preset priority.

[Subsystem bus]
Next, the configuration and operation of the subsystem bus 40 will be described. FIG. 2 is a block diagram showing the configuration of the subsystem bus 40.

The subsystem bus 40 includes an arbiter 302 and a decoder / selector 304 (see FIG. 2).
The arbiter 302 receives a request signal REQi (i: 0, 1,...) From a device connected to the master terminal Mj (j: 0, 1,. When the system bus 40 is free, the permission signal ACKn (n: 0, 1,...) Is output to one device to permit the use of the subsystem bus 40. If the subsystem bus 40 is in use, the permission signal ACKn is output after waiting until the subsystem bus becomes free.

  Here, when a plurality of request signals REQi are input when the bus is free, the permission signal ACKn is output to one device that has output the request signal REQi having the highest priority according to the priority. .

  The decoder / selector 304 is a device (slave terminal Sk (k: K) that is an access destination from the device (master terminal Mj) that the arbiter 302 has permitted to use the subsystem bus 40 (in other words, outputs the permission signal ACKn). 0, 1,...)) Are selected to connect the master / slave so that data can be transferred.

Although the configuration of the subsystem bus 40 has been described as described above, the backbone system bus 20 has the same configuration as the subsystem bus 40.
That is, the backbone system bus 20 connects the subsystem bus 40 as one of the devices connected to the backbone system bus 20, and the subsystem bus 40 is one of the devices connected to the subsystem bus 40. A backbone system bus 20 is connected.

  As a result, the device connected to the backbone system bus 20 and the device connected to the subsystem bus 40 can access each other as a master / slave. Specifically, the backbone system bus 20 and the subsystem bus 40 are configured so that the request signal REQ0 is output from the S1 terminal of the backbone system bus 20 to the M0 terminal of the subsystem bus 40 in FIG. Similarly, the request signal REQ1 is output from the S0 terminal of the subsystem bus 40 to the M1 terminal of the backbone system bus 20.

  In the subsystem bus 40, the first power supply receiving unit V1 is connected to a part related to the input / output interface of the subsystem bus 40 (hereinafter referred to as an interface unit), and the second power supply receiving unit V2 is The subsystem bus 40 is connected to a portion (hereinafter referred to as a non-interface portion) excluding a portion related to the input / output interface.

  The non-interface unit is, for example, a decoder / selector 304 (see FIG. 2) or a clock driver (not shown) provided at various places to maintain the driving power of the system clock CLK. The interface unit is configured such that the signal level of the output signal is set to an inactive level when the supply of the power supply Vcc to the non-interface unit is stopped.

  That is, while the power supply to the information processing system 1 is being performed, the power supply Vcc is always supplied to the input / output interface unit of the subsystem bus 40, and the power supply Vcc is supplied to the non-input / output interface unit. The stop is switched by a switch 35 controlled according to the power control signal BPC.

[Power supply clock adjustment section]
Next, the power supply clock adjustment unit 70 which is a main part of the present invention will be described. FIG. 3 is a block diagram showing the configuration of the power supply clock adjustment unit 70.

  The power supply clock adjustment unit 70 monitors a signal indicating whether or not there is an access request from the main system 10 to the subsystem bus 40 among signals supplied from the S1 terminal of the backbone system bus 20 to the M0 terminal of the subsystem bus. A monitor unit 73 and a subsystem monitor unit 71 that monitors a signal indicating the presence or absence of a DMA transfer request among signals supplied from the DMAC 42 to the M1 terminal of the subsystem bus 40 are provided.

  Further, the power supply clock adjustment unit 70 controls the state-dependent power supply control signal PSS for controlling the opening / closing of the switch 35 and the opening / closing of the switch 36 based on the monitoring results of the main system monitor unit 73 and the subsystem monitor unit 71. A control unit 75 that generates a state-dependent clock control signal CSS is included.

  Furthermore, the power supply clock adjustment unit 70 generates a power supply control signal BPC based on the state-dependent power supply control signal PSS and the power supply control command signal PCB for controlling the opening and closing of the switch 35 in accordance with a command from the CPU 11. And a clock switching unit 79 that generates a clock control signal BCC based on a state-dependent clock control signal CSS and a clock control command signal CCB for controlling opening and closing of the switch 36 in accordance with a command from the CPU 11.

  In this embodiment, the main system monitor unit 73 is a request signal input from the S1 terminal of the backbone system bus 20 to the M0 terminal of the subsystem bus 40 as a signal indicating the presence or absence of an access request from the main system 10 to the subsystem bus 40. It is configured to output REQ0 as it is to the control unit 75 (see FIGS. 1 and 3). Further, the subsystem monitor unit 71 is configured to output the request signal REQ1 input from the DMAC 42 to the M1 terminal of the subsystem bus 40 as a signal indicating the presence or absence of a DMA transfer request to the control unit 75 as it is.

  When the power control command signal PCB input from the power control unit 50 is at the active level, the power switching unit 77 outputs the power control command signal PCB as the power control signal BPC, that is, outputs the power control signal BPC at the active level. Is configured to do. Further, when the power control command signal PCB is at an inactive level, the power switching unit 77 is configured to output the state dependent power control signal PSS input from the control unit 75 to the switch 35 as the power control signal BPC.

  That is, when the supply of the power Vcc to the non-interface unit of the subsystem bus 40 is forcibly started, the power control command signal PCB set to the active level by the command of the CPU 11 is output from the power control unit 50. That's fine.

  As a result, the supply and stop of the power supply Vcc to the non-interface portion of the subsystem bus 40 is controlled without applying a load to the CPU 11 according to the operating state of the subsystem 30 except when the supply is forcibly started. The

  When the clock control command signal CCB input from the clock control unit 60 is at the active level, the clock switching unit 79 outputs the clock control command signal CCB as the clock control signal BCC, that is, the active level clock control signal BCC is output. It is configured to output. When the clock control command signal CCB is at an inactive level, the clock switching unit 79 is configured to output the state-dependent clock control signal CSS input from the control unit 75 to the switch 36 as the clock control signal BCC.

  That is, when the supply of the system clock CLK to the subsystem bus 40 is forcibly started, the clock control command signal CCB set to the active level may be output from the clock control unit 60 according to the command of the CPU 11.

  Thereby, the supply and stop of the system clock CLK to the subsystem bus 40 are controlled without applying a load to the CPU 11 according to the operating state of the subsystem 30 except when the supply is forcibly started.

[Control part]
Next, the control unit 75 will be described in detail. The control unit 75 generates an access request signal ARS indicating whether there is an access request to the subsystem bus 40 based on the request signal REQ0 input from the main system monitor unit 73 and the request signal REQ1 input from the subsystem monitor unit 71. The access presence / absence detection unit 81 to be generated, the switching control unit 85 that generates the state-dependent power supply control signal PSS and the state-dependent clock control signal CSS based on the access request signal ARS, and the values of various constants used in the switching control unit 85 are The control register 83 is set.

  The access presence / absence detection unit 81 is configured by a logic circuit so that the access request signal ARS is set to the active level when at least one of the request signal REQ0 and the request signal REQ1 is at the active level (FIG. 3). reference).

  The control register 83 outputs various constant values such as the access detection waiting time AWT, the power supply stabilization time PST, and the clock stabilization time CST to the switching control unit 85. The values of these various constants are set in the control register 83 by an initialization process that is first executed by the CPU 11 when power supply to the information processing system 1 is started.

  The switching control unit 85 performs state-dependent control signal setting processing for setting the signal level of the state-dependent power supply control signal PSS and the state-dependent clock control signal CSS to one of an active level and an inactive level. Here, the state-dependent power control signal PSS is set to the active level when the power Vcc is supplied to the non-interface unit of the subsystem bus 40, and is set to the inactive level when the supply of the power Vcc is stopped. . The state-dependent clock control signal CSS is set to an active level when the system clock CLK is supplied to the subsystem bus 40, and is set to an inactive level when the supply of the system clock CLK is stopped.

[State-dependent control signal setting processing]
FIG. 4 is a state transition diagram showing the transition of the internal state of the switching control unit 85 in the state-dependent control signal setting process, and FIG. 5 is a timing chart of this process. 5A is a time chart when the supply of the system clock CLK to the subsystem bus 40 is resumed by an access request from the main system 10, and FIG. 5B is a time chart when the DMA transfer request is sent to the subsystem bus 40. 4C is a time chart when restarting the supply of the system clock CLK, and FIG. 5C is a time chart when restarting the supply of the power supply Vcc and the system clock CLK to the subsystem bus 40 in response to an access request from the main system 10. (D) is a time chart when the supply of the power supply Vcc and the system clock CLK to the subsystem bus 40 is resumed in response to a DMA transfer request.

  In FIG. 5, each time indicated by t1 to t50 is the falling timing of the system clock CLK, and the interval between each time t1 to t50 is one cycle of the system clock CLK. For example, t5 is the falling timing of the fifth system clock CLK counted from t1.

  In this processing, in synchronization with the system clock CLK, the internal state of the switching control unit 85 is “access standby”, “clock supply stop”, “power supply stop”, “power supply stable standby”, and “clock stable standby”. Transition between two states (see FIG. 5).

[Access standby]
First, the internal state of the switching control unit 85 transitions to an “access standby” state (see FIG. 4).

  The switching control unit 85 generates a time when the access request signal ARS is in an inactive level as separate processing, that is, both an access request (REQ0) and a DMA transfer request (REQ1) from the main system 10 to the subsystem bus 40 are generated. No time is measured as the standby time WT1.

In the “access standby” state, the standby time WT1 is compared with the access detection waiting time AWT which is a preset value.
Here, when the waiting time WT1 is less than the access detection waiting time AWT (WT1 <AWT), the state transits to the current state, that is, the “access waiting” state (see times t5 to t10 in FIGS. 5A to 5D). ). On the other hand, when the waiting time WT1 is equal to or longer than the access detection waiting time AWT (WT1 ≧ AWT), the state transits to the “clock supply stop” state (see time t10 in FIGS. 5A to 5D).

[Clock supply stopped state]
In the “clock supply stop” state in which the standby time WT1 is equal to or longer than the access detection waiting time AWT (WT1 ≧ AWT), the switching control unit 85 changes the clock switching unit 79 from the active level to the inactive level. A state-dependent clock control signal CSS is output (see time t10 in FIGS. 5A to 5D). As a result, the supply of the system clock CLK to the subsystem bus 40 is stopped. In FIGS. 1 and 5, the system clock CLK supplied to the subsystem bus 40 is indicated by a clock BCLK.

  Here, as a separate process, the switching control unit 85 outputs the state-dependent clock control signal CSS changed to the inactive level and then the time when the access request signal ARS shows the inactive level, that is, from the main system 10 to the subsystem bus. A time during which neither an access request (REQ0) to 40 nor a DMA transfer request (REQ1) is generated is measured as a waiting time WT2.

  When the state in which the access request signal ARS indicates the inactive level continues and the standby time WT2 is smaller than the preset clock stop stabilization time CSST (WT2 <CSST), the current state, that is, the “clock supply stop” state (Refer to times t10 to t20 in FIGS. 5A and 5B).

  Here, when the access request signal ARS becomes active level while the “clock supply stop” state continues, that is, the access request (REQ0) and the DMA transfer request (REQ1) from the main system 10 to the subsystem bus 40. When at least one of the requests is generated (see time t20 in FIGS. 5A and 5B), the state transits to the “clock stabilization standby” state.

On the other hand, when the standby time WT2 becomes equal to or longer than the clock stop stabilization time CSST (CSST ≦ WT2), the state transits to the “power supply stop state” (see time t30 in FIGS. 5C and 5D).
[Power supply is stopped]
In the “power supply stop” state where the standby time WT2 becomes equal to or longer than the clock stop stabilization time CSST (CSST ≦ WT2), the switching control unit 85 causes the power supply switching unit 77 to change from the active level to the inactive level. The state-dependent power supply control signal PSS is output (see time t30 in FIGS. 5C and 5D). As a result, the supply of the power supply Vcc to the non-interface unit of the subsystem bus 40 is stopped. In FIGS. 1 and 5, the power supply Vcc supplied to the non-interface unit of the subsystem bus 40 is indicated by the symbol BVcc.

  After the state-dependent power control signal PSS changed to the inactive level is output, while the state (ARS = NA) in which the access request signal ARS indicates the inactive level (NA) continues, Transition to the “power supply stop” state (see times t30 to t39 in FIGS. 5C and 5D).

  If the access request signal ARS becomes active level (A) (ARS = A) while the “power supply stop” state continues, that is, an access request from the main system 10 to the subsystem bus 40. When at least one of (REQ0) and DMA transfer request (REQ1) is generated (see time t39 in FIGS. 5C and 5D), the state transits to the “power supply stable standby” state.

[Power stable standby state]
In the “power stabilization standby” state where the access request signal ARS becomes active level in the “power supply stop” state (ARS = A), the switching control unit 85 activates from the inactive level to the power switching unit 77. The state-dependent power supply control signal PSS changed to the level is output (see time t40 in FIGS. 5C and 5D). As a result, the supply of the power supply Vcc to the non-interface unit of the subsystem bus 40 is resumed.

  Here, the switching control unit 85 measures the elapsed time since the output of the state-dependent power control signal PSS at the active level as a separate process as the restart time RT1, and the restart time RT1 is a preset value. Is less than the power supply stabilization time PST (RT1 <PST), the current state, ie, the “power supply stabilization standby” state is entered (see times t40 to 43 in FIGS. 5C and 5D).

On the other hand, when the restart time RT1 becomes equal to or longer than the power supply stabilization time PST (RT1 ≧ PST), the state transits to the “clock stabilization standby” state.
[Clock stable standby state]
When the access request signal becomes active (ARS = A) in the “clock supply stop state”, or when the restart time RT1 becomes equal to or longer than the power supply stabilization time PST in the “power stabilization standby” state In the “clock stabilization standby” state where the transition is made to (RT1 ≧ PST), the switching control unit 85 outputs the state-dependent clock control signal CSS changed from the inactive level to the active level to the clock switching unit 79 (FIG. 5 ( a, (b) time t21 and (c), (d) time t43).

  Here, the switching control unit 85 measures the elapsed time from the output of the active level state-dependent clock control signal CSS as a separate process as the restart time RT2, and the restart time RT2 is a preset value. When the time is less than the clock stabilization time CST (RT2 ≦ CST), the current state, that is, the “clock stabilization standby” state is entered (time t21 to t24 and FIGS. 5C and 5D in FIGS. 5A and 5B). Time t43 to t46).

  On the other hand, when the restart time RT2 becomes equal to or longer than the clock stabilization time CST (CST ≦ RT2), the state transits again to the “access standby” state (time t24 and (c), (c) in FIG. (See d) at time t46).

  When the information processing system 1 is turned on and the above-described initialization setting process is executed by the CPU 11, the power supply control command signal PCB and the clock control command signal CCB are set to active to the subsystem bus 40. Supply of the power source Vcc and the system clock CLK is started. The state-dependent control signal setting process transitions to the “access standby” state described above when the initialization setting is completed.

  The switching control unit 85 that performs the state-dependent control signal setting process that operates in this manner may be configured by a logic circuit that operates according to a sequence set based on the setting value of the control register or the access request signal ARS. Or you may comprise as a program which CPU11 consisting of a microcomputer provided with CPU, ROM, RAM, etc. performs.

[effect]
As described above, in the information processing system 1, when a state in which neither an access request from the main system 10 nor a DMA transfer request is generated continues for a predetermined access detection waiting time AWT or longer, the non-interface of the subsystem bus 40 The supply of the system clock CLK to the unit is stopped. As a result, the supply of the system clock CLK to the selector / decoder, clock driver, etc. provided in the non-interface portion of the subsystem bus 40 is stopped. Therefore, power consumption in the subsystem bus 40 can be reduced. In addition, since the operating state is monitored in the subsystem 30, power consumption can be reduced without applying a load to the CPU 11. As a result, power consumption in the entire information processing system 1 can be reduced.

  In the information processing system 1, not only the supply of the system clock CLK to the subsystem bus 40 is stopped, but also the supply of the power supply Vcc to the subsystem bus 40 according to the generation interval of access requests to the subsystem bus 40. To stop. For this reason, the power consumption in the subsystem bus 40 can be further reduced as compared with the case where the supply of the system clock CLK is stopped without stopping the supply of the power supply Vcc.

[Correspondence with Invention]
The subsystem bus 40 in the present embodiment corresponds to a “system bus” in the claims, the power supply clock adjustment unit 70 corresponds to an “adjustment unit” in the claims, and the first function device 44 and the second function The device 46 corresponds to a “device” in the claims. The system clock CLK corresponds to a “clock” in the claims. Furthermore, the backbone system bus 20 of this embodiment corresponds to a “main bus” in the claims, and the subsystem bus 40 corresponds to a “sub bus” in the claims.

  Further, the operation of the “clock supply stop” state of the switching control unit 85 according to the state transition diagram in this embodiment corresponds to the “system bus clock stop step” in which the access detection waiting time AWT is defined in the claims. The operation in the “power supply stop” state of the switching control unit 85 along the drawing corresponds to the “system bus power supply stop step” in the claims.

[Second Embodiment]
Next, a second embodiment will be described.
FIG. 6 is a block diagram showing the configuration of the information processing system 2 of the second embodiment. In the information processing system 1 of the first embodiment, one subsystem 30 is connected to the main system 10, but in the information processing system 2 of this embodiment, two subsystems 30 a and 30 b are connected to the main system 10. ing.

  The subsystem 30a is configured by a device having a low occurrence frequency of access requests to the subsystem bus of the subsystem 30a, and the subsystem 30b is a device having a high occurrence frequency of access requests to the subsystem bus of the subsystem 30b. It is configured. Below, it demonstrates centering around a different point mainly.

  As shown in FIG. 6, the power supply control unit 50 and the clock control unit 60 are provided with the same power supply control signals PC1, PC2, clock control signals CC1, CC2, power supply control command signal PCB, and A clock control command signal CCB is output. However, in the following description, the signal supplied to the subsystem 30a is appended with _a after the code of the first embodiment, such as PC1_a, and the signal supplied to the subsystem 30b is code of the first embodiment, such as PC1_b. _B shall be appended after.

  In the subsystem 30b, the slave terminal S6 of the backbone system bus 20 is connected to the master terminal M0 of the subsystem bus (not shown), and the master terminal M6 of the backbone system bus 20 is connected to the slave terminal S0.

  Here, the subsystem 30a is configured in the same manner as the subsystem 30, and includes a power supply clock adjustment unit. That is, the subsystem 30a controls the supply and stop of power to the subsystem bus and the supply and stop of the system clock by the power supply clock adjustment unit. Thereby, the subsystem 30a operates similarly to the first embodiment.

  On the other hand, the subsystem 30b is partially different in configuration from the subsystem 30a. The subsystem 30b has a power supply clock adjustment unit. The power supply clock adjustment unit controls supply and stop of the system clock to the subsystem bus, and controls supply and stop of the power supply to the subsystem bus. do not do.

  When the subsystem 30b is configured in this way, in the state-dependent control signal setting process, the internal state of the switching control unit (not shown) is the “power supply stop” state and “power supply stable standby” in the state transition diagram shown in FIG. Transition is performed in a state where state transition to the state is omitted. Although a detailed description is omitted here, the internal states that the switching control unit can take are three states: an “access standby” state, a “clock supply stop” state, and a “clock stabilization standby” state. .

  According to this, in the subsystem 30b, when the access request to the subsystem bus is interrupted, the supply of power to the subsystem bus does not stop. Therefore, when the access request to the subsystem bus occurs again, the power supply is turned on. Without needing to enter the access standby state immediately.

Therefore, even when an access request is frequently generated, the generated access request is executed without delay.
As described above, in the information processing system 2, the main system 10 is connected to a plurality of subsystems having different occurrence frequencies of access requests to the subsystem bus. The subsystem 30b having a high frequency of access requests controls the stop of the clock supply to the subsystem bus and does not control the stop of the power supply. As a result, even when an access request is frequently generated, the generated access request is executed without delay.

  On the other hand, the subsystem 30a having a low occurrence frequency controls the stop of the power supply in addition to the clock supply. As a result, the power consumption can be further reduced when the access request generation interval is long.

  Therefore, the information processing system 2 can finely reduce power consumption according to the operation state, and can execute an access request without delay in a subsystem where the frequency of access requests is high.

[Third Embodiment]
In the above embodiment, the backbone system bus and the subsystem bus are divided and configured. However, the backbone system bus and the subsystem bus may not be divided. FIG. 7 is a block diagram showing the configuration of the information processing system 3 of this embodiment. Hereinafter, a description will be given focusing on differences from the first embodiment.

  In the information processing system 3, there is one system bus 25. In the system bus 25, the power supply clock adjustment unit 70 is connected to the slave terminal S2, the DMAC 42 is connected to the master terminal M1, the first functional device 44 is connected to the slave terminal S6, and the second functional device 46 is connected to the slave terminal S7. It is connected.

  In addition, the subsystem 30 includes a switch 35 that switches supply and stop of the power supply Vcc to the subsystem bus 40 and a switch 36 that switches supply and stop of the system clock CLK to the subsystem bus 40 according to the clock control signal BCC. ing.

  Furthermore, the system bus 25 is provided with a first power supply receiving unit V11 and a second power supply receiving unit V21, and the first power supply receiving unit V11 is supplied with power directly from the power supply Vcc. The power supply Vcc is supplied to the second power supply receiving unit V21 via the switch 35 controlled according to the power control signal BPC. Here, the first power supply receiving unit V11 is connected to the interface unit of the system bus 25, and the second power supply receiving unit V21 is connected to the non-interface unit of the system bus 25.

  The CPU 11 is a CPU that operates in a well-known sleep mode. The sleep mode here refers to a state in which the operation of the CPU 11 is stopped but the power supply to the CPU 11 is continued. The CPU 11 that has entered the sleep mode is configured to automatically resume its operation after a preset sleep time has elapsed.

Furthermore, the power supply clock adjustment unit 70 is connected so that the request signal REQ0 among the signals output from the CPU 11 to the master terminal M0 of the system bus 25 is input.
In the information processing system 3 configured as described above, while the CPU 11 is operating, that is, while an access request from the CPU 11 to the system bus 25 is generated and the request signal REQ0 is set to active, the system bus The power supply Vcc and the system clock CLK are supplied to all 25 parts.

  Further, while the CPU 11 is in the sleep mode, that is, while the access request from the CPU 11 to the system bus 25 is not generated and the request signal REQ0 is set inactive, the system clock CLK and the power supply to the system bus 25 are set. The supply of Vcc is controlled according to the signal level of the request signal REQ1 output from the DMAC 42.

  That is, while the CPU 11 is in the sleep mode, when there is a DMA transfer request from at least one of the first functional device 44 and the second functional device 46, the power supply Vcc and the system clock CLK are supplied to all parts of the system bus 25. Supply is made.

  Here, when there is no DMA transfer request from either the first function device 44 or the second function device 46 while the CPU 11 is in the sleep mode, the supply of the system clock CLK to the system bus 25 is stopped and the non-interface unit The stop of the supply of the power supply Vcc to is controlled in the same manner as in the first embodiment.

As described above, the information processing system 3 includes one system bus 25,
When the CPU 11 is in the sleep mode, the system bus 25 is accessed by DMA transfer, for example, the memory 15 is accessed from the first functional device 44. When the CPU 11 is in the sleep mode, the supply of the power supply Vcc and the system clock CLK to the system bus 25 is controlled according to the presence / absence of an access request from the CPU 11 to the system bus 25 and the presence / absence of DMA transfer.

  As a result, power consumption to the system bus 25 can be reduced according to the operating state. Therefore, in such an information processing system 3, when the CPU 11 and the DMAC 42 are stopped for a certain period of time, an effect of further reducing power consumption is achieved.

[Other Embodiments]
As mentioned above, although embodiment of this invention was described, this invention is not limited to the said embodiment, In the range which does not deviate from the summary of this invention, it is possible to implement in various aspects.

  In the above-described embodiment, the case where two devices are connected to the master terminal of the subsystem bus has been described. However, three or more devices may be connected to the master terminal of the subsystem bus. For example, this is a case where a CPU having a sleep mode, which is different from the main system, is further connected to the subsystem. Even in such a configuration, the same effect as the above-described embodiment can be obtained.

  1, 2, 3 ... Information processing system 20 ... Core system bus 25 ... System bus 40 ... Subsystem bus 43 ... Device group 44 ... First functional device 46 ... First Bifunctional device 70 ... Power supply clock adjustment unit Vcc ... Power supply CLK ... System clock

Claims (5)

A system bus that operates with a clock;
A device group consisting of a plurality of devices connected to the system bus;
Adjusting means for adjusting supply of at least a clock to the system bus;
An information processing system comprising:
The adjusting means uses a request to use the system bus from each device constituting the device group as an access request, and newly requests the access request after elapse of a preset access detection waiting time after the access request is interrupted. The information processing system is characterized in that the supply of the clock to the system bus is stopped until the error occurs.   The adjustment unit stops supplying power to the system bus after the clock supply to the system bus is stopped and until a new access request is generated after a preset clock stop stabilization time has elapsed. The information processing system according to claim 1.   The information processing system according to claim 2, wherein the system bus includes a CPU as one of the device groups. A main bus to which the CPU is connected, and a sub-bus composed of the system bus;
The information processing system according to claim 1, wherein the sub bus connects the main bus as one of the device groups. A system bus that operates with a clock;
A plurality of devices connected to the system bus;
A method for controlling a power supply and a clock in an information processing system comprising:
A request to use the system bus from the plurality of devices is set as an access request, and the access to the system bus is continued after the access detection waiting time set in advance after the access request is interrupted. A system bus clock stop step for stopping the supplied clock;
After the clock supplied to the system bus is stopped, the power supplied to the system bus is changed until the access request is newly generated after the preset clock stop stabilization time elapses after the access request is interrupted. A system bus power stop step to stop;
A method of controlling a power supply and a clock in an information processing system comprising:

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