JP2013004766A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Semiconductor device and semiconductor device manufacturing method Download PDF

Info

Publication number
JP2013004766A
JP2013004766A JP2011134952A JP2011134952A JP2013004766A JP 2013004766 A JP2013004766 A JP 2013004766A JP 2011134952 A JP2011134952 A JP 2011134952A JP 2011134952 A JP2011134952 A JP 2011134952A JP 2013004766 A JP2013004766 A JP 2013004766A
Authority
JP
Japan
Prior art keywords
resin
sealing resin
semiconductor device
electrode pattern
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2011134952A
Other languages
Japanese (ja)
Other versions
JP5812712B2 (en
Inventor
Hiroyuki Harada
啓行 原田
Mamoru Terai
護 寺井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2011134952A priority Critical patent/JP5812712B2/en
Publication of JP2013004766A publication Critical patent/JP2013004766A/en
Application granted granted Critical
Publication of JP5812712B2 publication Critical patent/JP5812712B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001Core members of the connector
    • H01L2224/37099Material
    • H01L2224/371Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/37147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/3754Coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401Disposition
    • H01L2224/40151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848Bonding techniques
    • H01L2224/84801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848Bonding techniques
    • H01L2224/8484Sintering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848Bonding techniques
    • H01L2224/8485Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

PROBLEM TO BE SOLVED: To provide a highly reliable semiconductor device which is hard to cause cracks in an encapsulation resin and detachment from a substrate even when a semiconductor element repeatedly operates at a high temperature to be subject to heat cycle.SOLUTION: A semiconductor device comprises: a semiconductor element substrate in which a surface electrode pattern is formed on one surface of an insulating substrate and a back electrode pattern is formed on another surface of the insulating substrate; a semiconductor element fastened to a surface of the surface electrode pattern via a joint material on the opposite side to the insulating substrate; a first encapsulation resin covering the semiconductor element and the surface electrode pattern; and a second encapsulation resin covering at least a part where the surface electrode pattern or the back electrode pattern is not formed and the first encapsulation resin. An elastic modulus of the second encapsulation resin is smaller than an elastic modulus of the first encapsulation resin.

Description

この発明は、半導体装置、特に高温で動作する半導体装置の実装構造に関するものである。   The present invention relates to a mounting structure of a semiconductor device, particularly a semiconductor device that operates at a high temperature.

産業機器や電鉄、自動車の進展に伴い、それらに使用される半導体素子の使用温度も向上している。近年、高温でも動作する半導体素子の開発が精力的に行われ、半導体素子の小型化や高耐圧化、高電流密度化が進んでいる。特に、SiCやGaNなどのワイドバンドギャップ半導体は、Si半導体よりもバンドギャップが大きく、半導体装置の高耐圧化、小型化、高電流密度化、高温動作が期待されている。このような特徴を持つ半導体素子を装置化するためには、半導体素子が150℃以上の高温で動作する場合も、接合材のクラックや配線の劣化を抑えて半導体装置の安定な動作を確保する必要がある。   With the progress of industrial equipment, electric railways, and automobiles, the operating temperature of semiconductor elements used for them has also increased. In recent years, semiconductor devices that operate even at high temperatures have been energetically developed, and miniaturization, high breakdown voltage, and high current density of semiconductor devices have been advanced. In particular, wide bandgap semiconductors such as SiC and GaN have a larger bandgap than Si semiconductors, and semiconductor devices are expected to have higher breakdown voltage, smaller size, higher current density, and higher temperature operation. In order to implement a semiconductor element having such characteristics as an apparatus, even when the semiconductor element operates at a high temperature of 150 ° C. or higher, a stable operation of the semiconductor device is ensured by suppressing the crack of the bonding material and the deterioration of the wiring. There is a need.

一方、半導体装置において半導体素子を樹脂で封止する方法として、特許文献1には、ダム材を用いて半導体素子の周囲を囲い、その内側を部分的に樹脂封止する方法が提案されている。また、特許文献2には、半導体素子を覆う樹脂が流れ広がるのを防止するために、半導体素子の周囲にダムを設ける方法が提案されている。   On the other hand, as a method of sealing a semiconductor element with a resin in a semiconductor device, Patent Document 1 proposes a method in which a dam material is used to surround the periphery of the semiconductor element and the inside thereof is partially resin-sealed. . Patent Document 2 proposes a method of providing a dam around the semiconductor element in order to prevent the resin covering the semiconductor element from flowing and spreading.

特開2003−124401号公報JP 2003-124401 A 特開昭58−17646号公報JP 58-17646 A

しかしながら、特許文献1および特許文献2に開示されている方法では、半導体素子がSiCなどワイドバンドギャップ半導体素子になって、これまで以上に高温で動作したり、これに対応してヒートサイクル試験の温度が高温になったりすると、ダム構造へのボイドの混入や、ダムと封止樹脂および絶縁基板の剥離により、半導体装置の絶縁耐性が低下し、破壊や誤動作など半導体装置の信頼性を損ねる課題があった。   However, in the methods disclosed in Patent Document 1 and Patent Document 2, the semiconductor element becomes a wide band gap semiconductor element such as SiC, and operates at a higher temperature than before, or in response to this, the heat cycle test is performed. When the temperature rises, problems such as voids in the dam structure and peeling of the dam from the sealing resin and insulating substrate will reduce the insulation resistance of the semiconductor device, which will damage the reliability of the semiconductor device such as destruction and malfunction. was there.

この発明は、上記のような問題点を解決するためになされたものであり、半導体素子が繰り返し高温で動作してヒートサイクルを受ける場合も、封止樹脂に亀裂が生じたり、基板から剥離を起こしたりし難い信頼性の高い半導体装置を得ることを目的とする。   The present invention has been made to solve the above problems, and even when the semiconductor element repeatedly operates at a high temperature and undergoes a heat cycle, the sealing resin is cracked or peeled off from the substrate. An object is to obtain a highly reliable semiconductor device that is difficult to cause.

この発明の半導体装置は、絶縁基板の片面に表面電極パターンが、および絶縁基板の他の面に裏面電極パターンが、それぞれ形成された半導体素子基板と、表面電極パターンの、絶縁基板とは反対側の面に接合材を介して固着された半導体素子と、この半導体素子および表面電極パターンを覆う第一の封止樹脂と、絶縁基板の表面で、少なくとも表面電極パターンまたは裏面電極パターンが形成されていない部分と第一の封止樹脂とを覆う第二の封止樹脂と、を備え、第二の封止樹脂の弾性率は、第一の封止樹脂の弾性率よりも小さいものである。   The semiconductor device according to the present invention includes a semiconductor element substrate having a surface electrode pattern formed on one surface of an insulating substrate and a back electrode pattern formed on the other surface of the insulating substrate, and the surface electrode pattern opposite to the insulating substrate. At least a surface electrode pattern or a back electrode pattern is formed on the surface of the semiconductor element, the first sealing resin that covers the semiconductor element and the surface electrode pattern, and the surface of the insulating substrate. And a second sealing resin that covers the first sealing resin, and the second sealing resin has an elastic modulus smaller than that of the first sealing resin.

また、この発明の半導体装置の製造方法は、少なくとも、絶縁基板の表面電極パターンおよび裏面電極パターンが形成されていない面を、絶縁基板の周辺部分には絶縁基板に垂直な面を有する仮設壁を形成するようマスキング樹脂で覆うマスキング樹脂被覆工程と、
表面電極パターンの、絶縁基板とは反対側の面に接合材を介して半導体素子を固着する半導体素子固着工程と、仮設壁の内部を第一の封止樹脂で満たした後、第一の封止樹脂を硬化させる第一の封止樹脂形成工程と、マスキング樹脂を除去するマスキング樹脂除去工程と、少なくとも第一の封止樹脂と、マスキング樹脂を除去して絶縁基板の表面が露出した部分を第二の封止樹脂で覆う第二の封止樹脂形成工程と、を備えたものである。
The method for manufacturing a semiconductor device according to the present invention includes at least a temporary wall having a surface perpendicular to the insulating substrate in a peripheral portion of the insulating substrate on the surface of the insulating substrate where the front electrode pattern and the back electrode pattern are not formed. A masking resin coating step of covering with a masking resin to form,
A semiconductor element fixing step for fixing the semiconductor element to the surface of the surface electrode pattern opposite to the insulating substrate via a bonding material, and filling the interior of the temporary wall with the first sealing resin; A first sealing resin forming step for curing the stop resin, a masking resin removing step for removing the masking resin, at least the first sealing resin, and a portion where the surface of the insulating substrate is exposed by removing the masking resin. And a second sealing resin forming step of covering with the second sealing resin.

この発明に係る半導体装置、および半導体装置の製造方法によれば、半導体素子基板の絶縁基板の表面が露出する部分が弾性率の小さい第二の封止樹脂で覆われるため、半導体素子が繰り返し高温で動作してヒートサイクルを受ける場合も、封止樹脂に亀裂が生じたり、基板から剥離を起こしたりし難い信頼性の高い半導体装置を得ることができる。   According to the semiconductor device and the method of manufacturing a semiconductor device according to the present invention, since the portion of the semiconductor element substrate where the surface of the insulating substrate is exposed is covered with the second sealing resin having a low elastic modulus, the semiconductor element is repeatedly heated. Even in the case of operating in a heat cycle, it is possible to obtain a highly reliable semiconductor device in which cracking is not generated in the sealing resin or peeling from the substrate is difficult.

この発明の実施の形態1による半導体装置の基本構造を示す断面図である。It is sectional drawing which shows the basic structure of the semiconductor device by Embodiment 1 of this invention. この発明の実施の形態1による半導体装置の基本構造を、部品の一部を取り除いて示す上面図である。1 is a top view showing a basic structure of a semiconductor device according to a first embodiment of the present invention with a part removed. FIG. この発明の実施の形態1による半導体装置の別の基本構造を示す断面図である。It is sectional drawing which shows another basic structure of the semiconductor device by Embodiment 1 of this invention. この発明の実施の形態2による半導体装置の製造方法を示す第一の模式図である。It is a 1st schematic diagram which shows the manufacturing method of the semiconductor device by Embodiment 2 of this invention. この発明の実施の形態2による半導体装置の製造方法を示す第二の模式図である。It is a 2nd schematic diagram which shows the manufacturing method of the semiconductor device by Embodiment 2 of this invention. この発明の実施の形態3による半導体装置の基本構造を示す断面図である。It is sectional drawing which shows the basic structure of the semiconductor device by Embodiment 3 of this invention. この発明の実施の形態3による半導体装置のモジュールを複数配置して一つの半導体装置とする基本構造を、封止樹脂や部品の一部を取り除いて示す斜視図である。FIG. 10 is a perspective view showing a basic structure in which a plurality of modules of a semiconductor device according to Embodiment 3 of the present invention are arranged to form one semiconductor device, with a part of sealing resin and parts removed.

実施の形態1.
図1は、本発明の実施の形態1による半導体装置の基本構造を示す断面図、図2は封止樹脂、配線、および端子を取り除いて示す本発明の実施の形態1による半導体装置の基本構造の上面図である。図1は図2のA−A位置に相当する位置で切断した断面図であり、封止樹脂、配線および端子を含めて示している。絶縁基板1の上面に表面電極パターン2、裏面に裏面電極パターン3が貼られた半導体素子基板4の表面電極パターン2の表面に半導体素子5、6がはんだなどの接合材7で固着されている。ここで、例えば半導体素子5は大電流を制御するMOSFETのような電力用半導体素子であり、半導体素子6は例えば電力用半導体素子5に並列に設けられる還流用のダイオードである。半導体素子基板4は裏面電極パターン3側がベース板10にはんだなどの接合材70で固着されており、このベース板10が底板となり、ベース板10とケース側板11とでケースが形成される。第一の封止樹脂12が、半導体素子5、6と表面電極パターン2を覆うように設けられている。また第一の封止樹脂12を含めて、ケース内のものを覆うように第二の封止樹脂120が設けられている。また、表面電極パターン2が無い部分(図1、図2において符号20で示す部分)も第二の封止樹脂120が注入され絶縁基板1の表面を覆っている。各半導体素子には各半導体素子の電極などを外部に電気接続するための配線13が接続され、配線13が端子14に接続されている。
Embodiment 1 FIG.
FIG. 1 is a cross-sectional view showing the basic structure of a semiconductor device according to the first embodiment of the present invention. FIG. 2 is a basic structure of the semiconductor device according to the first embodiment of the present invention with the sealing resin, wiring, and terminals removed. FIG. FIG. 1 is a cross-sectional view taken at a position corresponding to the position AA in FIG. 2 and includes a sealing resin, wiring, and terminals. The semiconductor elements 5 and 6 are fixed to the surface of the surface electrode pattern 2 of the semiconductor element substrate 4 having the surface electrode pattern 2 on the upper surface of the insulating substrate 1 and the back electrode pattern 3 on the back surface by a bonding material 7 such as solder. . Here, for example, the semiconductor element 5 is a power semiconductor element such as a MOSFET that controls a large current, and the semiconductor element 6 is, for example, a free-wheeling diode provided in parallel with the power semiconductor element 5. The semiconductor element substrate 4 has the back electrode pattern 3 side fixed to the base plate 10 with a bonding material 70 such as solder. The base plate 10 serves as a bottom plate, and the base plate 10 and the case side plate 11 form a case. A first sealing resin 12 is provided so as to cover the semiconductor elements 5 and 6 and the surface electrode pattern 2. A second sealing resin 120 is provided so as to cover the inside of the case including the first sealing resin 12. Further, the second sealing resin 120 is also injected into the portion where the surface electrode pattern 2 is not present (the portion indicated by reference numeral 20 in FIGS. 1 and 2) to cover the surface of the insulating substrate 1. Each semiconductor element is connected to a wiring 13 for electrically connecting an electrode of each semiconductor element to the outside, and the wiring 13 is connected to a terminal 14.

半導体素子基板4は、絶縁基板1の上面に表面電極パターン2、裏面に裏面電極パターン3が貼られたものであるが、絶縁基板1は、これら表面電極パターン2と裏面電極パターン3で完全に覆われておらず、半導体素子基板4単体では絶縁基板1が露出している部分がある。本実施の形態1では、この半導体素子基板4において、絶縁基板1が露出している部分(図1、図2において符号20で示す部分や絶縁基板1の周辺部分)も、第二の封止樹脂120で覆われている。ここで、第二の封止樹脂120は第一の封止樹脂12よりも弾性率が低い低弾性の樹脂である。   The semiconductor element substrate 4 has a surface electrode pattern 2 on the upper surface of the insulating substrate 1 and a back electrode pattern 3 on the back surface. The insulating substrate 1 is completely composed of the surface electrode pattern 2 and the back electrode pattern 3. There is a portion where the insulating substrate 1 is exposed when the semiconductor element substrate 4 is not covered. In the first embodiment, in the semiconductor element substrate 4, the portion where the insulating substrate 1 is exposed (the portion indicated by reference numeral 20 in FIGS. 1 and 2 and the peripheral portion of the insulating substrate 1) is also second sealed. Covered with resin 120. Here, the second sealing resin 120 is a low-elasticity resin having a lower elastic modulus than the first sealing resin 12.

第一の封止樹脂としては、例えばエポキシ樹脂を用いるが、これに限定するものではなく、所望の弾性率と耐熱性を有している樹脂であれば用いることが出来る。例えばエポキシ樹脂の他に、シリコーン樹脂、ウレタン樹脂、ポリイミド樹脂、ポリアミド樹脂、ポリアミドイミド樹脂、アクリル樹脂、等が好適に用いられる。また、第一の封止樹脂12は、半導体素子5や6が動作中に高温となった場合でも、熱応力により表面電極パターン2との間の接合材7が剥がれないように半導体素子5や6を押さえつける機能を持たせている。このため、ある程度固い、すなわち弾性率が高い樹脂を用いる必要がある。   As the first sealing resin, for example, an epoxy resin is used. However, the resin is not limited to this, and any resin having a desired elastic modulus and heat resistance can be used. For example, in addition to an epoxy resin, a silicone resin, a urethane resin, a polyimide resin, a polyamide resin, a polyamideimide resin, an acrylic resin, or the like is preferably used. Further, the first sealing resin 12 is used to prevent the bonding material 7 between the surface electrode pattern 2 from being peeled off due to thermal stress even when the semiconductor elements 5 and 6 are heated during operation. 6 has a function to hold down. For this reason, it is necessary to use a resin that is hard to some extent, that is, a high elastic modulus.

第二の封止樹脂120には、例えばシリコーン樹脂を用いるが、これに限定するものではなく、ウレタン樹脂やアクリル樹脂なども用いる事ができる。また、Al2O3、SiO2など
のセラミック粉を添加して用いることもできるが、これに限定するものではなく、AlN、BN、Si3N4、ダイアモンド、SiC、B2O3などを添加しても良く、シリコーン樹脂やアクリル
樹脂などの樹脂製の粉を添加しても良い。粉形状は、球状を用いることが多いが、これに限定するものではなく、破砕状、粒状、リン片状、凝集体などを用いても良い。粉体の充填量は、必要な流動性や絶縁性や接着性が得られる量であれば良い。ただし、第二の封止樹脂120の弾性率は、第一の封止樹脂12の弾性率よりも小さくなければならない。
For example, a silicone resin is used as the second sealing resin 120, but the present invention is not limited to this, and a urethane resin, an acrylic resin, or the like can also be used. In addition, ceramic powder such as Al 2 O 3 and SiO 2 can be added, but this is not restrictive, and AlN, BN, Si 3 N 4 , diamond, SiC, B 2 O 3 etc. You may add and you may add resin powder, such as a silicone resin and an acrylic resin. The powder shape is often spherical, but is not limited thereto, and a crushed shape, a granular shape, a flake shape, an aggregate, or the like may be used. The filling amount of the powder may be an amount that can provide the necessary fluidity, insulation, and adhesiveness. However, the elastic modulus of the second sealing resin 120 must be smaller than the elastic modulus of the first sealing resin 12.

本発明は、本実施の形態1のみならず他の実施の形態においても、電力用半導体素子として、150℃以上で動作する半導体素子に適用すると効果が大きい。特に、炭化珪素(SiC)、窒化ガリウム(GaN)系材料またはダイアモンドといった材料で形成された、珪素(Si)に比べてバンドギャップが大きい、いわゆるワイドバンドギャップ半導体に適用すると効果が大きい。また、図2では、一つのモールドされた半導体装置に半導体素子が4個しか搭載されていないが、これに限定するものではなく、使用される用途に応じて必要な個数の半導体素子を搭載することができる。   The present invention is effective not only in the first embodiment but also in other embodiments when applied to a semiconductor element operating at 150 ° C. or more as a power semiconductor element. In particular, the present invention is more effective when applied to a so-called wide band gap semiconductor, which is formed of a material such as silicon carbide (SiC), gallium nitride (GaN) -based material, or diamond and has a larger band gap than silicon (Si). Further, in FIG. 2, only four semiconductor elements are mounted on one molded semiconductor device, but the present invention is not limited to this, and a necessary number of semiconductor elements are mounted according to the intended use. be able to.

表面電極パターン2、裏面電極パターン3、ベース板10および端子14は、通常銅を用いるが、これに限定するものではなく、アルミや鉄を用いても良く、これらを複合した材料を用いても良い。また表面は、通常、ニッケルメッキを行うが、これに限定するものではなく、金や錫メッキを行っても良く、必要な電流と電圧を半導体素子に供給できる構造であれば構わない。また、銅/インバー/銅などの複合材料を用いても良く、SiCAl、CuMoなどの合金を用いても良い。また、端子14及び表面電極パターン2は、第一の封止樹脂12に埋設されるため、樹脂との密着性を向上させるため表面に微小な凹凸を設けても良く、化学的に結合するようにシランカップリング剤などで接着補助層を設けても良い。   The front electrode pattern 2, the back electrode pattern 3, the base plate 10 and the terminal 14 are usually made of copper, but are not limited to this, and aluminum or iron may be used, or a composite material of these may be used. good. The surface is usually nickel-plated, but the present invention is not limited to this, and gold or tin-plating may be performed, as long as a necessary current and voltage can be supplied to the semiconductor element. Further, a composite material such as copper / invar / copper may be used, and an alloy such as SiCAl or CuMo may be used. Further, since the terminal 14 and the surface electrode pattern 2 are embedded in the first sealing resin 12, a minute unevenness may be provided on the surface in order to improve the adhesion with the resin, so that they are chemically bonded. An adhesion auxiliary layer may be provided with a silane coupling agent or the like.

半導体素子基板4は、Al2O3、SiO2、AlN、BN、Si3N4などのセラミックの絶縁基板1に
銅やアルミの表面電極パターン2および裏面電極パターン3を設けてあるものを指す。半導体素子基板4は、放熱性と絶縁性を備えることが必要であり、上記に限らず、セラミック粉を分散させた樹脂硬化物、あるいはセラミック板を埋め込んだ樹脂硬化物のような絶縁基板1に表面電極パターン2および裏面電極パターン3を設けたものでも良い。また、絶縁基板1に使用するセラミック粉は、Al2O3、SiO2、AlN、BN、Si3N4などが用いられる
が、これに限定するものではなく、ダイアモンド、SiC、B2O3、などを用いても良い。ま
た、シリコーン樹脂やアクリル樹脂などの樹脂製の粉を用いても良い。粉形状は、球状を用いることが多いが、これに限定するものではなく、破砕状、粒状、リン片状、凝集体などを用いても良い。粉体の充填量は、必要な放熱性と絶縁性が得られる量が充填されていれば良い。絶縁基板1に用いる樹脂は、通常エポキシ樹脂が用いられるが、これに限定するものではなく、ポリイミド樹脂、シリコーン樹脂、アクリル樹脂などを用いても良く、絶縁性と接着性を兼ね備えた材料であれば構わない。
The semiconductor element substrate 4 refers to a ceramic insulating substrate 1 such as Al 2 O 3 , SiO 2 , AlN, BN, and Si 3 N 4 provided with a surface electrode pattern 2 and a back electrode pattern 3 of copper or aluminum. . The semiconductor element substrate 4 is required to have heat dissipation and insulating properties, and is not limited to the above, and the insulating substrate 1 such as a cured resin material in which ceramic powder is dispersed or a cured resin material in which a ceramic plate is embedded is used. A surface electrode pattern 2 and a back electrode pattern 3 may be provided. The ceramic powder used for the insulating substrate 1 is Al 2 O 3 , SiO 2 , AlN, BN, Si 3 N 4, etc., but is not limited to this, and diamond, SiC, B 2 O 3 , Etc. may be used. Further, resin powder such as silicone resin and acrylic resin may be used. The powder shape is often spherical, but is not limited thereto, and a crushed shape, a granular shape, a flake shape, an aggregate, or the like may be used. The filling amount of the powder is not limited as long as the necessary heat dissipation and insulation are obtained. The resin used for the insulating substrate 1 is usually an epoxy resin, but is not limited to this, and a polyimide resin, a silicone resin, an acrylic resin, or the like may be used as long as the material has both insulating properties and adhesiveness. It doesn't matter.

配線13は、アルミまたは金でできた断面が円形の線体を用いるが、これに限定するものではなく、例えば断面が方形の銅板を帯状にしたものを用いても良い。また図1では、半導体素子に3本の配線しか施されていないが、これに限定するものではなく、半導体素子の電流密度などにより、必要な本数を設けることができる。また、配線13は、銅や錫などの金属片を溶融金属で接合しても良く、必要な電流と電圧を半導体素子に供給できる構造であれば構わない。   The wiring 13 uses a wire body having a circular cross section made of aluminum or gold, but is not limited to this, and for example, a copper plate having a rectangular cross section may be used. In FIG. 1, only three wirings are provided in the semiconductor element. However, the number is not limited to this, and a necessary number can be provided depending on the current density of the semiconductor element. The wiring 13 may be a structure in which metal pieces such as copper and tin may be joined with molten metal as long as a necessary current and voltage can be supplied to the semiconductor element.

さらに、配線に銅板配線130を用いた例を図3に示す。図3において、図1と同一符号は同一または相当する部分を示す。銅板配線130の表面は、防錆のためにニッケル鍍金を用いてもよく、防錆剤などの化学的処理を行っても良い。また、各封止樹脂との密着性を高めるために、表面に凹凸を設けても良く、またプライマー処理等の密着性向上剤を設けても良い。密着性向上剤は、例えばシランカップリング剤やポリイミド、エポキシ樹脂等が用いられるが、用いる配線部材と、第一の封止樹脂との密着性を向上させるものであれば特に限定されない。ここでは、配線として銅板を用いた例を示したが、端子と電気的に接続することができ、半導体素子とも電気的に接続することができ、必要な電流容量を確保できる材料であれば、銅以外の金属を用いても良い事は言うまでも無い。   Further, an example in which the copper plate wiring 130 is used for the wiring is shown in FIG. 3, the same reference numerals as those in FIG. 1 denote the same or corresponding parts. The surface of the copper plate wiring 130 may use nickel plating for rust prevention or may be subjected to chemical treatment such as a rust prevention agent. Moreover, in order to improve adhesiveness with each sealing resin, an unevenness | corrugation may be provided in the surface and adhesiveness improvement agents, such as a primer process, may be provided. As the adhesion improver, for example, a silane coupling agent, polyimide, epoxy resin, or the like is used, but is not particularly limited as long as it improves the adhesion between the wiring member to be used and the first sealing resin. Here, an example in which a copper plate is used as the wiring is shown, but if it is a material that can be electrically connected to a terminal, can be electrically connected to a semiconductor element, and can secure a necessary current capacity, Needless to say, metals other than copper may be used.

本発明の実施の形態1による半導体装置の動作は以下のようである。半導体素子が高温で動作すると、半導体素子の周囲にある第一の封止樹脂12や半導体素子基板4が熱膨張し、半導体素子が動作を止めると、熱収縮が起こる。すなわちヒートサイクルが生じる。第一の封止樹脂12は、半導体素子基板4の材料のうち表面電極パターン2や裏面電極パターン3の材料(例えば銅)の線膨張係数に近い線膨張係数となるように調整されているため、絶縁基板1とは線膨張係数が異なる。従来の半導体装置では、半導体素子基板の表面電極パターン2や裏面電極パターン3が形成されていない部分は、第一の封止樹脂12と絶縁基板1が直接接しているため、ヒートサイクルを繰り返すうちに、両者の線膨張係数の違いにより、第一の封止樹脂12と絶縁基板1との接触部分で、第一の封止樹脂12の剥離や亀裂が発生し、半導体装置の信頼性を著しく低下させていた。しかしながら、図1に示す本発明の実施の形態1による半導体装置では、半導体素子基板4単体において絶縁基板1が露出している部分は、第一の封止樹脂12よりも弾性率が低い樹脂材料で形成された第二の封止樹脂120で覆われている。このため、ヒートサイクルが生じた場合、第一の封止樹脂12よりも低弾性、すなわち軟らかい第二の封止樹脂120の部分で、膨張係数の違いにより発生する応力が緩和され、第一の封止樹脂12の剥離や亀裂が生じ難く、信頼性の高い半導体装置を得ることができる。   The operation of the semiconductor device according to the first embodiment of the present invention is as follows. When the semiconductor element operates at a high temperature, the first sealing resin 12 and the semiconductor element substrate 4 around the semiconductor element thermally expand, and when the semiconductor element stops operating, thermal contraction occurs. That is, a heat cycle occurs. The first sealing resin 12 is adjusted so as to have a linear expansion coefficient close to the linear expansion coefficient of the material (for example, copper) of the surface electrode pattern 2 and the back electrode pattern 3 among the materials of the semiconductor element substrate 4. The linear expansion coefficient is different from that of the insulating substrate 1. In the conventional semiconductor device, since the first sealing resin 12 and the insulating substrate 1 are in direct contact with the portion of the semiconductor element substrate where the front electrode pattern 2 and the back electrode pattern 3 are not formed, the heat cycle is repeated. In addition, due to the difference in linear expansion coefficient between them, the first sealing resin 12 is peeled off or cracked at the contact portion between the first sealing resin 12 and the insulating substrate 1, and the reliability of the semiconductor device is remarkably increased. It was decreasing. However, in the semiconductor device according to the first embodiment of the present invention shown in FIG. 1, the portion where the insulating substrate 1 is exposed in the single semiconductor element substrate 4 is a resin material having a lower elastic modulus than the first sealing resin 12. It is covered with the second sealing resin 120 formed in (1). For this reason, when a heat cycle occurs, the stress generated by the difference in the expansion coefficient is relieved in the portion of the second sealing resin 120 that is lower in elasticity than the first sealing resin 12, that is, softer. A highly reliable semiconductor device can be obtained in which peeling or cracking of the sealing resin 12 hardly occurs.

さらに、図1や図3に示すように、第一の封止樹脂12の側面121の形状が、絶縁基板1に対して垂直な面で切り取った断面において直線となる形状である。この形状は、以下の実施の形態2で説明する製造方法によって実現されるものであり、従来行われていたように、材料となる樹脂を半導体素子の上に、いわゆるポッティングにより形成したものでは実現できない形状である。この形状により、従来のポッティングによって形成される樹脂の形状に比較して、第一の封止樹脂の底面積が小さくても絶縁距離を確保できる半導体装置が得られる。   Furthermore, as shown in FIG. 1 and FIG. 3, the shape of the side surface 121 of the first sealing resin 12 is a shape that is a straight line in a cross section cut by a plane perpendicular to the insulating substrate 1. This shape is realized by the manufacturing method described in the second embodiment below, and is realized when a resin as a material is formed on a semiconductor element by so-called potting as conventionally performed. It is a shape that cannot be done. With this shape, it is possible to obtain a semiconductor device that can secure an insulation distance even when the bottom area of the first sealing resin is small compared to the shape of a resin formed by conventional potting.

実施の形態2.
図4、図5は、本発明の実施の形態2による半導体装置の製造方法を示す模式図である。図4、図5において、図1、図2と同一符号は同一または相当する部分を示す。本製造方法の概要は、以下のようである。まず、半導体素子基板4における絶縁基板1の表面電極パターン2または裏面電極パターン3が形成されていない面を、絶縁基板1の周辺部分においては半導体素子の厚みよりも高さが高い仮設壁9を形成するようマスキング樹脂で覆う(マスキング樹脂被覆工程)。次に、表面電極パターン2に半導体素子を固着して、仮設壁9の内部を第一の封止樹脂12で覆い(第一の封止樹脂形成工程)、マスキング樹脂を除去する(マスキング樹脂除去工程)。その後、絶縁基板1の表面電極パターン2または裏面電極パターン3が形成されていない面、および第一の封止樹脂12を覆うように第二の封止樹脂120を設ける(第二の封止樹脂形成工程)。マスキング樹脂は、注射器に未硬化の樹脂を入れて、必要な箇所に押し出しながら描画したり、スクリーンマスクを用いて印刷を行ったりして作製できる。しかし、これらの方法では作製に時間がかかる。半導体素子基板4の表面電極パターン2と裏面電極パターン3を、溝を設けた治具で挟み、その後に未硬化のマスキング樹脂を注入硬化すれば、溝の位置や形状を変えることで多様な仮設壁9を設けることができ、また絶縁基板1の表面電極パターンまたは裏面電極パターンが形成されていない面がマスキング樹脂で覆われた基板を作製できる。
Embodiment 2. FIG.
4 and 5 are schematic views showing a method of manufacturing a semiconductor device according to the second embodiment of the present invention. 4 and 5, the same reference numerals as those in FIGS. 1 and 2 denote the same or corresponding parts. The outline of this manufacturing method is as follows. First, a surface of the semiconductor element substrate 4 on which the surface electrode pattern 2 or the back electrode pattern 3 of the insulating substrate 1 is not formed is provided on the peripheral portion of the insulating substrate 1 with a temporary wall 9 having a height higher than the thickness of the semiconductor element. Cover with masking resin to form (masking resin coating step). Next, a semiconductor element is fixed to the surface electrode pattern 2, and the interior of the temporary wall 9 is covered with the first sealing resin 12 (first sealing resin forming step), and the masking resin is removed (masking resin removal). Process). Thereafter, a second sealing resin 120 is provided so as to cover the surface of the insulating substrate 1 where the front electrode pattern 2 or the back electrode pattern 3 is not formed and the first sealing resin 12 (second sealing resin). Forming step). The masking resin can be produced by putting an uncured resin in a syringe and drawing it while extruding it to a required location, or printing using a screen mask. However, these methods take time to produce. If the front surface electrode pattern 2 and the back surface electrode pattern 3 of the semiconductor element substrate 4 are sandwiched by a jig provided with a groove, and then uncured masking resin is injected and cured, various temporary structures can be obtained by changing the position and shape of the groove. A wall 9 can be provided, and a substrate on which the surface electrode pattern or the back electrode pattern of the insulating substrate 1 is not formed can be produced.

図4は、マスキング樹脂被覆工程を説明する模式図である。まず、絶縁基板1の片面に表面電極パターン2、他方の面に裏面電極パターン3、が貼りつけられた半導体素子基板4を準備する(図4(A))。また、テフロン(登録商標)で作製された上治具21と下治具22で構成される分割式の治具を準備する(図4(B))。上治具21にはマスキング樹脂を注入するための樹脂注入穴23が設けられている。下治具22の所定の位置に半導体素子基板4を置き、位置がずれない様に上治具21を用いて蓋をし、ねじ留めや油圧プレス等の方法を用いて、後にマスキング樹脂が注入された際に上下の治具からマスキング樹脂が漏れないよう十分締め付ける。上治具21および下治具22は、表面電極パターン2および裏面電極パターン3の表面にマスキング樹脂が流れないよう、十分な平面度をもって作製しておく。次に半導体素子基板4を内包した治具の内部を減圧チャンバー31等を用いて10torrまで減圧する(図4(C))。その後、図4(C)の矢印で示すように未硬化のマスキング樹脂41を上治具21の樹脂注入穴23から約1MPaの押圧力で注入
する。治具の空間部分の全部にマスキング樹脂が注入されたら、760torr(大気)に戻し
、マスキング樹脂を熱硬化させる。例えば、マスキング樹脂としてシリコーン樹脂である信越化学工業社製KE-1833を用いる場合は、120℃で1時間の硬化を行う。熱硬化後は、治
具を室温まで冷却してから、上下の治具を分割して基板を取り出せば、マスキング樹脂で形成された仮設壁9が成型され、また図4(C)に示す表面電極パターン2が存在しない部分20もマスキング樹脂90で満たされた基板が作製できる(図4(D))。
FIG. 4 is a schematic diagram for explaining the masking resin coating step. First, a semiconductor element substrate 4 having a surface electrode pattern 2 attached to one surface of an insulating substrate 1 and a back electrode pattern 3 attached to the other surface is prepared (FIG. 4A). Further, a split-type jig composed of an upper jig 21 and a lower jig 22 made of Teflon (registered trademark) is prepared (FIG. 4B). The upper jig 21 is provided with a resin injection hole 23 for injecting a masking resin. The semiconductor element substrate 4 is placed at a predetermined position of the lower jig 22, and the upper jig 21 is covered so that the position does not shift, and then a masking resin is injected later using a method such as screwing or hydraulic press. Tighten the masking resin so that it does not leak from the upper and lower jigs. The upper jig 21 and the lower jig 22 are prepared with sufficient flatness so that the masking resin does not flow on the surfaces of the front electrode pattern 2 and the back electrode pattern 3. Next, the inside of the jig containing the semiconductor element substrate 4 is decompressed to 10 torr using the decompression chamber 31 or the like (FIG. 4C). Thereafter, as shown by an arrow in FIG. 4C, uncured masking resin 41 is injected from the resin injection hole 23 of the upper jig 21 with a pressing force of about 1 MPa. When the masking resin is injected into the entire space of the jig, it is returned to 760 torr (atmosphere), and the masking resin is thermally cured. For example, when KE-1833 manufactured by Shin-Etsu Chemical Co., Ltd., which is a silicone resin, is used as the masking resin, curing is performed at 120 ° C. for 1 hour. After thermosetting, the jig is cooled to room temperature, and then the upper and lower jigs are divided and the substrate is taken out, whereby the temporary wall 9 formed of the masking resin is formed, and the surface shown in FIG. A substrate filled with the masking resin 90 in the portion 20 where the electrode pattern 2 does not exist can be manufactured (FIG. 4D).

この時、一か所の樹脂注入穴23から全ての空間部分に樹脂が注入されるよう、表面電極パターン2および裏面電極パターン3以外の表面、例えば図4(C)に示す表面電極パターン2がない部分20と、仮設壁9を設ける箇所は、治具内部の空間で繋がっていなければならない。ここで、治具には、脱気用の穴を設けても良い。また、治具の壁面に、脱型性を向上させるために、離型剤を塗布しても良いことは言うまでもなく、治具の材質もテフロン(登録商標)以外の材料を用いて良い事はいうまでもない。   At this time, the surface other than the front surface electrode pattern 2 and the back surface electrode pattern 3, for example, the front surface electrode pattern 2 shown in FIG. 4C is provided so that the resin is injected into all the space portions from one resin injection hole 23. The part 20 where the temporary wall 9 is not provided must be connected to the space inside the jig. Here, the jig may be provided with a deaeration hole. Moreover, it goes without saying that a mold release agent may be applied to the wall surface of the jig to improve the demolding property, and that the jig may be made of a material other than Teflon (registered trademark). Needless to say.

なお、実施の形態1および実施の形態2では、表面電極パターン2が、例えば図2で示すように分離されて、間に絶縁基板が露出している部分20があるものを例として説明したが、表面電極パターン2が分離せず1枚で、絶縁基板が露出している部分は周辺部分のみのものにも、本発明を適用できるのは言うまでもない。   In the first and second embodiments, the surface electrode pattern 2 is separated as shown in FIG. 2, for example, and the insulating substrate is exposed between the surface electrode patterns 2 as an example. Needless to say, the present invention can be applied to the case where the surface electrode pattern 2 is not separated but is a single piece and the portion where the insulating substrate is exposed is only the peripheral portion.

次に、仮設壁9が設けられた半導体素子基板4を用いて半導体装置を製造する製造方法を、図5を参照して説明する。端子14が取り付けられたケース側板11とベース板10とで形成されるケースを、仮設壁9が設けられた半導体素子基板4とは別に準備する。このケースの底板となったベース板に仮設壁9が設けられた半導体素子基板4を、はんだなどの接合材70により固着する。同時に半導体素子基板4の表面電極パターンに半導体素子5や6をはんだなどの接合材7により固着する(半導体素子固着工程)。その後、半導体素子5、6、表面電極パターン2、端子14の間を配線13で接続する(図5(A))。   Next, a manufacturing method for manufacturing a semiconductor device using the semiconductor element substrate 4 provided with the temporary walls 9 will be described with reference to FIG. A case formed by the case side plate 11 to which the terminal 14 is attached and the base plate 10 is prepared separately from the semiconductor element substrate 4 provided with the temporary wall 9. The semiconductor element substrate 4 provided with the temporary wall 9 is fixed to the base plate which is the bottom plate of the case by a bonding material 70 such as solder. At the same time, the semiconductor elements 5 and 6 are fixed to the surface electrode pattern of the semiconductor element substrate 4 with a bonding material 7 such as solder (semiconductor element fixing step). Thereafter, the semiconductor elements 5 and 6, the surface electrode pattern 2, and the terminals 14 are connected by wiring 13 (FIG. 5A).

次に、仮設壁9内部を第一の封止樹脂12で満たして硬化させた(第一の封止樹脂形成工程、図5(B))後、マスキング樹脂で形成されている仮設壁9および表面電極パターン2が無い部分20のマスキング樹脂90を溶剤により除去する(マスキング樹脂除去工程、図5(C))。この時、マスキング樹脂を完全に除去するために、必要に応じて加温や、複数回の洗浄処理を行う。ここで、マスキング樹脂が除去された後、第一の封止樹脂12が仮設壁9と接していた面、すなわち第一の封止樹脂の側面121の形状は、絶縁基板1に垂直な断面である図5(C)において、直線となる形状になる。マスキング樹脂が完全に除去された後、ケース内に第二の封止樹脂を注入して全体をモールドする(第二の封止樹脂形成工程、図5(D))。この注入に際し、表面電極パターン2が無い部分20にも第二の封止樹脂120が完全に注入されるように、必要に応じて脱泡処理を行う。   Next, after the inside of the temporary wall 9 is filled with the first sealing resin 12 and cured (first sealing resin forming step, FIG. 5B), the temporary wall 9 formed of the masking resin and The masking resin 90 in the portion 20 without the surface electrode pattern 2 is removed with a solvent (masking resin removal step, FIG. 5C). At this time, in order to completely remove the masking resin, heating or a plurality of washing processes are performed as necessary. Here, after the masking resin is removed, the surface of the first sealing resin 12 in contact with the temporary wall 9, that is, the shape of the side surface 121 of the first sealing resin is a cross section perpendicular to the insulating substrate 1. In FIG. 5C, the shape becomes a straight line. After the masking resin is completely removed, a second sealing resin is injected into the case and the whole is molded (second sealing resin forming step, FIG. 5D). At the time of this injection, a defoaming process is performed as necessary so that the second sealing resin 120 is completely injected also into the portion 20 without the surface electrode pattern 2.

マスキング樹脂には、熱可塑性樹脂および熱硬化性樹脂を用いることができる。マスキング樹脂材料は、半導体素子を覆う第一の封止樹脂が流れ広がるのを防止するダム壁として機能し、第一の封止樹脂の硬化温度領域において形状を維持できて、しかも第一の封止樹脂が硬化後に溶剤処理および熱処理等の方法で除去することが可能であれば特に限定されない。   As the masking resin, a thermoplastic resin and a thermosetting resin can be used. The masking resin material functions as a dam wall that prevents the first sealing resin covering the semiconductor element from flowing and spreading, and can maintain its shape in the curing temperature region of the first sealing resin, and also the first sealing resin. There is no particular limitation as long as the stop resin can be removed by a method such as solvent treatment and heat treatment after curing.

例えば、マスキング樹脂には、シリコーン樹脂を用いることができる。シリコーン樹脂で作製されたマスキング樹脂は、シリコーン溶解液により室温で除去が可能であることがわかった。また、マスキング樹脂には、熱可塑性のワックスを用いてもよい。熱可塑性のワックスを用いて、仮設壁を作製した場合は、ワックス溶解液もしくは、炭化水素系溶剤により除去が可能であることがわかった。熱可塑性ワックスをマスキング樹脂として仮設壁に用いる際は、第一の封止樹脂の硬化温度より熱可塑性ワックスの軟化温度が高ければ、第一の封止樹脂が半導体素子上を覆う際に、仮設壁としての役割を果たせることができた。また、熱可塑性ワックスの軟化温度が第一の封止樹脂の硬化温度より低い場合は、第一の封止樹脂の1段階目の硬化温度を熱可塑性ワックスの軟化温度より低い温度に設定し、第一の封止樹脂を半硬化させ、ワックス溶解液により熱可塑性ワックスを除去した後、第一の封止樹脂を所定の硬化温度でさらに硬化させることで、絶縁信頼性の高い半導体装置を作製できることがわかった。   For example, a silicone resin can be used as the masking resin. It was found that the masking resin made of silicone resin can be removed at room temperature with a silicone solution. A thermoplastic wax may be used as the masking resin. It has been found that when a temporary wall is made using a thermoplastic wax, it can be removed with a wax solution or a hydrocarbon solvent. When the thermoplastic wax is used as a masking resin for the temporary wall, if the softening temperature of the thermoplastic wax is higher than the curing temperature of the first sealing resin, the temporary sealing is performed when the first sealing resin covers the semiconductor element. I was able to play the role of a wall. Further, when the softening temperature of the thermoplastic wax is lower than the curing temperature of the first sealing resin, the first stage curing temperature of the first sealing resin is set to a temperature lower than the softening temperature of the thermoplastic wax, After semi-curing the first sealing resin and removing the thermoplastic wax with a wax solution, the first sealing resin is further cured at a predetermined curing temperature, thereby producing a semiconductor device with high insulation reliability. I knew it was possible.

仮設壁9の高さは、第一の封止樹脂12が半導体素子5、6を覆うように、半導体素子5、6の高さ以上であれば、特に限定するものではないが、半導体装置のケース側板11の高さを超えない高さ程度が好ましい。また、仮設壁9の幅は、絶縁基板1の大きさが100mm×100mm以下のサイズが多い事から、1〜2mm程度が良いが、これに限定するものではなく、第一の封止樹脂を変形しないように区画するのに必要な幅であれば構わない。   The height of the temporary wall 9 is not particularly limited as long as it is equal to or higher than the height of the semiconductor elements 5 and 6 so that the first sealing resin 12 covers the semiconductor elements 5 and 6. A height that does not exceed the height of the case side plate 11 is preferable. The width of the temporary wall 9 is preferably about 1 to 2 mm because the size of the insulating substrate 1 is often 100 mm × 100 mm or less. However, the width is not limited to this, and the first sealing resin is used. Any width may be used as long as it is necessary for partitioning so as not to be deformed.

以上のように、本発明の実施の形態2による半導体装置の製造方法においては、仮設壁を用いて第一の封止樹脂を形成するため、仮設壁の高さを変更することにより容易に、第一の封止樹脂の封止量を変更することができ、絶縁距離を調整することができる。また、仮設壁9を残したまま、第二の封止樹脂で覆うことも考えられるが、仮設壁9にボイドが発生していたり、仮設壁9と絶縁基板1の接触部の密着性が悪かったりすると、耐絶縁性が低下する恐れがある。これに対し本発明では、仮設壁を除去し、絶縁基板が露出する部分を弾性率が小さい第二の封止樹脂で覆うため、耐絶縁性が低下する恐れが小さい。したがって、信頼性の高い半導体装置を得ることができる。   As described above, in the method for manufacturing a semiconductor device according to the second embodiment of the present invention, since the first sealing resin is formed using the temporary wall, it is easy to change the height of the temporary wall. The sealing amount of the first sealing resin can be changed, and the insulation distance can be adjusted. Further, it is conceivable to cover the temporary wall 9 with the second sealing resin while leaving the temporary wall 9, but voids are generated in the temporary wall 9 or the adhesion between the temporary wall 9 and the insulating substrate 1 is poor. In such a case, the insulation resistance may be reduced. On the other hand, in the present invention, the temporary wall is removed, and the portion where the insulating substrate is exposed is covered with the second sealing resin having a low elastic modulus, so that there is little possibility that the insulation resistance is lowered. Therefore, a highly reliable semiconductor device can be obtained.

実施の形態3.
図6は、本発明の実施の形態3による半導体装置の構造を示す断面図である。図6において、図1、図3と同一符号は、同一または相当する部分を示す。本実施の形態3では、半導体素子5や6に配線を接続するためのソケット131を設けた。第一の封止樹脂12
で覆った後に外部からソケット131に配線を差し込むことができるよう、ソケット131は、第一の封止樹脂12の表面に露出するように設けられている。
Embodiment 3 FIG.
FIG. 6 is a cross-sectional view showing the structure of the semiconductor device according to the third embodiment of the present invention. 6, the same reference numerals as those in FIGS. 1 and 3 denote the same or corresponding parts. In the third embodiment, the socket 131 for connecting the wiring to the semiconductor elements 5 and 6 is provided. First sealing resin 12
The socket 131 is provided so as to be exposed on the surface of the first sealing resin 12 so that wiring can be inserted into the socket 131 from the outside after being covered with.

通常、ソケットは、パイプ上の金属に金属状のピンを挿入することで両者の電気的な接続を行うが、この方法に限定するものではなく、第一の封止樹脂12に埋め込まれた半導体素子5や6と配線を電気的に繋げる構造であれば構わない。また、ソケット131の表面は、第一の封止樹脂12や第二の封止樹脂120との密着性を向上させるために表面に凹凸を設けても良く、シランカップリング剤などの化学的な処理を行っても良い。半導体素子5や6とソケット131の電気的な接続は、通常、はんだ材を用いて接続するがこれに限定するものではなく、銀ペーストや焼結により金属結合する材料を用いても良い。図6では、ソケット131への配線は銅板配線130を用いているが、通常の線状の配線を用いても良いのは言うまでもない。   Normally, the socket is electrically connected to each other by inserting a metal pin into the metal on the pipe, but the method is not limited to this method, and the semiconductor embedded in the first sealing resin 12 is used. Any structure that electrically connects the elements 5 and 6 and the wiring may be used. Further, the surface of the socket 131 may be provided with irregularities on the surface in order to improve the adhesion with the first sealing resin 12 or the second sealing resin 120, and a chemical such as a silane coupling agent may be provided. Processing may be performed. The electrical connection between the semiconductor elements 5 and 6 and the socket 131 is usually performed using a solder material, but is not limited to this, and a silver paste or a material that is metal-bonded by sintering may be used. In FIG. 6, the copper wiring 130 is used for the wiring to the socket 131, but it goes without saying that a normal linear wiring may be used.

図6の破線で囲んだ部分、すなわち第一の封止樹脂12で半導体素子5、6を封止したものをモジュール100として、このモジュール100をケース側板11内に複数個配置して一つの半導体装置とした構成の概念図を図7に示す。図7において、図6と同一符号は同一または相当する部分を示す。図7は、第二の封止樹脂120、端子14および銅板配線130を取り除き、さらに一部は第一の封止樹脂12も取り除き半導体素子が見える状態を示す斜視図である。図7において、各モジュールの間に設けられているバー110は、各モジュールからの配線を橋渡しするための端子(図7では取り除いて示している。)を取り付けるための部材である。   A portion surrounded by a broken line in FIG. 6, that is, the semiconductor element 5, 6 sealed with the first sealing resin 12 is used as a module 100, and a plurality of modules 100 are arranged in the case side plate 11 to form one semiconductor. A conceptual diagram of the configuration of the apparatus is shown in FIG. 7, the same reference numerals as those in FIG. 6 denote the same or corresponding parts. FIG. 7 is a perspective view showing a state in which the second sealing resin 120, the terminal 14 and the copper plate wiring 130 are removed, and a part of the first sealing resin 12 is also removed, and the semiconductor element can be seen. In FIG. 7, a bar 110 provided between the modules is a member for attaching a terminal (not shown in FIG. 7) for bridging the wiring from each module.

この構造では、第一の封止樹脂12で半導体素子5、6を封止した後、第二の封止樹脂120でモジュールを封止する前に、ソケット131から通電することにより各モジュール100の動作試験を行うことができる。動作試験において不良モジュールが判明した場合、不良モジュールについては、半導体素子基板4とベース板10の間の接合を取り除き、良品モジュールと置き換えることができるため、半導体装置の歩留まりの向上が図れる。   In this structure, the semiconductor elements 5 and 6 are sealed with the first sealing resin 12 and then energized from the socket 131 before the module is sealed with the second sealing resin 120. An operation test can be performed. When a defective module is found in the operation test, the defective module can be replaced with a non-defective module by removing the bonding between the semiconductor element substrate 4 and the base plate 10, so that the yield of the semiconductor device can be improved.

実施の形態4.
本実施の形態4では、試験用の半導体装置モジュールを、種々の材料を用いた封止樹脂により作製し、パワーサイクル試験およびヒートサイクル試験を行った結果を実施例として示す。パワーサイクル試験は、半導体素子の温度が200℃になるまで通電し、その温度に達したら通電を止め、半導体素子の温度が120℃になるまで冷却し、冷却された後に再び通電した。またヒートサイクル試験は、半導体装置全体を、温度制御が可能な恒温曹に入れ、恒温曹の温度を−40℃〜150℃の間で繰り返し変化させて実施した。
Embodiment 4 FIG.
In the fourth embodiment, a test semiconductor device module is manufactured using a sealing resin using various materials, and the results of a power cycle test and a heat cycle test are shown as examples. In the power cycle test, energization was performed until the temperature of the semiconductor element reached 200 ° C., and when the temperature reached that temperature, the energization was stopped, the temperature of the semiconductor element was cooled to 120 ° C., and the current was again energized. In addition, the heat cycle test was performed by putting the entire semiconductor device in a thermostat capable of temperature control, and repeatedly changing the temperature of the thermostat so as to be between −40 ° C. and 150 ° C.

実施例1.
表1には、図2に示した構造、すなわち半導体素子基板を封止する第一の封止樹脂の弾性率を変化させた時のパワーサイクル試験およびヒートサイクル試験の結果を示す。
Example 1.
Table 1 shows the structure shown in FIG. 2, that is, the results of the power cycle test and the heat cycle test when the elastic modulus of the first sealing resin for sealing the semiconductor element substrate is changed.

表1の例1−1について説明する。信越化学工業社製KER-4000-UVにガラスフィラーを
約50wt%添加し、弾性率を900MPaに調整した封止樹脂で封止した結果、パワーサイクル試
験では、90000サイクル後に封止樹脂に剥離が発生し、ヒートサイクル試験でも50サイク
ル後に封止樹脂の剥離と亀裂が発生して半導体装置が動作しなくなることがわかった。
Example 1-1 in Table 1 will be described. As a result of adding about 50 wt% glass filler to KER-4000-UV manufactured by Shin-Etsu Chemical Co., Ltd. and sealing with a sealing resin with an elastic modulus adjusted to 900 MPa, in the power cycle test, the sealing resin was peeled after 90000 cycles. In the heat cycle test, it was found that after 50 cycles, peeling and cracking of the sealing resin occurred and the semiconductor device stopped operating.

例1−2では、信越化学工業社製KER-4000-UVにガラスフィラーを約58wt%添加し、弾性率を1GPaに調整した封止樹脂で封止した結果、パワーサイクル試験では、160000サイクル、ヒートサイクル試験では、300サイクルまで改善することがわかった。   In Example 1-2, as a result of adding about 58 wt% of a glass filler to KER-4000-UV manufactured by Shin-Etsu Chemical Co., Ltd. and sealing with a sealing resin with an elastic modulus adjusted to 1 GPa, in the power cycle test, 160,000 cycles, In the heat cycle test, it was found to improve up to 300 cycles.

例1−3では、サンユレック社製EX-550(弾性率7.0GPa)を第一の封止樹脂に用いた結果、パワーサイクル試験では、180000サイクル、ヒートサイクル試験では、800サイクル
まで改善することがわかった。
In Example 1-3, as a result of using EX-550 (elastic modulus: 7.0 GPa) manufactured by San Yulec Co., Ltd. as the first sealing resin, it can be improved to 180,000 cycles in the power cycle test and 800 cycles in the heat cycle test. all right.

例1−4では、サンユレック社製EX-550にシリカフィラーを15wt%添加し、弾性率を12GPaに調整した封止樹脂を使用した結果、パワーサイクル試験では、160000サイクル、ヒートサイクル試験では、600サイクルになることがわかった。   In Example 1-4, 15% by weight of silica filler was added to EX-550 manufactured by San Yulec Co., Ltd., and a sealing resin having an elastic modulus adjusted to 12 GPa was used. As a result, 160,000 cycles were used in the power cycle test and 600 samples were used in the heat cycle test. It turned out to be a cycle.

例1−5では、サンユレック社製EX-550にシリカフィラーを20wt%添加し、弾性率を14GPaに調整した封止樹脂を使用した結果、パワーサイクル試験では、140000サイクル、ヒートサイクル試験では、500サイクルになることがわかった。   In Example 1-5, as a result of using a sealing resin in which 20 wt% of silica filler was added to EX-550 manufactured by San Yulec Co., Ltd. and the elastic modulus was adjusted to 14 GPa, it was 14,000 cycles in the power cycle test, and 500 in the heat cycle test. It turned out to be a cycle.

例1−6では、サンユレック社製EX-550にシリカフィラーを36wt%添加し、弾性率を20GPaに調整した封止樹脂を使用した結果、パワーサイクル試験では、110000サイクル、ヒートサイクル試験では、450サイクルになることがわかった。   In Example 1-6, 36 wt% of silica filler was added to EX-550 manufactured by Sanyu Rec Co., Ltd., and a sealing resin having an elastic modulus adjusted to 20 GPa was used. As a result, 110000 cycles in the power cycle test and 450 cycles in the heat cycle test. It turned out to be a cycle.

例1−7では、サンユレック社製EX-550にシリカフィラーを40wt%添加し、弾性率を22 GPaに調整した封止樹脂を使用した結果、パワーサイクル試験では、100000サイクル、ヒ
ートサイクル試験では、200サイクルになることがわかった。
In Example 1-7, 40 wt% of silica filler was added to EX-550 manufactured by Sanyu Rec Co., Ltd., and a sealing resin with an elastic modulus adjusted to 22 GPa was used. As a result, in the power cycle test, 100,000 cycles, It turned out to be 200 cycles.

以上の結果より、第一の封止樹脂の弾性率Mは、1GPa以上20GPa以下の範囲が適切であ
ることが判明した。
From the above results, it has been found that the elastic modulus M of the first sealing resin is appropriately in the range of 1 GPa to 20 GPa.

Figure 2013004766
Figure 2013004766

実施例2.
次に、第二の封止樹脂を種々の弾性率の樹脂により作製し、絶縁特性を評価した実施例について説明する。半導体装置には、ベース板のサイズが50×92×3mm、AlNを用いた絶縁基板のサイズが23.2×23.4×1.12mm、SiCを用いた半導体素子のサイズが5×5×0.35mm、
接合材には千住金属製M731、ポリフェニレンサルファイド(PPS)を用いたケース、直径
が0.4mmのアルミを用いた配線を使用した。また、本試験では、モジュール内部にSiC半導体素子を1個のみ搭載し、ヒートサイクル試験およびコロナ開始電圧測定を行った。
Example 2
Next, examples in which the second sealing resin is made of various elastic modulus resins and the insulating properties are evaluated will be described. In the semiconductor device, the size of the base plate is 50 × 92 × 3 mm, the size of the insulating substrate using AlN is 23.2 × 23.4 × 1.12 mm, the size of the semiconductor element using SiC is 5 × 5 × 0.35 mm,
We used Senju Metal M731, a case using polyphenylene sulfide (PPS), and wiring using aluminum with a diameter of 0.4 mm. In this test, only one SiC semiconductor element was mounted inside the module, and a heat cycle test and a corona start voltage measurement were performed.

表2に、実施の形態2に示したプロセスにより作製した半導体装置、すなわち半導体素子基板外周に仮設壁を設け、第一の封止樹脂に弾性率が7.0GPaのサンユレック製EX-550を封止し、仮説壁を所定の溶剤により除去した後に、封止する第二の封止樹脂の弾性率を変化させたときのヒートサイクル試験および部分放電開始電圧(コロナ開始電圧)の結果を示す。   Table 2 shows a semiconductor device manufactured by the process shown in the second embodiment, that is, a temporary wall is provided on the outer periphery of the semiconductor element substrate, and the first sealing resin is sealed with EX-550 made by Sanyu Rec with an elastic modulus of 7.0 GPa Then, after removing the hypothetical wall with a predetermined solvent, the results of a heat cycle test and a partial discharge start voltage (corona start voltage) when the elastic modulus of the second sealing resin to be sealed is changed are shown.

例2−1について説明する。第二の封止樹脂として、東レダウコーニング製SE1886(弾性率30kPa)を用いて、半導体素子基板および第一の封止樹脂を封止し、半導体装置を作
製した場合、ヒートサイクル試験において、800サイクルまで半導体装置の特性が維持し
、コロナ開始電圧は6.0kV以上であることが判明した。
Example 2-1 will be described. When SE1886 (elastic modulus 30 kPa) manufactured by Toray Dow Corning is used as the second sealing resin, the semiconductor element substrate and the first sealing resin are sealed, and a semiconductor device is manufactured. It was found that the characteristics of the semiconductor device were maintained until the cycle, and the corona onset voltage was 6.0 kV or higher.

例2−2では、第二の封止樹脂として信越化学製KE1833(弾性率3.5MPa)を用いて、半導体装置を作製した結果、ヒートサイクル試験において1200サイクル以上半導体装置の特性を維持し、コロナ開始電圧は6.0kV以上であることが判明した。   In Example 2-2, as a result of manufacturing a semiconductor device using KE1833 (elastic modulus: 3.5 MPa) manufactured by Shin-Etsu Chemical as the second sealing resin, the characteristics of the semiconductor device were maintained for 1200 cycles or more in the heat cycle test. The starting voltage was found to be over 6.0 kV.

例2−3では、第二の封止樹脂として信越化学製KER-4000-UVにガラスフィラーを約50wt%添加し、弾性率を900MPaに調整し、半導体装置を作製した結果、ヒートサイクル試験では1200サイクル以上半導体装置の特性が維持し、コロナ開始電圧は6.0kVであることが判明した。   In Example 2-3, as a second sealing resin, about 50 wt% of glass filler was added to Shin-Etsu Chemical KER-4000-UV, the elastic modulus was adjusted to 900 MPa, and a semiconductor device was manufactured. It was found that the semiconductor device characteristics were maintained for 1200 cycles or more, and the corona onset voltage was 6.0 kV.

例2−4では、第二の封止樹脂として信越化学製SCR-1016(弾性率1.4GPa)を用いて、半導体装置を作製した結果、ヒートサイクル試験寿命は800サイクルに低下し、コロナ開始
電圧は4.5kVであることがわかった。
In Example 2-4, a semiconductor device was fabricated using SCR-1016 (elastic modulus 1.4 GPa) manufactured by Shin-Etsu Chemical as the second sealing resin. As a result, the heat cycle test life decreased to 800 cycles, and the corona start voltage Was found to be 4.5 kV.

例2−5では、第二の封止樹脂として信越化学製SCR-1016にガラスフィラーを約54wt%
添加し、弾性率を3GPaに調整し、半導体装置を作製した結果、ヒートサイクル試験寿命は200サイクルに低下し、コロナ開始電圧は2.5kVに低下することがわかった。
In Example 2-5, about 54 wt% of glass filler is added to Shin-Etsu Chemical SCR-1016 as the second sealing resin.
As a result of adding and adjusting the elastic modulus to 3 GPa to fabricate a semiconductor device, it was found that the heat cycle test life decreased to 200 cycles and the corona onset voltage decreased to 2.5 kV.

以上のヒートサイクル試験寿命およびコロナ開始電圧の試験結果を総合的に判断することにより、第二の封止樹脂の弾性率Nは、30kPa以上1GPa以下の範囲が適切であることが
わかった。

Figure 2013004766
By comprehensively judging the test results of the heat cycle test life and the corona start voltage described above, it was found that the elastic modulus N of the second sealing resin is suitably in the range of 30 kPa to 1 GPa.
Figure 2013004766

1:絶縁基板 2:表面電極パターン
3:裏面電極パターン 4:半導体素子基板
5、6:半導体素子 7、70:接合材
9:仮設壁 10:ベース板
11:ケース側板 12:第一の封止樹脂
13、130:配線 14:端子
21:上治具 22:下治具
23:樹脂注入穴 120:第二の封止樹脂
121:第一の封止樹脂の側面 131:ソケット
1: Insulating substrate 2: Surface electrode pattern
3: Back electrode pattern 4: Semiconductor element substrate 5, 6: Semiconductor element 7, 70: Bonding material 9: Temporary wall 10: Base plate 11: Case side plate 12: First sealing resin 13, 130: Wiring 14: Terminal 21: Upper jig 22: Lower jig 23: Resin injection hole 120: Second sealing resin 121: Side surface of the first sealing resin 131: Socket

Claims (11)

絶縁基板の片面に表面電極パターンが、および上記絶縁基板の他の面に裏面電極パターンが、それぞれ形成された半導体素子基板と、
上記表面電極パターンの、上記絶縁基板とは反対側の面に接合材を介して固着された半導体素子と、
この半導体素子および上記表面電極パターンを覆う第一の封止樹脂と、
上記絶縁基板の表面で、少なくとも上記表面電極パターンまたは上記裏面電極パターンが形成されていない部分と、上記第一の封止樹脂とを覆う第二の封止樹脂と、を備え、
上記第二の封止樹脂の弾性率は、上記第一の封止樹脂の弾性率よりも小さいことを特徴とする半導体装置。
A semiconductor element substrate having a surface electrode pattern formed on one side of the insulating substrate and a back electrode pattern formed on the other side of the insulating substrate;
A semiconductor element fixed to the surface of the surface electrode pattern opposite to the insulating substrate via a bonding material;
A first sealing resin covering the semiconductor element and the surface electrode pattern;
On the surface of the insulating substrate, at least a portion where the surface electrode pattern or the back electrode pattern is not formed, and a second sealing resin that covers the first sealing resin,
The semiconductor device according to claim 1, wherein the elastic modulus of the second sealing resin is smaller than the elastic modulus of the first sealing resin.
上記第一の封止樹脂の外形の側面形状が、上記絶縁基板に対して垂直な面での断面において直線となる形状であることを特徴とする請求項1に記載の半導体装置。   2. The semiconductor device according to claim 1, wherein a side shape of an outer shape of the first sealing resin is a shape that is a straight line in a cross section in a plane perpendicular to the insulating substrate. 上記第二の封止樹脂の弾性率が30kPaから1GPaの範囲であることを特徴とする請求項1または2に記載の半導体装置。   The semiconductor device according to claim 1, wherein the second sealing resin has an elastic modulus in a range of 30 kPa to 1 GPa. 第一の封止樹脂の弾性率が1GPaから20GPaの範囲であることを特徴とする請求項1〜3のいずれか1項に記載の半導体装置。   4. The semiconductor device according to claim 1, wherein the elastic modulus of the first sealing resin is in a range of 1 GPa to 20 GPa. 半導体素子がワイドバンドギャップ半導体により形成されていることを特徴とする請求項1〜4のいずれか1項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the semiconductor element is formed of a wide band gap semiconductor. ワイドバンドギャップ半導体は、炭化珪素、窒化ガリウム系材料、ダイアモンドのうちいずれかの材料の半導体であることを特徴とする請求項5に記載の半導体装置。   6. The semiconductor device according to claim 5, wherein the wide band gap semiconductor is a semiconductor made of any one of silicon carbide, gallium nitride-based material, and diamond. 請求項2に記載の半導体装置の製造方法であって、
少なくとも、上記絶縁基板の表面電極パターンおよび裏面電極パターンが形成されていない面を、上記絶縁基板の周辺部分においては上記半導体素子の厚みよりも高さが高い仮設壁を形成するようマスキング樹脂で覆うマスキング樹脂被覆工程と、
上記表面電極パターンの、上記絶縁基板とは反対側の面に接合材を介して上記半導体素子を固着する半導体素子固着工程と、
上記仮設壁の内部を第一の封止樹脂で満たした後、上記第一の封止樹脂を硬化させる第一の封止樹脂形成工程と、
上記マスキング樹脂を除去するマスキング樹脂除去工程と、
少なくとも上記第一の封止樹脂と、上記マスキング樹脂を除去して上記絶縁基板の表面が露出した部分を第二の封止樹脂で覆う第二の封止樹脂形成工程と、
を備えたことを特徴とする半導体装置の製造方法。
A method of manufacturing a semiconductor device according to claim 2,
At least the surface of the insulating substrate on which the front electrode pattern and the back electrode pattern are not formed is covered with a masking resin so as to form a temporary wall having a height higher than the thickness of the semiconductor element in the peripheral portion of the insulating substrate. Masking resin coating process;
A semiconductor element fixing step of fixing the semiconductor element to a surface of the surface electrode pattern opposite to the insulating substrate via a bonding material;
A first sealing resin forming step of curing the first sealing resin after filling the inside of the temporary wall with the first sealing resin;
A masking resin removal step of removing the masking resin;
A second sealing resin forming step of covering at least the first sealing resin and the portion where the surface of the insulating substrate is exposed by removing the masking resin with a second sealing resin;
A method for manufacturing a semiconductor device, comprising:
上記第一の封止樹脂形成工程において、上記第一の封止樹脂を硬化させる温度は上記マスキング樹脂の耐熱温度以下の温度であることを特徴とする請求項7に記載の半導体装置の製造方法。   8. The method of manufacturing a semiconductor device according to claim 7, wherein, in the first sealing resin forming step, the temperature for curing the first sealing resin is a temperature equal to or lower than a heat resistant temperature of the masking resin. . 上記マスキング樹脂被覆工程は、
半導体素子基板を、樹脂注入穴を有する上治具と下治具で挟む工程と、
上記上治具と上記下治具とで上記半導体素子基板を挟んだ状態で減圧環境に設置する工程と、
この減圧環境で上記樹脂注入穴から未硬化のマスキング樹脂を注入する工程と、
上記未硬化のマスキング樹脂を注入した後大気圧環境下に取り出し、注入した上記未硬化
のマスキング樹脂を硬化させた後、上記上治具と上記下治具を取り外して脱型する工程と、
を備えることを特徴とする請求項7に記載の半導体装置の製造方法。
The masking resin coating step
Sandwiching the semiconductor element substrate with an upper jig and a lower jig having resin injection holes;
Installing in a reduced pressure environment with the semiconductor element substrate sandwiched between the upper jig and the lower jig;
Injecting uncured masking resin from the resin injection hole in this reduced pressure environment;
After injecting the uncured masking resin, taking it out in an atmospheric pressure environment, curing the injected uncured masking resin, removing the upper jig and the lower jig, and demolding;
The method of manufacturing a semiconductor device according to claim 7, comprising:
上記マスキング樹脂の材料はシリコーン樹脂であることを特徴とする請求項7に記載の半導体装置の製造方法。   8. The method of manufacturing a semiconductor device according to claim 7, wherein the material of the masking resin is a silicone resin. 上記マスキング樹脂の材料は熱可塑性樹脂であることを特徴とする請求項7に記載の半導体装置の製造方法。   8. The method of manufacturing a semiconductor device according to claim 7, wherein the material of the masking resin is a thermoplastic resin.
JP2011134952A 2011-06-17 2011-06-17 Semiconductor device and manufacturing method of semiconductor device Expired - Fee Related JP5812712B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2011134952A JP5812712B2 (en) 2011-06-17 2011-06-17 Semiconductor device and manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011134952A JP5812712B2 (en) 2011-06-17 2011-06-17 Semiconductor device and manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JP2013004766A true JP2013004766A (en) 2013-01-07
JP5812712B2 JP5812712B2 (en) 2015-11-17

Family

ID=47673003

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011134952A Expired - Fee Related JP5812712B2 (en) 2011-06-17 2011-06-17 Semiconductor device and manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JP5812712B2 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2013111276A1 (en) * 2012-01-25 2015-05-11 三菱電機株式会社 Power semiconductor device
JP2015095655A (en) * 2013-11-14 2015-05-18 三星電子株式会社Samsung Electronics Co.,Ltd. Semiconductor package and manufacturing method of the same
EP3276660A1 (en) * 2016-07-27 2018-01-31 Infineon Technologies AG Double-encapsulated power semiconductor module and method for producing the same
US10308034B2 (en) 2016-04-15 2019-06-04 Rohm Co., Ltd. Liquid container, liquid remaining amount detection circuit of liquid container, liquid remaining amount detection method, liquid container identification method, ink mounting unit, printer, and print system
EP4270453A1 (en) * 2022-04-28 2023-11-01 Infineon Technologies AG Method for fabricating a power semiconductor module comprising an encapsulation material with a high thermostability and power semiconductor module
EP4270454A3 (en) * 2022-04-28 2023-11-22 Infineon Technologies AG Power semiconductor module comprising a first and a second compartment and method for fabricating the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006351737A (en) * 2005-06-15 2006-12-28 Hitachi Ltd Semiconductor power module
JP2008258292A (en) * 2007-04-03 2008-10-23 Sumitomo Electric Ind Ltd Semiconductor device
JP2009200088A (en) * 2008-02-19 2009-09-03 Fuji Electric Device Technology Co Ltd Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006351737A (en) * 2005-06-15 2006-12-28 Hitachi Ltd Semiconductor power module
JP2008258292A (en) * 2007-04-03 2008-10-23 Sumitomo Electric Ind Ltd Semiconductor device
JP2009200088A (en) * 2008-02-19 2009-09-03 Fuji Electric Device Technology Co Ltd Semiconductor device

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2013111276A1 (en) * 2012-01-25 2015-05-11 三菱電機株式会社 Power semiconductor device
JP2015095655A (en) * 2013-11-14 2015-05-18 三星電子株式会社Samsung Electronics Co.,Ltd. Semiconductor package and manufacturing method of the same
US10308034B2 (en) 2016-04-15 2019-06-04 Rohm Co., Ltd. Liquid container, liquid remaining amount detection circuit of liquid container, liquid remaining amount detection method, liquid container identification method, ink mounting unit, printer, and print system
EP3276660A1 (en) * 2016-07-27 2018-01-31 Infineon Technologies AG Double-encapsulated power semiconductor module and method for producing the same
CN107665867A (en) * 2016-07-27 2018-02-06 英飞凌科技股份有限公司 The power semiconductor modular and its manufacture method of double-contracting envelope
US10134654B2 (en) 2016-07-27 2018-11-20 Infineon Technologies Ag Double-encapsulated power semiconductor module and method for producing the same
CN107665867B (en) * 2016-07-27 2021-01-26 英飞凌科技股份有限公司 Double-encapsulated power semiconductor module and method for producing same
EP4270453A1 (en) * 2022-04-28 2023-11-01 Infineon Technologies AG Method for fabricating a power semiconductor module comprising an encapsulation material with a high thermostability and power semiconductor module
EP4270454A3 (en) * 2022-04-28 2023-11-22 Infineon Technologies AG Power semiconductor module comprising a first and a second compartment and method for fabricating the same

Also Published As

Publication number Publication date
JP5812712B2 (en) 2015-11-17

Similar Documents

Publication Publication Date Title
JP5638623B2 (en) Semiconductor device and manufacturing method of semiconductor device
JP5847165B2 (en) Semiconductor device
JP5570476B2 (en) Semiconductor device and manufacturing method of semiconductor device
JP5832557B2 (en) Power semiconductor device
JP5812712B2 (en) Semiconductor device and manufacturing method of semiconductor device
JP6045749B2 (en) Semiconductor device
JP6676079B2 (en) Semiconductor device and manufacturing method thereof
TWI502695B (en) Semiconductor device and method for manufacturing the same
JP6336138B2 (en) Semiconductor device
JP2011228336A (en) Semiconductor device and method for manufacturing the same
JP5072948B2 (en) Semiconductor device
JP5328740B2 (en) Semiconductor device and manufacturing method of semiconductor device
JP2015130457A (en) Semiconductor device
JP3972821B2 (en) Power semiconductor device
CN114078790A (en) Power semiconductor module device and method for manufacturing the same
JP5258825B2 (en) Power semiconductor device and manufacturing method thereof
JP2007027261A (en) Power module
US20210166986A1 (en) Package with encapsulant under compressive stress
JP5297419B2 (en) Semiconductor device and manufacturing method of semiconductor device
JP2013038259A (en) Semiconductor device
JP5928324B2 (en) Power semiconductor device
US20230317554A1 (en) Embedded heat slug in a substrate
WO2023073831A1 (en) Semiconductor device and method for manufacturing semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20130927

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20140411

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20140422

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140613

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20150127

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20150313

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20150818

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20150915

R151 Written notification of patent or utility model registration

Ref document number: 5812712

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R151

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees