JP2012523055A5 - - Google Patents
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- JP2012523055A5 JP2012523055A5 JP2012504076A JP2012504076A JP2012523055A5 JP 2012523055 A5 JP2012523055 A5 JP 2012523055A5 JP 2012504076 A JP2012504076 A JP 2012504076A JP 2012504076 A JP2012504076 A JP 2012504076A JP 2012523055 A5 JP2012523055 A5 JP 2012523055A5
- Authority
- JP
- Japan
- Prior art keywords
- memory
- thread
- request
- address
- write
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000004888 barrier function Effects 0.000 claims 14
- 238000001514 detection method Methods 0.000 claims 10
- 238000000034 method Methods 0.000 claims 4
- 230000006978 adaptation Effects 0.000 claims 1
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB0906066A GB2469299B (en) | 2009-04-07 | 2009-04-07 | Ensuring consistency between a data cache and a main memory |
| GB0906066.6 | 2009-04-07 | ||
| PCT/GB2010/000727 WO2010116151A1 (en) | 2009-04-07 | 2010-04-07 | Ensuring consistency between a data cache and a main memory |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2012523055A JP2012523055A (ja) | 2012-09-27 |
| JP2012523055A5 true JP2012523055A5 (cg-RX-API-DMAC7.html) | 2013-05-23 |
| JP5619869B2 JP5619869B2 (ja) | 2014-11-05 |
Family
ID=40750290
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2012504076A Active JP5619869B2 (ja) | 2009-04-07 | 2010-04-07 | データキャッシュとメインメモリ間の一貫性の保証 |
Country Status (6)
| Country | Link |
|---|---|
| US (3) | US8234455B2 (cg-RX-API-DMAC7.html) |
| EP (1) | EP2417526B1 (cg-RX-API-DMAC7.html) |
| JP (1) | JP5619869B2 (cg-RX-API-DMAC7.html) |
| CN (1) | CN102388372B (cg-RX-API-DMAC7.html) |
| GB (1) | GB2469299B (cg-RX-API-DMAC7.html) |
| WO (1) | WO2010116151A1 (cg-RX-API-DMAC7.html) |
Families Citing this family (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120290780A1 (en) * | 2011-01-27 | 2012-11-15 | Mips Technologies Inc. | Multithreaded Operation of A Microprocessor Cache |
| US8812621B2 (en) * | 2011-05-03 | 2014-08-19 | Cisco Technology, Inc. | Reducing fetching load on cache servers in adaptive streaming |
| US9195596B2 (en) * | 2011-11-02 | 2015-11-24 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Mapping of valid and dirty flags in a caching system |
| CN103543954B (zh) * | 2012-07-16 | 2018-03-23 | 深圳市中兴微电子技术有限公司 | 一种数据存储管理方法和装置 |
| US9483325B2 (en) | 2012-09-28 | 2016-11-01 | Hewlett Packard Enterprise Development Lp | Synchronizing timestamp counters |
| CN105453055B (zh) * | 2012-10-25 | 2018-09-21 | 英派尔科技开发有限公司 | 晶片、维持多核处理器一致性和处理特定块请求的方法 |
| US9146678B2 (en) * | 2013-04-29 | 2015-09-29 | International Business Machines Corporation | High throughput hardware acceleration using pre-staging buffers |
| US9563561B2 (en) * | 2013-06-25 | 2017-02-07 | Intel Corporation | Initiation of cache flushes and invalidations on graphics processors |
| KR101968501B1 (ko) * | 2014-05-29 | 2019-04-15 | 삼성에스디에스 주식회사 | 데이터 처리 장치 및 데이터 처리 장치의 메모리에 기록된 데이터의 확인 방법 |
| GB2542214B (en) * | 2015-11-11 | 2019-08-28 | Imagination Tech Ltd | Hardware monitor to verify memory units |
| CN105357305B (zh) * | 2015-11-13 | 2018-11-20 | 北京金山安全软件有限公司 | 文件发送方法和装置、文件接收方法和装置和终端设备 |
| KR102381862B1 (ko) | 2015-12-10 | 2022-04-01 | 삼성전자주식회사 | 데이터 통신 장치 |
| US10585623B2 (en) * | 2015-12-11 | 2020-03-10 | Vivante Corporation | Software defined FIFO buffer for multithreaded access |
| US10572399B2 (en) * | 2016-07-13 | 2020-02-25 | Qualcomm Incorporated | Memory request arbitration |
| US11379242B2 (en) | 2017-06-29 | 2022-07-05 | Intel Corporation | Methods and apparatus for using load and store addresses to resolve memory dependencies |
| US10936496B2 (en) | 2019-06-07 | 2021-03-02 | Micron Technology, Inc. | Managing collisions in a non-volatile memory system with a coherency checker |
| US11023172B2 (en) | 2019-07-26 | 2021-06-01 | Micron Technology, Inc. | Selecting read voltage using write transaction data |
| US11656796B2 (en) | 2021-03-31 | 2023-05-23 | Advanced Micro Devices, Inc. | Adaptive memory consistency in disaggregated datacenters |
| CN114035980B (zh) * | 2021-11-08 | 2023-11-14 | 海飞科(南京)信息技术有限公司 | 基于便笺存储器来共享数据的方法和电子装置 |
| CN114116531B (zh) * | 2022-01-28 | 2022-04-22 | 苏州浪潮智能科技有限公司 | 一种缓存一致性写回的方法、装置、设备及介质 |
| US12536056B2 (en) * | 2022-03-10 | 2026-01-27 | Nvidia Corporation | Hardware accelerated synchronization with asynchronous transaction support |
| CN118885412B (zh) * | 2024-10-08 | 2025-04-11 | 上海赛昉半导体科技有限公司 | 用于risc-v处理器二级缓存的cmo指令执行电路 |
Family Cites Families (50)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55147744A (en) * | 1979-05-07 | 1980-11-17 | Hitachi Ltd | Memory controlling unit |
| JP3644959B2 (ja) * | 1992-09-29 | 2005-05-11 | セイコーエプソン株式会社 | マイクロプロセッサシステム |
| US5465336A (en) * | 1994-06-30 | 1995-11-07 | International Business Machines Corporation | Fetch and store buffer that enables out-of-order execution of memory instructions in a data processing system |
| US5551023A (en) * | 1994-08-05 | 1996-08-27 | Panasonic Technologies, Inc. | System of database concurrency control based on transaction types and prior access to a data set |
| US5671407A (en) * | 1994-12-07 | 1997-09-23 | Xerox Corporation | Application-specific conflict detection for weakly consistent replicated databases |
| US5784586A (en) * | 1995-02-14 | 1998-07-21 | Fujitsu Limited | Addressing method for executing load instructions out of order with respect to store instructions |
| US5666494A (en) * | 1995-03-31 | 1997-09-09 | Samsung Electronics Co., Ltd. | Queue management mechanism which allows entries to be processed in any order |
| US5809275A (en) * | 1996-03-01 | 1998-09-15 | Hewlett-Packard Company | Store-to-load hazard resolution system and method for a processor that executes instructions out of order |
| US5930822A (en) * | 1996-09-27 | 1999-07-27 | Hewlett-Packard Co. | Method and system for maintaining strong ordering in a coherent memory system |
| JP3139392B2 (ja) | 1996-10-11 | 2001-02-26 | 日本電気株式会社 | 並列処理システム |
| US5802571A (en) * | 1996-10-21 | 1998-09-01 | International Business Machines Corporation | Apparatus and method for enforcing data coherency in an information handling system having multiple hierarchical levels of cache memory |
| US5918005A (en) * | 1997-03-25 | 1999-06-29 | International Business Machines Corporation | Apparatus region-based detection of interference among reordered memory operations in a processor |
| US6324623B1 (en) | 1997-05-30 | 2001-11-27 | Oracle Corporation | Computing system for implementing a shared cache |
| US6772324B2 (en) * | 1997-12-17 | 2004-08-03 | Intel Corporation | Processor having multiple program counters and trace buffers outside an execution pipeline |
| US6237067B1 (en) * | 1998-08-31 | 2001-05-22 | International Business Machines Corporation | System and method for handling storage consistency conflict |
| US6256713B1 (en) * | 1999-04-29 | 2001-07-03 | International Business Machines Corporation | Bus optimization with read/write coherence including ordering responsive to collisions |
| EP1050807A1 (en) * | 1999-05-03 | 2000-11-08 | Sgs Thomson Microelectronics Sa | Memory access in a computer memory |
| US6640292B1 (en) * | 1999-09-10 | 2003-10-28 | Rambus Inc. | System and method for controlling retire buffer operation in a memory system |
| US6327645B1 (en) * | 1999-11-08 | 2001-12-04 | Silicon Integrated Systems Corp. | Cache memory system with memory request address queue, cache write address queue, and cache read address queue |
| US6360298B1 (en) * | 2000-02-10 | 2002-03-19 | Kabushiki Kaisha Toshiba | Load/store instruction control circuit of microprocessor and load/store instruction control method |
| US6490635B1 (en) * | 2000-04-28 | 2002-12-03 | Western Digital Technologies, Inc. | Conflict detection for queued command handling in disk drive controller |
| US6915395B1 (en) * | 2000-05-03 | 2005-07-05 | Sun Microsystems, Inc. | Active address content addressable memory |
| JP3729064B2 (ja) * | 2000-11-29 | 2005-12-21 | 日本電気株式会社 | データ依存関係検出装置 |
| US6502170B2 (en) | 2000-12-15 | 2002-12-31 | Intel Corporation | Memory-to-memory compare/exchange instructions to support non-blocking synchronization schemes |
| JP2003029967A (ja) * | 2001-07-17 | 2003-01-31 | Fujitsu Ltd | マイクロプロセッサ |
| AU2002217653A1 (en) | 2001-12-12 | 2003-07-09 | Telefonaktiebolaget Lm Ericsson (Publ) | Collision handling apparatus and method |
| US7127561B2 (en) | 2001-12-31 | 2006-10-24 | Intel Corporation | Coherency techniques for suspending execution of a thread until a specified memory access occurs |
| US6912623B2 (en) * | 2002-06-04 | 2005-06-28 | Sandbridge Technologies, Inc. | Method and apparatus for multithreaded cache with simplified implementation of cache replacement policy |
| US20040044881A1 (en) * | 2002-08-28 | 2004-03-04 | Sun Microsystems, Inc. | Method and system for early speculative store-load bypass |
| US20040153611A1 (en) * | 2003-02-04 | 2004-08-05 | Sujat Jamil | Methods and apparatus for detecting an address conflict |
| US7743223B2 (en) * | 2003-08-18 | 2010-06-22 | Cray Inc. | Decoupling of write address from its associated write data in a store to a shared memory in a multiprocessor system |
| US7073031B1 (en) * | 2003-12-18 | 2006-07-04 | Emc Corporation | Multi-processor system having data coherency |
| US7343477B1 (en) * | 2003-12-29 | 2008-03-11 | Sun Microsystems, Inc. | Efficient read after write bypass |
| US7243200B2 (en) * | 2004-07-15 | 2007-07-10 | International Business Machines Corporation | Establishing command order in an out of order DMA command queue |
| US7725618B2 (en) * | 2004-07-29 | 2010-05-25 | International Business Machines Corporation | Memory barriers primitives in an asymmetric heterogeneous multiprocessor environment |
| US20060047934A1 (en) * | 2004-08-31 | 2006-03-02 | Schmisseur Mark A | Integrated circuit capable of memory access control |
| US8402224B2 (en) | 2005-09-20 | 2013-03-19 | Vmware, Inc. | Thread-shared software code caches |
| US7861060B1 (en) * | 2005-12-15 | 2010-12-28 | Nvidia Corporation | Parallel data processing systems and methods using cooperative thread arrays and thread identifier values to determine processing behavior |
| US20070186056A1 (en) * | 2006-02-07 | 2007-08-09 | Bratin Saha | Hardware acceleration for a software transactional memory system |
| US20080189501A1 (en) * | 2007-02-05 | 2008-08-07 | Irish John D | Methods and Apparatus for Issuing Commands on a Bus |
| GB2447907B (en) * | 2007-03-26 | 2009-02-18 | Imagination Tech Ltd | Processing long-latency instructions in a pipelined processor |
| US8060881B2 (en) * | 2007-05-15 | 2011-11-15 | Microsoft Corporation | Small barrier with local spinning |
| US7849354B2 (en) * | 2007-06-12 | 2010-12-07 | Microsoft Corporation | Gracefully degradable versioned storage systems |
| CN101689143B (zh) * | 2007-06-20 | 2012-07-04 | 富士通株式会社 | 高速缓存控制装置以及控制方法 |
| US9207997B2 (en) * | 2007-08-09 | 2015-12-08 | Novell, Inc. | Multithreaded lock management |
| US20090089510A1 (en) * | 2007-09-28 | 2009-04-02 | Mips Technologies, Inc. | Speculative read in a cache coherent microprocessor |
| US7899997B2 (en) * | 2008-03-12 | 2011-03-01 | International Business Machines Corporation | Systems and methods for implementing key-based transactional memory conflict detection |
| US20100058034A1 (en) * | 2008-08-29 | 2010-03-04 | International Business Machines Corporation | Creating register dependencies to model hazardous memory dependencies |
| US7941584B2 (en) * | 2009-03-26 | 2011-05-10 | Arm Limited | Data processing apparatus and method for performing hazard detection |
| US8099566B2 (en) * | 2009-05-15 | 2012-01-17 | Oracle America, Inc. | Load/store ordering in a threaded out-of-order processor |
-
2009
- 2009-04-07 GB GB0906066A patent/GB2469299B/en not_active Expired - Fee Related
- 2009-09-25 US US12/586,649 patent/US8234455B2/en active Active
-
2010
- 2010-04-07 EP EP10723271.2A patent/EP2417526B1/en active Active
- 2010-04-07 CN CN201080016118.3A patent/CN102388372B/zh active Active
- 2010-04-07 WO PCT/GB2010/000727 patent/WO2010116151A1/en not_active Ceased
- 2010-04-07 JP JP2012504076A patent/JP5619869B2/ja active Active
-
2012
- 2012-07-23 US US13/555,894 patent/US9075724B2/en active Active
-
2015
- 2015-07-06 US US14/791,699 patent/US9703709B2/en active Active
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