JP2012257172A - Imaging apparatus and imaging element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an imaging apparatus for obtaining an imaging signal of sufficient image quality upon photographing in a state where photographing sensitivity is set to be low by using an imaging element for amplifying the imaging signal by amplifier circuits which are cascade-connected in two stages.SOLUTION: The imaging element includes: a first amplifier circuit for amplifying and outputting a signal inputted from a vertical output line (column output line) for outputting the imaging signals from a plurality of pixels including a photoelectric conversion element at every column; and a second amplifier circuit for amplifying and outputting an output signal of the first amplifier circuit. The element also includes a changeover switch for selecting and outputting the output signal of the first amplifier circuit or the output signal of the second amplifier circuit. A first reading mode for reading the imaging signal without passing through the second amplifier circuit and a second reading mode for reading the imaging signal via the second amplifier circuit can be switched. During photographing in a state where the photographing sensitivity is set to be low, the imaging signal is read at the first reading mode.

Description

  The present invention relates to an imaging element having a plurality of amplifier circuits connected in cascade, and an imaging apparatus.

  In recent years, with the increase in sensitivity of digital cameras, imaging signals are amplified before performing digital signal processing related to various image processing and the like. Furthermore, with the increase in the number of pixels of the image sensor, it is also required to increase the reading speed of the image signal from the image sensor. For example, in Patent Document 1 below, an analog front end composed of a correlated double sampling circuit configured by cascading two stages of amplification circuits, a variable amplifier, and an AD converter for amplifying the output signal of the image sensor. A circuit is used.

JP 2006-157335 A

  However, in the technique disclosed in Patent Document 1, since the imaging signal from the imaging device passes through the amplification circuit connected in two stages, the imaging sensitivity is set low due to thermal noise generated by driving the amplification circuit. There is a concern about the deterioration of the S / N ratio at the time of shooting at (low ISO sensitivity).

  An object of the present invention is to provide an imaging device that uses an imaging device that amplifies an imaging signal by an amplification circuit connected in two stages, and that can obtain an imaging signal with good image quality when shooting with a low shooting sensitivity. Is to provide.

  An imaging apparatus according to the present invention includes a plurality of pixels including a photoelectric conversion element that generates a charge according to incident light by photoelectric conversion, a column output line that outputs an imaging signal from the plurality of pixels for each column, A first amplifier circuit that amplifies and outputs a signal input via a column output line; a second amplifier circuit that amplifies and outputs an output signal of the first amplifier circuit; and An image pickup device comprising: an output control unit that selects and outputs an output signal or an output signal of the second amplifier circuit; and controls the output control unit from the pixel without passing through the second amplifier circuit. Control means for switching between a first readout mode for reading out the imaging signal and a second readout mode for controlling the output control means to read out the imaging signal from the pixel via the second amplifier circuit; It is characterized by having.

  According to the present invention, it is possible to switch between reading out an image pickup signal from a pixel only through the first amplifier circuit or reading out through the first amplifier circuit and the second amplifier circuit. Therefore, at the time of shooting in a state where the shooting sensitivity is set low, the imaging signal is read without going through the second amplifier circuit, thereby suppressing the deterioration of the S / N ratio and obtaining an imaging signal with good image quality. Can do.

It is a figure which shows the structural example of the imaging device by the 1st Embodiment of this invention. It is a figure which shows the structural example of the image pick-up element in 1st Embodiment. It is a figure which shows the structural example of the pixel in 1st Embodiment. It is a figure which shows the structural example of the column circuit in 1st Embodiment. 4 is a timing chart illustrating an example of drive timing of the image sensor according to the first embodiment. 6 is a timing chart illustrating an example of drive timing of an image sensor according to the second embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
A first embodiment of the present invention will be described.
FIG. 1 is a block diagram illustrating a configuration example of an imaging apparatus 100 according to the first embodiment.

  In FIG. 1, the imaging lens 101 forms an optical image of a subject on the imaging surface of the imaging element 102. The imaging element 102 converts the optical image formed on the imaging surface into an imaging signal by photoelectric conversion, reads out the converted imaging signal from the pixel array, and outputs it. The imaging element 102 has a plurality of pixels including a photoelectric conversion element, and these are arranged two-dimensionally (in the row direction and the column direction). The image sensor 102 is, for example, a CMOS image sensor.

  An analog front end (AFE) 103 is controlled by a CPU (Central Processing Unit) 108. The AFE 103 receives and amplifies the analog imaging signal output from the imaging element 102, and generates a digital imaging signal by performing A / D conversion processing. A digital signal processor (DSP) 104 is controlled by the CPU 108, receives a digital imaging signal output from the AFE 103, and performs various image processing, compression processing, and the like. The recording image data generated by the DSP 104 is recorded on a recording medium 109 that is detachably connected to the imaging apparatus 100, for example. The recording medium 109 is, for example, a semiconductor memory.

  The image memory 105 temporarily stores the digital image data generated by the DSP 104 and supplies the digital image data to the display unit 106. The display unit 106 displays a menu screen that allows the user to perform various settings such as aperture and ISO sensitivity (photographing sensitivity), and displays digital image data supplied to the image memory 105 (live view). A timing generator (TG) 107 is controlled by the CPU 108. The TG 107 generates a predetermined drive signal and supplies the generated drive signal to the image sensor 102.

  The CPU 108 controls the image sensor 102, AFE 103, DSP 104, and TG 107. The CPU 108 controls, for example, the amplification factor of the imaging signal in the imaging element 102 according to the set ISO sensitivity (imaging sensitivity).

  Next, the configuration of the image sensor 102 will be described with reference to FIGS. FIG. 2 is a diagram illustrating a configuration example of the image sensor 102. FIG. 3 is a diagram illustrating a configuration example of the pixel 201 included in the image sensor 102.

  As shown in FIG. 2, in the image sensor 102, a plurality of pixels 201 including photoelectric conversion elements are arranged in the row direction and the column direction. In FIG. 2, for convenience of explanation, among the image sensors in which a plurality of pixels are arranged in the row direction and the column direction, pixels for 4 rows × 4 columns and signal lines for reading signals from these pixels And a readout circuit.

  Each pixel 201 includes a photodiode 301, a transfer gate 302, a storage capacitor 303, a reset switch 304, a source follower 305, and a row selection switch 306 as shown in FIG. 3. The photodiode 301 is a photoelectric conversion element, and generates and accumulates signal charges corresponding to incident light by photoelectric conversion. The transfer gate 302 controls the transfer of the signal charge accumulated in the photodiode 301 to the storage capacitor 303. The transfer gate 302 is controlled to be conductive / non-conductive (ON / OFF) by a signal φTX.

  The reset switch 304 controls resetting of unnecessary signal charges accumulated in the photodiode 301 and the storage capacitor 303. The reset switch 304 is controlled to be conductive / non-conductive (ON / OFF) by a signal φRES. The source follower 305 amplifies the signal charge stored in the storage capacitor 303 and converts it into a signal voltage. Here, the storage capacitor 303, the reset switch 304, and the source follower 305 constitute a floating diffusion amplifier. The row selection switch 306 controls the connection between the output of the source follower 305 and the vertical output line (column output line) 203. The row selection switch 306 is controlled to be conductive / non-conductive (ON / OFF) by a signal φSEL.

  The vertical scanning circuit 202 outputs a signal φTX (i) to each pixel 201 in the i-th row (i is an integer, i = n, (n + 1), (n + 2), (n + 3) in the example shown in FIG. 2). ), ΦRES (i) and φSEL (i) are supplied to control readout of signal charges from the pixel 201. A vertical output line (column output line) 203 is a signal line for outputting an imaging signal (signal charge) from the pixel 201 for each column, and is connected to a column circuit 205 prepared for each column. The load current source 204 drives the source follower 305 in the selected row via the vertical output line 203 when the row selection switch 306 is turned on (conductive state).

  The column circuit 205 is connected in common to a plurality of pixels 201 in the corresponding column via a vertical output line (column output line) 203, and amplifies and stores an imaging signal from the pixel 201. Column selection switches 206 and 207 control connection between the output terminal of the column circuit 205 and the horizontal output lines 208 and 209. The horizontal scanning circuit 213 supplies a signal φH to the column selection switches 206 and 207 and controls output of output signals from the column circuit 205 to the horizontal output lines 208 and 209.

  The differential amplifier 212 amplifies and outputs the difference signal between the horizontal output line 208 and the horizontal output line 209 with a predetermined amplification rate according to the input dynamic range of the AFE 103 in the subsequent stage. The reset switches 210 and 211 are controlled to be conductive / non-conductive (ON / OFF) by the signal φCHR, and reset the horizontal output lines 208 and 209 with the voltage VCHR.

  FIG. 4 is a diagram illustrating a configuration example of the column circuit 205. In the present embodiment, the column circuit 205 amplifies the imaging signal from the pixel 201 by using two stages of cascade-connected amplifier circuits (first amplifier circuit 401 and second amplifier circuit 402). A vertical output line (column output line) 203 that outputs an imaging signal from the pixel 201 for each column is connected to an input terminal of the first amplifier circuit 401. Further, the output terminal of the first amplifier circuit 401 and the input terminal of the second amplifier circuit 402 are connected. The first amplifier circuit 401 amplifies and outputs an output signal (imaging signal from the pixel 201) of the vertical output line (column output line) 203, and the second amplifier circuit 402 includes the first amplifier circuit 401. The output signal is amplified and output.

  In the first amplifier circuit 401, the vertical output line 203 is connected to the clamp capacitor 403, and the clamp capacitor 403 is connected to the inverting input terminal of the inverting amplifier 404. Further, the inverting input terminal of the inverting amplifier 404 is connected to the feedback capacitance group 406 via the feedback capacitance changeover switch group 405. The output terminal of the inverting amplifier 404 is connected to a feedback capacitor group 406 whose connection is controlled by a feedback capacitor changeover switch group 405. The feedback capacitance changeover switch group 405 includes switches corresponding to the capacitances of the feedback capacitance group 406. A plurality of series circuits in which the capacitance of the feedback capacitance group 406 and the corresponding switch of the feedback capacitance switching switch group 405 are connected in series are connected in parallel between the inverting input terminal and the output terminal of the inverting amplifier 404.

  Each switch of the feedback capacitance changeover switch group 405 is controlled to be conductive / non-conductive (ON / OFF) by signals φCf1_1 to φCf1_6 output from the CPU. That is, the feedback capacitance connected between the inverting input terminal and the output terminal of the inverting amplifier 404 is controlled by the signals φCf1_1 to φCf1_6 output from the CPU. The amplification factor in the first amplifier circuit 401 depends on the ratio between the capacitance value of the clamp capacitor 403 and the capacitance value of the feedback capacitor connected between the inverting input terminal and the output terminal of the inverting amplifier 404 in the feedback capacitor group 406. It is determined. The amplification factor in the first amplifier circuit 401 can be switched by signals φCf1_1 to φCf1_6 output from the CPU.

  Also, a clamp switch 407 whose conduction / non-conduction (on / off) is controlled by a signal φCLAMP is connected between the inverting input terminal and the output terminal of the inverting amplifier 404. The reference power supply VREF is input to the non-inverting input terminal of the inverting amplifier 404.

  In the second amplifier circuit 402, the output signal of the first amplifier circuit 401 is input to a non-inverting input terminal of an inverting amplifier 408 that is driven and controlled by a signal φPAMPENB output from the CPU. Further, the inverting input terminal of the inverting amplifier 408 is connected to the feedback capacitance group 410 via the feedback capacitance changeover switch group 409. The output terminal of the inverting amplifier 408 is connected to a feedback capacitance group 410 that is connection-controlled by a feedback capacitance changeover switch group 409. The feedback capacitance switching switch group 409 includes switches corresponding to the respective capacitances of the feedback capacitance group 410. A plurality of series circuits in which the capacitance of the feedback capacitance group 410 and the corresponding switch of the feedback capacitance switching switch group 409 are connected in series are connected in parallel between the inverting input terminal and the output terminal of the inverting amplifier 408.

  Each switch of the feedback capacitance changeover switch group 409 is controlled to be conductive / non-conductive (ON / OFF) by signals φCf2_1 to φCf2_2 output from the CPU. That is, the feedback capacitance connected between the inverting input terminal and the output terminal of the inverting amplifier 408 is controlled by the signals φCf2_1 to φCf2_2 output from the CPU 108. The amplification factor in the second amplifier circuit 402 depends on the ratio between the capacitance value of the sampling capacitor 412 and the capacitance value of the feedback capacitor connected between the inverting input terminal and the output terminal of the inverting amplifier 408 in the feedback capacitor group 410. It is determined. The amplification factor in the second amplifier circuit 402 can be switched by signals φCf2_1 to φCf2_2 output from the CPU.

  The sampling capacitor 412 is connected to the inverting input terminal of the inverting amplifier 408 via a sampling capacitor connection changeover switch 411 whose conduction / non-conduction (on / off) is controlled by a signal φCs output from the CPU 108. Further, a changeover switch 414 whose conduction / non-conduction (ON / OFF) is controlled by a signal φUNITY is connected between the inverting input terminal and the output terminal of the inverting amplifier 408. By turning on the changeover switch 414 and turning off the sampling capacitor connection changeover switch 411, it is also possible to output the output signal of the first amplification circuit 401 to the subsequent stage using the second amplification circuit 402 as a voltage follower. .

  Here, the output signal of the second amplifier circuit 402 is output to the subsequent stage by turning on the changeover switch 415 connected to the output terminal (conductive state). Further, when the changeover switch 413 connected to the output terminal of the first amplifier circuit 401 is turned on (conductive state) and the changeover switch 415 is turned off (nonconductive state), the output signal of the first amplifier circuit 401 is output. Is output to the subsequent stage without passing through the second amplifier circuit 402.

  The changeover switch 415 is controlled to be conductive / non-conductive (ON / OFF) by a signal φPAMPOFF output from the CPU 108, and the changeover switch 413 is controlled to be conductive / nonconductive (ON / OFF) by a signal φTH output from the CPU 108. Is done. The changeover switch 413 that is the first switch and the changeover switch 415 that is the second switch constitute an output control means, and the changeover switches 413 and 415 are exclusively turned on according to the read mode.

  For example, in the first embodiment, the CPU 108 performs control related to the column circuit 205 as follows according to the ISO sensitivity (photographing sensitivity) selected by the user from the display unit 106 or an operation member (not shown). That is, the CPU 108 uses the first readout mode in which the imaging signal is read without going through the second amplification circuit 402 and the second amplification circuit 402 in accordance with the selected ISO sensitivity (shooting sensitivity). The second readout mode for reading out the imaging signal is switched.

<When shooting sensitivity from ISO100 to ISO800 (low ISO sensitivity) is selected>
Control related to the column circuit 205 is performed so as to read the imaging signal in the first reading mode.
The CPU 108 turns on / off each switch of the feedback capacitance changeover switch group 405 by the control signals φCf1_1 to φCf1_6 so that the first amplification circuit 401 can obtain a predetermined amplification factor required in accordance with the set ISO sensitivity. To control. Further, the CPU 108 controls the signal φTH and the signal φPAMPOFF to turn on the changeover switch 413 and turn off the changeover switch 415. That is, control is performed so that the imaging signal is read without going through the second amplifier circuit 402.

  At this time, the CPU 108 controls the signal φPAMPENB to cut off the supply of the drive current to the inverting amplifier 408 of the second amplifier circuit 402 and stop the driving of the inverting amplifier 408. Alternatively, when the high ISO sensitivity is set, it is necessary to reduce the supply of the drive current to the inverting amplifier 408 in consideration of the time required to start the second amplifier circuit 402 again. May be.

<When photographing sensitivity from ISO 1600 to ISO 3200 is selected>
Control related to the column circuit 205 is performed so as to read the imaging signal in the second reading mode.
The CPU 108 controls on / off of each switch of the feedback capacitance changeover switch group 405 by the control signals φCf1_1 to φCf1_6 so that the first amplification circuit 401 can obtain a predetermined amplification factor required according to the ISO sensitivity. . Further, the CPU 108 controls the signal φUNITY, the signal φCs, and the signals φCf2_1 to φCf2_2 to turn on the changeover switch 414 and turn off the sampling capacitor connection changeover switch 411 and the feedback capacitor changeover switch group 409. As a result, the second amplifier circuit 402 is operated as a voltage follower, and the output signal of the first amplifier circuit 401 is output to the subsequent stage.

<When ISO 6400 or higher shooting sensitivity is selected>
Control related to the column circuit 205 is performed so as to read the imaging signal in the second reading mode.
The CPU 108 controls on / off of each switch of the feedback capacitance changeover switch group 405 by the control signals φCf1_1 to φCf1_6 so that the first amplification circuit 401 can obtain a predetermined amplification factor. Further, the CPU 108 controls on / off of each switch of the feedback capacitance changeover switch group 409 by the control signals φCf2_1 to φCf2_2 so that the second amplification circuit 402 can obtain a predetermined amplification factor. As described above, when a sensitivity of ISO 6400 or higher is selected, the CPU 108 can obtain a predetermined amplification factor required according to the ISO sensitivity by the first amplifier circuit 401 and the second amplifier circuit 402. In addition, each amplification factor is controlled.

  Further, the CPU 108 controls the signal φTH and the signal φPAMPOFF to turn off the changeover switch 413 and turn on the changeover switch 415. That is, control is performed so that the imaging signal is read out via the first amplifier circuit 401 and the second amplifier circuit 402.

  As described above, the imaging signal and the noise signal amplified by the first amplifier circuit 401 or the first amplifier circuit 401 and the second amplifier circuit 402 are transferred via the transfer gates 416 and 417 to the transfer capacitor 418, 419, respectively. The transfer gate 416 is controlled to be conductive / non-conductive (ON / OFF) by a signal φTS, and the transfer gate 417 is controlled to be conductive / non-conductive (ON / OFF) by a signal φTN.

  The imaging signal stored in the transfer capacitor 418 is output to the horizontal output line 208 via the column selection switch 206. Similarly, the noise signal stored in the transfer capacitor 419 is output to the horizontal output line 209 via the column selection switch 207. The column selection switches 206 and 207 are controlled to be on / off (on / off) by a signal φH supplied from the horizontal scanning circuit 213. Then, the difference between the image pickup signal and the noise signal output to the horizontal output lines 208 and 209 is amplified by the differential amplifier 212 with a predetermined amplification factor and output to the AFE 103. The horizontal output lines 208 and 209 are controlled to be conductive / non-conductive (ON / OFF) of the reset switches 210 and 211 by a signal φCHR, and are reset with the voltage VCHR every predetermined period.

  FIG. 5 is a timing chart showing an example of drive timing of the image sensor 102 in the first embodiment. FIG. 5 shows drive timings in one horizontal period when an imaging signal (signal charge) is read from the pixels 201 included in the imaging element 102. Note that each signal in the drawing assumes a high state (high level, hereinafter referred to as “H”) or a low state (low level, hereinafter referred to as “L”). Each signal is generated and output by the vertical scanning circuit 202 and the horizontal scanning circuit 213 in the image sensor 102 based on the drive signal from the TG 107.

  The signal HD indicates the head of one horizontal period and is set to “L” in a pulse form at the start of one horizontal period. The signal φHST indicates the start of the horizontal scanning period, that is, the start of reading of the output signal for each column to the horizontal output lines 208 and 209 controlled by the horizontal scanning circuit 213, and “H” is pulsed at the start of the horizontal scanning period. " During a period from time t1 when the signal HD becomes “L” to time t10 when the signal φHST becomes “H”, the imaging signal and noise signal for one row read from the pixel 201 are transferred to the transfer capacitors 418 and 419. This is a period during which the operation until storing is performed.

  Hereinafter, a reading operation for a pixel arranged in the n-th row among the plurality of pixels 201 arranged in a matrix in the image sensor 102 will be described. For convenience of explanation, “signal φSEL in the nth row” is referred to as “signal φSEL (n)”. Similarly, when “signal name (n)” is written for other signals as well, it indicates that the signal is an n-th row signal.

  At time t2, the signal φSEL (n) is set to “H”. As a result, the row selection switch 306 is turned on. At the same time, the signal φRES (n) is set to “H”, the reset switch 304 is turned on, and unnecessary charges accumulated in the storage capacitor 303 are reset.

  At time t3, the signal φRES (n) is set to “L”, the reset switch 304 is turned off, and the resetting of unnecessary charges is completed. At the same time, the signal φCLAMP is set to “H”, and the clamp switch 407 is turned on. As a result, a noise signal generated in the pixel 201 is clamped by the clamp capacitor 403 connected via the vertical output line 203.

  At time t4, the signal φCLAMP is set to “L”, the clamp switch 407 is turned off, and the clamping operation of the noise signal generated in the pixel 201 is completed. At the same time, the signal φTN is set to “H”, the transfer gate 417 is turned on, and the noise signal amplified by the first amplifier circuit 401 or the first amplifier circuit 401 and the second amplifier circuit 402 is transferred. It is stored in the capacity 419.

  At time t5, the signal φTN is set to “L”, the transfer gate 417 is turned off, and the storage of the noise signal in the transfer capacitor 419 is completed. At time t6, the signal φTX (n) is set to “H”, the transfer gate 302 is turned on, and the signal charge stored in the photodiode 301 is transferred to the storage capacitor 303.

  At time t7, the signal φTX (n) is set to “L”, the transfer gate 302 is turned off, and the accumulation of signal charges in the storage capacitor 303 is completed. At the same time, the signal φTS is set to “H” and the transfer gate 416 is turned on. As a result, the signal charge of the storage capacitor 303 in the pixel 201 is amplified by the source follower 305, converted into a voltage, and output to the vertical output line 203. The signal output to the vertical output line 203 is amplified by the first amplifier circuit 401 or the first amplifier circuit 401 and the second amplifier circuit 402 via the clamp capacitor 403, transferred to the transfer capacitor 418, and stored. The

  At time t8, the signal φTS is set to “L”, the transfer gate 416 is turned off, and the storage of the imaging signal in the transfer capacitor 418 is finished. Further, at time t9, the signal φSEL (n) is set to “L”, the row selection switch 306 is turned off, and the readout of the imaging signal from the pixel 201 in the n-th row is ended.

  From time t10, a horizontal scanning period starts for the signal of the pixel 201 in the nth row. In the horizontal scanning period, input of the signal φH is started to the horizontal scanning circuit 213, and the horizontal scanning circuit 213 sequentially turns on the column selection switches 206 and 207 in accordance with the input signal φH. When the column selection switches 206 and 207 are turned on, the signals stored in the transfer capacitors 418 and 419 are output to the horizontal output lines 208 and 209, respectively. Then, the differential amplifier 212 subtracts the noise component input from the horizontal output line 209 from the image pickup signal input from the horizontal output line 208 and amplifies it at a predetermined amplification rate to obtain an image signal for one row. Is output.

  According to the first embodiment, when a low ISO sensitivity (for example, ISO 100 to ISO 800) is set as the imaging sensitivity, the first amplification circuit among the two stages of amplification circuits 401 and 402 connected in cascade. The image pickup signal from the pixel 201 is amplified and output only by 401. Thus, at the time of low ISO sensitivity imaging, the first amplification circuit 401 amplifies the imaging signal and reads the imaging signal without going through the second amplification circuit 402, thereby suppressing the degradation of the S / N ratio. An imaging signal (image data) with good image quality can be obtained. Further, when photographing with low ISO sensitivity, driving of the inverting amplifier 408 of the second amplifier circuit 402 is stopped or unnecessary driving power is reduced to reduce unnecessary power consumption, thereby reducing power consumption in the image sensor 102. It is possible.

  In the above description, in accordance with the set ISO sensitivity (imaging sensitivity), the first readout mode for reading the imaging signal without going through the second amplification circuit 402 and the second amplification circuit 402 are used. Thus, the second readout mode for reading out the imaging signal is switched. Here, since the required amplification factor of the imaging signal changes according to the set ISO sensitivity, the first readout mode and the second readout mode are switched according to the required amplification factor. Also good. For example, when the required amplification factor is smaller than a certain threshold value, the imaging signal is read out in the first readout mode. Otherwise (when the required amplification factor is larger than the certain threshold value), the second readout is performed. The imaging signal may be read out in the mode.

(Second Embodiment)
Next, a second embodiment of the present invention will be described.
In the second embodiment, switching control related to driving of the second amplifier circuit 402 in the column circuit 205 of the image sensor 102 is performed in accordance with the operation mode of the imaging device. Note that the configuration of the imaging apparatus according to the second embodiment is the same as that of the first embodiment described above, and a description thereof will be omitted. In the second embodiment, the control related to the column circuit 205 is different from the first embodiment described above.

  In the second embodiment, the first operation mode is a still image shooting mode, and the second operation mode is a moving image shooting mode. The reading method in the first operation mode is omitted because it has been described in the first embodiment, and the reading method in the second operation mode will be described below. Switching between the first operation mode and the second operation mode related to the operation mode of the imaging apparatus is performed by the user from the display unit 106 or an operation member (not shown).

  When switched to the second operation mode, the inverting amplifier 408 in the second amplifier circuit 402 of the column circuit 205 stops driving by a signal φPAMPENB output from the CPU 108. Alternatively, driving may be performed by reducing the supply of drive current to the inverting amplifier circuit 408.

  In the second operation mode, the changeover switch 413, which is the first switch, is turned on by the signal φTH output from the CPU 108, and the changeover switch 415, which is the second switch, is turned off by the signal φPAMPOFF. That is, when operating in the second operation mode, the imaging signal is read out in the second readout mode, that is, the column circuit 205 is controlled to read out the imaging signal without passing through the second amplifier circuit 402. .

  When the imaging signal is read without going through the second amplification circuit 402, the imaging signal of the imaging signal is obtained with a predetermined amplification factor required according to the set ISO sensitivity (imaging sensitivity) in the first amplification circuit 401. Amplification will be performed. If a high ISO sensitivity is set, it is possible that a desired amplification factor cannot be obtained only by the first amplifier circuit 401. In such a case, amplification is performed by either the AFE 103 or the DSP 104 in the subsequent stage. Should be done.

  FIG. 6 is a timing chart showing an example of the drive timing of the image sensor 102 in the second embodiment. FIG. 6 shows the drive timing when the imaging signal of the pixel 201 in the n-th row is read from the imaging element 102 in the second operation mode. Here, for convenience of explanation, the readout row start row of the imaging signal is the n-th row. In the second operation mode, the read operation from time t1 to time t18 is repeatedly performed for each of a plurality of rows such as the nth row, the (n + 3) th row, and the (n + 6) th row.

  The signal VD indicates the beginning of one frame period, and is set to “L” in a pulse form at the start of one frame period. In the example shown in FIG. 6, reading for one frame is started from time t7 when the signal VD becomes “L”. Prior to the start of the frame period from time t7, reset scanning of the accumulated unnecessary charges is performed on the pixels 201 in the row where reading is performed.

  The time t1 when the signal HD is “L” indicates the beginning of the reset scanning period of the nth row. At time t2, the signal φSEL (n) is set to “H”. As a result, the row selection switch 306 is turned on. At the same time, the signal φRES (n) is set to “H”, the reset switch 304 is turned on, and unnecessary charges accumulated in the storage capacitor 303 are reset. Further, at the same time, the signal φTX (n) is set to “H”, the transfer gate 302 is turned on, and the charge of the photodiode 301 is also reset. At time t3, the signal φTX (n) is set to “L”, the transfer gate 302 is turned off, and the reset is completed.

  At time t4, the signal φRES (n) is set to “L”, the reset switch 304 is turned off, and the resetting of unnecessary charges in the storage capacitor 303 is completed. At time t5, the signal φSEL (n) is set to “L”, the row selection switch 306 is turned off, and reset scanning for unnecessary charges in the pixels 201 in the n-th row is completed.

  Thereafter, at time t7, the signal VD becomes “L”, and readout of the imaging signal for one frame is started. At the same time, the signal HD becomes “L”, and the readout scanning period for the pixels in the n-th row starts. . The drive timing in the period from time t7 to time t18 is the same as the drive timing in the first embodiment described above (time t1 to t11 shown in FIG. 5), and thus description thereof is omitted.

  According to the second embodiment, when the operation mode of the imaging apparatus is the moving image shooting mode, the imaging signal is amplified by the first amplification circuit 401 in the column circuit 205 and passes through the second amplification circuit 402. Control is performed so that the imaging signal is read without causing the image signal to be read. Thereby, it is possible to obtain an image pickup signal (image data) having a good image quality in which the deterioration of the S / N ratio is suppressed. In the moving image shooting mode, driving of the inverting amplifier 408 of the second amplifier circuit 402 is stopped or unnecessary drive current is reduced to reduce unnecessary power consumption, thereby reducing power consumption in the image sensor 102. be able to.

(Other embodiments of the present invention)
The present invention can also be realized by executing the following processing. That is, software (program) that realizes the functions of the above-described embodiments is supplied to a system or apparatus via a network or various storage media, and a computer (or CPU, MPU, or the like) of the system or apparatus reads the program. It is a process to be executed.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereto. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

DESCRIPTION OF SYMBOLS 100 Imaging device, 102 Imaging element, 107 Timing generation part (TG), 108 CPU, 201 pixel, 202 Vertical scanning circuit, 203 Vertical output line (column output line), 205 Column circuit, 401 1st amplifier circuit, 402 1st 2 amplifier circuit, 403 clamp capacitor, 404 inverting amplifier, 405 feedback capacitor switching switch group, 406 feedback capacitor group, 407 clamp switch, 408 inverting amplifier, 409 feedback capacitor switching switch group, 410 feedback capacitor group, 411 sampling capacitor connection switching Switch, 412 Sampling capacity, 413 selector switch, 414 selector switch, 415 selector switch

Claims (9)

A plurality of pixels including a photoelectric conversion element that generates charges according to incident light by photoelectric conversion;
A column output line for outputting the imaging signals from the plurality of pixels for each column;
A first amplifier circuit that amplifies and outputs a signal input via the column output line;
A second amplifier circuit for amplifying and outputting the output signal of the first amplifier circuit;
An image pickup device comprising: output control means for selecting and outputting the output signal of the first amplifier circuit or the output signal of the second amplifier circuit;
A first reading mode for reading the image pickup signal from the pixel without passing through the second amplifier circuit by controlling the output control means, and via the second amplifier circuit by controlling the output control means An image pickup apparatus comprising: a control unit that switches between a second read mode for reading an image pickup signal from the pixel.   The imaging apparatus according to claim 1, wherein the control unit switches between the first readout mode and the second readout mode according to imaging sensitivity.   The imaging apparatus according to claim 1, wherein the control unit switches between the first readout mode and the second readout mode in accordance with an operation mode of the imaging apparatus.   The control means switches to the first readout mode when the operation mode of the imaging device is the moving image shooting mode, and switches to the second readout mode when the operation mode of the imaging device is the still image shooting mode. The imaging apparatus according to claim 1, wherein the imaging apparatus is switched.   5. The imaging apparatus according to claim 1, wherein, in the first readout mode, the control unit cuts off or reduces the supply of drive current to the second amplifier circuit. 6. . The output control means includes a first switch connected to an output terminal of the first amplifier circuit, and a second switch connected to an output terminal of the second amplifier circuit,
The imaging apparatus according to claim 1, wherein the first switch and the second switch are exclusively turned on by the control unit according to a read mode.   The imaging apparatus according to claim 1, wherein the first amplification circuit and the second amplification circuit can switch an amplification factor.   Each of the first amplifier circuit and the second amplifier circuit includes an inverting amplifier and a plurality of series circuits connected in parallel between an input terminal and an output terminal of the inverting amplifier, and the series circuit includes: The imaging apparatus according to claim 1, wherein a switch and a feedback capacitor are connected in series. A plurality of pixels including a photoelectric conversion element that generates charges according to incident light by photoelectric conversion;
A column output line for outputting the imaging signals from the plurality of pixels for each column;
A first amplifier circuit that amplifies and outputs a signal input via the column output line;
A second amplifier circuit for amplifying and outputting the output signal of the first amplifier circuit;
Output control means for selecting and outputting the output signal of the first amplifier circuit or the output signal of the second amplifier circuit in accordance with an input control signal; An imaging device comprising: a first switch connected to an output terminal of an amplifier circuit; and a second switch connected to an output terminal of the second amplifier circuit.

Images