JP2012252443A - Phase synchronization detection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve phase synchronization control which is high in safety and readiness for achieving a phase synchronization moving average filter in which one cyclic section of synchronization detection angular frequency ωcan be accurately synchronized, and a moving average arithmetic operation can be performed by reducing detection delay.SOLUTION: A phase synchronization moving average filter 3B for extracting higher harmonic removal voltagesv,vfrom voltage components v, vsubjected to rotating coordinate transformation sets a phase input of a moving average arithmetic operation to a synchronization detection phase θ, calculates the rate of an asynchronization detection period in a phase section as a weight in order to obtain information of the detected synchronization detection phase θand one element of the phase section synchronized with the cycle of the synchronization detection angular frequency ω, performs multiplication and correction of a detection value vof the voltage components with the weight, transforms the voltage components after the weight correction into an average voltage synchronized with the cycle of the synchronization detection angular frequency ωby integrating the voltage components for each phase section, and performs moving and averaging of the transformed average voltage.

Description

  The present invention relates to a phase synchronization detection circuit for obtaining a phase synchronized with a voltage of a power supply system, and more particularly to a phase synchronization detection circuit corresponding to a sample detection signal asynchronous with the voltage of the power supply system.

  In distributed power supplies that use natural energy to supply power to the commercial power system, a power converter is provided to link the supplied power with the commercial power system, but an appropriate current synchronized with the voltage of the commercial power system It is necessary to control the output (frequency, amplitude, phase) of the power converter so that current flows. Of these, a phase locked loop (PLL) system is often used for voltage phase synchronization control of the power converter and the commercial power supply system.

  This phase synchronization method can be broadly classified according to the type of power supply voltage detection signal. It detects zero crossing of three-phase phase voltage and line voltage and uses a pulse-like signal several times in one cycle of the power supply voltage. And a method of constantly controlling phase synchronization using three-phase two-phase conversion, rotational coordinate conversion, etc. while sequentially detecting three-phase power supply voltages at high speed.

  Patent Documents 1, 2, and 3 are systems for calculating the phase by sequentially detecting the latter power supply voltage. Patent Document 1 and Non-Patent Document 1 are systems that take into consideration even when the power supply voltage waveform is unbalanced or when harmonic components are superimposed.

  As for the stability by the interconnection control of the power converter and the distributed power source to which these phase synchronization methods are applied, a function of continuing the operation without stopping even when the instantaneous voltage drop of the interconnection system is desired. For this purpose, it is necessary to obtain a stable reference synchronization signal from these voltage information even when not only the amplitude of the power supply voltage but also the unbalanced state and the harmonic component fluctuate transiently. In particular, since a positive phase component and a negative phase component are mixed in the power supply voltage when unbalanced, if the negative phase component cannot be accurately removed, the reference phase fluctuates due to the second harmonic, and stable energy control cannot be performed.

FIG. 6 shows a configuration of a general voltage detection type phase synchronization detection circuit. This phase synchronization detection circuit has a continuous phase synchronization detection circuit configuration in which the input is a three-phase voltage detection component and the output is a synchronization detection phase θ _S and a synchronization detection angular frequency ω _S.

  In FIG. 6, the three-phase / two-phase converter 1 converts the detection signal of the three-phase AC voltage into an orthogonal two-axis coordinate system (αβ coordinate). As a result, the zero-phase voltage component can be removed.

The rotating coordinate conversion unit 2 converts the rotating two-axis voltage components v _α and v _β into rotating coordinate components (dq coordinates) voltage components v _d and v _q synchronized with the synchronous detection phase θ _S. As a result, in the steady state after synchronization detection, the d-axis and q-axis voltage components v _d and v _q are DC. Therefore, a low-pass filter can be used as a filter for removing disturbance.

The low-pass filter 3 of the phase error detector removes harmonic components mixed in the d-axis and q-axis voltage components v _d and v _q . For example, if the detection voltage of the power supply is a three-phase unbalanced voltage, the second harmonic component is superimposed, and the rectifying load or the like often superimposes the sixth harmonic component. removed to harmonic rejection voltage ^- v _d, ^- v extracting the _q (Note that reference numerals used before the variable symbols mean DC component ^"-" indicates subjected to the top of the characters v is in the drawings ).

Polar coordinate conversion of the phase error detection unit 4, the harmonic removal voltage of the low-pass filter 3 ^- v _d, ^- v obtains a synchronization error phase Δθ from _q. Since the output through the low-pass filter 3 is a voltage in the coordinate system synchronized with the synchronization detection phase θ _S , the voltage vector should exist on the set reference axis if the synchronization is completed. However, if there is a phase synchronization shift, the vector component of the DC voltage exists in a different phase with respect to the reference axis. Therefore, the harmonic removal voltage polar coordinate transformation unit 4 ^- v _d, ^- v phase information calculated by the polar coordinate conversion from _q, and outputs it as a synchronization error phase [Delta] [theta].

The PI calculation unit 5 applies proportional integral control from the synchronization error phase Δθ of the polar coordinate conversion unit 4 to estimate the synchronization detection angular frequency ω _S. The angular velocity time integration unit 6 time-integrates the estimated synchronization detection angular frequency ω _S to calculate the above-described synchronization detection phase θ _S.

  In the phase synchronization detection circuit described above, the phase synchronization control is shown as a general PI control as a representative example, but is not limited to this method, and other feedback calculation methods may be used. There is also a method of reversing the calculation order of the filter 3 and the polar coordinate converter 4. In this method, phase information is first obtained by polar coordinate conversion and processed by a low-pass filter, and a similar effect can be obtained even when compared with the synchronous phase method using the circuit configuration of FIG.

FIG. 6 shows an example of a phase synchronization detection circuit using a continuous system expression. However, when a digital circuit is used, it is composed of a discrete system as shown in FIG. In FIG. 7, only the difference from FIG. 6 is shown. The power supply voltage is sampled and held by the sampler 7 in the detection cycle T _S and converted into a digital quantity by the A / D (analog / digital) converter 8 or the like. . In place from the synchronization detection angular frequency omega _S estimated to an integrator 6 to obtain the synchronization detection phase theta _S, the sampler 9 which stores the previous detection phase, the discrete time detector period T _S multiplied by the synchronization detection angular frequency omega _S The time integration of the synchronous detection angular frequency ω _S is approximated by Euler by the adder 11 for calculating the integration with the unit 10 and the previous synchronous detection phase θ _n = (Z ⁻¹ · θ _S ). Here, when it is desired to correct the delay time of this sampler, there are methods such as applying delayed phase compensation using the synchronous detection angular frequency ω _S to the detected phase, and many calculation methods approximating the integral. Although there is no direct relationship with the present invention, it is omitted.

Yasuo Jyohara and Atsio Kawamura, “A Method for Deriving Instantaneous Values of Star-Shaped Voltage and Zero-Phase Divided Voltage Based on Line Voltage of Unbalanced Three-phase Three-wire AC and Application to Three-Phase PWM Converter Control”, D 131, no. 3, pp. 372-379 (2011)

Japanese Patent No. 3374585 JP 55-34851 A Japanese Utility Model Publication No. 01-101175

  In the phase synchronization detection circuit, a problem occurs in the characteristics of the low-pass filter portion. In the above description, a steady state is assumed. However, a transient state such as an instantaneous voltage drop actually occurs in the system. In addition, the voltage unbalanced state also changes. Therefore, the phase-locked filter is required to have both a quick response and a broadband suppression characteristic in a transient phenomenon in which the fundamental wave component of the power supply frequency is passed with a small time delay but a high-order component and a disturbance component are cut off. This responsiveness and frequency cutoff characteristics are contradictory, and it is necessary to select an appropriate filter.

  There are many types of digital filters, such as IIR filters (infinite impulse response filters) and FIR filters (finite impulse response filters), but it can be said that FIR filters are suitable when response performance is required. One example of a simple configuration of this FIR filter is a moving average filter that uses a multiplication period of a power supply frequency as a calculation interval. A normal FIR filter requires detection data for a period of several cycles and a gain setting such as a window function so that the influence of an error due to aliasing (folding signal) does not occur, and it takes not only calculation time, There is a drawback that the detection delay at the time of transient phenomenon becomes large.

  As a method for preventing this, there is a method of taking a moving average in the same period as the synchronization frequency. The point is to eliminate the influence of aliasing by applying an accurate moving average to the fundamental wave period of the voltage to be detected. It has the advantage of being about ½ of the fundamental wave period.

However, a drawback of this moving average method is that the voltage component to be detected must be accurately synchronized with the synchronous detection angular frequency ω _S. When the voltage component detection cycle T _S is fixed, the synchronous detection angular frequency ω _S is not always an integral multiple of the detection cycle T _S. Since the power supply frequency fluctuates, the synchronization detection angular frequency ω _S and the voltage component detection cycle T _S are not synchronized, and in this case, an accurate moving average cannot be obtained.

FIG. 8 shows a trial example in which the function is improved to suppress the error of the moving average with a simple idea when the detection cycle and the fundamental wave cycle are not synchronized. In FIG. 8, a moving average filter 3A is provided instead of the low-pass filter 3, and the number-of-detections calculation unit 12 uses the synchronous detection angular frequency ω _S detected synchronously,
N = (2π / ω _S ) / T _S (1)
Thus, the moving average detection number N is calculated, and the moving average filter 3 is instructed to average the detection number N.

In FIG. 9, time is taken on the horizontal axis, reference phase data θ _n (corresponding to a synchronization detection phase (previous value) Z ⁻¹ · θ _S in FIG. 1 described later) synchronized with the detection cycle T _S on the upper stage, and on the lower stage. The voltage detection value v _n (corresponding to v _d and v _q in FIG. 1 described later) at that time is shown.

However, since the number N of moving average detections is not necessarily an integer, “2π = one cycle section where moving average is desired” shown in FIG. 9 does not coincide with the detection cycle T _S. A voltage component included in a period below the decimal point, which is an error between the detection cycle T _S and the desired moving average period 2π, appears as an error. If this error period is ignored, the harmonic component fluctuates due to the error component, and the synchronization detection angular frequency ω _S increases or decreases depending on the polarity of the error. Furthermore, the number of detection times N obtained by the above-described equation (1) is also affected. Therefore, when this conventional method is simulated, a moving average synchronized with one period period (= 2π) of the synchronization detection angular frequency ω _S cannot be realized accurately, and the phase synchronization control becomes unstable and stable. It turned out that the synchronous phase detection of a power supply cannot be performed.

The object of the present invention is to further improve the above method and realize a phase-synchronized moving average filter that can be accurately synchronized with one period of the synchronous detection angular frequency ω _S and that can perform a moving average calculation with reduced detection delay. Thus, an object of the present invention is to provide a phase synchronization detection circuit capable of stable and highly responsive phase synchronization control.

The present invention for solving the above problems, a voltage component obtained by converting a rotating coordinate v _d, the harmonic removal voltage from v _q ^- v _d, ^- v moving average filter for extracting the _q, the synchronization phase input of the moving average operation a detection period T sync detected phase synchronized with the _S theta _n asynchronous voltage component to detect angular frequency omega _S, and information of the detected synchronization detection phase theta _n, the phase interval in synchronization with the synchronization detection angular frequency omega _S 1 to obtain the number of elements, the ratio of the asynchronous detection period in the phase interval calculated as a weight, a voltage detection value v _n of the voltage component multiplied corrected by this weight, the weight after the correction voltage component individual phase A phase-synchronous moving average filter that integrates the sections and converts them into an average voltage synchronized with the synchronous detection angular frequency ω _S and performs a moving average on the average voltage after conversion is characterized by the following configuration.

(1) 3-phase voltage detecting components of the power supply system and the three-phase / two-phase conversion of the voltage component v _alpha of the 3-phase / 2-phase converted orthogonal biaxial coordinate, v _beta synchronization with the detection period T _S of the voltage component from the voltage component of the synchronization detection phase θ using _n dq coordinate system v _d, v rotated coordinate transformation _q, the voltage component v _d, the harmonic removal voltage from v _q by the moving average filter ^- v _d, ^- v _q was removed, the harmonic rejection voltage ^- v _d, ^- v _q obtains the synchronization error phase [Delta] [theta] to calculate the phase information by a polar coordinate conversion from estimated synchronization detection angular frequency omega _S than the synchronization error phase [Delta] [theta], the synchronization detection In the phase synchronization detection circuit for obtaining the phase θ _S ,
The moving average filter, a phase input of the moving average operation and the sync detection phase theta _n, the synchronization detection phase theta _n that the detected information and, one of the phase interval synchronized with the period of the synchronization detecting angular frequency omega _S In order to obtain an element, the ratio of the asynchronous detection period in this phase interval is calculated as a weight, the voltage component detection value v _n is multiplied and corrected by this weight, and the voltage component after this weight correction is calculated for each phase interval. A phase-locked moving average filter that integrates and converts to an average voltage synchronized with the period of the synchronous detection angular frequency ω _S and performs a moving average of the converted average voltage is provided.

(2) The phase-locked moving average filter is
The reference phase data θ _n is multiplied by “number of moving average points M / one period interval (= 2π) of the synchronous detection angular frequency ω _S ” and an integer part m (n) corresponding to the phase interval m and the weight of each interval m seek minority portion k _n corresponding to the coefficient k _n, these extracted to separate the fractional part k _n an integer portion m (n), of the detected value v _n of the voltage component obtained by converting the rotational coordinate, interval m and obtains a v _n · k _n multiplied by the weighting factor k _n is the first data voltage component comprising one previous sections of this interval m, the data contained all sections m weighting factor (k _n - v _n · (k _n −k _n−1 ) multiplied by k _n−1 ), and the last data of the voltage component including the interval m and the next interval of the interval m is represented by a weight coefficient (1.0− k _n-1) to v _n · multiplied (1.0-k _n) weight calculation section for obtaining the (20),
The sum of the detected voltage components Δv _{n, m} , Δv _{n + 1, m} , Δv _{n + 2, m} ... Obtained by multiplying each voltage sample value Δv _n in the interval m by the weight in the weight calculation unit (20) average voltage data m ^- v as _ma (m), determined by utilizing the timing of the integer part m is changed from the previous value asynchronous → synchronization converting unit (30),
The asynchronous → average voltage data obtained by the synchronous conversion unit (30) ^- v moving average data _ma (m) to converted sequentially stored to synchronizing phase into M stack memory ^- for v (Δθ _mM), their A moving average calculation unit (40) is provided that calculates the moving average output v _ma by adding (1 / M) after the total addition.

(3) The phase-locked moving average filter is
The synchronization detection phase θ _n is multiplied by “moving average number M / one period interval (= 2π) of the synchronization detection angular frequency ω _S ” and an integer part m (n) corresponding to the phase interval m and the weight of each interval m seek minority portion k _n corresponding to the coefficient k _n, these extracted to separate the fractional part k _n an integer portion m (n), of the detected value v _n of the voltage component obtained by converting the rotational coordinate, interval m and obtains a v _n · k _n is the first data voltage component obtained by multiplying the weighting factor k _n comprising one previous sections of this interval m, the voltage component which includes the following sections of this interval m and the interval m All included data is multiplied by a weighting factor (k _n −k _n−1 ) to obtain v _n · (k _n −k _n−1 ), and the last data in the interval m is a weighting factor (1.0− k _n-1) to v _n · multiplied (1.0-k _n) weight calculation section for obtaining the (20),
Detection value Delta] v n of the voltage component obtained by multiplying the weight to the detection value Delta] v _n of the voltage component of the interval m in the weight calculation unit _{(20), m, Δv n} + 1, m, a Δv n _{+ 2, m ...,} data were converted to synchronous phase with the write and addition while selecting data address in the stack memory ^- v and (Δθ _m) ^- v asynchronous → synchronous conversion unit for obtaining the (Δθ _mM) (30A),
And v (Δθ _m) ^{- -} the asynchronous → synchronous conversion unit data obtained in (30A) v as input data ([Delta] [theta] _mM), data at the time of change of the integer part m ^- adds v (Δθ _{m), M} pieces previous data ^- v obtains an integrated value D _SUM (m) of the M detection period by subtracting the ([Delta] [theta] _mM), moving average this integrated value D _SUM (m) by multiplying the (1 / M) A moving average calculation unit (40A) for obtaining the output v _ma is provided.

As described above, according to the present invention, the voltage component was converted rotational coordinate v _d, the harmonic removal voltage from v _q ^- v _d, ^- v moving average filter for extracting the _q, the synchronization detection angle phase input of the moving average operation The synchronization detection phase θ _n synchronized with the detection period T _S of the voltage component asynchronous to the frequency ω _S is set, and the information of the detected synchronization detection phase θ _n and the phase for the moving average synchronized with the synchronization detection angular frequency ω _S to obtain one of the elements of the section, the ratio of the asynchronous detection period in the phase interval calculated as a weight, a voltage detection value v _n of the voltage component multiplied corrected by the weight, further, the voltage after the weight correction converts the components into individual average voltage synchronized with integration to synchronization detection angular frequency omega _S for the phase time section, due to a phase-locked moving average filter to a moving average of the average voltage of the converted, synchronization detection angular frequency omega _S Cycle and movement A phase-synchronized moving average filter that can perform a moving average calculation with the average interval accurately synchronized and with reduced detection delay can be realized, and thus stable and highly responsive phase-synchronized control can be realized.

  Specifically, even when components such as system voltage amplitude and unbalance change, it is possible to realize a phase-synchronization detection circuit having features of suppressing high-order harmonic components and reducing detection delay of fundamental components.

  As a result, the phase synchronization detection circuit can be applied to the interconnection control of the power converter and the distributed power supply to stabilize the current waveform of the regenerative power.

  In addition, if a moving average filter having the same characteristics as the rotating coordinate transformation of the antiphase is added, various applications such as detecting the antiphase component, that is, the second harmonic component in the synchronous coordinate system, are possible. Become. If the negative-phase voltage component at the time of unbalance can be detected stably and highly responsively, the power quality in the system power supply device of the distributed power source can be improved even at the time of unbalanced voltage.

The schematic block diagram of the phase-synchronization detection circuit of embodiment. Explanatory drawing of the moving average calculation of an electrical angle-cycle by phase interpolation calculation. Explanatory drawing of the conversion method of the asynchronous detection value to the synchronous detection data. 1 is a circuit configuration diagram of a phase-locked moving average filter according to an embodiment (part 1). FIG. 3 is a circuit configuration diagram of a phase-locked moving average filter according to the embodiment (part 2). Configuration diagram of voltage detection type phase synchronization detection circuit (continuous system). 1 is a configuration diagram of a voltage detection type phase synchronization detection circuit (discrete system). A phase synchronization detection circuit (discrete system) using a moving average filter. FIG. 4 is a relationship diagram between reference phase data θ _n and a detected value v _n of a voltage component at that time.

(1) Schematic Configuration of Phase Synchronization Detection Circuit FIG. 1 is a schematic configuration diagram of a phase synchronization detection circuit proposed in the present invention. Portions figure differs from FIG. 8, instead of the moving average filter 3A with detection count calculation unit 12, a phase synchronization moving average filter 3B is provided, the synchronization detection phase of the moving average phase input detection period T _S θ _n ( The previous value) = Z ⁻¹ · θ _S, and the voltage component of the detection cycle T _S is accurately moving averaged by this synchronization detection phase θ _n .

(2) Principle Explanation of Phase Synchronization Detection The time chart of FIG. 9 is drawn with the horizontal axis as time and the synchronization phase of the phase synchronization detection circuit as the vertical axis. FIG. 2 is a diagram in which the horizontal axis and the vertical axis of the time axis and the phase axis are interchanged. The lower shows the detection value v _n of the voltage component as the vertical axis component, is equivalent to Figure 9 because in synchronism with the phase corresponding to the detected period T _S.

  The proposed moving average method converts a plurality of asynchronous detection data (n-th data) into M-point data (m-th data) synchronized with the phase, and outputs the result after performing M-point moving average calculation. It is.

FIG. 2 shows an example in which a section of one cycle period (= 2π) component of the synchronization detection angular frequency ω _S is divided into M = 8 points for simplicity of explanation. Of course, the number of divisions can be arbitrarily set. In FIG. 2, it is set so that at least one detection period T _S exists in this phase interval, but this is also for the sake of simplicity. If no detection is made, exception processing is performed. Apply. In actual implementation, this exception handling method can be easily inferred by extending the concept of interval averaging shown below, and therefore the description thereof will be omitted in the following description.

  The following are used as input / output signals and internal variables in FIG.

(A) Variable θ _n related to asynchronous detection input: Phase synchronized with voltage component detection cycle T _S (corresponding to synchronous detection phase (previous value) Z ⁻¹ · θ _S in FIG. 1)
v _n : voltage detected at the same timing as phase θ _n (corresponding to voltage components v _d and v _q in FIG. 1)
{EMBED Equation.3,}: Number of moving average points (number of phase divisions) synchronized to one period (= 2π) of the synchronous detection angular frequency ω _S
Enable: Control signal indicating the calculation start timing of the moving average calculation (1 = calculation enable, 0 = calculation stop and reset)
(B) Variables for synchronous conversion n: Asynchronous detection data number m: Number indicating a specific section among M divided one period (2π) components of the synchronous detection angular frequency ω _S θ _m : {EMBED Equation.3,} Phase segmentation phase segment (initial phase of segment)
k _n , k _{n + 1} , k _{n + 2} ,...: weight function Δv _{n, m} from the initial phase θ _m to θ _n , θ _{n + 1} , θ _{n + 2} ,. , Δv _{n + 1, m} , Δv _{n + 2, m} ... k _n : In the section m, the weights k _n , k _{n + 1} , k _n for the section average are added to the n, n + 1, n + 2 _,. Voltage component corrected by multiplying ₊₂ …
^- v ^(Δθ _{m): m-th} synchronous average voltage converted value to the component sections of M to the classification by the phase interval _{(Δv n, m, Δv n} + 1, m, Δv n + 2, m, ... of Integrated value)
(C) Output signal
^- v _ma (m): M-number of ^- v voltage output components to remove high-order harmonic components that moving average _{(Δθ m) EN ma: Enable} = 1 moving average are M after input (operation permission) signal A status flag indicating that normal output is obtained and the principle of converting asynchronous data to synchronous data will be described with reference to FIG. An example of obtaining the synchronous voltage component in the section m = −1 (section from θ _m−1 to θ _m ) in FIG. 3 will be described. In this section m, the voltage data is related to the (n−1) th to (n + 3) th data. Therefore, the average voltage interval m by utilizing the detection data of these voltage components ^- calculating the v ([Delta] [theta] _m).

  Here, it should be noted that the first and last (n−1) number and (n + 3) number data are cut in the middle by the phase break of the section m. On the other hand, the other detection data of the nth to (n + 2) th are included in the section m. Therefore, in order to accurately calculate the average voltage in the interval m, it is necessary to apply an accurate correction operation to the data across the phase interval. Therefore, the following three types of weighting factors are applied to each voltage component. To accurately extract a synchronized portion from the asynchronous n-th data.

  -The first data of the section m (here (n-1)) is obtained from the following equation.

  Intermediate data (here, n, (n + 1), (n + 2)) all included in the section m is obtained from the following equation in the example of (n + 1), for example.

  -The last data of the section m (here, (n + 3)) is obtained from the following equation.

Do this three calculations, Δv n _{+ i,} the average voltage synchronized the sum of _m in the interval m ^- v and _ma (m). This is the principle of converting asynchronous detection data into phase synchronization data.

Even if the voltage component detection cycle T _S is not synchronized with the phase of the synchronous detection angular frequency ω _S as shown in FIG. 9 by such data conversion, the phase synchronous data is temporarily displayed as shown in FIG. Thus, even for asynchronous data, a moving average calculation can be performed with a cycle that is an integer multiple of the synchronous detection angular frequency ω _S more accurately.

(3) Specific circuit configuration of phase-locked moving average filter (part 1)
FIG. 4 shows a circuit configuration example of the phase-locked moving average filter 3B. The figure includes an asynchronous-to-synchronous conversion weight calculation unit 20, an asynchronous-to-synchronous conversion unit 30, and a moving average calculation unit 40 of the synchronously converted data, each of which will be described in detail below.

(A) Asynchronous to synchronous conversion weight calculation unit 20
The synchronization detection phase θ _n is assumed to be periodic data of (0 ≦ θ _n <2π). By multiplying the M / (2π) m (n ) + k n ( where, m (n) is an integer unit, k _n denotes the fractional part) by the multiplier 21 to the weight calculation section 20 decimal as To ask. Then, the integer part to extract an integer portion extracting section 22 m (n) (0 ≦ m <M), the following partial point extraction with fewer lower brewing unit 23 with k _n. Few lower extraction unit 23, the removal of m multiplied by M / (2π) (n) + k n from the integer unit m (n), the calculation result k _n is

Is equivalent to

As a result, the weight function of the basic θ _m and θ _n intervals can be calculated. Therefore, the weight multiplier 24 applies v _n to the first data of the voltage component including the interval m and the immediately preceding interval m. A multiplication value using k _n and the weight coefficient k _n is output as it is, and a value v _n. (() Obtained by multiplying the data included in all the intervals m by a coefficient that is different from the previous value by the sampler 27 by the weight multiplier 25. k _n −k _n−1 ), and the weight multiplier 26 multiplies the last data of the voltage component including the interval m and the next interval of the interval m by a coefficient corresponding to the period up to 1.0. the output value v _n · a (1.0-k _n).

(B) Asynchronous → synchronous conversion unit 30
The asynchronous-to-synchronous conversion unit 30 uses voltage components Δv _{n, m} , Δv _{n + 1, m} , Δv _{n + 2, m} ... Obtained by multiplying each voltage component Δv _n in the interval m by three types of weights in the weight calculation unit 20. average voltage data sum of the interval m ^- v obtained as _ma (m). Of the data obtained by multiplying the three types of weights, the first two types of addition control are determined by whether the integer part m has changed from the previous value. As a result of this determination, a signal obtained by the determination unit 32 determining whether the phase section number m (n) extracted by the integer part extraction unit 22 and the previous phase section number m (n−1) stored by the sampler 28 match / do not match. Give as sel.

  The phase interval data averaging integrator 31 performs the following operation.

· If the integer portion m has changed from the previous value (sel = 1): v is stored in the sum of _{n-k n} as an initial value.

· If the integer portion m is not changed from the previous value (sel = 0): adding the _{v n · (k n -k n} -1) to the previous value sum.

  Of the three types of weights multiplied, the last type of data is always added to the output sum of the phase interval data averaging integrator 31. In practice, however, it is stored in the moving average data memory in the next stage. The stored timing is when the integer part m changes, and is just latched at the next stage at the timing when the last data is valid. In other words, it is ignored at other times, so even if it is always added, it is ignored and there is no actual harm.

(C) Moving average calculation unit 40 of synchronously converted data
Moving average average voltage data output of the arithmetic unit 40 in the phase interval m ^- v from (Δθ _m) ^- v sequentially stores data ([Delta] [theta] _mM) to M stack memory 41, a multiplier after total addition of them 42 To calculate (1 / M) and obtain the moving average output v _ma . As a result, the moving average synchronized with the synchronization detection angular frequency ω _S can be sequentially output at the update timing of the integer part m.

By the way, since the moving average cannot output accurate data until M pieces of data are accumulated, it is measured by the update timing counter 43 of v _ma (m), and it is detected that it has been updated M times, and the data is valid. / Invalid status flag _ENma is output. This status flag EN _ma is not indispensable, it is also possible to substitute with appropriate weights timer. This phase-synchronized data output is added in FIG. 4 only to indicate an invalid period at the start.

(4) Specific circuit configuration of the phase-locked moving average filter (part 2)
FIG. 5 shows another circuit configuration of the phase-locked moving average filter. FIG. 4 differs from FIG. 4 only in the moving average calculation method. In FIG. 5, a method of constructing a moving average with an accumulator and an adder / subtracter is applied, and M adders 41 are not required as in FIG. Otherwise, an arithmetic circuit equivalent to the moving average calculation of FIG. 4 is used.

The method to configure a moving average in integrator and adder-subtractor is because it is already well-known method, the following ^- v input instead of ([Delta] [theta] _mM) in the general variable, D (m) Only a simple principle expression is shown.

When M moving averages are taken in D (m) input data-First (1 to M-1) detection periods

  ・ Calculation of detection period m after M

Asynchronous → synchronous conversion unit (synchronous data memory stack unit) 30A “stack memory writing / adding / reading unit 31A receives the voltage component multiplied by the weighting coefficient in the above equation and inputs the data address to stack memory 31B. by performing the selection while the write adds data obtained by converting the stack memory to the diverting while synchronizing phase as storage memory integrated value ^- v and (Δθ _m) ^- v is calculating (Δθ _mM). This subtraction data required for the operation of the D _SUM (m) ^- equivalent to controlling the reading of v (Δθ _mM) ^- v and ([Delta] [theta] _m).

The integrating unit 44 of the moving average calculation section 40A, and performs the calculation corresponding to the D _SUM (m), data at the time of change of the integer part m ^- adds v (Δθ _{m), M-previous} data ^- v (Δθ _mM ) is subtracted to obtain an integrated value D _SUM (m) for M detection periods.

  Of course, even in this case, the moving average cannot output accurate data until M pieces of data are accumulated. Further, when Enable = 0, a function for clearing the memory stack of the counter 43 and 31B is added as necessary.

  As described above, according to the configuration of FIG. 5, the calculation time can be greatly shortened when realized by a CPU or the like, and the number of logics can be greatly reduced when realized by a logic circuit such as an FPGA.

DESCRIPTION OF SYMBOLS 1 3 phase / 2 phase conversion part 2 Rotation coordinate conversion part 3 Low-pass filter 3A Moving average filter 3B Phase synchronous moving average filter 4 Polar coordinate conversion part 5 PI calculating part 7, 9 Sampler 12 Detection frequency calculating part 20 Weight calculating part 30 , 30A Asynchronous → Synchronous conversion unit 40, 40A Moving average calculation unit

Claims (3)

Synchronous detection in which the three-phase voltage detection component of the power supply system is converted into three-phase / two-phase, and the three-phase / two-phase converted voltage components v _α and v _{β of} the orthogonal two-axis coordinates are synchronized with the voltage component detection cycle T _S rotated coordinate conversion voltage component v _d, v _q in the dq coordinate system using the phase theta _n, wherein the moving average filter voltage component v _d, the harmonic removal voltage from ^{_{v q - v d, - v}} q was removed, the harmonic rejection voltage ^- v _d, ^- v _q obtains the synchronization error phase [Delta] [theta] to calculate the phase information by a polar coordinate conversion from estimated synchronization detection angular frequency omega _S than the synchronization error phase [Delta] [theta], the synchronization detection phase theta _S In the phase synchronization detection circuit for obtaining
The moving average filter, a phase input of the moving average operation and the sync detection phase theta _n, the synchronization detection phase theta _n that the detected information and, one of the phase interval synchronized with the period of the synchronization detecting angular frequency omega _S In order to obtain an element, the ratio of the asynchronous detection period in this phase interval is calculated as a weight, the voltage component detection value v _n is multiplied and corrected by this weight, and the voltage component after this weight correction is calculated for each phase interval. A phase synchronization detection circuit characterized in that a phase synchronization moving average filter that integrates and converts to an average voltage synchronized with a cycle of the synchronization detection angular frequency ω _S and performs a moving average of the converted average voltage. The phase-locked moving average filter is
The reference phase data θ _n is multiplied by “number of moving average points M / one period interval (= 2π) of the synchronous detection angular frequency ω _S ” and an integer part m (n) corresponding to the phase interval m and the weight of each interval m seek minority portion k _n corresponding to the coefficient k _n, these extracted to separate the fractional part k _n an integer portion m (n), of the detected value v _n of the voltage component obtained by converting the rotational coordinate, interval m and obtains a v _n · k _n multiplied by the weighting factor k _n is the first data voltage component comprising one previous sections of this interval m, the data contained all sections m weighting factor (k _n - v _n · (k _n −k _n−1 ) multiplied by k _n−1 ), and the last data of the voltage component including the interval m and the next interval of the interval m is represented by a weight coefficient (1.0− k _n-1) to v _n · multiplied (1.0-k _n) weight calculation section for obtaining the (20),
The sum of the detected voltage components Δv _{n, m} , Δv _{n + 1, m} , Δv _{n + 2, m} ... Obtained by multiplying each voltage sample value Δv _n in the interval m by the weight in the weight calculation unit (20) average voltage data m ^- v as _ma (m), determined by utilizing the timing of the integer part m is changed from the previous value asynchronous → synchronization converting unit (30),
The asynchronous → average voltage data obtained by the synchronous conversion unit (30) ^- v moving average data _ma (m) to converted sequentially stored to synchronizing phase into M stack memory ^- for v (Δθ _mM), their The phase synchronization detection circuit according to claim 1, further comprising a moving average calculation unit (40) for _obtaining a moving average output _vma by multiplying the sum by (1 / M). The phase-locked moving average filter is
The synchronization detection phase θ _n is multiplied by “moving average number M / one period interval (= 2π) of the synchronization detection angular frequency ω _S ” and an integer part m (n) corresponding to the phase interval m and the weight of each interval m seek minority portion k _n corresponding to the coefficient k _n, these extracted to separate the fractional part k _n an integer portion m (n), of the detected value v _n of the voltage component obtained by converting the rotational coordinate, interval m and obtains a v _n · k _n is the first data voltage component obtained by multiplying the weighting factor k _n comprising one previous sections of this interval m, the voltage component which includes the following sections of this interval m and the interval m All included data is multiplied by a weighting factor (k _n −k _n−1 ) to obtain v _n · (k _n −k _n−1 ), and the last data in the interval m is a weighting factor (1.0− k _n-1) to v _n · multiplied (1.0-k _n) weight calculation section for obtaining the (20),
Detection value Delta] v n of the voltage component obtained by multiplying the weight to the detection value Delta] v _n of the voltage component of the interval m in the weight calculation unit _{(20), m, Δv n} + 1, m, a Δv n _{+ 2, m ...,} data were converted to synchronous phase with the write and addition while selecting data address in the stack memory ^- v and (Δθ _m) ^- v asynchronous → synchronous conversion unit for obtaining the (Δθ _mM) (30A),
And v (Δθ _m) ^{- -} the asynchronous → synchronous conversion unit data obtained in (30A) v as input data ([Delta] [theta] _mM), data at the time of change of the integer part m ^- adds v (Δθ _{m), M} pieces previous data ^- v obtains an integrated value D _SUM (m) of the M detection period by subtracting the ([Delta] [theta] _mM), moving average this integrated value D _SUM (m) by multiplying the (1 / M) The phase synchronization detection circuit according to claim 1, further comprising a moving average calculation unit (40A) for obtaining an output _vma .

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