JP2012244379A - Solid state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an output signal without losing color balance even if incident light changes from high luminance to low luminance during an exposure period.SOLUTION: A TX signal has a voltage value V3 at which Q1 is placed in a fully conductive state at the starting point of the exposure period. The TX signal decreases afterward in one direction of turning off the Q1 toward at the end point of the exposure period. At the starting point of the exposure period, light having quantities X1, X2 is incident, but the voltage value of the TX signal is V3, or high, so that a PD can be stored with only a small amount of electric charge. When the quantity of the incident light becomes 0, the amount of electric charge stored in the PD does not decrease below a sub-threshold level of the Q1, so it approximates a certain electric charge amount (y). In this case, the voltage value of the TX signal is set substantially to the voltage value V3 and the PD is stored with only a small amount of electric charge while the light having quantities X1, X2 is incident. Consequently, the electric charge amount (y) is much smaller than an electric charge amount (y) of a conventional pixel circuit.

Description

  The present invention relates to a solid-state imaging device having photoelectric conversion characteristics that are linear with respect to incident light with low luminance and logarithm with respect to incident light with high luminance.

  2. Description of the Related Art In recent years, in an imaging apparatus such as a digital camera, with the demand for higher image quality, it has become a major theme to expand the luminance range of a subject that can be handled by an imaging sensor, that is, the dynamic range (DR). . Regarding the expansion of the dynamic range, for example, by using the sub-threshold characteristic of the MOSFET, the electrical signal is converted linearly according to the incident light quantity with low brightness, and the electrical signal is converted logarithmically according to the incident light quantity with high brightness. There is known an imaging sensor having output characteristics, that is, an imaging sensor having a photoelectric conversion characteristic composed of a linear characteristic region and a logarithmic characteristic region (referred to as a linear log sensor) (for example, Patent Document 1).

  Since the linear log sensor can obtain an output logarithmically converted with respect to the incident light quantity with high luminance as described above, the linear log sensor has a wider dynamic range than an imaging sensor having photoelectric conversion characteristics only in the linear characteristic region. Secured.

  In the linear log sensor, a transfer transistor having subthreshold characteristics is disposed adjacent to a photoelectric conversion unit (for example, a photodiode). For high-intensity incident light that can generate a charge exceeding the subthreshold level, the charge generated by the photodiode flows out of the transfer transistor according to the subthreshold characteristic.

  For this reason, the linear log sensor outputs an output signal having a logarithmic relationship with the amount of incident light with respect to incident light with high luminance. Such an operation of the linear log sensor will be referred to as a logarithmic domain operation. In this logarithmic domain operation, the output signal output from the linear log sensor does not have time integration.

  On the other hand, for low-intensity incident light that cannot generate charges exceeding the subthreshold level of the transfer transistor, the charges generated in the photodiode are only accumulated in the photodiode. Therefore, the linear log sensor outputs an output signal proportional to the time integration of the incident light quantity for low-luminance incident light. Here, such an operation of the linear log sensor is referred to as a linear region operation. In this linear region operation, the output signal output from the linear log sensor has time integration.

  The above is an explanation of the operation of the linear log sensor when the amount of incident light does not change during the exposure period (in the case of steady light).

  On the other hand, the linear log sensor exhibits a behavior different from the above when the amount of incident light changes greatly during the exposure period. Hereinafter, this will be described with reference to FIGS. 15 and 16. FIGS. 15 and 16 are timing charts showing the conventional operation of the linear log sensor shown in the pixel circuit 11 described in detail in FIG. 3, for example. The pixel circuit 11 operates as a linear log sensor by applying a voltage value V2 as the transfer signal TX applied to the gate of the transfer transistor Q1 during the exposure period.

  FIG. 15 shows a case where the incident light amount does not change during the exposure period, and FIG. 16 shows a case where the incident light amount changes from a high value to a low value during the exposure period. In FIG. 15, the amount of incident light is constant at the amount of light X1 or X2 during the exposure period. Here, the light amount X1 or X2 is a light amount that causes the linear log sensor to operate in a logarithmic region if the value is constant during the exposure period.

  In FIG. 15, the linear log sensor continues logarithmic domain operation during the exposure period. For this reason, the charge amount y1 or the charge amount y2 stored in the photodiode has a linear relationship with the logarithm of the incident light amount. Therefore, the output signal output from the linear log sensor has a value depending on the amount of incident light.

JP 2002-077733 A

  On the other hand, in FIG. 16, the linear log sensor has the incident light amount X1 or X2 in the initial period of the exposure period, but the light amount has decreased to 0 in the remaining exposure period.

  Therefore, the linear log sensor performs the logarithmic region operation in the initial period. However, in the remaining exposure period, the amount of incident light is reduced, and the logarithmic region operation is not integrated, so that the charge amount of the photodiode decreases.

  However, since the amount of charge stored in the photodiode does not fall below the subthreshold level of the transfer transistor, it approaches a certain amount of charge y. Therefore, strictly speaking, the output signal output from the linear log sensor is a value close to a certain value, although it depends on the amount of incident light. For this reason, it is difficult to reversely calculate the amount of incident light from the output signal output from the linear log sensor, which causes deterioration in image quality during image formation.

  Specifically, if the linear log sensor is a color sensor, the light transmittance is different for each color of the color filter. For this reason, the amount of incident light should be different for each color, but if the amount of light changes during the exposure period as shown in FIG. 16, the output signal of each color will have almost the same value, so the output of each color that should originally be obtained The signal ratio cannot be obtained. Therefore, the color balance is lost and the image quality is deteriorated.

  More specifically, when a complementary color filter is employed as the color filter, the color component is calculated from the difference between the output signals of the respective colors. For example, when W (white), Y (yellow), and R (red) filters are employed as complementary color filters, B = W−Y is employed for B (blue), and G = green is employed for G (green). The value of YR is adopted, but the value of the output signal is adopted as it is for R (red).

  Therefore, when the light quantity changes as shown in FIG. 16 during the exposure period, the output signals of W, Y, and R have substantially the same level. For this reason, the B and G output signals are calculated to be very small values, only the R output signal is emphasized, and a large color noise is observed.

  An object of the present invention is to provide a solid-state imaging device capable of obtaining an output signal without losing color balance even when incident light changes from high luminance to low luminance during an exposure period.

  (1) The solid-state imaging device according to the present invention has a photoelectric conversion characteristic that is linear for low-luminance light and logarithm for high-luminance light, and is one of a plurality of predetermined color components. A solid-state imaging device including a plurality of pixel circuits having spectral characteristics of color components, wherein the pixel circuit generates a charge according to an incident light amount and stores the charge, and a charge amount stored by the charge storage unit. A control transistor for controlling, a charge reading unit for converting the charge accumulated in the charge accumulation unit into a voltage signal and reading it as an output signal, and an amplification transistor for amplifying the output signal read by the charge reading unit, At least at the end of the period, the control is performed in a predetermined intermediate conduction state between a fully open conduction state in which the control transistor is in an on state and a non-conduction state in which the control transistor is in an off state. A control unit that drives a transistor to cause the charge accumulation unit to accumulate charges with the photoelectric conversion characteristics, and to drive the control transistor in a conduction state higher than the predetermined intermediate conduction state at least at the start of the exposure period. Is provided.

  According to this configuration, the control transistor is driven to a conductive state higher than the intermediate conductive state at the start of the exposure period. For this reason, when high-intensity light is incident during the first period of the exposure period, only a small amount of charge is stored in the charge storage portion. Therefore, the amount of charge stored in the charge storage unit at the end of the exposure period is significantly smaller than when the control transistor is constantly driven in the intermediate state during the exposure period. As a result, using output signals obtained from the pixel circuits having different color components, at least one color component has the same color component as any one of the color components of the pixel circuit, and the remaining color components are any of the pixel circuits. Even if an output signal having a color component different from the color component is obtained, the output signal can be obtained without losing the color balance.

  (2) It is preferable that the control unit changes the conduction state of the control transistor in one direction toward the non-conduction state during the exposure period.

  According to this configuration, the conduction state of the control transistor is changed in one direction from the fully open conduction state to the intermediate conduction state. Therefore, when light in a linear region is incident during the exposure period, it is possible to prevent all of the charges generated at that time from being discharged. Therefore, the amount of charge stored in the charge storage unit when receiving light in a linear region with time integration is greatly reduced compared to the conventional configuration that is always maintained in an intermediate conduction state during the exposure period. Is prevented.

  (3) It is preferable that the control unit sets the conduction state of the control transistor to the fully open conduction state at the start of the exposure period.

  According to this configuration, the conductive state of the control transistor is set to the fully open conductive state at the start of the exposure period. Therefore, when high-luminance light is incident in the initial period of the exposure period and then low-luminance light is incident, more charge is discharged from the charge storage portion in this initial period. Therefore, at the end of the exposure period, the amount of charge accumulated in the charge accumulation unit can be reduced, and the color balance can be better maintained.

  (4) The charge storage unit is configured by a photodiode, the charge readout unit is configured by a floating diffusion layer, and the control transistor is connected between the charge storage unit and the charge readout unit. It is preferable.

  According to this configuration, even when the control transistor is connected between the charge storage unit and the charge reading unit, that is, when the control transistor is configured by a so-called transfer transistor, color balance can be prevented from being lost. it can.

  (5) The charge storage unit is configured by a photodiode, the charge readout unit is configured by a floating diffusion layer, and the control transistor is connected to the charge storage unit via the charge readout unit. Is preferred.

  According to this configuration, according to this configuration, even when the control transistor is connected to the charge reading unit via the charge reading unit, that is, when the control transistor is configured by a so-called reset transistor, the color balance is lost. Can be prevented.

  (6) It is preferable that the control unit continuously changes a conduction state of the control transistor in the exposure period.

  According to this configuration, since the conduction state of the control transistor is continuously changed, the control transistor can finely control the amount of charge accumulated in the charge accumulation unit.

  (7) It is preferable that the control unit changes the conduction state of the control transistor stepwise in the exposure period.

  According to this configuration, since the conduction state of the control transistor is changed stepwise, the driving of the control transistor can be simplified.

  According to the present invention, the conductive state of the control transistor is set to the fully open conductive state at the start of the exposure period, and the conductive state of the control transistor is a predetermined intermediate between the fully open conductive state and the nonconductive state at the end of the exposure period. It is in a conductive state. Therefore, even if high-intensity light is incident in the initial period of the exposure period and low-intensity light is incident in the remaining period, most of the charge generated by the high-intensity light is discharged. The amount of charge accumulated in the photodiode at the end of the period is reduced. As a result, using the output signals obtained from the pixels having different color components, at least one color component has the same color component as any one of the color components of the pixel circuit, and the remaining color components are any of the pixel circuits. Even when an output signal having a color component different from the color component is obtained, the color balance can be maintained.

1 is a block diagram illustrating an overall configuration outline of a solid-state imaging device according to an embodiment of the present invention. It is the block diagram which showed another example of the whole structure outline of the solid-state imaging device by the modification of FIG. FIG. 3 is a circuit diagram of a pixel circuit corresponding to the pixel shown in FIG. 1 or FIG. 2. FIG. 4 is a circuit diagram of a pixel circuit of a modification of the pixel circuit shown in FIG. 3. 5 is a timing chart of the pixel circuit shown in FIG. 3 or the pixel circuit shown in FIG. FIG. 5 is a timing chart of the pixel circuit shown in FIG. 3 or FIG. 4 when a certain amount of light is incident during an exposure period. 3 is a diagram illustrating a connection relationship between a pixel array unit and a voltage application circuit of the solid-state imaging device according to Embodiment 1. FIG. 6 is a diagram illustrating a connection relationship between a pixel array unit and a voltage application circuit in a solid-state imaging device according to a modification of Example 1. FIG. In the solid-state imaging device of Example 2, it is the figure which showed the connection relation of a pixel array part and a voltage application circuit. FIG. 10 is a diagram illustrating a connection relationship between a voltage application circuit and a pixel array unit of a solid-state imaging device according to a modification of Example 2. 6 is a diagram illustrating a connection relationship between a pixel array unit and a voltage application circuit of a solid-state imaging device according to Embodiment 3. FIG. It is a timing chart which shows the relationship between the TX signal output from a voltage application circuit and the TX signal applied to Q1 of each row for rows # 1 to #n (n is a positive integer) in one block. It is a timing chart which shows the relationship between the RST signal output from a voltage application circuit, and the RST signal applied to Q2 of each row about row # 1-#n (n is a positive integer) in one block. 10 is a timing chart of a pixel circuit in a pixel configuration 2. It is a timing chart of the linear log sensor in an exposure period and a signal reading period. It is a timing chart of the linear log sensor in an exposure period and a signal reading period.

  FIG. 1 is a block diagram showing an overall schematic configuration of a solid-state imaging device according to an embodiment of the present invention. The solid-state imaging device includes a solid-state imaging device 1 and an imaging circuit 60. The solid-state imaging device 1 includes a pixel array unit 10, a vertical scanning circuit 20 (an example of a control unit), a timing generator (hereinafter referred to as “TG”) 30, a readout unit 40, and an output amplifier 50. An imaging circuit 60 that controls the solid-state imaging device 1 is connected to the solid-state imaging device 1. The solid-state imaging device 1 shown in FIG. 1 is an analog output solid-state imaging device from which an analog signal is output from the output amplifier 50.

  The pixel array unit 10 includes pixels GE arranged in a matrix with m (m is an integer of 1 or more) columns in the horizontal direction and n (n is an integer of 1 or more) rows in the vertical direction. The pixel GE has a photoelectric conversion characteristic that is linear for low-luminance light and logarithm for high-luminance light, and has a spectral characteristic of any one of a plurality of predetermined color components. It is a pixel that has.

  Here, a color filter is attached to each pixel GE. As the color filter, for example, a complementary color filter in which filters that transmit light of W (white), Y (yellow), and R (red) color components are arranged in a Bayer array, for example, can be employed. That is, the pixel GE has a spectral sensitivity of any one of W, Y, and R color components.

  The vertical scanning circuit 20 scans the pixel array unit 10 in the vertical direction and sequentially selects each row. Each pixel GE in the row selected by the vertical scanning circuit 20 outputs various output signals to the reading unit 40.

  The TG 30 outputs synchronization signals to the vertical scanning circuit 20, the sample hold processing circuit 41, the output circuit 42, and the horizontal scanning circuit 43 under the control of the imaging circuit 60, and synchronizes the operations of these circuits.

  The reading unit 40 includes a sample hold processing circuit 41, an output circuit 42, and a horizontal scanning circuit 43. The sample and hold processing circuit 41 includes m sample and hold elements 411 corresponding to each column of the pixel array unit 10.

  The sample hold element 411 reads the output signal from the pixel GE of the corresponding column among the m pixels GE of the row selected by the vertical scanning circuit 20, and holds the read output signal. Here, the pixel GE first outputs an output signal indicating a noise component, and then outputs an output signal indicating a noise component + signal component. Therefore, the sample hold element 411 executes processing for holding a noise component, processing for subtracting the noise component + signal component from the held noise component, and extracting the signal component.

  The output circuit 42 includes m output elements 421 corresponding to each column of the pixel array unit 10. When the output element 421 is selected by the horizontal scanning circuit 43, the signal element is read from the sample and hold element 411 in the corresponding column, and is output to the imaging circuit 60 via the output amplifier 50.

  Under the control of the TG 30, the horizontal scanning circuit 43 horizontally scans the output circuit 42 to sequentially select the output elements 421, and sequentially outputs output signals from the output circuit 42.

  The above solid-state imaging device 1 operates as follows. First, each row of the pixel array unit 10 is sequentially selected from the upper side to the lower side or from the lower side to the upper side by the vertical scanning circuit 20. From the m pixels GE in the selected row, first, an output signal of a noise component is output, and subsequently, an output signal of noise component + signal component is output. Each sample and hold element 411 subtracts the noise component + the signal component from the noise component, and extracts and holds the signal component. The output signal for one row held by each sample and hold element 411 is sequentially output to the outside of the solid-state imaging device 1 via the output element 421 by horizontal scanning of the horizontal scanning circuit 43. The processing for one row is performed for each row, and one frame of image data is taken into the imaging circuit 60.

  Then, in the imaging circuit 60, the missing pixels of the W, Y, and R complementary color filters are interpolated to generate image data including three color components of W, Y, and R. In each pixel, calculation of B = W−Y and G = Y−R is performed on the output signals of W, Y, and R, and image data including three color components of R, G, and B is obtained. Generated. That is, in the imaging circuit 60, at least one color component (R) has the same color component as the color component of the pixel GE, and the remaining color components (B, G) have different color components from any color component of the pixel GE. Calculate the output signal.

  FIG. 2 is a block diagram showing another example of the overall schematic configuration of the solid-state imaging device according to the modification of FIG. The solid-state imaging device of FIG. 2 includes a solid-state imaging element 1a. The solid-state imaging device 1a is a solid-state imaging device that assumes digital output. The main difference from FIG. 1 is that the reading unit 40 has an output circuit 42 and a column ADC array unit 72 instead. In addition, the solid-state imaging device 1 a includes a clock input terminal 80, a PLL 90, a temperature sensor 100, a lamp generator 110, a sense amplifier 120, a serializer 130, and an output terminal 140.

  The column ADC array unit 72 includes m column ADC elements 721 corresponding to the respective columns of the pixel array unit 10 and one column ADC element 721 for A / D converting analog measurement data of the temperature sensor 100. ing.

  The column ADC element 721 A / D converts the analog output signal held by the sample hold element 411 and holds it as a digital output signal of a predetermined bit (for example, 14 bits). Here, the column ADC element 721 counts the time from when the ramp signal is input until the level of the output signal exceeds or falls below the level of the ramp signal, and sets the count value as the digital value of the output signal.

  The horizontal scanning circuit 43 sequentially selects the column ADC elements 721 from the left side to the right side or from the right side to the left side, and causes the column ADC element 721 to output a digital output signal.

  The clock input terminal 80 takes in a clock signal output from, for example, a clock generation circuit (not shown) provided outside the solid-state imaging device 1a. The PLL 90 multiplies the frequency of the clock signal captured by the clock input terminal 80 to a predetermined value. The TG 30 generates various synchronization signals based on the clock signal multiplied by the PLL 90, and synchronizes the operations of the vertical scanning circuit 20, the sample hold processing circuit 41, the column ADC array unit 72, and the horizontal scanning circuit 43.

  The ramp generator 110 generates a ramp signal that is used when each column ADC element 721 performs A / D conversion on the signal component. The ramp signal is a signal whose level increases or decreases linearly.

  The sense amplifier 120 shapes the waveform of the output signal that is sequentially output from the column ADC array unit 72. The serializer 130 converts an output signal of a predetermined bit output in parallel from the sense amplifier 130 into a serial signal and outputs the serial signal to the output terminal 140. The output terminal 140 outputs a serial output signal output from the serializer 130 to, for example, an image processing circuit (not shown) provided outside the solid-state imaging device 1a.

  The above solid-state imaging device 1a operates as follows. The operation until each sample and hold element 411 extracts a signal component is the same as that of the solid-state imaging device 1. The output signal for one row held by each sample and hold element 411 is taken into each column ADC element 721 and A / D converted and held. The output signal held in each column ADC element 721 is sequentially output to the outside of the solid-state imaging device 1 a via the sense amplifier 120, the serializer 130, and the output terminal 140 by horizontal scanning of the horizontal scanning circuit 43. The processing for one row is performed on each row, and one frame of image data is taken into an image processing circuit (not shown). In the image processing circuit, the missing pixels of the W, Y, and R complementary color filters are interpolated to generate image data including the three color components of W, Y, and R. In each pixel, calculation of B = W−Y and G = Y−R is performed on the output signals of W, Y, and R, and image data including three color components of R, G, and B is obtained. Generated.

(Pixel configuration 1)
FIG. 3 is a circuit diagram of the pixel circuit 11 corresponding to the pixel GE shown in FIG. 1 or FIG. The pixel circuit 11 is described as a photodiode (hereinafter referred to as “PD”) and a transfer transistor “hereinafter referred to as“ Q1 ”. ), A reset transistor (hereinafter referred to as “Q2”), an amplifying transistor (hereinafter referred to as “Q3”), a row selection transistor (hereinafter referred to as “Q4”), and a floating diffusion layer. (Hereinafter referred to as “FD”. FD: Floating diffusion). In the pixel configuration 1, Q1 corresponds to a control transistor. PD corresponds to a charge storage unit, and FD corresponds to a charge reading unit.

The PD is composed of an embedded photodiode. Each of Q1 to Q4 is configured by a MOSFET. In Q1, a transfer signal (hereinafter referred to as “TX signal”) is applied to the gate, the drain is connected to Q2 via the FD, and the source is connected to the PD. Q1 transfers the charge accumulated in the PD to the FD.

  In the PD, for example, an anode is grounded to a substrate, a reference voltage VSS (hereinafter referred to as “VSS”) is input, and a cathode is connected to Q1. The PD generates charges according to the amount of incident light, and accumulates the charges in the parasitic capacitance of the PD. In Q2, a reset signal (hereinafter referred to as “RST signal”) is applied to the gate, the drain is connected to the voltage source of the drive voltage VDD (hereinafter referred to as “VDD”), and the source is connected to the FD. Has been. Q2 resets the FD by discharging the charge transferred to the FD.

  Q3 has a gate connected to FD, a source connected to Q4, and a drain connected to a voltage source of VDD. Q3 current-amplifies the charge accumulated in the FD. In Q4, a read signal (hereinafter referred to as "SX signal") is applied to the gate, and for example, the drain is connected to Q3 and the source is connected to the read line L_1. Q4 functions as a switch for outputting an output signal from the pixel circuit 11.

  FIG. 4 is a circuit diagram of a pixel circuit 11a which is a modification of the pixel circuit shown in FIG. The pixel circuit 11a is different from the pixel circuit 11 in the connection relationship between Q3 and Q4, but each function is the same as Q3 and Q4 of the pixel circuit 11. That is, the drain of Q3 is connected to Q4, and the source of Q3 is connected to the read line L_1. The drain of Q4 is connected to the VDD voltage source.

  Q1, Q2, and Q4 are connected to the vertical scanning circuit 20 through TX wiring, RST wiring, and SX wiring, respectively. The TX signal, the RST signal, and the SX signal are output by the vertical scanning circuit 20 through, for example, the TX wiring, the RST wiring, and the SX wiring.

  A voltage application circuit for supplying a TX signal to the gate of Q1 is connected to the TX wiring. In order to apply individual TX signals to Q1 of each row, a voltage application circuit may be provided for each row. A plurality of voltage application circuits may be provided, and a selection switch for selecting a voltage application circuit to be connected may be provided in each row.

  FIG. 5 is a timing chart of the pixel circuit 11 shown in FIG. 3 or the pixel circuit 11a shown in FIG. In FIG. 5, the amount of incident light is as high as the amount of light X1 or X2 at the beginning of the exposure period, but the amount of light is 0 in the remaining exposure period.

  The RST signal is set to Hi during the exposure period. Thereby, in the exposure period, the charge leaked from the PD to the FD through Q1 is discharged to the outside of the pixel circuits 11 and 11a by Q2.

  The TX signal has a voltage value V1 that turns Q1 into a non-conducting state, that is, a state in which Q1 is turned off before the start of the exposure period. At the start of the exposure period, Q1 is in a fully open conduction state, that is, Q1. Has a voltage value V3 to turn on. Thereafter, the TX signal gradually decreases in one direction that makes Q1 non-conductive toward the end of the exposure period. At the end of the exposure period, the TX signal has a voltage value V2. The voltage value V2 is an intermediate voltage value between the voltage value V1 and the voltage value V3, and is a voltage value set in order to realize linear log characteristics in the conventional pixel circuit. That is, the voltage value V2 is a voltage value for setting Q1 to an intermediate conduction state between the fully open conduction state and the non-conduction state in order to realize the linear log characteristic.

  The light amounts X1 and X2 are high light amounts that can bring Q1 into a subthreshold state. When Q1 enters the sub-threshold state, a part of the charge accumulated in the PD leaks to the FD through Q1, so that the relationship between the incident light quantity and the output signal becomes a logarithm. Here, high-intensity light that makes the relationship between the incident light quantity and the output signal logarithmically is described as light in the logarithmic region. If the amount of incident light is low, Q1 does not enter the subthreshold state. In this case, since the charge accumulated in the PD does not leak to the FD via Q1, the relationship between the incident light quantity and the output signal is linear. Here, low-luminance light that linearizes the relationship between the amount of incident light and the output signal is described as light in the linear region.

  At the start of the exposure period, light of the light amounts X1 and X2 is incident. However, since the voltage value of the TX signal is V3 and high, the PD can store only a small amount of charge. Thereafter, the incidence of light of the light amounts X1 and X2 is continued, but the voltage value of the TX signal gradually decreases and the gate of Q1 is gradually closed, so that the amount of charge leaking from the PD gradually decreases. However, the charge accumulated in the PD gradually increases. In the waveform of the light amount and the charge amount of PD, the dotted line indicates the case where the light amount X1 is incident, and the solid line indicates the case where the light amount X2 is incident.

  When the amount of incident light becomes 0, the TX signal has a voltage value less than the voltage value V3 and greater than or equal to the voltage value V2, and Q1 is in a conduction state between the fully open conduction state and the intermediate conduction state. The amount of charge that accumulates decreases. However, the amount of charge accumulated in the PD does not fall below the sub-threshold level of Q1, and therefore approaches a certain amount of charge y.

  When the exposure period ends, a signal reading period starts. In the period T1, the SX signal becomes Hi, and the voltage value of the FD is output to the reading unit 40 as an output signal of the noise component. In the period T2, the TX signal is set to the voltage value V3, and the charge accumulated in the PD is transferred to the FD. As a result, the voltage value of the FD changes to a value corresponding to the transferred charge amount. Thereafter, in the period T3, the SX signal becomes Hi, and the voltage value of the FD is output to the reading unit 40 as an output signal of noise component + signal component. Then, the difference between the noise component output signal and the noise component + signal component output signal is taken, and an output signal consisting only of the signal component is obtained.

  Here, during the period when the light amounts X1 and X2 are incident, the voltage value of the TX signal is set to a value near the voltage value V3, and only a small amount of charge is accumulated in the PD. Therefore, the charge amount y is significantly smaller than the charge amount y shown in FIG. As a result, color balance can be maintained.

  Specifically, the amount of light X1 represents the amount of light received by the pixel GE having a Y (yellow) color filter, and the amount of light X2 represents the amount of light received by the pixel GE having an R (red) color filter. . In this case, the amount of charge accumulated in the R and G pixels GE is both y and the same. Therefore, when the difference between the Y output signal and the R output signal is taken to obtain the G (= Y−R) output signal, the G output signal becomes zero.

  However, since the charge amount y is significantly smaller than the charge amount y shown in FIG. 16, the output signal of R is also almost zero. Therefore, the R output signal is prevented from becoming higher than the G output signal, and the color balance can be maintained.

  FIG. 6 is a timing chart of the pixel circuits 11 and 11a when light of constant light amounts X1 and X2 is incident during the exposure period. In the case of FIG. 6, the amount of incident light is constant at X1 or X2 during the exposure period. On the other hand, the TX signal has a voltage value V3 at the start of exposure and gradually decreases from the voltage value V2 toward the voltage value V2. Therefore, as the exposure period elapses, the gate of Q1 is gradually closed, the amount of charge leaking from the PD is gradually decreased, and the amount of charge accumulated in the PD is gradually increased. In FIG. 6, in the waveform of the light amount and the charge amount of the PD, the dotted line indicates the case where the light amount X1 is incident, and the solid line indicates the case where the light amount X2 is incident. The light of the light amounts X1 and X2 is light in the logarithmic region, and the charge accumulated in the PD with respect to the light in the logarithmic region has no time integration. Therefore, the amount of charge accumulated in the PD is determined by the voltage value of the TX signal at the final point of the exposure period.

  At the end of the exposure period, the TX signal has a voltage value V2 and the same voltage value as the conventional linear log sensor. Therefore, the amount of charge accumulated in the PD is at the same level as that of a conventional linear log sensor. As a result, an output signal having a level similar to that of a conventional pixel circuit is obtained when light of a constant light amount X1, X2 is incident during the exposure period.

  In the present embodiment, the TX signal gradually decreases from the voltage value V3. Thereby, it can respond also to the light of a linear area | region.

  For example, consider a case where the TX signal is set to the voltage value V3 for a certain initial period from the start of the exposure period and then switched to the voltage value V2. In this case, almost no charge is accumulated in the PD in this initial fixed period. PD has time integration with respect to light in the linear region. Therefore, if no charge is accumulated in the PD during this initial fixed period, the output for the light in the linear region is larger than when the voltage value of the TX signal is fixed from the start point to the end point of the exposure period as in the prior art. The signal level is greatly reduced.

  On the other hand, in the present embodiment, since the voltage value of the TX signal gradually decreases from the voltage value V3, the charge is accumulated in the PD even during the initial fixed period as described above. Compared with the case where the voltage value of the TX signal is kept constant from the start point to the end point of the exposure period, a significant decrease in the level of the output signal with respect to the light in the linear region is suppressed.

  In the above description, the voltage value of the TX signal is V3 at the start of the exposure period. However, the voltage value is not limited to this, and any voltage may be used as long as the voltage value is greater than the voltage value V2 and less than the voltage value V3. A value may be adopted. Even if the voltage value at the start of the exposure period is lower than the voltage value V3, even if a high amount of light is incident during the initial period and a low amount of light is incident during the remaining exposure period, Since the amount of charge y that is finally accumulated becomes small, the color balance can be maintained.

(Pixel configuration 2)
The circuit configuration of the pixel configuration 2 is the same as that of the pixel configuration 1 shown in FIG. 3 or FIG. 4. However, during the exposure period, the Q1 is always in a fully open conduction state, and the charge amount stored in the PD is controlled by the Q2. That is, in the pixel configuration 2, Q2 instead of Q1 corresponds to the control transistor.

  FIG. 14 is a timing chart of the pixel circuits 11 and 11a in the pixel configuration 2. In pixel configuration 2, the RST signal has the same waveform as the TX signal in pixel configuration 1. That is, the RST signal has the voltage value V3 at the start of the exposure period and has the voltage value V2 at the end of the exposure period. The voltage value of the RST signal gradually decreases from the voltage value V3 to the voltage value V2 during the exposure period.

  On the other hand, the TX signal always maintains the voltage value V3 (= Hi). Therefore, Q1 is always on and PD and FD are directly connected. Therefore, in FIG. 14, the waveform indicating the PD charge amount in FIG. 5 is the waveform of the FD change amount.

  In the pixel configuration 2 as well, in order to individually apply the RST signal to Q2 of each row, a voltage application circuit may be provided for each row. A plurality of voltage application circuits may be provided, and a selection switch for selecting a voltage application circuit to be connected may be provided in each row.

  In the configuration 2 of the pixel, the charge generated in the PD with respect to the light in the linear region remains in the parasitic capacitance and FD of the PD even during the exposure period, and the total amount of charges in the PD and FD and the incident light. There is a linear relationship with the amount of light. On the other hand, for the light in the logarithmic region, since Q2 is in a subthreshold state, the charge generated in the PD flows out to the voltage source side of VDD through Q2. At this time, the amount of charge accumulated in the PD and the amount of incident light have a logarithmic relationship. Therefore, the pixel configuration 2 has a linear log characteristic.

  The pixel configuration 2 is the same as the pixel configuration 1 except that Q2 instead of Q1 controls the amount of charge accumulated by the PD. The RST signal applied to the gate of Q2 has the same waveform as the TX signal applied to the gate of Q1 of the pixel configuration 1. Therefore, in the pixel configuration 2, even if a high amount of light enters during the first period of the exposure period and a low amount of light enters during the remaining exposure period, the charge accumulated in the PD at the end of the exposure period The amount is kept low, and the color balance can be maintained as in the pixel configuration 1.

  Further, when light having a constant light amount X1 or X2 is incident during the exposure period, there is no time integration for the light in the log area, and the RST signal at the final point of the exposure period is a voltage similar to the conventional pixel circuit. It has the value V2. Therefore, it is possible to output an output signal having the same level as the conventional one. Furthermore, the voltage value of the RST signal gradually decreases from the start time to the end time of the exposure period, as in the pixel configuration 1, and thus there is a period in which the PD does not accumulate any charge for light in the linear region. Such a situation is prevented. For this reason, in the configuration 1 of the pixel, as in the configuration 1 of the pixel, the level of the output signal obtained with respect to the light in the linear region may be significantly lower than the level of the output signal obtained in the conventional pixel circuit. It is suppressed and can exhibit good behavior even for light in the linear region.

Example 1
The solid-state imaging device according to the first embodiment is characterized by a connection relationship with the voltage application circuit 700 of the pixel array unit 10. FIG. 7 is a diagram illustrating a connection relationship between the pixel array unit 10 and the voltage application circuit 700 of the solid-state imaging device according to the first embodiment. In the solid-state imaging device according to the first embodiment, the pixel configuration 1 is adopted as the pixel GE, and the voltage application circuit 700 is provided in each row of the pixel array unit 10. The voltage application circuit 700 is connected to the gate of Q1 of the pixel GE in the corresponding row via a TX wiring. The voltage application circuit 700 generates a TX signal whose voltage value decreases stepwise from the voltage value V3 toward the voltage value V2, and supplies the TX signal to the pixel GE.

  As described above, by providing the voltage application circuit 700 in each row, the TX signal having the same waveform can be applied to the pixels GE in each row while being shifted by a certain time, and the solid-state imaging device is driven by the rolling shutter method. An appropriate TX signal can be applied to each row. Further, when the solid-state imaging device is driven by the global shutter method, the TX signal may be applied to each row at the same timing.

  FIG. 8 is a diagram illustrating a connection relationship between the pixel array unit 10 and the voltage application circuit 700 in the solid-state imaging device according to the modification of the first embodiment. The difference from FIG. 7 is that the voltage application circuit 700 supplies a continuously changing TX signal instead of a stepped shape. In this case as well, the TX signal has a voltage value V3 at the start of the exposure period and has a voltage value V2 at the end of the exposure period, and the voltage value gradually decreases. In FIG. 8, the same effect as in FIG. 7 can be obtained.

  In the pixel configuration 2, in the reading period, when the exposure period ends, the SX signal is set to Hi and the voltage value of the FD is output as an output signal of noise component + signal component. Next, in the reset period, the RST signal becomes Hi and the FD is reset, the SX signal becomes Hi, and the voltage value of the FD is output as an output signal of the noise component.

(Example 2)
The solid-state imaging device according to the second embodiment is characterized in that the pixel array unit 10 is connected to one voltage application circuit 700 via the connection unit 900. FIG. 9 is a diagram illustrating a connection relationship between the pixel array unit 10 and the voltage application circuit 700 in the solid-state imaging device according to the second embodiment. In the solid-state imaging device according to the second embodiment, the pixel configuration 1 is employed as the pixel GE.

  Similar to the voltage application circuit 700 of FIG. 8, the voltage application circuit 700 generates a continuously changing TX signal. The connection unit 900 is provided in each row of the pixel array unit 10. The connection unit 900 includes a signal reading waveform generation circuit 910 and a switch 920.

  The signal reading waveform generation circuit 910 generates a signal having the waveform of the TX signal in the signal reading period of FIGS.

  In the second embodiment, since there is one voltage application circuit 700, it is preferable to employ a global shutter system in which the exposure periods of all rows are the same. In the global shutter system, it is necessary to shift the output timing of output signals from the pixels GE in each row. Therefore, the solid-state imaging device of Example 2 operates as follows.

  First, when the exposure period is started, the switches 920 in each row connect the voltage application circuit 700 to the pixel array unit 10 all at once. As a result, the TX signal of the exposure period is applied to each row of the pixel array unit 10 all at once.

  When the exposure period ends, the signal reading period starts, and the pixel GE in each row has a predetermined timing for each row, the SX signal is set to Hi, and the output signal of the noise component from the pixel GE in each row Is output. Thereby, the output signal of the noise component is output from the pixel GE with the timing shifted for each row.

  Next, the switch 920 in each row connects the signal reading waveform generation circuit 910 to the pixel GE in the same row at a predetermined timing for each row, and causes the pixel GE to apply the TX signal in the signal reading period. As a result, charges are transferred from the PD to the FD at different timings for each row. Next, at a predetermined timing for each row, the SX signal is set to Hi, and an output signal of noise component + signal component is output from the pixel GE of each row. Thereby, the output signal of the noise component + the signal component is output from the pixel GE while shifting the timing for each row.

  FIG. 10 is a diagram illustrating a connection relationship between the voltage application circuit 700 and the pixel array unit 10 of the solid-state imaging device according to the modification of the second embodiment. The difference from FIG. 9 is that the TX signal output from the voltage application circuit 700 changes in a stepped manner instead of a continuous one, and the rest is the same as FIG.

  In the second embodiment, since the voltage application circuit 700 is common to all rows, the circuit scale can be reduced. As a result, the area of the chip constituting the solid-state image sensor 1 is reduced, and the cost of the solid-state image sensor 1 can be reduced. Moreover, since the area of the chip of the solid-state imaging device 1 can be reduced, power consumption can be reduced.

(Example 3)
The solid-state imaging device according to the third embodiment is characterized in that the pixel array unit 10 is divided into one block 1100 for each plurality of rows, and a voltage application circuit 700 is provided for each block 1100. In the third embodiment, the pixel configuration 1 is employed as the pixel GE. FIG. 11 is a diagram illustrating a connection relationship between the pixel array unit 10 and the voltage application circuit 700 of the solid-state imaging device according to the third embodiment.

  This configuration can be applied to both the global shutter method and the rolling shutter method. First, a global shutter method in which the exposure periods of all rows are the same will be described. Since the operation when the global shutter method is adopted is the same as that of the second embodiment, only the case where the rolling shutter method with different exposure timing for each row is adopted will be described.

  FIG. 12 shows the relationship between the TX signal output from the voltage application circuit 700 and the TX signal applied to Q1 of each row for rows # 1 to #n (n is a positive integer) in one block 1100. It is a timing chart which shows. In the example of FIG. 12, the TX signal generated by the voltage application circuit 700 has a maximum voltage value of level LV1, and as the exposure period elapses, the voltage value increases by a certain level such as levels LV2, LV3,. is decreasing.

  The TX signal is applied to the exposure period of each row, but since the start timing of the exposure period is different for each row, the TX signal actually applied to the rows # 1 to #n is the row as shown in FIG. Everything is off. Specifically, when the exposure period starts, the voltage application circuit 700 starts outputting the TX signal. At the same time, the switch 920 in the row # 1 connects the voltage application circuit 700 and the pixel GE in the row # 1. Therefore, there is no difference between the TX signal applied to the pixel GE in the row # 1 and the TX signal output from the voltage application circuit 700.

  Next, after a certain period ΔT has elapsed, the switch 920 in the row # 2 connects the voltage application circuit 700 and the pixel GE in the row # 2. Therefore, the start time of the exposure period of the pixel GE in row # 2 is deviated by a certain period ΔT from the start time of the TX signal. Therefore, the period of the level LV1 of the TX signal applied to the pixel GE in the row # 2 is shortened by a certain period ΔT.

  Similarly, in the block 1100, the TX signal is applied to the pixels GE in the rows # 1 to #n while being shifted by a certain period ΔT toward the rows # 1 to #n. Therefore, the period of the level LV1 of the TX signal applied to the pixels GE toward the rows # 2 to #n is shortened by a certain period ΔT. In the example of FIG. 12, the period T_LV1 of the level LV1 of the TX signal generated by the voltage application circuit 700 is set to be greater than (n−1) · ΔT.

  Further, the voltage application circuit 700 of the block 1100 in the next row shifts the output of the TX signal by n · ΔT from the time when the voltage application circuit 700 of the block 1100 in the next row starts outputting the TX signal. Start.

  Thus, in Example 3, in the same block 1100, strictly, TX signals having the same waveform cannot be applied to the pixels GE in each row. However, since all the rows of the pixel array unit 10 are divided into a plurality of blocks 1100, the TX signal shift within one block 1100 can be reduced. Since the TX signal whose voltage value gradually decreases is applied to the pixels GE in each row, the effect of the solid-state imaging device of the present embodiment can be obtained.

  As described above, in Example 3, since all the rows of the pixel array unit 10 are divided into the plurality of blocks 1100, the voltage application circuit 700 may be provided for each block 1100. As a result, the circuit scale can be reduced. Can do.

Example 4
The fourth embodiment employs the pixel configuration 2 as the pixel GE in the solid-state imaging device of the first embodiment. In this case, in FIG. 7 and FIG. 8, the TX signal output from the voltage application circuit 700 may be read as the RST signal, and this RST signal may be applied to Q2 of the pixel GE. By doing so, the same effects as those of the first embodiment can be obtained even when the pixel configuration 2 is adopted.

(Example 5)
In Example 5, the pixel configuration 2 is adopted as the pixel GE in the solid-state imaging device of Example 2. In this case, in FIG. 9 and FIG. 10, the TX signal output from the voltage application circuit 700 may be read as the RST signal, and this RST signal may be applied to Q2 of the pixel GE. By doing so, the same effect as in the second embodiment can be obtained even when the pixel configuration 2 is adopted.

(Example 6)
In the sixth embodiment, the pixel configuration 2 is used as the pixel GE in the solid-state imaging device according to the third embodiment. In this case, in FIG. 11, the TX signal output from the voltage application circuit 700 may be read as an RST signal, and this RST signal may be applied to Q2 of the pixel GE. By doing so, the same effects as those of the first embodiment can be obtained even when the pixel configuration 2 is adopted.

  FIG. 13 shows the relationship between the RST signal output from the voltage application circuit 700 and the RST signal applied to Q2 of each row for rows # 1 to #n (n is a positive integer) in one block 1100. It is a timing chart which shows.

  As described above, in the sixth embodiment, in the same block 1100, strictly, it is not possible to apply the RST signal having the same waveform to the pixels GE in each row. However, since all the rows of the pixel array section 10 are divided into a plurality of blocks 1100, the shift of the RST signal in one block 1100 can be reduced. Therefore, in Example 6, the same effect as Example 3 is acquired.

DESCRIPTION OF SYMBOLS 1,1a Solid-state image sensor 10 Pixel array part 11, 11a Pixel circuit 20 Vertical scanning circuit 30 Timing generator 40 Reading unit 50 Output amplifier 60 Imaging circuit 700 Voltage application circuit 900 Connection part 910 Signal reading waveform generation circuit 920 Switch 1100 Block GE Pixel V1, V2, V3 voltage value

Claims (7)

Multiple pixel circuits that have linear photoelectric conversion characteristics for low-luminance light and logarithmic photoelectric conversion characteristics for high-luminance light, and have spectral characteristics of any one of a plurality of predetermined color components A solid-state imaging device comprising:
The pixel circuit includes a charge accumulation unit that generates and accumulates charges according to the amount of incident light, a control transistor that controls the amount of charge accumulated in the charge accumulation unit, and converts the charges accumulated in the charge accumulation unit into a voltage signal. A charge reading unit that reads out as an output signal, and an amplification transistor that amplifies the output signal read out by the charge reading unit,
By driving the control transistor in a predetermined intermediate conduction state between a fully open conduction state in which the control transistor is in an on state and a non-conduction state in which the control transistor is in an off state at least at the end of the exposure period, A solid-state imaging device comprising: a control unit that accumulates charges with the photoelectric conversion characteristics in a charge accumulation unit and drives the control transistor in a conduction state higher than the predetermined intermediate conduction state at least at the start of the exposure period.   The solid-state imaging device according to claim 1, wherein the control unit changes a conduction state of the control transistor in one direction toward the non-conduction state during the exposure period.   3. The solid-state imaging device according to claim 1, wherein the control unit sets the conduction state of the control transistor to the fully open conduction state at a start time of the exposure period. The charge storage unit is configured by a photodiode,
The charge reading unit is constituted by a floating diffusion layer,
The solid-state imaging device according to claim 1, wherein the control transistor is connected between the charge storage unit and the charge reading unit. The charge storage unit is configured by a photodiode,
The charge reading unit is constituted by a floating diffusion layer,
The solid-state imaging device according to claim 1, wherein the control transistor is connected to the charge storage unit via the charge reading unit.   The solid-state imaging device according to claim 1, wherein the control unit continuously changes a conduction state of the control transistor during the exposure period.   The solid-state imaging device according to claim 1, wherein the control unit changes the conduction state of the control transistor stepwise during the exposure period.

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